if_skreg.h revision 147256
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 147256 2005-06-10 16:49:24Z brooks $ 35 */ 36 37/*- 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart (SK_CHIPVER). */ 54#define SK_GENESIS 0x0A 55#define SK_YUKON 0xB0 56#define SK_YUKON_LITE 0xB1 57#define SK_YUKON_LP 0xB2 58#define SK_YUKON_FAMILY(x) ((x) & 0xB0) 59 60/* Known revisions in SK_CONFIG. */ 61#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 62#define SK_YUKON_LITE_REV_A1 0x3 63#define SK_YUKON_LITE_REV_A3 0x7 64 65/* 66 * SysKonnect PCI vendor ID 67 */ 68#define VENDORID_SK 0x1148 69 70/* 71 * Marvell PCI vendor ID 72 */ 73#define VENDORID_MARVELL 0x11AB 74 75/* 76 * SK-NET gigabit ethernet device IDs 77 */ 78#define DEVICEID_SK_V1 0x4300 79#define DEVICEID_SK_V2 0x4320 80 81/* 82 * Belkin F5D5005 83 */ 84#define DEVICEID_BELKIN_5005 0x5005 85 86/* 87 * 3Com PCI vendor ID 88 */ 89#define VENDORID_3COM 0x10b7 90 91/* 92 * 3Com gigabit ethernet device ID 93 */ 94#define DEVICEID_3COM_3C940 0x1700 95 96/* 97 * Linksys PCI vendor ID 98 */ 99#define VENDORID_LINKSYS 0x1737 100 101/* 102 * Linksys gigabit ethernet device ID 103 */ 104#define DEVICEID_LINKSYS_EG1032 0x1032 105 106/* 107 * D-Link PCI vendor ID 108 */ 109#define VENDORID_DLINK 0x1186 110 111/* 112 * D-Link gigabit ethernet device ID 113 */ 114#define DEVICEID_DLINK_DGE530T 0x4c00 115 116/* 117 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 118 * but internally it has a 16K register space. This 16K space is 119 * divided into 128-byte blocks. The first 128 bytes of the I/O 120 * window represent the first block, which is permanently mapped 121 * at the start of the window. The other 127 blocks can be mapped 122 * to the second 128 bytes of the I/O window by setting the desired 123 * block value in the RAP register in block 0. Not all of the 127 124 * blocks are actually used. Most registers are 32 bits wide, but 125 * there are a few 16-bit and 8-bit ones as well. 126 */ 127 128 129/* Start of remappable register window. */ 130#define SK_WIN_BASE 0x0080 131 132/* Size of a window */ 133#define SK_WIN_LEN 0x80 134 135#define SK_WIN_MASK 0x3F80 136#define SK_REG_MASK 0x7F 137 138/* Compute the window of a given register (for the RAP register) */ 139#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 140 141/* Compute the relative offset of a register within the window */ 142#define SK_REG(reg) ((reg) & SK_REG_MASK) 143 144#define SK_PORT_A 0 145#define SK_PORT_B 1 146 147/* 148 * Compute offset of port-specific register. Since there are two 149 * ports, there are two of some GEnesis modules (e.g. two sets of 150 * DMA queues, two sets of FIFO control registers, etc...). Normally, 151 * the block for port 0 is at offset 0x0 and the block for port 1 is 152 * at offset 0x80 (i.e. the next page over). However for the transmit 153 * BMUs and RAMbuffers, there are two blocks for each port: one for 154 * the sync transmit queue and one for the async queue (which we don't 155 * use). However instead of ordering them like this: 156 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 157 * SysKonnect has instead ordered them like this: 158 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 159 * This means that when referencing the TX BMU and RAMbuffer registers, 160 * we have to double the block offset (0x80 * 2) in order to reach the 161 * second queue. This prevents us from using the same formula 162 * (sk_port * 0x80) to compute the offsets for all of the port-specific 163 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 164 * The simplest thing is to provide an extra argument to these macros: 165 * the 'skip' parameter. The 'skip' value is the number of extra pages 166 * for skip when computing the port0/port1 offsets. For most registers, 167 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 168 */ 169#define SK_IF_READ_4(sc_if, skip, reg) \ 170 sk_win_read_4(sc_if->sk_softc, reg + \ 171 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 172#define SK_IF_READ_2(sc_if, skip, reg) \ 173 sk_win_read_2(sc_if->sk_softc, reg + \ 174 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 175#define SK_IF_READ_1(sc_if, skip, reg) \ 176 sk_win_read_1(sc_if->sk_softc, reg + \ 177 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 178 179#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 180 sk_win_write_4(sc_if->sk_softc, \ 181 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 182#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 183 sk_win_write_2(sc_if->sk_softc, \ 184 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 185#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 186 sk_win_write_1(sc_if->sk_softc, \ 187 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 188 189/* Block 0 registers, permanently mapped at iobase. */ 190#define SK_RAP 0x0000 191#define SK_CSR 0x0004 192#define SK_LED 0x0006 193#define SK_ISR 0x0008 /* interrupt source */ 194#define SK_IMR 0x000C /* interrupt mask */ 195#define SK_IESR 0x0010 /* interrupt hardware error source */ 196#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 197#define SK_ISSR 0x0018 /* special interrupt source */ 198#define SK_XM_IMR0 0x0020 199#define SK_XM_ISR0 0x0028 200#define SK_XM_PHYADDR0 0x0030 201#define SK_XM_PHYDATA0 0x0034 202#define SK_XM_IMR1 0x0040 203#define SK_XM_ISR1 0x0048 204#define SK_XM_PHYADDR1 0x0050 205#define SK_XM_PHYDATA1 0x0054 206#define SK_BMU_RX_CSR0 0x0060 207#define SK_BMU_RX_CSR1 0x0064 208#define SK_BMU_TXS_CSR0 0x0068 209#define SK_BMU_TXA_CSR0 0x006C 210#define SK_BMU_TXS_CSR1 0x0070 211#define SK_BMU_TXA_CSR1 0x0074 212 213/* SK_CSR register */ 214#define SK_CSR_SW_RESET 0x0001 215#define SK_CSR_SW_UNRESET 0x0002 216#define SK_CSR_MASTER_RESET 0x0004 217#define SK_CSR_MASTER_UNRESET 0x0008 218#define SK_CSR_MASTER_STOP 0x0010 219#define SK_CSR_MASTER_DONE 0x0020 220#define SK_CSR_SW_IRQ_CLEAR 0x0040 221#define SK_CSR_SW_IRQ_SET 0x0080 222#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 223#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 224 225/* SK_LED register */ 226#define SK_LED_GREEN_OFF 0x01 227#define SK_LED_GREEN_ON 0x02 228 229/* SK_ISR register */ 230#define SK_ISR_TX2_AS_CHECK 0x00000001 231#define SK_ISR_TX2_AS_EOF 0x00000002 232#define SK_ISR_TX2_AS_EOB 0x00000004 233#define SK_ISR_TX2_S_CHECK 0x00000008 234#define SK_ISR_TX2_S_EOF 0x00000010 235#define SK_ISR_TX2_S_EOB 0x00000020 236#define SK_ISR_TX1_AS_CHECK 0x00000040 237#define SK_ISR_TX1_AS_EOF 0x00000080 238#define SK_ISR_TX1_AS_EOB 0x00000100 239#define SK_ISR_TX1_S_CHECK 0x00000200 240#define SK_ISR_TX1_S_EOF 0x00000400 241#define SK_ISR_TX1_S_EOB 0x00000800 242#define SK_ISR_RX2_CHECK 0x00001000 243#define SK_ISR_RX2_EOF 0x00002000 244#define SK_ISR_RX2_EOB 0x00004000 245#define SK_ISR_RX1_CHECK 0x00008000 246#define SK_ISR_RX1_EOF 0x00010000 247#define SK_ISR_RX1_EOB 0x00020000 248#define SK_ISR_LINK2_OFLOW 0x00040000 249#define SK_ISR_MAC2 0x00080000 250#define SK_ISR_LINK1_OFLOW 0x00100000 251#define SK_ISR_MAC1 0x00200000 252#define SK_ISR_TIMER 0x00400000 253#define SK_ISR_EXTERNAL_REG 0x00800000 254#define SK_ISR_SW 0x01000000 255#define SK_ISR_I2C_RDY 0x02000000 256#define SK_ISR_TX2_TIMEO 0x04000000 257#define SK_ISR_TX1_TIMEO 0x08000000 258#define SK_ISR_RX2_TIMEO 0x10000000 259#define SK_ISR_RX1_TIMEO 0x20000000 260#define SK_ISR_RSVD 0x40000000 261#define SK_ISR_HWERR 0x80000000 262 263/* SK_IMR register */ 264#define SK_IMR_TX2_AS_CHECK 0x00000001 265#define SK_IMR_TX2_AS_EOF 0x00000002 266#define SK_IMR_TX2_AS_EOB 0x00000004 267#define SK_IMR_TX2_S_CHECK 0x00000008 268#define SK_IMR_TX2_S_EOF 0x00000010 269#define SK_IMR_TX2_S_EOB 0x00000020 270#define SK_IMR_TX1_AS_CHECK 0x00000040 271#define SK_IMR_TX1_AS_EOF 0x00000080 272#define SK_IMR_TX1_AS_EOB 0x00000100 273#define SK_IMR_TX1_S_CHECK 0x00000200 274#define SK_IMR_TX1_S_EOF 0x00000400 275#define SK_IMR_TX1_S_EOB 0x00000800 276#define SK_IMR_RX2_CHECK 0x00001000 277#define SK_IMR_RX2_EOF 0x00002000 278#define SK_IMR_RX2_EOB 0x00004000 279#define SK_IMR_RX1_CHECK 0x00008000 280#define SK_IMR_RX1_EOF 0x00010000 281#define SK_IMR_RX1_EOB 0x00020000 282#define SK_IMR_LINK2_OFLOW 0x00040000 283#define SK_IMR_MAC2 0x00080000 284#define SK_IMR_LINK1_OFLOW 0x00100000 285#define SK_IMR_MAC1 0x00200000 286#define SK_IMR_TIMER 0x00400000 287#define SK_IMR_EXTERNAL_REG 0x00800000 288#define SK_IMR_SW 0x01000000 289#define SK_IMR_I2C_RDY 0x02000000 290#define SK_IMR_TX2_TIMEO 0x04000000 291#define SK_IMR_TX1_TIMEO 0x08000000 292#define SK_IMR_RX2_TIMEO 0x10000000 293#define SK_IMR_RX1_TIMEO 0x20000000 294#define SK_IMR_RSVD 0x40000000 295#define SK_IMR_HWERR 0x80000000 296 297#define SK_INTRS1 \ 298 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 299 300#define SK_INTRS2 \ 301 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 302 303/* SK_IESR register */ 304#define SK_IESR_PAR_RX2 0x00000001 305#define SK_IESR_PAR_RX1 0x00000002 306#define SK_IESR_PAR_MAC2 0x00000004 307#define SK_IESR_PAR_MAC1 0x00000008 308#define SK_IESR_PAR_WR_RAM 0x00000010 309#define SK_IESR_PAR_RD_RAM 0x00000020 310#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 311#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 312#define SK_IESR_NO_STS_MAC2 0x00000100 313#define SK_IESR_NO_STS_MAC1 0x00000200 314#define SK_IESR_IRQ_STS 0x00000400 315#define SK_IESR_MASTERERR 0x00000800 316 317/* SK_IEMR register */ 318#define SK_IEMR_PAR_RX2 0x00000001 319#define SK_IEMR_PAR_RX1 0x00000002 320#define SK_IEMR_PAR_MAC2 0x00000004 321#define SK_IEMR_PAR_MAC1 0x00000008 322#define SK_IEMR_PAR_WR_RAM 0x00000010 323#define SK_IEMR_PAR_RD_RAM 0x00000020 324#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 325#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 326#define SK_IEMR_NO_STS_MAC2 0x00000100 327#define SK_IEMR_NO_STS_MAC1 0x00000200 328#define SK_IEMR_IRQ_STS 0x00000400 329#define SK_IEMR_MASTERERR 0x00000800 330 331/* Block 2 */ 332#define SK_MAC0_0 0x0100 333#define SK_MAC0_1 0x0104 334#define SK_MAC1_0 0x0108 335#define SK_MAC1_1 0x010C 336#define SK_MAC2_0 0x0110 337#define SK_MAC2_1 0x0114 338#define SK_CONNTYPE 0x0118 339#define SK_PMDTYPE 0x0119 340#define SK_CONFIG 0x011A 341#define SK_CHIPVER 0x011B 342#define SK_EPROM0 0x011C 343#define SK_EPROM1 0x011D 344#define SK_EPROM2 0x011E 345#define SK_EPROM3 0x011F 346#define SK_EP_ADDR 0x0120 347#define SK_EP_DATA 0x0124 348#define SK_EP_LOADCTL 0x0128 349#define SK_EP_LOADTST 0x0129 350#define SK_TIMERINIT 0x0130 351#define SK_TIMER 0x0134 352#define SK_TIMERCTL 0x0138 353#define SK_TIMERTST 0x0139 354#define SK_IMTIMERINIT 0x0140 355#define SK_IMTIMER 0x0144 356#define SK_IMTIMERCTL 0x0148 357#define SK_IMTIMERTST 0x0149 358#define SK_IMMR 0x014C 359#define SK_IHWEMR 0x0150 360#define SK_TESTCTL1 0x0158 361#define SK_TESTCTL2 0x0159 362#define SK_GPIO 0x015C 363#define SK_I2CHWCTL 0x0160 364#define SK_I2CHWDATA 0x0164 365#define SK_I2CHWIRQ 0x0168 366#define SK_I2CSW 0x016C 367#define SK_BLNKINIT 0x0170 368#define SK_BLNKCOUNT 0x0174 369#define SK_BLNKCTL 0x0178 370#define SK_BLNKSTS 0x0179 371#define SK_BLNKTST 0x017A 372 373#define SK_IMCTL_STOP 0x02 374#define SK_IMCTL_START 0x04 375 376#define SK_IMTIMER_TICKS 54 377#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 378 379#define SK_IM_MIN 10 380#define SK_IM_DEFAULT 100 381#define SK_IM_MAX 10000 382 383/* 384 * The SK_EPROM0 register contains a byte that describes the 385 * amount of SRAM mounted on the NIC. The value also tells if 386 * the chips are 64K or 128K. This affects the RAMbuffer address 387 * offset that we need to use. 388 */ 389#define SK_RAMSIZE_512K_64 0x1 390#define SK_RAMSIZE_1024K_128 0x2 391#define SK_RAMSIZE_1024K_64 0x3 392#define SK_RAMSIZE_2048K_128 0x4 393 394#define SK_RBOFF_0 0x0 395#define SK_RBOFF_80000 0x80000 396 397/* 398 * SK_EEPROM1 contains the PHY type, which may be XMAC for 399 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 400 * PHY. 401 */ 402#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 403#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 404#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 405#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 406#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 407#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 408 409/* 410 * PHY addresses. 411 */ 412#define SK_PHYADDR_XMAC 0x0 413#define SK_PHYADDR_BCOM 0x1 414#define SK_PHYADDR_LONE 0x3 415#define SK_PHYADDR_NAT 0x0 416#define SK_PHYADDR_MARV 0x0 417 418#define SK_CONFIG_SINGLEMAC 0x01 419#define SK_CONFIG_DIS_DSL_CLK 0x02 420 421#define SK_PMD_1000BASELX 0x4C 422#define SK_PMD_1000BASESX 0x53 423#define SK_PMD_1000BASECX 0x43 424#define SK_PMD_1000BASETX 0x54 425 426/* GPIO bits */ 427#define SK_GPIO_DAT0 0x00000001 428#define SK_GPIO_DAT1 0x00000002 429#define SK_GPIO_DAT2 0x00000004 430#define SK_GPIO_DAT3 0x00000008 431#define SK_GPIO_DAT4 0x00000010 432#define SK_GPIO_DAT5 0x00000020 433#define SK_GPIO_DAT6 0x00000040 434#define SK_GPIO_DAT7 0x00000080 435#define SK_GPIO_DAT8 0x00000100 436#define SK_GPIO_DAT9 0x00000200 437#define SK_GPIO_DIR0 0x00010000 438#define SK_GPIO_DIR1 0x00020000 439#define SK_GPIO_DIR2 0x00040000 440#define SK_GPIO_DIR3 0x00080000 441#define SK_GPIO_DIR4 0x00100000 442#define SK_GPIO_DIR5 0x00200000 443#define SK_GPIO_DIR6 0x00400000 444#define SK_GPIO_DIR7 0x00800000 445#define SK_GPIO_DIR8 0x01000000 446#define SK_GPIO_DIR9 0x02000000 447 448/* Block 3 Ram interface and MAC arbiter registers */ 449#define SK_RAMADDR 0x0180 450#define SK_RAMDATA0 0x0184 451#define SK_RAMDATA1 0x0188 452#define SK_TO0 0x0190 453#define SK_TO1 0x0191 454#define SK_TO2 0x0192 455#define SK_TO3 0x0193 456#define SK_TO4 0x0194 457#define SK_TO5 0x0195 458#define SK_TO6 0x0196 459#define SK_TO7 0x0197 460#define SK_TO8 0x0198 461#define SK_TO9 0x0199 462#define SK_TO10 0x019A 463#define SK_TO11 0x019B 464#define SK_RITIMEO_TMR 0x019C 465#define SK_RAMCTL 0x01A0 466#define SK_RITIMER_TST 0x01A2 467 468#define SK_RAMCTL_RESET 0x0001 469#define SK_RAMCTL_UNRESET 0x0002 470#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 471#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 472 473/* Mac arbiter registers */ 474#define SK_MINIT_RX1 0x01B0 475#define SK_MINIT_RX2 0x01B1 476#define SK_MINIT_TX1 0x01B2 477#define SK_MINIT_TX2 0x01B3 478#define SK_MTIMEO_RX1 0x01B4 479#define SK_MTIMEO_RX2 0x01B5 480#define SK_MTIMEO_TX1 0x01B6 481#define SK_MTIEMO_TX2 0x01B7 482#define SK_MACARB_CTL 0x01B8 483#define SK_MTIMER_TST 0x01BA 484#define SK_RCINIT_RX1 0x01C0 485#define SK_RCINIT_RX2 0x01C1 486#define SK_RCINIT_TX1 0x01C2 487#define SK_RCINIT_TX2 0x01C3 488#define SK_RCTIMEO_RX1 0x01C4 489#define SK_RCTIMEO_RX2 0x01C5 490#define SK_RCTIMEO_TX1 0x01C6 491#define SK_RCTIMEO_TX2 0x01C7 492#define SK_RECOVERY_CTL 0x01C8 493#define SK_RCTIMER_TST 0x01CA 494 495/* Packet arbiter registers */ 496#define SK_RXPA1_TINIT 0x01D0 497#define SK_RXPA2_TINIT 0x01D4 498#define SK_TXPA1_TINIT 0x01D8 499#define SK_TXPA2_TINIT 0x01DC 500#define SK_RXPA1_TIMEO 0x01E0 501#define SK_RXPA2_TIMEO 0x01E4 502#define SK_TXPA1_TIMEO 0x01E8 503#define SK_TXPA2_TIMEO 0x01EC 504#define SK_PKTARB_CTL 0x01F0 505#define SK_PKTATB_TST 0x01F2 506 507#define SK_PKTARB_TIMEOUT 0x2000 508 509#define SK_PKTARBCTL_RESET 0x0001 510#define SK_PKTARBCTL_UNRESET 0x0002 511#define SK_PKTARBCTL_RXTO1_OFF 0x0004 512#define SK_PKTARBCTL_RXTO1_ON 0x0008 513#define SK_PKTARBCTL_RXTO2_OFF 0x0010 514#define SK_PKTARBCTL_RXTO2_ON 0x0020 515#define SK_PKTARBCTL_TXTO1_OFF 0x0040 516#define SK_PKTARBCTL_TXTO1_ON 0x0080 517#define SK_PKTARBCTL_TXTO2_OFF 0x0100 518#define SK_PKTARBCTL_TXTO2_ON 0x0200 519#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 520#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 521#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 522#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 523 524#define SK_MINIT_XMAC_B2 54 525#define SK_MINIT_XMAC_C1 63 526 527#define SK_MACARBCTL_RESET 0x0001 528#define SK_MACARBCTL_UNRESET 0x0002 529#define SK_MACARBCTL_FASTOE_OFF 0x0004 530#define SK_MACARBCRL_FASTOE_ON 0x0008 531 532#define SK_RCINIT_XMAC_B2 54 533#define SK_RCINIT_XMAC_C1 0 534 535#define SK_RECOVERYCTL_RX1_OFF 0x0001 536#define SK_RECOVERYCTL_RX1_ON 0x0002 537#define SK_RECOVERYCTL_RX2_OFF 0x0004 538#define SK_RECOVERYCTL_RX2_ON 0x0008 539#define SK_RECOVERYCTL_TX1_OFF 0x0010 540#define SK_RECOVERYCTL_TX1_ON 0x0020 541#define SK_RECOVERYCTL_TX2_OFF 0x0040 542#define SK_RECOVERYCTL_TX2_ON 0x0080 543 544#define SK_RECOVERY_XMAC_B2 \ 545 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 546 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 547 548#define SK_RECOVERY_XMAC_C1 \ 549 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 550 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 551 552/* Block 4 -- TX Arbiter MAC 1 */ 553#define SK_TXAR1_TIMERINIT 0x0200 554#define SK_TXAR1_TIMERVAL 0x0204 555#define SK_TXAR1_LIMITINIT 0x0208 556#define SK_TXAR1_LIMITCNT 0x020C 557#define SK_TXAR1_COUNTERCTL 0x0210 558#define SK_TXAR1_COUNTERTST 0x0212 559#define SK_TXAR1_COUNTERSTS 0x0212 560 561/* Block 5 -- TX Arbiter MAC 2 */ 562#define SK_TXAR2_TIMERINIT 0x0280 563#define SK_TXAR2_TIMERVAL 0x0284 564#define SK_TXAR2_LIMITINIT 0x0288 565#define SK_TXAR2_LIMITCNT 0x028C 566#define SK_TXAR2_COUNTERCTL 0x0290 567#define SK_TXAR2_COUNTERTST 0x0291 568#define SK_TXAR2_COUNTERSTS 0x0292 569 570#define SK_TXARCTL_OFF 0x01 571#define SK_TXARCTL_ON 0x02 572#define SK_TXARCTL_RATECTL_OFF 0x04 573#define SK_TXARCTL_RATECTL_ON 0x08 574#define SK_TXARCTL_ALLOC_OFF 0x10 575#define SK_TXARCTL_ALLOC_ON 0x20 576#define SK_TXARCTL_FSYNC_OFF 0x40 577#define SK_TXARCTL_FSYNC_ON 0x80 578 579/* Block 6 -- External registers */ 580#define SK_EXTREG_BASE 0x300 581#define SK_EXTREG_END 0x37C 582 583/* Block 7 -- PCI config registers */ 584#define SK_PCI_BASE 0x0380 585#define SK_PCI_END 0x03FC 586 587/* Compute offset of mirrored PCI register */ 588#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 589 590/* Block 8 -- RX queue 1 */ 591#define SK_RXQ1_BUFCNT 0x0400 592#define SK_RXQ1_BUFCTL 0x0402 593#define SK_RXQ1_NEXTDESC 0x0404 594#define SK_RXQ1_RXBUF_LO 0x0408 595#define SK_RXQ1_RXBUF_HI 0x040C 596#define SK_RXQ1_RXSTAT 0x0410 597#define SK_RXQ1_TIMESTAMP 0x0414 598#define SK_RXQ1_CSUM1 0x0418 599#define SK_RXQ1_CSUM2 0x041A 600#define SK_RXQ1_CSUM1_START 0x041C 601#define SK_RXQ1_CSUM2_START 0x041E 602#define SK_RXQ1_CURADDR_LO 0x0420 603#define SK_RXQ1_CURADDR_HI 0x0424 604#define SK_RXQ1_CURCNT_LO 0x0428 605#define SK_RXQ1_CURCNT_HI 0x042C 606#define SK_RXQ1_CURBYTES 0x0430 607#define SK_RXQ1_BMU_CSR 0x0434 608#define SK_RXQ1_WATERMARK 0x0438 609#define SK_RXQ1_FLAG 0x043A 610#define SK_RXQ1_TEST1 0x043C 611#define SK_RXQ1_TEST2 0x0440 612#define SK_RXQ1_TEST3 0x0444 613 614/* Block 9 -- RX queue 2 */ 615#define SK_RXQ2_BUFCNT 0x0480 616#define SK_RXQ2_BUFCTL 0x0482 617#define SK_RXQ2_NEXTDESC 0x0484 618#define SK_RXQ2_RXBUF_LO 0x0488 619#define SK_RXQ2_RXBUF_HI 0x048C 620#define SK_RXQ2_RXSTAT 0x0490 621#define SK_RXQ2_TIMESTAMP 0x0494 622#define SK_RXQ2_CSUM1 0x0498 623#define SK_RXQ2_CSUM2 0x049A 624#define SK_RXQ2_CSUM1_START 0x049C 625#define SK_RXQ2_CSUM2_START 0x049E 626#define SK_RXQ2_CURADDR_LO 0x04A0 627#define SK_RXQ2_CURADDR_HI 0x04A4 628#define SK_RXQ2_CURCNT_LO 0x04A8 629#define SK_RXQ2_CURCNT_HI 0x04AC 630#define SK_RXQ2_CURBYTES 0x04B0 631#define SK_RXQ2_BMU_CSR 0x04B4 632#define SK_RXQ2_WATERMARK 0x04B8 633#define SK_RXQ2_FLAG 0x04BA 634#define SK_RXQ2_TEST1 0x04BC 635#define SK_RXQ2_TEST2 0x04C0 636#define SK_RXQ2_TEST3 0x04C4 637 638#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 639#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 640#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 641#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 642#define SK_RXBMU_RX_START 0x00000010 643#define SK_RXBMU_RX_STOP 0x00000020 644#define SK_RXBMU_POLL_OFF 0x00000040 645#define SK_RXBMU_POLL_ON 0x00000080 646#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 647#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 648#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 649#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 650#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 651#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 652#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 653#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 654#define SK_RXBMU_PFI_SM_RESET 0x00010000 655#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 656#define SK_RXBMU_FIFO_RESET 0x00040000 657#define SK_RXBMU_FIFO_UNRESET 0x00080000 658#define SK_RXBMU_DESC_RESET 0x00100000 659#define SK_RXBMU_DESC_UNRESET 0x00200000 660#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 661 662#define SK_RXBMU_ONLINE \ 663 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 664 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 665 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 666 SK_RXBMU_DESC_UNRESET) 667 668#define SK_RXBMU_OFFLINE \ 669 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 670 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 671 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 672 SK_RXBMU_DESC_RESET) 673 674/* Block 12 -- TX sync queue 1 */ 675#define SK_TXQS1_BUFCNT 0x0600 676#define SK_TXQS1_BUFCTL 0x0602 677#define SK_TXQS1_NEXTDESC 0x0604 678#define SK_TXQS1_RXBUF_LO 0x0608 679#define SK_TXQS1_RXBUF_HI 0x060C 680#define SK_TXQS1_RXSTAT 0x0610 681#define SK_TXQS1_CSUM_STARTVAL 0x0614 682#define SK_TXQS1_CSUM_STARTPOS 0x0618 683#define SK_TXQS1_CSUM_WRITEPOS 0x061A 684#define SK_TXQS1_CURADDR_LO 0x0620 685#define SK_TXQS1_CURADDR_HI 0x0624 686#define SK_TXQS1_CURCNT_LO 0x0628 687#define SK_TXQS1_CURCNT_HI 0x062C 688#define SK_TXQS1_CURBYTES 0x0630 689#define SK_TXQS1_BMU_CSR 0x0634 690#define SK_TXQS1_WATERMARK 0x0638 691#define SK_TXQS1_FLAG 0x063A 692#define SK_TXQS1_TEST1 0x063C 693#define SK_TXQS1_TEST2 0x0640 694#define SK_TXQS1_TEST3 0x0644 695 696/* Block 13 -- TX async queue 1 */ 697#define SK_TXQA1_BUFCNT 0x0680 698#define SK_TXQA1_BUFCTL 0x0682 699#define SK_TXQA1_NEXTDESC 0x0684 700#define SK_TXQA1_RXBUF_LO 0x0688 701#define SK_TXQA1_RXBUF_HI 0x068C 702#define SK_TXQA1_RXSTAT 0x0690 703#define SK_TXQA1_CSUM_STARTVAL 0x0694 704#define SK_TXQA1_CSUM_STARTPOS 0x0698 705#define SK_TXQA1_CSUM_WRITEPOS 0x069A 706#define SK_TXQA1_CURADDR_LO 0x06A0 707#define SK_TXQA1_CURADDR_HI 0x06A4 708#define SK_TXQA1_CURCNT_LO 0x06A8 709#define SK_TXQA1_CURCNT_HI 0x06AC 710#define SK_TXQA1_CURBYTES 0x06B0 711#define SK_TXQA1_BMU_CSR 0x06B4 712#define SK_TXQA1_WATERMARK 0x06B8 713#define SK_TXQA1_FLAG 0x06BA 714#define SK_TXQA1_TEST1 0x06BC 715#define SK_TXQA1_TEST2 0x06C0 716#define SK_TXQA1_TEST3 0x06C4 717 718/* Block 14 -- TX sync queue 2 */ 719#define SK_TXQS2_BUFCNT 0x0700 720#define SK_TXQS2_BUFCTL 0x0702 721#define SK_TXQS2_NEXTDESC 0x0704 722#define SK_TXQS2_RXBUF_LO 0x0708 723#define SK_TXQS2_RXBUF_HI 0x070C 724#define SK_TXQS2_RXSTAT 0x0710 725#define SK_TXQS2_CSUM_STARTVAL 0x0714 726#define SK_TXQS2_CSUM_STARTPOS 0x0718 727#define SK_TXQS2_CSUM_WRITEPOS 0x071A 728#define SK_TXQS2_CURADDR_LO 0x0720 729#define SK_TXQS2_CURADDR_HI 0x0724 730#define SK_TXQS2_CURCNT_LO 0x0728 731#define SK_TXQS2_CURCNT_HI 0x072C 732#define SK_TXQS2_CURBYTES 0x0730 733#define SK_TXQS2_BMU_CSR 0x0734 734#define SK_TXQS2_WATERMARK 0x0738 735#define SK_TXQS2_FLAG 0x073A 736#define SK_TXQS2_TEST1 0x073C 737#define SK_TXQS2_TEST2 0x0740 738#define SK_TXQS2_TEST3 0x0744 739 740/* Block 15 -- TX async queue 2 */ 741#define SK_TXQA2_BUFCNT 0x0780 742#define SK_TXQA2_BUFCTL 0x0782 743#define SK_TXQA2_NEXTDESC 0x0784 744#define SK_TXQA2_RXBUF_LO 0x0788 745#define SK_TXQA2_RXBUF_HI 0x078C 746#define SK_TXQA2_RXSTAT 0x0790 747#define SK_TXQA2_CSUM_STARTVAL 0x0794 748#define SK_TXQA2_CSUM_STARTPOS 0x0798 749#define SK_TXQA2_CSUM_WRITEPOS 0x079A 750#define SK_TXQA2_CURADDR_LO 0x07A0 751#define SK_TXQA2_CURADDR_HI 0x07A4 752#define SK_TXQA2_CURCNT_LO 0x07A8 753#define SK_TXQA2_CURCNT_HI 0x07AC 754#define SK_TXQA2_CURBYTES 0x07B0 755#define SK_TXQA2_BMU_CSR 0x07B4 756#define SK_TXQA2_WATERMARK 0x07B8 757#define SK_TXQA2_FLAG 0x07BA 758#define SK_TXQA2_TEST1 0x07BC 759#define SK_TXQA2_TEST2 0x07C0 760#define SK_TXQA2_TEST3 0x07C4 761 762#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 763#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 764#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 765#define SK_TXBMU_TX_START 0x00000010 766#define SK_TXBMU_TX_STOP 0x00000020 767#define SK_TXBMU_POLL_OFF 0x00000040 768#define SK_TXBMU_POLL_ON 0x00000080 769#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 770#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 771#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 772#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 773#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 774#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 775#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 776#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 777#define SK_TXBMU_PFI_SM_RESET 0x00010000 778#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 779#define SK_TXBMU_FIFO_RESET 0x00040000 780#define SK_TXBMU_FIFO_UNRESET 0x00080000 781#define SK_TXBMU_DESC_RESET 0x00100000 782#define SK_TXBMU_DESC_UNRESET 0x00200000 783#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 784 785#define SK_TXBMU_ONLINE \ 786 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 787 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 788 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 789 SK_TXBMU_DESC_UNRESET) 790 791#define SK_TXBMU_OFFLINE \ 792 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 793 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 794 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 795 SK_TXBMU_DESC_RESET) 796 797/* Block 16 -- Receive RAMbuffer 1 */ 798#define SK_RXRB1_START 0x0800 799#define SK_RXRB1_END 0x0804 800#define SK_RXRB1_WR_PTR 0x0808 801#define SK_RXRB1_RD_PTR 0x080C 802#define SK_RXRB1_UTHR_PAUSE 0x0810 803#define SK_RXRB1_LTHR_PAUSE 0x0814 804#define SK_RXRB1_UTHR_HIPRIO 0x0818 805#define SK_RXRB1_UTHR_LOPRIO 0x081C 806#define SK_RXRB1_PKTCNT 0x0820 807#define SK_RXRB1_LVL 0x0824 808#define SK_RXRB1_CTLTST 0x0828 809 810/* Block 17 -- Receive RAMbuffer 2 */ 811#define SK_RXRB2_START 0x0880 812#define SK_RXRB2_END 0x0884 813#define SK_RXRB2_WR_PTR 0x0888 814#define SK_RXRB2_RD_PTR 0x088C 815#define SK_RXRB2_UTHR_PAUSE 0x0890 816#define SK_RXRB2_LTHR_PAUSE 0x0894 817#define SK_RXRB2_UTHR_HIPRIO 0x0898 818#define SK_RXRB2_UTHR_LOPRIO 0x089C 819#define SK_RXRB2_PKTCNT 0x08A0 820#define SK_RXRB2_LVL 0x08A4 821#define SK_RXRB2_CTLTST 0x08A8 822 823/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 824#define SK_TXRBS1_START 0x0A00 825#define SK_TXRBS1_END 0x0A04 826#define SK_TXRBS1_WR_PTR 0x0A08 827#define SK_TXRBS1_RD_PTR 0x0A0C 828#define SK_TXRBS1_PKTCNT 0x0A20 829#define SK_TXRBS1_LVL 0x0A24 830#define SK_TXRBS1_CTLTST 0x0A28 831 832/* Block 21 -- Async. Transmit RAMbuffer 1 */ 833#define SK_TXRBA1_START 0x0A80 834#define SK_TXRBA1_END 0x0A84 835#define SK_TXRBA1_WR_PTR 0x0A88 836#define SK_TXRBA1_RD_PTR 0x0A8C 837#define SK_TXRBA1_PKTCNT 0x0AA0 838#define SK_TXRBA1_LVL 0x0AA4 839#define SK_TXRBA1_CTLTST 0x0AA8 840 841/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 842#define SK_TXRBS2_START 0x0B00 843#define SK_TXRBS2_END 0x0B04 844#define SK_TXRBS2_WR_PTR 0x0B08 845#define SK_TXRBS2_RD_PTR 0x0B0C 846#define SK_TXRBS2_PKTCNT 0x0B20 847#define SK_TXRBS2_LVL 0x0B24 848#define SK_TXRBS2_CTLTST 0x0B28 849 850/* Block 23 -- Async. Transmit RAMbuffer 2 */ 851#define SK_TXRBA2_START 0x0B80 852#define SK_TXRBA2_END 0x0B84 853#define SK_TXRBA2_WR_PTR 0x0B88 854#define SK_TXRBA2_RD_PTR 0x0B8C 855#define SK_TXRBA2_PKTCNT 0x0BA0 856#define SK_TXRBA2_LVL 0x0BA4 857#define SK_TXRBA2_CTLTST 0x0BA8 858 859#define SK_RBCTL_RESET 0x00000001 860#define SK_RBCTL_UNRESET 0x00000002 861#define SK_RBCTL_OFF 0x00000004 862#define SK_RBCTL_ON 0x00000008 863#define SK_RBCTL_STORENFWD_OFF 0x00000010 864#define SK_RBCTL_STORENFWD_ON 0x00000020 865 866/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 867#define SK_RXF1_END 0x0C00 868#define SK_RXF1_WPTR 0x0C04 869#define SK_RXF1_RPTR 0x0C0C 870#define SK_RXF1_PKTCNT 0x0C10 871#define SK_RXF1_LVL 0x0C14 872#define SK_RXF1_MACCTL 0x0C18 873#define SK_RXF1_CTL 0x0C1C 874#define SK_RXLED1_CNTINIT 0x0C20 875#define SK_RXLED1_COUNTER 0x0C24 876#define SK_RXLED1_CTL 0x0C28 877#define SK_RXLED1_TST 0x0C29 878#define SK_LINK_SYNC1_CINIT 0x0C30 879#define SK_LINK_SYNC1_COUNTER 0x0C34 880#define SK_LINK_SYNC1_CTL 0x0C38 881#define SK_LINK_SYNC1_TST 0x0C39 882#define SK_LINKLED1_CTL 0x0C3C 883 884#define SK_FIFO_END 0x3F 885 886/* Receive MAC FIFO 1 (Yukon Only) */ 887#define SK_RXMF1_END 0x0C40 888#define SK_RXMF1_THRESHOLD 0x0C44 889#define SK_RXMF1_CTRL_TEST 0x0C48 890#define SK_RXMF1_WRITE_PTR 0x0C60 891#define SK_RXMF1_WRITE_LEVEL 0x0C68 892#define SK_RXMF1_READ_PTR 0x0C70 893#define SK_RXMF1_READ_LEVEL 0x0C78 894 895#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 896#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 897#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 898#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 899#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 900#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 901#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 902#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 903#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 904#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 905#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 906#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 907 908/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 909#define SK_RXF2_END 0x0C80 910#define SK_RXF2_WPTR 0x0C84 911#define SK_RXF2_RPTR 0x0C8C 912#define SK_RXF2_PKTCNT 0x0C90 913#define SK_RXF2_LVL 0x0C94 914#define SK_RXF2_MACCTL 0x0C98 915#define SK_RXF2_CTL 0x0C9C 916#define SK_RXLED2_CNTINIT 0x0CA0 917#define SK_RXLED2_COUNTER 0x0CA4 918#define SK_RXLED2_CTL 0x0CA8 919#define SK_RXLED2_TST 0x0CA9 920#define SK_LINK_SYNC2_CINIT 0x0CB0 921#define SK_LINK_SYNC2_COUNTER 0x0CB4 922#define SK_LINK_SYNC2_CTL 0x0CB8 923#define SK_LINK_SYNC2_TST 0x0CB9 924#define SK_LINKLED2_CTL 0x0CBC 925 926#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 927#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 928#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 929#define SK_RXMACCTL_RSTAMP_ON 0x00000008 930#define SK_RXMACCTL_FLUSH_OFF 0x00000010 931#define SK_RXMACCTL_FLUSH_ON 0x00000020 932#define SK_RXMACCTL_PAUSE_OFF 0x00000040 933#define SK_RXMACCTL_PAUSE_ON 0x00000080 934#define SK_RXMACCTL_AFULL_OFF 0x00000100 935#define SK_RXMACCTL_AFULL_ON 0x00000200 936#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 937#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 938#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 939#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 940#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 941#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 942 943#define SK_RXLEDCTL_ENABLE 0x0001 944#define SK_RXLEDCTL_COUNTER_STOP 0x0002 945#define SK_RXLEDCTL_COUNTER_START 0x0004 946 947#define SK_LINKLED_OFF 0x0001 948#define SK_LINKLED_ON 0x0002 949#define SK_LINKLED_LINKSYNC_OFF 0x0004 950#define SK_LINKLED_LINKSYNC_ON 0x0008 951#define SK_LINKLED_BLINK_OFF 0x0010 952#define SK_LINKLED_BLINK_ON 0x0020 953 954/* Block 26 -- TX MAC FIFO 1 regisrers */ 955#define SK_TXF1_END 0x0D00 956#define SK_TXF1_WPTR 0x0D04 957#define SK_TXF1_RPTR 0x0D0C 958#define SK_TXF1_PKTCNT 0x0D10 959#define SK_TXF1_LVL 0x0D14 960#define SK_TXF1_MACCTL 0x0D18 961#define SK_TXF1_CTL 0x0D1C 962#define SK_TXLED1_CNTINIT 0x0D20 963#define SK_TXLED1_COUNTER 0x0D24 964#define SK_TXLED1_CTL 0x0D28 965#define SK_TXLED1_TST 0x0D29 966 967/* Receive MAC FIFO 1 (Yukon Only) */ 968#define SK_TXMF1_END 0x0D40 969#define SK_TXMF1_THRESHOLD 0x0D44 970#define SK_TXMF1_CTRL_TEST 0x0D48 971#define SK_TXMF1_WRITE_PTR 0x0D60 972#define SK_TXMF1_WRITE_SHADOW 0x0D64 973#define SK_TXMF1_WRITE_LEVEL 0x0D68 974#define SK_TXMF1_READ_PTR 0x0D70 975#define SK_TXMF1_RESTART_PTR 0x0D74 976#define SK_TXMF1_READ_LEVEL 0x0D78 977 978#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 979#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 980#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 981#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 982#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 983#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 984#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 985#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 986#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 987#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 988#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 989#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 990#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 991 992/* Block 27 -- TX MAC FIFO 2 regisrers */ 993#define SK_TXF2_END 0x0D80 994#define SK_TXF2_WPTR 0x0D84 995#define SK_TXF2_RPTR 0x0D8C 996#define SK_TXF2_PKTCNT 0x0D90 997#define SK_TXF2_LVL 0x0D94 998#define SK_TXF2_MACCTL 0x0D98 999#define SK_TXF2_CTL 0x0D9C 1000#define SK_TXLED2_CNTINIT 0x0DA0 1001#define SK_TXLED2_COUNTER 0x0DA4 1002#define SK_TXLED2_CTL 0x0DA8 1003#define SK_TXLED2_TST 0x0DA9 1004 1005#define SK_TXMACCTL_XMAC_RESET 0x00000001 1006#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1007#define SK_TXMACCTL_LOOP_OFF 0x00000004 1008#define SK_TXMACCTL_LOOP_ON 0x00000008 1009#define SK_TXMACCTL_FLUSH_OFF 0x00000010 1010#define SK_TXMACCTL_FLUSH_ON 0x00000020 1011#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1012#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1013#define SK_TXMACCTL_AFULL_OFF 0x00000100 1014#define SK_TXMACCTL_AFULL_ON 0x00000200 1015#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1016#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1017#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1018#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1019#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1020#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1021 1022#define SK_TXLEDCTL_ENABLE 0x0001 1023#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1024#define SK_TXLEDCTL_COUNTER_START 0x0004 1025 1026#define SK_FIFO_RESET 0x00000001 1027#define SK_FIFO_UNRESET 0x00000002 1028#define SK_FIFO_OFF 0x00000004 1029#define SK_FIFO_ON 0x00000008 1030 1031/* Block 28 -- Descriptor Poll Timer */ 1032#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1033#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1034 1035#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1036#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1037#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1038 1039#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1040#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1041#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1042#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1043 1044/* Block 29 -- reserved */ 1045 1046/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1047#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1048#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1049#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1050#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1051#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1052#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1053#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1054#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1055#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1056#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1057#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1058#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1059#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1060#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1061#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1062#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1063#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1064#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1065#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1066#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1067#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1068#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1069#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1070#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1071#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1072#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1073#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1074#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1075#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1076 1077#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1078#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1079#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1080#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1081#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1082#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1083 1084#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1085#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1086#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1087#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1088#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1089#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1090#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1091#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1092#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1093#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1094#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1095#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1096#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1097#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1098#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1099#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1100#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1101#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1102#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1103#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1104#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1105#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1106#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1107 1108#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1109 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1110#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1111 SK_GPHY_HWCFG_M_2 ) 1112#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1113 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1114 1115#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1116#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1117#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1118#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1119#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1120#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1121 1122#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1123#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1124 1125/* Block 31 -- reserved */ 1126 1127/* Block 32-33 -- Pattern Ram */ 1128#define SK_WOL_PRAM 0x1000 1129 1130/* Block 0x22 - 0x3f -- reserved */ 1131 1132/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1133#define SK_XMAC1_BASE 0x2000 1134 1135/* Block 0x50 to 0x5F -- MARV 1 registers */ 1136#define SK_MARV1_BASE 0x2800 1137 1138/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1139#define SK_XMAC2_BASE 0x3000 1140 1141/* Block 0x70 to 0x7F -- MARV 2 registers */ 1142#define SK_MARV2_BASE 0x3800 1143 1144/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1145#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1146 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1147 1148#if 0 1149#define SK_XM_READ_4(sc, reg) \ 1150 ((sk_win_read_2(sc->sk_softc, \ 1151 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1152 ((sk_win_read_2(sc->sk_softc, \ 1153 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1154 1155#define SK_XM_WRITE_4(sc, reg, val) \ 1156 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1157 ((val) & 0xFFFF)); \ 1158 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1159 ((val) >> 16) & 0xFFFF) 1160#else 1161#define SK_XM_READ_4(sc, reg) \ 1162 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1163 1164#define SK_XM_WRITE_4(sc, reg, val) \ 1165 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1166#endif 1167 1168#define SK_XM_READ_2(sc, reg) \ 1169 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1170 1171#define SK_XM_WRITE_2(sc, reg, val) \ 1172 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1173 1174#define SK_XM_SETBIT_4(sc, reg, x) \ 1175 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1176 1177#define SK_XM_CLRBIT_4(sc, reg, x) \ 1178 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1179 1180#define SK_XM_SETBIT_2(sc, reg, x) \ 1181 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1182 1183#define SK_XM_CLRBIT_2(sc, reg, x) \ 1184 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1185 1186/* Compute relative offset of an MARV register in the MARV window(s). */ 1187#define SK_YU_REG(sc, reg) \ 1188 ((reg) + SK_MARV1_BASE + \ 1189 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1190 1191#define SK_YU_READ_4(sc, reg) \ 1192 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1193 1194#define SK_YU_READ_2(sc, reg) \ 1195 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1196 1197#define SK_YU_WRITE_4(sc, reg, val) \ 1198 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1199 1200#define SK_YU_WRITE_2(sc, reg, val) \ 1201 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1202 1203#define SK_YU_SETBIT_4(sc, reg, x) \ 1204 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1205 1206#define SK_YU_CLRBIT_4(sc, reg, x) \ 1207 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1208 1209#define SK_YU_SETBIT_2(sc, reg, x) \ 1210 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1211 1212#define SK_YU_CLRBIT_2(sc, reg, x) \ 1213 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1214 1215/* 1216 * The default FIFO threshold on the XMAC II is 4 bytes. On 1217 * dual port NICs, this often leads to transmit underruns, so we 1218 * bump the threshold a little. 1219 */ 1220#define SK_XM_TX_FIFOTHRESH 512 1221 1222#define SK_PCI_VENDOR_ID 0x0000 1223#define SK_PCI_DEVICE_ID 0x0002 1224#define SK_PCI_COMMAND 0x0004 1225#define SK_PCI_STATUS 0x0006 1226#define SK_PCI_REVID 0x0008 1227#define SK_PCI_CLASSCODE 0x0009 1228#define SK_PCI_CACHELEN 0x000C 1229#define SK_PCI_LATENCY_TIMER 0x000D 1230#define SK_PCI_HEADER_TYPE 0x000E 1231#define SK_PCI_LOMEM 0x0010 1232#define SK_PCI_LOIO 0x0014 1233#define SK_PCI_SUBVEN_ID 0x002C 1234#define SK_PCI_SYBSYS_ID 0x002E 1235#define SK_PCI_BIOSROM 0x0030 1236#define SK_PCI_INTLINE 0x003C 1237#define SK_PCI_INTPIN 0x003D 1238#define SK_PCI_MINGNT 0x003E 1239#define SK_PCI_MINLAT 0x003F 1240 1241/* device specific PCI registers */ 1242#define SK_PCI_OURREG1 0x0040 1243#define SK_PCI_OURREG2 0x0044 1244#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1245#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1246#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1247#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1248#define SK_PCI_PME_EVENT 0x004F 1249#define SK_PCI_VPD_CAPID 0x0050 1250#define SK_PCI_VPD_NEXTPTR 0x0051 1251#define SK_PCI_VPD_ADDR 0x0052 1252#define SK_PCI_VPD_DATA 0x0054 1253 1254#define SK_PSTATE_MASK 0x0003 1255#define SK_PSTATE_D0 0x0000 1256#define SK_PSTATE_D1 0x0001 1257#define SK_PSTATE_D2 0x0002 1258#define SK_PSTATE_D3 0x0003 1259#define SK_PME_EN 0x0010 1260#define SK_PME_STATUS 0x8000 1261 1262/* 1263 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1264 * read is complete. Set to 1 to initiate a write, will become 0 1265 * when write is finished. 1266 */ 1267#define SK_VPD_FLAG 0x8000 1268 1269/* VPD structures */ 1270struct vpd_res { 1271 u_int8_t vr_id; 1272 u_int8_t vr_len; 1273 u_int8_t vr_pad; 1274}; 1275 1276struct vpd_key { 1277 char vk_key[2]; 1278 u_int8_t vk_len; 1279}; 1280 1281#define VPD_RES_ID 0x82 /* ID string */ 1282#define VPD_RES_READ 0x90 /* start of read only area */ 1283#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1284#define VPD_RES_END 0x78 /* end tag */ 1285 1286#define CSR_WRITE_4(sc, reg, val) \ 1287 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1288#define CSR_WRITE_2(sc, reg, val) \ 1289 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1290#define CSR_WRITE_1(sc, reg, val) \ 1291 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1292 1293#define CSR_READ_4(sc, reg) \ 1294 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1295#define CSR_READ_2(sc, reg) \ 1296 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1297#define CSR_READ_1(sc, reg) \ 1298 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1299 1300struct sk_type { 1301 u_int16_t sk_vid; 1302 u_int16_t sk_did; 1303 char *sk_name; 1304}; 1305 1306/* RX queue descriptor data structure */ 1307struct sk_rx_desc { 1308 u_int32_t sk_ctl; 1309 u_int32_t sk_next; 1310 u_int32_t sk_data_lo; 1311 u_int32_t sk_data_hi; 1312 u_int32_t sk_xmac_rxstat; 1313 u_int32_t sk_timestamp; 1314 u_int16_t sk_csum2; 1315 u_int16_t sk_csum1; 1316 u_int16_t sk_csum2_start; 1317 u_int16_t sk_csum1_start; 1318}; 1319 1320#define SK_OPCODE_DEFAULT 0x00550000 1321#define SK_OPCODE_CSUM 0x00560000 1322 1323#define SK_RXCTL_LEN 0x0000FFFF 1324#define SK_RXCTL_OPCODE 0x00FF0000 1325#define SK_RXCTL_TSTAMP_VALID 0x01000000 1326#define SK_RXCTL_STATUS_VALID 0x02000000 1327#define SK_RXCTL_DEV0 0x04000000 1328#define SK_RXCTL_EOF_INTR 0x08000000 1329#define SK_RXCTL_EOB_INTR 0x10000000 1330#define SK_RXCTL_LASTFRAG 0x20000000 1331#define SK_RXCTL_FIRSTFRAG 0x40000000 1332#define SK_RXCTL_OWN 0x80000000 1333 1334#define SK_RXSTAT \ 1335 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1336 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1337 1338struct sk_tx_desc { 1339 u_int32_t sk_ctl; 1340 u_int32_t sk_next; 1341 u_int32_t sk_data_lo; 1342 u_int32_t sk_data_hi; 1343 u_int32_t sk_xmac_txstat; 1344 u_int16_t sk_rsvd0; 1345 u_int16_t sk_csum_startval; 1346 u_int16_t sk_csum_startpos; 1347 u_int16_t sk_csum_writepos; 1348 u_int32_t sk_rsvd1; 1349}; 1350 1351#define SK_TXCTL_LEN 0x0000FFFF 1352#define SK_TXCTL_OPCODE 0x00FF0000 1353#define SK_TXCTL_SW 0x01000000 1354#define SK_TXCTL_NOCRC 0x02000000 1355#define SK_TXCTL_STORENFWD 0x04000000 1356#define SK_TXCTL_EOF_INTR 0x08000000 1357#define SK_TXCTL_EOB_INTR 0x10000000 1358#define SK_TXCTL_LASTFRAG 0x20000000 1359#define SK_TXCTL_FIRSTFRAG 0x40000000 1360#define SK_TXCTL_OWN 0x80000000 1361 1362#define SK_TXSTAT \ 1363 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1364 1365#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1366#define SK_TXBYTES SK_RXBYTES 1367 1368#define SK_TX_RING_CNT 512 1369#define SK_RX_RING_CNT 256 1370 1371/* 1372 * Jumbo buffer stuff. Note that we must allocate more jumbo 1373 * buffers than there are descriptors in the receive ring. This 1374 * is because we don't know how long it will take for a packet 1375 * to be released after we hand it off to the upper protocol 1376 * layers. To be safe, we allocate 1.5 times the number of 1377 * receive descriptors. 1378 */ 1379#define SK_JUMBO_FRAMELEN 9018 1380#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1381#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2) 1382 1383#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1384#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1385 (SK_JRAWLEN % sizeof(u_int64_t)))) 1386#define SK_JPAGESZ PAGE_SIZE 1387#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1388#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1389 1390struct sk_jpool_entry { 1391 int slot; 1392 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1393}; 1394 1395struct sk_chain { 1396 void *sk_desc; 1397 struct mbuf *sk_mbuf; 1398 struct sk_chain *sk_next; 1399}; 1400 1401struct sk_chain_data { 1402 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1403 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1404 int sk_tx_prod; 1405 int sk_tx_cons; 1406 int sk_tx_cnt; 1407 int sk_rx_prod; 1408 int sk_rx_cons; 1409 int sk_rx_cnt; 1410 /* Stick the jumbo mem management stuff here too. */ 1411 caddr_t sk_jslots[SK_JSLOTS]; 1412 void *sk_jumbo_buf; 1413 1414}; 1415 1416struct sk_ring_data { 1417 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1418 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1419}; 1420 1421struct sk_bcom_hack { 1422 int reg; 1423 int val; 1424}; 1425 1426#define SK_INC(x, y) (x) = (x + 1) % y 1427 1428/* Forward decl. */ 1429struct sk_if_softc; 1430 1431/* Softc for the GEnesis controller. */ 1432struct sk_softc { 1433 bus_space_handle_t sk_bhandle; /* bus space handle */ 1434 bus_space_tag_t sk_btag; /* bus space tag */ 1435 void *sk_intrhand; /* irq handler handle */ 1436 struct resource *sk_irq; /* IRQ resource handle */ 1437 struct resource *sk_res; /* I/O or shared mem handle */ 1438 u_int8_t sk_unit; /* controller number */ 1439 u_int8_t sk_type; 1440 u_int8_t sk_rev; 1441 u_int8_t spare; 1442 char *sk_vpd_prodname; 1443 char *sk_vpd_readonly; 1444 uint16_t sk_vpd_readonly_len; 1445 u_int32_t sk_rboff; /* RAMbuffer offset */ 1446 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1447 u_int32_t sk_pmd; /* physical media type */ 1448 u_int32_t sk_intrmask; 1449 int sk_int_mod; 1450 struct sk_if_softc *sk_if[2]; 1451 device_t sk_devs[2]; 1452 struct mtx sk_mtx; 1453}; 1454 1455#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1456#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1457#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1458#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1459#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1460#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1461 1462/* Softc for each logical interface */ 1463struct sk_if_softc { 1464 struct ifnet *sk_ifp; /* interface info */ 1465 device_t sk_miibus; 1466 u_int8_t sk_unit; /* interface number */ 1467 u_int8_t sk_port; /* port # on controller */ 1468 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1469 u_int32_t sk_rx_ramstart; 1470 u_int32_t sk_rx_ramend; 1471 u_int32_t sk_tx_ramstart; 1472 u_int32_t sk_tx_ramend; 1473 int sk_phytype; 1474 int sk_phyaddr; 1475 device_t sk_dev; 1476 int sk_cnt; 1477 int sk_link; 1478 struct callout_handle sk_tick_ch; 1479 struct sk_chain_data sk_cdata; 1480 struct sk_ring_data *sk_rdata; 1481 struct sk_softc *sk_softc; /* parent controller */ 1482 int sk_tx_bmu; /* TX BMU register */ 1483 int sk_if_flags; 1484 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1485 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1486 struct mtx sk_jlist_mtx; 1487}; 1488 1489#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx) 1490#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx) 1491 1492#define SK_MAXUNIT 256 1493#define SK_TIMEOUT 1000 1494#define ETHER_ALIGN 2 1495 1496#ifdef __alpha__ 1497#undef vtophys 1498#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1499#endif 1500