if_skreg.h revision 134072
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 134072 2004-08-20 06:22:04Z jmg $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart */ 54#define SK_GENESIS 0 55#define SK_YUKON 1 56 57/* 58 * SysKonnect PCI vendor ID 59 */ 60#define VENDORID_SK 0x1148 61 62/* 63 * Marvell PCI vendor ID 64 */ 65#define VENDORID_MARVELL 0x11AB 66 67/* 68 * SK-NET gigabit ethernet device IDs 69 */ 70#define DEVICEID_SK_V1 0x4300 71#define DEVICEID_SK_V2 0x4320 72 73/* 74 * Belkin F5D5005 75 */ 76#define DEVICEID_BELKIN_5005 0x5005 77 78/* 79 * 3Com PCI vendor ID 80 */ 81#define VENDORID_3COM 0x10b7 82 83/* 84 * 3Com gigabit ethernet device ID 85 */ 86#define DEVICEID_3COM_3C940 0x1700 87 88/* 89 * Linksys PCI vendor ID 90 */ 91#define VENDORID_LINKSYS 0x1737 92 93/* 94 * Linksys gigabit ethernet device ID 95 */ 96#define DEVICEID_LINKSYS_EG1032 0x1032 97 98/* 99 * D-Link PCI vendor ID 100 */ 101#define VENDORID_DLINK 0x1186 102 103/* 104 * D-Link gigabit ethernet device ID 105 */ 106#define DEVICEID_DLINK_DGE530T 0x4c00 107 108/* 109 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 110 * but internally it has a 16K register space. This 16K space is 111 * divided into 128-byte blocks. The first 128 bytes of the I/O 112 * window represent the first block, which is permanently mapped 113 * at the start of the window. The other 127 blocks can be mapped 114 * to the second 128 bytes of the I/O window by setting the desired 115 * block value in the RAP register in block 0. Not all of the 127 116 * blocks are actually used. Most registers are 32 bits wide, but 117 * there are a few 16-bit and 8-bit ones as well. 118 */ 119 120 121/* Start of remappable register window. */ 122#define SK_WIN_BASE 0x0080 123 124/* Size of a window */ 125#define SK_WIN_LEN 0x80 126 127#define SK_WIN_MASK 0x3F80 128#define SK_REG_MASK 0x7F 129 130/* Compute the window of a given register (for the RAP register) */ 131#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 132 133/* Compute the relative offset of a register within the window */ 134#define SK_REG(reg) ((reg) & SK_REG_MASK) 135 136#define SK_PORT_A 0 137#define SK_PORT_B 1 138 139/* 140 * Compute offset of port-specific register. Since there are two 141 * ports, there are two of some GEnesis modules (e.g. two sets of 142 * DMA queues, two sets of FIFO control registers, etc...). Normally, 143 * the block for port 0 is at offset 0x0 and the block for port 1 is 144 * at offset 0x80 (i.e. the next page over). However for the transmit 145 * BMUs and RAMbuffers, there are two blocks for each port: one for 146 * the sync transmit queue and one for the async queue (which we don't 147 * use). However instead of ordering them like this: 148 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 149 * SysKonnect has instead ordered them like this: 150 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 151 * This means that when referencing the TX BMU and RAMbuffer registers, 152 * we have to double the block offset (0x80 * 2) in order to reach the 153 * second queue. This prevents us from using the same formula 154 * (sk_port * 0x80) to compute the offsets for all of the port-specific 155 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 156 * The simplest thing is to provide an extra argument to these macros: 157 * the 'skip' parameter. The 'skip' value is the number of extra pages 158 * for skip when computing the port0/port1 offsets. For most registers, 159 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 160 */ 161#define SK_IF_READ_4(sc_if, skip, reg) \ 162 sk_win_read_4(sc_if->sk_softc, reg + \ 163 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 164#define SK_IF_READ_2(sc_if, skip, reg) \ 165 sk_win_read_2(sc_if->sk_softc, reg + \ 166 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 167#define SK_IF_READ_1(sc_if, skip, reg) \ 168 sk_win_read_1(sc_if->sk_softc, reg + \ 169 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 170 171#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 172 sk_win_write_4(sc_if->sk_softc, \ 173 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 174#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 175 sk_win_write_2(sc_if->sk_softc, \ 176 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 177#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 178 sk_win_write_1(sc_if->sk_softc, \ 179 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 180 181/* Block 0 registers, permanently mapped at iobase. */ 182#define SK_RAP 0x0000 183#define SK_CSR 0x0004 184#define SK_LED 0x0006 185#define SK_ISR 0x0008 /* interrupt source */ 186#define SK_IMR 0x000C /* interrupt mask */ 187#define SK_IESR 0x0010 /* interrupt hardware error source */ 188#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 189#define SK_ISSR 0x0018 /* special interrupt source */ 190#define SK_XM_IMR0 0x0020 191#define SK_XM_ISR0 0x0028 192#define SK_XM_PHYADDR0 0x0030 193#define SK_XM_PHYDATA0 0x0034 194#define SK_XM_IMR1 0x0040 195#define SK_XM_ISR1 0x0048 196#define SK_XM_PHYADDR1 0x0050 197#define SK_XM_PHYDATA1 0x0054 198#define SK_BMU_RX_CSR0 0x0060 199#define SK_BMU_RX_CSR1 0x0064 200#define SK_BMU_TXS_CSR0 0x0068 201#define SK_BMU_TXA_CSR0 0x006C 202#define SK_BMU_TXS_CSR1 0x0070 203#define SK_BMU_TXA_CSR1 0x0074 204 205/* SK_CSR register */ 206#define SK_CSR_SW_RESET 0x0001 207#define SK_CSR_SW_UNRESET 0x0002 208#define SK_CSR_MASTER_RESET 0x0004 209#define SK_CSR_MASTER_UNRESET 0x0008 210#define SK_CSR_MASTER_STOP 0x0010 211#define SK_CSR_MASTER_DONE 0x0020 212#define SK_CSR_SW_IRQ_CLEAR 0x0040 213#define SK_CSR_SW_IRQ_SET 0x0080 214#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 215#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 216 217/* SK_LED register */ 218#define SK_LED_GREEN_OFF 0x01 219#define SK_LED_GREEN_ON 0x02 220 221/* SK_ISR register */ 222#define SK_ISR_TX2_AS_CHECK 0x00000001 223#define SK_ISR_TX2_AS_EOF 0x00000002 224#define SK_ISR_TX2_AS_EOB 0x00000004 225#define SK_ISR_TX2_S_CHECK 0x00000008 226#define SK_ISR_TX2_S_EOF 0x00000010 227#define SK_ISR_TX2_S_EOB 0x00000020 228#define SK_ISR_TX1_AS_CHECK 0x00000040 229#define SK_ISR_TX1_AS_EOF 0x00000080 230#define SK_ISR_TX1_AS_EOB 0x00000100 231#define SK_ISR_TX1_S_CHECK 0x00000200 232#define SK_ISR_TX1_S_EOF 0x00000400 233#define SK_ISR_TX1_S_EOB 0x00000800 234#define SK_ISR_RX2_CHECK 0x00001000 235#define SK_ISR_RX2_EOF 0x00002000 236#define SK_ISR_RX2_EOB 0x00004000 237#define SK_ISR_RX1_CHECK 0x00008000 238#define SK_ISR_RX1_EOF 0x00010000 239#define SK_ISR_RX1_EOB 0x00020000 240#define SK_ISR_LINK2_OFLOW 0x00040000 241#define SK_ISR_MAC2 0x00080000 242#define SK_ISR_LINK1_OFLOW 0x00100000 243#define SK_ISR_MAC1 0x00200000 244#define SK_ISR_TIMER 0x00400000 245#define SK_ISR_EXTERNAL_REG 0x00800000 246#define SK_ISR_SW 0x01000000 247#define SK_ISR_I2C_RDY 0x02000000 248#define SK_ISR_TX2_TIMEO 0x04000000 249#define SK_ISR_TX1_TIMEO 0x08000000 250#define SK_ISR_RX2_TIMEO 0x10000000 251#define SK_ISR_RX1_TIMEO 0x20000000 252#define SK_ISR_RSVD 0x40000000 253#define SK_ISR_HWERR 0x80000000 254 255/* SK_IMR register */ 256#define SK_IMR_TX2_AS_CHECK 0x00000001 257#define SK_IMR_TX2_AS_EOF 0x00000002 258#define SK_IMR_TX2_AS_EOB 0x00000004 259#define SK_IMR_TX2_S_CHECK 0x00000008 260#define SK_IMR_TX2_S_EOF 0x00000010 261#define SK_IMR_TX2_S_EOB 0x00000020 262#define SK_IMR_TX1_AS_CHECK 0x00000040 263#define SK_IMR_TX1_AS_EOF 0x00000080 264#define SK_IMR_TX1_AS_EOB 0x00000100 265#define SK_IMR_TX1_S_CHECK 0x00000200 266#define SK_IMR_TX1_S_EOF 0x00000400 267#define SK_IMR_TX1_S_EOB 0x00000800 268#define SK_IMR_RX2_CHECK 0x00001000 269#define SK_IMR_RX2_EOF 0x00002000 270#define SK_IMR_RX2_EOB 0x00004000 271#define SK_IMR_RX1_CHECK 0x00008000 272#define SK_IMR_RX1_EOF 0x00010000 273#define SK_IMR_RX1_EOB 0x00020000 274#define SK_IMR_LINK2_OFLOW 0x00040000 275#define SK_IMR_MAC2 0x00080000 276#define SK_IMR_LINK1_OFLOW 0x00100000 277#define SK_IMR_MAC1 0x00200000 278#define SK_IMR_TIMER 0x00400000 279#define SK_IMR_EXTERNAL_REG 0x00800000 280#define SK_IMR_SW 0x01000000 281#define SK_IMR_I2C_RDY 0x02000000 282#define SK_IMR_TX2_TIMEO 0x04000000 283#define SK_IMR_TX1_TIMEO 0x08000000 284#define SK_IMR_RX2_TIMEO 0x10000000 285#define SK_IMR_RX1_TIMEO 0x20000000 286#define SK_IMR_RSVD 0x40000000 287#define SK_IMR_HWERR 0x80000000 288 289#define SK_INTRS1 \ 290 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 291 292#define SK_INTRS2 \ 293 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 294 295/* SK_IESR register */ 296#define SK_IESR_PAR_RX2 0x00000001 297#define SK_IESR_PAR_RX1 0x00000002 298#define SK_IESR_PAR_MAC2 0x00000004 299#define SK_IESR_PAR_MAC1 0x00000008 300#define SK_IESR_PAR_WR_RAM 0x00000010 301#define SK_IESR_PAR_RD_RAM 0x00000020 302#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 303#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 304#define SK_IESR_NO_STS_MAC2 0x00000100 305#define SK_IESR_NO_STS_MAC1 0x00000200 306#define SK_IESR_IRQ_STS 0x00000400 307#define SK_IESR_MASTERERR 0x00000800 308 309/* SK_IEMR register */ 310#define SK_IEMR_PAR_RX2 0x00000001 311#define SK_IEMR_PAR_RX1 0x00000002 312#define SK_IEMR_PAR_MAC2 0x00000004 313#define SK_IEMR_PAR_MAC1 0x00000008 314#define SK_IEMR_PAR_WR_RAM 0x00000010 315#define SK_IEMR_PAR_RD_RAM 0x00000020 316#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 317#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 318#define SK_IEMR_NO_STS_MAC2 0x00000100 319#define SK_IEMR_NO_STS_MAC1 0x00000200 320#define SK_IEMR_IRQ_STS 0x00000400 321#define SK_IEMR_MASTERERR 0x00000800 322 323/* Block 2 */ 324#define SK_MAC0_0 0x0100 325#define SK_MAC0_1 0x0104 326#define SK_MAC1_0 0x0108 327#define SK_MAC1_1 0x010C 328#define SK_MAC2_0 0x0110 329#define SK_MAC2_1 0x0114 330#define SK_CONNTYPE 0x0118 331#define SK_PMDTYPE 0x0119 332#define SK_CONFIG 0x011A 333#define SK_CHIPVER 0x011B 334#define SK_EPROM0 0x011C 335#define SK_EPROM1 0x011D 336#define SK_EPROM2 0x011E 337#define SK_EPROM3 0x011F 338#define SK_EP_ADDR 0x0120 339#define SK_EP_DATA 0x0124 340#define SK_EP_LOADCTL 0x0128 341#define SK_EP_LOADTST 0x0129 342#define SK_TIMERINIT 0x0130 343#define SK_TIMER 0x0134 344#define SK_TIMERCTL 0x0138 345#define SK_TIMERTST 0x0139 346#define SK_IMTIMERINIT 0x0140 347#define SK_IMTIMER 0x0144 348#define SK_IMTIMERCTL 0x0148 349#define SK_IMTIMERTST 0x0149 350#define SK_IMMR 0x014C 351#define SK_IHWEMR 0x0150 352#define SK_TESTCTL1 0x0158 353#define SK_TESTCTL2 0x0159 354#define SK_GPIO 0x015C 355#define SK_I2CHWCTL 0x0160 356#define SK_I2CHWDATA 0x0164 357#define SK_I2CHWIRQ 0x0168 358#define SK_I2CSW 0x016C 359#define SK_BLNKINIT 0x0170 360#define SK_BLNKCOUNT 0x0174 361#define SK_BLNKCTL 0x0178 362#define SK_BLNKSTS 0x0179 363#define SK_BLNKTST 0x017A 364 365#define SK_IMCTL_STOP 0x02 366#define SK_IMCTL_START 0x04 367 368#define SK_IMTIMER_TICKS 54 369#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 370 371/* 372 * The SK_EPROM0 register contains a byte that describes the 373 * amount of SRAM mounted on the NIC. The value also tells if 374 * the chips are 64K or 128K. This affects the RAMbuffer address 375 * offset that we need to use. 376 */ 377#define SK_RAMSIZE_512K_64 0x1 378#define SK_RAMSIZE_1024K_128 0x2 379#define SK_RAMSIZE_1024K_64 0x3 380#define SK_RAMSIZE_2048K_128 0x4 381 382#define SK_RBOFF_0 0x0 383#define SK_RBOFF_80000 0x80000 384 385/* 386 * SK_EEPROM1 contains the PHY type, which may be XMAC for 387 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 388 * PHY. 389 */ 390#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 391#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 392#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 393#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 394#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 395#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 396 397/* 398 * PHY addresses. 399 */ 400#define SK_PHYADDR_XMAC 0x0 401#define SK_PHYADDR_BCOM 0x1 402#define SK_PHYADDR_LONE 0x3 403#define SK_PHYADDR_NAT 0x0 404#define SK_PHYADDR_MARV 0x0 405 406#define SK_CONFIG_SINGLEMAC 0x01 407#define SK_CONFIG_DIS_DSL_CLK 0x02 408 409#define SK_PMD_1000BASELX 0x4C 410#define SK_PMD_1000BASESX 0x53 411#define SK_PMD_1000BASECX 0x43 412#define SK_PMD_1000BASETX 0x54 413 414/* GPIO bits */ 415#define SK_GPIO_DAT0 0x00000001 416#define SK_GPIO_DAT1 0x00000002 417#define SK_GPIO_DAT2 0x00000004 418#define SK_GPIO_DAT3 0x00000008 419#define SK_GPIO_DAT4 0x00000010 420#define SK_GPIO_DAT5 0x00000020 421#define SK_GPIO_DAT6 0x00000040 422#define SK_GPIO_DAT7 0x00000080 423#define SK_GPIO_DAT8 0x00000100 424#define SK_GPIO_DAT9 0x00000200 425#define SK_GPIO_DIR0 0x00010000 426#define SK_GPIO_DIR1 0x00020000 427#define SK_GPIO_DIR2 0x00040000 428#define SK_GPIO_DIR3 0x00080000 429#define SK_GPIO_DIR4 0x00100000 430#define SK_GPIO_DIR5 0x00200000 431#define SK_GPIO_DIR6 0x00400000 432#define SK_GPIO_DIR7 0x00800000 433#define SK_GPIO_DIR8 0x01000000 434#define SK_GPIO_DIR9 0x02000000 435 436/* Block 3 Ram interface and MAC arbiter registers */ 437#define SK_RAMADDR 0x0180 438#define SK_RAMDATA0 0x0184 439#define SK_RAMDATA1 0x0188 440#define SK_TO0 0x0190 441#define SK_TO1 0x0191 442#define SK_TO2 0x0192 443#define SK_TO3 0x0193 444#define SK_TO4 0x0194 445#define SK_TO5 0x0195 446#define SK_TO6 0x0196 447#define SK_TO7 0x0197 448#define SK_TO8 0x0198 449#define SK_TO9 0x0199 450#define SK_TO10 0x019A 451#define SK_TO11 0x019B 452#define SK_RITIMEO_TMR 0x019C 453#define SK_RAMCTL 0x01A0 454#define SK_RITIMER_TST 0x01A2 455 456#define SK_RAMCTL_RESET 0x0001 457#define SK_RAMCTL_UNRESET 0x0002 458#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 459#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 460 461/* Mac arbiter registers */ 462#define SK_MINIT_RX1 0x01B0 463#define SK_MINIT_RX2 0x01B1 464#define SK_MINIT_TX1 0x01B2 465#define SK_MINIT_TX2 0x01B3 466#define SK_MTIMEO_RX1 0x01B4 467#define SK_MTIMEO_RX2 0x01B5 468#define SK_MTIMEO_TX1 0x01B6 469#define SK_MTIEMO_TX2 0x01B7 470#define SK_MACARB_CTL 0x01B8 471#define SK_MTIMER_TST 0x01BA 472#define SK_RCINIT_RX1 0x01C0 473#define SK_RCINIT_RX2 0x01C1 474#define SK_RCINIT_TX1 0x01C2 475#define SK_RCINIT_TX2 0x01C3 476#define SK_RCTIMEO_RX1 0x01C4 477#define SK_RCTIMEO_RX2 0x01C5 478#define SK_RCTIMEO_TX1 0x01C6 479#define SK_RCTIMEO_TX2 0x01C7 480#define SK_RECOVERY_CTL 0x01C8 481#define SK_RCTIMER_TST 0x01CA 482 483/* Packet arbiter registers */ 484#define SK_RXPA1_TINIT 0x01D0 485#define SK_RXPA2_TINIT 0x01D4 486#define SK_TXPA1_TINIT 0x01D8 487#define SK_TXPA2_TINIT 0x01DC 488#define SK_RXPA1_TIMEO 0x01E0 489#define SK_RXPA2_TIMEO 0x01E4 490#define SK_TXPA1_TIMEO 0x01E8 491#define SK_TXPA2_TIMEO 0x01EC 492#define SK_PKTARB_CTL 0x01F0 493#define SK_PKTATB_TST 0x01F2 494 495#define SK_PKTARB_TIMEOUT 0x2000 496 497#define SK_PKTARBCTL_RESET 0x0001 498#define SK_PKTARBCTL_UNRESET 0x0002 499#define SK_PKTARBCTL_RXTO1_OFF 0x0004 500#define SK_PKTARBCTL_RXTO1_ON 0x0008 501#define SK_PKTARBCTL_RXTO2_OFF 0x0010 502#define SK_PKTARBCTL_RXTO2_ON 0x0020 503#define SK_PKTARBCTL_TXTO1_OFF 0x0040 504#define SK_PKTARBCTL_TXTO1_ON 0x0080 505#define SK_PKTARBCTL_TXTO2_OFF 0x0100 506#define SK_PKTARBCTL_TXTO2_ON 0x0200 507#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 508#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 509#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 510#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 511 512#define SK_MINIT_XMAC_B2 54 513#define SK_MINIT_XMAC_C1 63 514 515#define SK_MACARBCTL_RESET 0x0001 516#define SK_MACARBCTL_UNRESET 0x0002 517#define SK_MACARBCTL_FASTOE_OFF 0x0004 518#define SK_MACARBCRL_FASTOE_ON 0x0008 519 520#define SK_RCINIT_XMAC_B2 54 521#define SK_RCINIT_XMAC_C1 0 522 523#define SK_RECOVERYCTL_RX1_OFF 0x0001 524#define SK_RECOVERYCTL_RX1_ON 0x0002 525#define SK_RECOVERYCTL_RX2_OFF 0x0004 526#define SK_RECOVERYCTL_RX2_ON 0x0008 527#define SK_RECOVERYCTL_TX1_OFF 0x0010 528#define SK_RECOVERYCTL_TX1_ON 0x0020 529#define SK_RECOVERYCTL_TX2_OFF 0x0040 530#define SK_RECOVERYCTL_TX2_ON 0x0080 531 532#define SK_RECOVERY_XMAC_B2 \ 533 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 534 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 535 536#define SK_RECOVERY_XMAC_C1 \ 537 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 538 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 539 540/* Block 4 -- TX Arbiter MAC 1 */ 541#define SK_TXAR1_TIMERINIT 0x0200 542#define SK_TXAR1_TIMERVAL 0x0204 543#define SK_TXAR1_LIMITINIT 0x0208 544#define SK_TXAR1_LIMITCNT 0x020C 545#define SK_TXAR1_COUNTERCTL 0x0210 546#define SK_TXAR1_COUNTERTST 0x0212 547#define SK_TXAR1_COUNTERSTS 0x0212 548 549/* Block 5 -- TX Arbiter MAC 2 */ 550#define SK_TXAR2_TIMERINIT 0x0280 551#define SK_TXAR2_TIMERVAL 0x0284 552#define SK_TXAR2_LIMITINIT 0x0288 553#define SK_TXAR2_LIMITCNT 0x028C 554#define SK_TXAR2_COUNTERCTL 0x0290 555#define SK_TXAR2_COUNTERTST 0x0291 556#define SK_TXAR2_COUNTERSTS 0x0292 557 558#define SK_TXARCTL_OFF 0x01 559#define SK_TXARCTL_ON 0x02 560#define SK_TXARCTL_RATECTL_OFF 0x04 561#define SK_TXARCTL_RATECTL_ON 0x08 562#define SK_TXARCTL_ALLOC_OFF 0x10 563#define SK_TXARCTL_ALLOC_ON 0x20 564#define SK_TXARCTL_FSYNC_OFF 0x40 565#define SK_TXARCTL_FSYNC_ON 0x80 566 567/* Block 6 -- External registers */ 568#define SK_EXTREG_BASE 0x300 569#define SK_EXTREG_END 0x37C 570 571/* Block 7 -- PCI config registers */ 572#define SK_PCI_BASE 0x0380 573#define SK_PCI_END 0x03FC 574 575/* Compute offset of mirrored PCI register */ 576#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 577 578/* Block 8 -- RX queue 1 */ 579#define SK_RXQ1_BUFCNT 0x0400 580#define SK_RXQ1_BUFCTL 0x0402 581#define SK_RXQ1_NEXTDESC 0x0404 582#define SK_RXQ1_RXBUF_LO 0x0408 583#define SK_RXQ1_RXBUF_HI 0x040C 584#define SK_RXQ1_RXSTAT 0x0410 585#define SK_RXQ1_TIMESTAMP 0x0414 586#define SK_RXQ1_CSUM1 0x0418 587#define SK_RXQ1_CSUM2 0x041A 588#define SK_RXQ1_CSUM1_START 0x041C 589#define SK_RXQ1_CSUM2_START 0x041E 590#define SK_RXQ1_CURADDR_LO 0x0420 591#define SK_RXQ1_CURADDR_HI 0x0424 592#define SK_RXQ1_CURCNT_LO 0x0428 593#define SK_RXQ1_CURCNT_HI 0x042C 594#define SK_RXQ1_CURBYTES 0x0430 595#define SK_RXQ1_BMU_CSR 0x0434 596#define SK_RXQ1_WATERMARK 0x0438 597#define SK_RXQ1_FLAG 0x043A 598#define SK_RXQ1_TEST1 0x043C 599#define SK_RXQ1_TEST2 0x0440 600#define SK_RXQ1_TEST3 0x0444 601 602/* Block 9 -- RX queue 2 */ 603#define SK_RXQ2_BUFCNT 0x0480 604#define SK_RXQ2_BUFCTL 0x0482 605#define SK_RXQ2_NEXTDESC 0x0484 606#define SK_RXQ2_RXBUF_LO 0x0488 607#define SK_RXQ2_RXBUF_HI 0x048C 608#define SK_RXQ2_RXSTAT 0x0490 609#define SK_RXQ2_TIMESTAMP 0x0494 610#define SK_RXQ2_CSUM1 0x0498 611#define SK_RXQ2_CSUM2 0x049A 612#define SK_RXQ2_CSUM1_START 0x049C 613#define SK_RXQ2_CSUM2_START 0x049E 614#define SK_RXQ2_CURADDR_LO 0x04A0 615#define SK_RXQ2_CURADDR_HI 0x04A4 616#define SK_RXQ2_CURCNT_LO 0x04A8 617#define SK_RXQ2_CURCNT_HI 0x04AC 618#define SK_RXQ2_CURBYTES 0x04B0 619#define SK_RXQ2_BMU_CSR 0x04B4 620#define SK_RXQ2_WATERMARK 0x04B8 621#define SK_RXQ2_FLAG 0x04BA 622#define SK_RXQ2_TEST1 0x04BC 623#define SK_RXQ2_TEST2 0x04C0 624#define SK_RXQ2_TEST3 0x04C4 625 626#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 627#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 628#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 629#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 630#define SK_RXBMU_RX_START 0x00000010 631#define SK_RXBMU_RX_STOP 0x00000020 632#define SK_RXBMU_POLL_OFF 0x00000040 633#define SK_RXBMU_POLL_ON 0x00000080 634#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 635#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 636#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 637#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 638#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 639#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 640#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 641#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 642#define SK_RXBMU_PFI_SM_RESET 0x00010000 643#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 644#define SK_RXBMU_FIFO_RESET 0x00040000 645#define SK_RXBMU_FIFO_UNRESET 0x00080000 646#define SK_RXBMU_DESC_RESET 0x00100000 647#define SK_RXBMU_DESC_UNRESET 0x00200000 648#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 649 650#define SK_RXBMU_ONLINE \ 651 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 652 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 653 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 654 SK_RXBMU_DESC_UNRESET) 655 656#define SK_RXBMU_OFFLINE \ 657 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 658 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 659 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 660 SK_RXBMU_DESC_RESET) 661 662/* Block 12 -- TX sync queue 1 */ 663#define SK_TXQS1_BUFCNT 0x0600 664#define SK_TXQS1_BUFCTL 0x0602 665#define SK_TXQS1_NEXTDESC 0x0604 666#define SK_TXQS1_RXBUF_LO 0x0608 667#define SK_TXQS1_RXBUF_HI 0x060C 668#define SK_TXQS1_RXSTAT 0x0610 669#define SK_TXQS1_CSUM_STARTVAL 0x0614 670#define SK_TXQS1_CSUM_STARTPOS 0x0618 671#define SK_TXQS1_CSUM_WRITEPOS 0x061A 672#define SK_TXQS1_CURADDR_LO 0x0620 673#define SK_TXQS1_CURADDR_HI 0x0624 674#define SK_TXQS1_CURCNT_LO 0x0628 675#define SK_TXQS1_CURCNT_HI 0x062C 676#define SK_TXQS1_CURBYTES 0x0630 677#define SK_TXQS1_BMU_CSR 0x0634 678#define SK_TXQS1_WATERMARK 0x0638 679#define SK_TXQS1_FLAG 0x063A 680#define SK_TXQS1_TEST1 0x063C 681#define SK_TXQS1_TEST2 0x0640 682#define SK_TXQS1_TEST3 0x0644 683 684/* Block 13 -- TX async queue 1 */ 685#define SK_TXQA1_BUFCNT 0x0680 686#define SK_TXQA1_BUFCTL 0x0682 687#define SK_TXQA1_NEXTDESC 0x0684 688#define SK_TXQA1_RXBUF_LO 0x0688 689#define SK_TXQA1_RXBUF_HI 0x068C 690#define SK_TXQA1_RXSTAT 0x0690 691#define SK_TXQA1_CSUM_STARTVAL 0x0694 692#define SK_TXQA1_CSUM_STARTPOS 0x0698 693#define SK_TXQA1_CSUM_WRITEPOS 0x069A 694#define SK_TXQA1_CURADDR_LO 0x06A0 695#define SK_TXQA1_CURADDR_HI 0x06A4 696#define SK_TXQA1_CURCNT_LO 0x06A8 697#define SK_TXQA1_CURCNT_HI 0x06AC 698#define SK_TXQA1_CURBYTES 0x06B0 699#define SK_TXQA1_BMU_CSR 0x06B4 700#define SK_TXQA1_WATERMARK 0x06B8 701#define SK_TXQA1_FLAG 0x06BA 702#define SK_TXQA1_TEST1 0x06BC 703#define SK_TXQA1_TEST2 0x06C0 704#define SK_TXQA1_TEST3 0x06C4 705 706/* Block 14 -- TX sync queue 2 */ 707#define SK_TXQS2_BUFCNT 0x0700 708#define SK_TXQS2_BUFCTL 0x0702 709#define SK_TXQS2_NEXTDESC 0x0704 710#define SK_TXQS2_RXBUF_LO 0x0708 711#define SK_TXQS2_RXBUF_HI 0x070C 712#define SK_TXQS2_RXSTAT 0x0710 713#define SK_TXQS2_CSUM_STARTVAL 0x0714 714#define SK_TXQS2_CSUM_STARTPOS 0x0718 715#define SK_TXQS2_CSUM_WRITEPOS 0x071A 716#define SK_TXQS2_CURADDR_LO 0x0720 717#define SK_TXQS2_CURADDR_HI 0x0724 718#define SK_TXQS2_CURCNT_LO 0x0728 719#define SK_TXQS2_CURCNT_HI 0x072C 720#define SK_TXQS2_CURBYTES 0x0730 721#define SK_TXQS2_BMU_CSR 0x0734 722#define SK_TXQS2_WATERMARK 0x0738 723#define SK_TXQS2_FLAG 0x073A 724#define SK_TXQS2_TEST1 0x073C 725#define SK_TXQS2_TEST2 0x0740 726#define SK_TXQS2_TEST3 0x0744 727 728/* Block 15 -- TX async queue 2 */ 729#define SK_TXQA2_BUFCNT 0x0780 730#define SK_TXQA2_BUFCTL 0x0782 731#define SK_TXQA2_NEXTDESC 0x0784 732#define SK_TXQA2_RXBUF_LO 0x0788 733#define SK_TXQA2_RXBUF_HI 0x078C 734#define SK_TXQA2_RXSTAT 0x0790 735#define SK_TXQA2_CSUM_STARTVAL 0x0794 736#define SK_TXQA2_CSUM_STARTPOS 0x0798 737#define SK_TXQA2_CSUM_WRITEPOS 0x079A 738#define SK_TXQA2_CURADDR_LO 0x07A0 739#define SK_TXQA2_CURADDR_HI 0x07A4 740#define SK_TXQA2_CURCNT_LO 0x07A8 741#define SK_TXQA2_CURCNT_HI 0x07AC 742#define SK_TXQA2_CURBYTES 0x07B0 743#define SK_TXQA2_BMU_CSR 0x07B4 744#define SK_TXQA2_WATERMARK 0x07B8 745#define SK_TXQA2_FLAG 0x07BA 746#define SK_TXQA2_TEST1 0x07BC 747#define SK_TXQA2_TEST2 0x07C0 748#define SK_TXQA2_TEST3 0x07C4 749 750#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 751#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 752#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 753#define SK_TXBMU_TX_START 0x00000010 754#define SK_TXBMU_TX_STOP 0x00000020 755#define SK_TXBMU_POLL_OFF 0x00000040 756#define SK_TXBMU_POLL_ON 0x00000080 757#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 758#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 759#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 760#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 761#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 762#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 763#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 764#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 765#define SK_TXBMU_PFI_SM_RESET 0x00010000 766#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 767#define SK_TXBMU_FIFO_RESET 0x00040000 768#define SK_TXBMU_FIFO_UNRESET 0x00080000 769#define SK_TXBMU_DESC_RESET 0x00100000 770#define SK_TXBMU_DESC_UNRESET 0x00200000 771#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 772 773#define SK_TXBMU_ONLINE \ 774 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 775 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 776 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 777 SK_TXBMU_DESC_UNRESET) 778 779#define SK_TXBMU_OFFLINE \ 780 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 781 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 782 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 783 SK_TXBMU_DESC_RESET) 784 785/* Block 16 -- Receive RAMbuffer 1 */ 786#define SK_RXRB1_START 0x0800 787#define SK_RXRB1_END 0x0804 788#define SK_RXRB1_WR_PTR 0x0808 789#define SK_RXRB1_RD_PTR 0x080C 790#define SK_RXRB1_UTHR_PAUSE 0x0810 791#define SK_RXRB1_LTHR_PAUSE 0x0814 792#define SK_RXRB1_UTHR_HIPRIO 0x0818 793#define SK_RXRB1_UTHR_LOPRIO 0x081C 794#define SK_RXRB1_PKTCNT 0x0820 795#define SK_RXRB1_LVL 0x0824 796#define SK_RXRB1_CTLTST 0x0828 797 798/* Block 17 -- Receive RAMbuffer 2 */ 799#define SK_RXRB2_START 0x0880 800#define SK_RXRB2_END 0x0884 801#define SK_RXRB2_WR_PTR 0x0888 802#define SK_RXRB2_RD_PTR 0x088C 803#define SK_RXRB2_UTHR_PAUSE 0x0890 804#define SK_RXRB2_LTHR_PAUSE 0x0894 805#define SK_RXRB2_UTHR_HIPRIO 0x0898 806#define SK_RXRB2_UTHR_LOPRIO 0x089C 807#define SK_RXRB2_PKTCNT 0x08A0 808#define SK_RXRB2_LVL 0x08A4 809#define SK_RXRB2_CTLTST 0x08A8 810 811/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 812#define SK_TXRBS1_START 0x0A00 813#define SK_TXRBS1_END 0x0A04 814#define SK_TXRBS1_WR_PTR 0x0A08 815#define SK_TXRBS1_RD_PTR 0x0A0C 816#define SK_TXRBS1_PKTCNT 0x0A20 817#define SK_TXRBS1_LVL 0x0A24 818#define SK_TXRBS1_CTLTST 0x0A28 819 820/* Block 21 -- Async. Transmit RAMbuffer 1 */ 821#define SK_TXRBA1_START 0x0A80 822#define SK_TXRBA1_END 0x0A84 823#define SK_TXRBA1_WR_PTR 0x0A88 824#define SK_TXRBA1_RD_PTR 0x0A8C 825#define SK_TXRBA1_PKTCNT 0x0AA0 826#define SK_TXRBA1_LVL 0x0AA4 827#define SK_TXRBA1_CTLTST 0x0AA8 828 829/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 830#define SK_TXRBS2_START 0x0B00 831#define SK_TXRBS2_END 0x0B04 832#define SK_TXRBS2_WR_PTR 0x0B08 833#define SK_TXRBS2_RD_PTR 0x0B0C 834#define SK_TXRBS2_PKTCNT 0x0B20 835#define SK_TXRBS2_LVL 0x0B24 836#define SK_TXRBS2_CTLTST 0x0B28 837 838/* Block 23 -- Async. Transmit RAMbuffer 2 */ 839#define SK_TXRBA2_START 0x0B80 840#define SK_TXRBA2_END 0x0B84 841#define SK_TXRBA2_WR_PTR 0x0B88 842#define SK_TXRBA2_RD_PTR 0x0B8C 843#define SK_TXRBA2_PKTCNT 0x0BA0 844#define SK_TXRBA2_LVL 0x0BA4 845#define SK_TXRBA2_CTLTST 0x0BA8 846 847#define SK_RBCTL_RESET 0x00000001 848#define SK_RBCTL_UNRESET 0x00000002 849#define SK_RBCTL_OFF 0x00000004 850#define SK_RBCTL_ON 0x00000008 851#define SK_RBCTL_STORENFWD_OFF 0x00000010 852#define SK_RBCTL_STORENFWD_ON 0x00000020 853 854/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 855#define SK_RXF1_END 0x0C00 856#define SK_RXF1_WPTR 0x0C04 857#define SK_RXF1_RPTR 0x0C0C 858#define SK_RXF1_PKTCNT 0x0C10 859#define SK_RXF1_LVL 0x0C14 860#define SK_RXF1_MACCTL 0x0C18 861#define SK_RXF1_CTL 0x0C1C 862#define SK_RXLED1_CNTINIT 0x0C20 863#define SK_RXLED1_COUNTER 0x0C24 864#define SK_RXLED1_CTL 0x0C28 865#define SK_RXLED1_TST 0x0C29 866#define SK_LINK_SYNC1_CINIT 0x0C30 867#define SK_LINK_SYNC1_COUNTER 0x0C34 868#define SK_LINK_SYNC1_CTL 0x0C38 869#define SK_LINK_SYNC1_TST 0x0C39 870#define SK_LINKLED1_CTL 0x0C3C 871 872#define SK_FIFO_END 0x3F 873 874/* Receive MAC FIFO 1 (Yukon Only) */ 875#define SK_RXMF1_END 0x0C40 876#define SK_RXMF1_THRESHOLD 0x0C44 877#define SK_RXMF1_CTRL_TEST 0x0C48 878#define SK_RXMF1_WRITE_PTR 0x0C60 879#define SK_RXMF1_WRITE_LEVEL 0x0C68 880#define SK_RXMF1_READ_PTR 0x0C70 881#define SK_RXMF1_READ_LEVEL 0x0C78 882 883#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 884#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 885#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 886#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 887#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 888#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 889#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 890#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 891#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 892#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 893#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 894#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 895 896/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 897#define SK_RXF2_END 0x0C80 898#define SK_RXF2_WPTR 0x0C84 899#define SK_RXF2_RPTR 0x0C8C 900#define SK_RXF2_PKTCNT 0x0C90 901#define SK_RXF2_LVL 0x0C94 902#define SK_RXF2_MACCTL 0x0C98 903#define SK_RXF2_CTL 0x0C9C 904#define SK_RXLED2_CNTINIT 0x0CA0 905#define SK_RXLED2_COUNTER 0x0CA4 906#define SK_RXLED2_CTL 0x0CA8 907#define SK_RXLED2_TST 0x0CA9 908#define SK_LINK_SYNC2_CINIT 0x0CB0 909#define SK_LINK_SYNC2_COUNTER 0x0CB4 910#define SK_LINK_SYNC2_CTL 0x0CB8 911#define SK_LINK_SYNC2_TST 0x0CB9 912#define SK_LINKLED2_CTL 0x0CBC 913 914#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 915#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 916#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 917#define SK_RXMACCTL_RSTAMP_ON 0x00000008 918#define SK_RXMACCTL_FLUSH_OFF 0x00000010 919#define SK_RXMACCTL_FLUSH_ON 0x00000020 920#define SK_RXMACCTL_PAUSE_OFF 0x00000040 921#define SK_RXMACCTL_PAUSE_ON 0x00000080 922#define SK_RXMACCTL_AFULL_OFF 0x00000100 923#define SK_RXMACCTL_AFULL_ON 0x00000200 924#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 925#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 926#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 927#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 928#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 929#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 930 931#define SK_RXLEDCTL_ENABLE 0x0001 932#define SK_RXLEDCTL_COUNTER_STOP 0x0002 933#define SK_RXLEDCTL_COUNTER_START 0x0004 934 935#define SK_LINKLED_OFF 0x0001 936#define SK_LINKLED_ON 0x0002 937#define SK_LINKLED_LINKSYNC_OFF 0x0004 938#define SK_LINKLED_LINKSYNC_ON 0x0008 939#define SK_LINKLED_BLINK_OFF 0x0010 940#define SK_LINKLED_BLINK_ON 0x0020 941 942/* Block 26 -- TX MAC FIFO 1 regisrers */ 943#define SK_TXF1_END 0x0D00 944#define SK_TXF1_WPTR 0x0D04 945#define SK_TXF1_RPTR 0x0D0C 946#define SK_TXF1_PKTCNT 0x0D10 947#define SK_TXF1_LVL 0x0D14 948#define SK_TXF1_MACCTL 0x0D18 949#define SK_TXF1_CTL 0x0D1C 950#define SK_TXLED1_CNTINIT 0x0D20 951#define SK_TXLED1_COUNTER 0x0D24 952#define SK_TXLED1_CTL 0x0D28 953#define SK_TXLED1_TST 0x0D29 954 955/* Receive MAC FIFO 1 (Yukon Only) */ 956#define SK_TXMF1_END 0x0D40 957#define SK_TXMF1_THRESHOLD 0x0D44 958#define SK_TXMF1_CTRL_TEST 0x0D48 959#define SK_TXMF1_WRITE_PTR 0x0D60 960#define SK_TXMF1_WRITE_SHADOW 0x0D64 961#define SK_TXMF1_WRITE_LEVEL 0x0D68 962#define SK_TXMF1_READ_PTR 0x0D70 963#define SK_TXMF1_RESTART_PTR 0x0D74 964#define SK_TXMF1_READ_LEVEL 0x0D78 965 966#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 967#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 968#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 969#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 970#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 971#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 972#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 973#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 974#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 975#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 976#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 977#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 978#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 979 980/* Block 27 -- TX MAC FIFO 2 regisrers */ 981#define SK_TXF2_END 0x0D80 982#define SK_TXF2_WPTR 0x0D84 983#define SK_TXF2_RPTR 0x0D8C 984#define SK_TXF2_PKTCNT 0x0D90 985#define SK_TXF2_LVL 0x0D94 986#define SK_TXF2_MACCTL 0x0D98 987#define SK_TXF2_CTL 0x0D9C 988#define SK_TXLED2_CNTINIT 0x0DA0 989#define SK_TXLED2_COUNTER 0x0DA4 990#define SK_TXLED2_CTL 0x0DA8 991#define SK_TXLED2_TST 0x0DA9 992 993#define SK_TXMACCTL_XMAC_RESET 0x00000001 994#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 995#define SK_TXMACCTL_LOOP_OFF 0x00000004 996#define SK_TXMACCTL_LOOP_ON 0x00000008 997#define SK_TXMACCTL_FLUSH_OFF 0x00000010 998#define SK_TXMACCTL_FLUSH_ON 0x00000020 999#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1000#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1001#define SK_TXMACCTL_AFULL_OFF 0x00000100 1002#define SK_TXMACCTL_AFULL_ON 0x00000200 1003#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1004#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1005#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1006#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1007#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1008#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1009 1010#define SK_TXLEDCTL_ENABLE 0x0001 1011#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1012#define SK_TXLEDCTL_COUNTER_START 0x0004 1013 1014#define SK_FIFO_RESET 0x00000001 1015#define SK_FIFO_UNRESET 0x00000002 1016#define SK_FIFO_OFF 0x00000004 1017#define SK_FIFO_ON 0x00000008 1018 1019/* Block 28 -- Descriptor Poll Timer */ 1020#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1021#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1022 1023#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1024#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1025#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1026 1027#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1028#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1029#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1030#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1031 1032/* Block 29 -- reserved */ 1033 1034/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1035#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1036#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1037#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1038#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1039#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1040#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1041#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1042#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1043#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1044#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1045#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1046#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1047#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1048#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1049#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1050#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1051#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1052#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1053#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1054#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1055#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1056#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1057#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1058#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1059#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1060#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1061#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1062#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1063#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1064 1065#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1066#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1067#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1068#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1069#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1070#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1071 1072#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1073#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1074#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1075#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1076#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1077#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1078#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1079#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1080#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1081#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1082#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1083#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1084#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1085#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1086#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1087#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1088#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1089#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1090#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1091#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1092#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1093#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1094#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1095 1096#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1097 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1098#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1099 SK_GPHY_HWCFG_M_2 ) 1100#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1101 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1102 1103#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1104#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1105#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1106#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1107#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1108#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1109 1110#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1111#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1112 1113/* Block 31 -- reserved */ 1114 1115/* Block 32-33 -- Pattern Ram */ 1116#define SK_WOL_PRAM 0x1000 1117 1118/* Block 0x22 - 0x3f -- reserved */ 1119 1120/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1121#define SK_XMAC1_BASE 0x2000 1122 1123/* Block 0x50 to 0x5F -- MARV 1 registers */ 1124#define SK_MARV1_BASE 0x2800 1125 1126/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1127#define SK_XMAC2_BASE 0x3000 1128 1129/* Block 0x70 to 0x7F -- MARV 2 registers */ 1130#define SK_MARV2_BASE 0x3800 1131 1132/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1133#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1134 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1135 1136#if 0 1137#define SK_XM_READ_4(sc, reg) \ 1138 ((sk_win_read_2(sc->sk_softc, \ 1139 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1140 ((sk_win_read_2(sc->sk_softc, \ 1141 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1142 1143#define SK_XM_WRITE_4(sc, reg, val) \ 1144 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1145 ((val) & 0xFFFF)); \ 1146 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1147 ((val) >> 16) & 0xFFFF) 1148#else 1149#define SK_XM_READ_4(sc, reg) \ 1150 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1151 1152#define SK_XM_WRITE_4(sc, reg, val) \ 1153 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1154#endif 1155 1156#define SK_XM_READ_2(sc, reg) \ 1157 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1158 1159#define SK_XM_WRITE_2(sc, reg, val) \ 1160 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1161 1162#define SK_XM_SETBIT_4(sc, reg, x) \ 1163 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1164 1165#define SK_XM_CLRBIT_4(sc, reg, x) \ 1166 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1167 1168#define SK_XM_SETBIT_2(sc, reg, x) \ 1169 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1170 1171#define SK_XM_CLRBIT_2(sc, reg, x) \ 1172 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1173 1174/* Compute relative offset of an MARV register in the MARV window(s). */ 1175#define SK_YU_REG(sc, reg) \ 1176 ((reg) + SK_MARV1_BASE + \ 1177 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1178 1179#define SK_YU_READ_4(sc, reg) \ 1180 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1181 1182#define SK_YU_READ_2(sc, reg) \ 1183 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1184 1185#define SK_YU_WRITE_4(sc, reg, val) \ 1186 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1187 1188#define SK_YU_WRITE_2(sc, reg, val) \ 1189 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1190 1191#define SK_YU_SETBIT_4(sc, reg, x) \ 1192 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1193 1194#define SK_YU_CLRBIT_4(sc, reg, x) \ 1195 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1196 1197#define SK_YU_SETBIT_2(sc, reg, x) \ 1198 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1199 1200#define SK_YU_CLRBIT_2(sc, reg, x) \ 1201 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1202 1203/* 1204 * The default FIFO threshold on the XMAC II is 4 bytes. On 1205 * dual port NICs, this often leads to transmit underruns, so we 1206 * bump the threshold a little. 1207 */ 1208#define SK_XM_TX_FIFOTHRESH 512 1209 1210#define SK_PCI_VENDOR_ID 0x0000 1211#define SK_PCI_DEVICE_ID 0x0002 1212#define SK_PCI_COMMAND 0x0004 1213#define SK_PCI_STATUS 0x0006 1214#define SK_PCI_REVID 0x0008 1215#define SK_PCI_CLASSCODE 0x0009 1216#define SK_PCI_CACHELEN 0x000C 1217#define SK_PCI_LATENCY_TIMER 0x000D 1218#define SK_PCI_HEADER_TYPE 0x000E 1219#define SK_PCI_LOMEM 0x0010 1220#define SK_PCI_LOIO 0x0014 1221#define SK_PCI_SUBVEN_ID 0x002C 1222#define SK_PCI_SYBSYS_ID 0x002E 1223#define SK_PCI_BIOSROM 0x0030 1224#define SK_PCI_INTLINE 0x003C 1225#define SK_PCI_INTPIN 0x003D 1226#define SK_PCI_MINGNT 0x003E 1227#define SK_PCI_MINLAT 0x003F 1228 1229/* device specific PCI registers */ 1230#define SK_PCI_OURREG1 0x0040 1231#define SK_PCI_OURREG2 0x0044 1232#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1233#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1234#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1235#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1236#define SK_PCI_PME_EVENT 0x004F 1237#define SK_PCI_VPD_CAPID 0x0050 1238#define SK_PCI_VPD_NEXTPTR 0x0051 1239#define SK_PCI_VPD_ADDR 0x0052 1240#define SK_PCI_VPD_DATA 0x0054 1241 1242#define SK_PSTATE_MASK 0x0003 1243#define SK_PSTATE_D0 0x0000 1244#define SK_PSTATE_D1 0x0001 1245#define SK_PSTATE_D2 0x0002 1246#define SK_PSTATE_D3 0x0003 1247#define SK_PME_EN 0x0010 1248#define SK_PME_STATUS 0x8000 1249 1250/* 1251 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1252 * read is complete. Set to 1 to initiate a write, will become 0 1253 * when write is finished. 1254 */ 1255#define SK_VPD_FLAG 0x8000 1256 1257/* VPD structures */ 1258struct vpd_res { 1259 u_int8_t vr_id; 1260 u_int8_t vr_len; 1261 u_int8_t vr_pad; 1262}; 1263 1264struct vpd_key { 1265 char vk_key[2]; 1266 u_int8_t vk_len; 1267}; 1268 1269#define VPD_RES_ID 0x82 /* ID string */ 1270#define VPD_RES_READ 0x90 /* start of read only area */ 1271#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1272#define VPD_RES_END 0x78 /* end tag */ 1273 1274#define CSR_WRITE_4(sc, reg, val) \ 1275 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1276#define CSR_WRITE_2(sc, reg, val) \ 1277 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1278#define CSR_WRITE_1(sc, reg, val) \ 1279 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1280 1281#define CSR_READ_4(sc, reg) \ 1282 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1283#define CSR_READ_2(sc, reg) \ 1284 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1285#define CSR_READ_1(sc, reg) \ 1286 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1287 1288struct sk_type { 1289 u_int16_t sk_vid; 1290 u_int16_t sk_did; 1291 char *sk_name; 1292}; 1293 1294/* RX queue descriptor data structure */ 1295struct sk_rx_desc { 1296 u_int32_t sk_ctl; 1297 u_int32_t sk_next; 1298 u_int32_t sk_data_lo; 1299 u_int32_t sk_data_hi; 1300 u_int32_t sk_xmac_rxstat; 1301 u_int32_t sk_timestamp; 1302 u_int16_t sk_csum2; 1303 u_int16_t sk_csum1; 1304 u_int16_t sk_csum2_start; 1305 u_int16_t sk_csum1_start; 1306}; 1307 1308#define SK_OPCODE_DEFAULT 0x00550000 1309#define SK_OPCODE_CSUM 0x00560000 1310 1311#define SK_RXCTL_LEN 0x0000FFFF 1312#define SK_RXCTL_OPCODE 0x00FF0000 1313#define SK_RXCTL_TSTAMP_VALID 0x01000000 1314#define SK_RXCTL_STATUS_VALID 0x02000000 1315#define SK_RXCTL_DEV0 0x04000000 1316#define SK_RXCTL_EOF_INTR 0x08000000 1317#define SK_RXCTL_EOB_INTR 0x10000000 1318#define SK_RXCTL_LASTFRAG 0x20000000 1319#define SK_RXCTL_FIRSTFRAG 0x40000000 1320#define SK_RXCTL_OWN 0x80000000 1321 1322#define SK_RXSTAT \ 1323 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1324 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1325 1326struct sk_tx_desc { 1327 u_int32_t sk_ctl; 1328 u_int32_t sk_next; 1329 u_int32_t sk_data_lo; 1330 u_int32_t sk_data_hi; 1331 u_int32_t sk_xmac_txstat; 1332 u_int16_t sk_rsvd0; 1333 u_int16_t sk_csum_startval; 1334 u_int16_t sk_csum_startpos; 1335 u_int16_t sk_csum_writepos; 1336 u_int32_t sk_rsvd1; 1337}; 1338 1339#define SK_TXCTL_LEN 0x0000FFFF 1340#define SK_TXCTL_OPCODE 0x00FF0000 1341#define SK_TXCTL_SW 0x01000000 1342#define SK_TXCTL_NOCRC 0x02000000 1343#define SK_TXCTL_STORENFWD 0x04000000 1344#define SK_TXCTL_EOF_INTR 0x08000000 1345#define SK_TXCTL_EOB_INTR 0x10000000 1346#define SK_TXCTL_LASTFRAG 0x20000000 1347#define SK_TXCTL_FIRSTFRAG 0x40000000 1348#define SK_TXCTL_OWN 0x80000000 1349 1350#define SK_TXSTAT \ 1351 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1352 1353#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1354#define SK_TXBYTES SK_RXBYTES 1355 1356#define SK_TX_RING_CNT 512 1357#define SK_RX_RING_CNT 256 1358 1359/* 1360 * Jumbo buffer stuff. Note that we must allocate more jumbo 1361 * buffers than there are descriptors in the receive ring. This 1362 * is because we don't know how long it will take for a packet 1363 * to be released after we hand it off to the upper protocol 1364 * layers. To be safe, we allocate 1.5 times the number of 1365 * receive descriptors. 1366 */ 1367#define SK_JUMBO_FRAMELEN 9018 1368#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1369#define SK_JSLOTS 384 1370 1371#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1372#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1373 (SK_JRAWLEN % sizeof(u_int64_t)))) 1374#define SK_JPAGESZ PAGE_SIZE 1375#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1376#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1377 1378struct sk_jpool_entry { 1379 int slot; 1380 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1381}; 1382 1383struct sk_chain { 1384 void *sk_desc; 1385 struct mbuf *sk_mbuf; 1386 struct sk_chain *sk_next; 1387}; 1388 1389struct sk_chain_data { 1390 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1391 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1392 int sk_tx_prod; 1393 int sk_tx_cons; 1394 int sk_tx_cnt; 1395 int sk_rx_prod; 1396 int sk_rx_cons; 1397 int sk_rx_cnt; 1398 /* Stick the jumbo mem management stuff here too. */ 1399 caddr_t sk_jslots[SK_JSLOTS]; 1400 void *sk_jumbo_buf; 1401 1402}; 1403 1404struct sk_ring_data { 1405 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1406 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1407}; 1408 1409struct sk_bcom_hack { 1410 int reg; 1411 int val; 1412}; 1413 1414#define SK_INC(x, y) (x) = (x + 1) % y 1415 1416/* Forward decl. */ 1417struct sk_if_softc; 1418 1419/* Softc for the GEnesis controller. */ 1420struct sk_softc { 1421 bus_space_handle_t sk_bhandle; /* bus space handle */ 1422 bus_space_tag_t sk_btag; /* bus space tag */ 1423 void *sk_intrhand; /* irq handler handle */ 1424 struct resource *sk_irq; /* IRQ resource handle */ 1425 struct resource *sk_res; /* I/O or shared mem handle */ 1426 u_int8_t sk_unit; /* controller number */ 1427 u_int8_t sk_type; 1428 char *sk_vpd_prodname; 1429 char *sk_vpd_readonly; 1430 u_int32_t sk_rboff; /* RAMbuffer offset */ 1431 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1432 u_int32_t sk_pmd; /* physical media type */ 1433 u_int32_t sk_intrmask; 1434 struct sk_if_softc *sk_if[2]; 1435 device_t sk_devs[2]; 1436 struct mtx sk_mtx; 1437}; 1438 1439#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1440#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1441#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1442#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1443#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1444 1445/* Softc for each logical interface */ 1446struct sk_if_softc { 1447 struct arpcom arpcom; /* interface info */ 1448 device_t sk_miibus; 1449 u_int8_t sk_unit; /* interface number */ 1450 u_int8_t sk_port; /* port # on controller */ 1451 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1452 u_int32_t sk_rx_ramstart; 1453 u_int32_t sk_rx_ramend; 1454 u_int32_t sk_tx_ramstart; 1455 u_int32_t sk_tx_ramend; 1456 int sk_phytype; 1457 int sk_phyaddr; 1458 device_t sk_dev; 1459 int sk_cnt; 1460 int sk_link; 1461 struct callout_handle sk_tick_ch; 1462 struct sk_chain_data sk_cdata; 1463 struct sk_ring_data *sk_rdata; 1464 struct sk_softc *sk_softc; /* parent controller */ 1465 int sk_tx_bmu; /* TX BMU register */ 1466 int sk_if_flags; 1467 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1468 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1469}; 1470 1471#define SK_MAXUNIT 256 1472#define SK_TIMEOUT 1000 1473#define ETHER_ALIGN 2 1474 1475#ifdef __alpha__ 1476#undef vtophys 1477#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1478#endif 1479