if_skreg.h revision 122689
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 122689 2003-11-14 19:00:32Z sam $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart */ 54#define SK_GENESIS 0 55#define SK_YUKON 1 56 57/* 58 * SysKonnect PCI vendor ID 59 */ 60#define VENDORID_SK 0x1148 61 62/* 63 * Marvell PCI vendor ID 64 */ 65#define VENDORID_MARVELL 0x11AB 66 67/* 68 * SK-NET gigabit ethernet device IDs 69 */ 70#define DEVICEID_SK_V1 0x4300 71#define DEVICEID_SK_V2 0x4320 72 73/* 74 * 3Com PCI vendor ID 75 */ 76#define VENDORID_3COM 0x10b7 77 78/* 79 * 3Com gigabit ethernet device ID 80 */ 81#define DEVICEID_3COM_3C940 0x1700 82 83/* 84 * Linksys PCI vendor ID 85 */ 86#define VENDORID_LINKSYS 0x1737 87 88/* 89 * Linksys gigabit ethernet device ID 90 */ 91#define DEVICEID_LINKSYS_EG1032 0x1032 92 93/* 94 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 95 * but internally it has a 16K register space. This 16K space is 96 * divided into 128-byte blocks. The first 128 bytes of the I/O 97 * window represent the first block, which is permanently mapped 98 * at the start of the window. The other 127 blocks can be mapped 99 * to the second 128 bytes of the I/O window by setting the desired 100 * block value in the RAP register in block 0. Not all of the 127 101 * blocks are actually used. Most registers are 32 bits wide, but 102 * there are a few 16-bit and 8-bit ones as well. 103 */ 104 105 106/* Start of remappable register window. */ 107#define SK_WIN_BASE 0x0080 108 109/* Size of a window */ 110#define SK_WIN_LEN 0x80 111 112#define SK_WIN_MASK 0x3F80 113#define SK_REG_MASK 0x7F 114 115/* Compute the window of a given register (for the RAP register) */ 116#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 117 118/* Compute the relative offset of a register within the window */ 119#define SK_REG(reg) ((reg) & SK_REG_MASK) 120 121#define SK_PORT_A 0 122#define SK_PORT_B 1 123 124/* 125 * Compute offset of port-specific register. Since there are two 126 * ports, there are two of some GEnesis modules (e.g. two sets of 127 * DMA queues, two sets of FIFO control registers, etc...). Normally, 128 * the block for port 0 is at offset 0x0 and the block for port 1 is 129 * at offset 0x80 (i.e. the next page over). However for the transmit 130 * BMUs and RAMbuffers, there are two blocks for each port: one for 131 * the sync transmit queue and one for the async queue (which we don't 132 * use). However instead of ordering them like this: 133 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 134 * SysKonnect has instead ordered them like this: 135 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 136 * This means that when referencing the TX BMU and RAMbuffer registers, 137 * we have to double the block offset (0x80 * 2) in order to reach the 138 * second queue. This prevents us from using the same formula 139 * (sk_port * 0x80) to compute the offsets for all of the port-specific 140 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 141 * The simplest thing is to provide an extra argument to these macros: 142 * the 'skip' parameter. The 'skip' value is the number of extra pages 143 * for skip when computing the port0/port1 offsets. For most registers, 144 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 145 */ 146#define SK_IF_READ_4(sc_if, skip, reg) \ 147 sk_win_read_4(sc_if->sk_softc, reg + \ 148 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 149#define SK_IF_READ_2(sc_if, skip, reg) \ 150 sk_win_read_2(sc_if->sk_softc, reg + \ 151 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 152#define SK_IF_READ_1(sc_if, skip, reg) \ 153 sk_win_read_1(sc_if->sk_softc, reg + \ 154 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 155 156#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 157 sk_win_write_4(sc_if->sk_softc, \ 158 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 159#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 160 sk_win_write_2(sc_if->sk_softc, \ 161 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 162#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 163 sk_win_write_1(sc_if->sk_softc, \ 164 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 165 166/* Block 0 registers, permanently mapped at iobase. */ 167#define SK_RAP 0x0000 168#define SK_CSR 0x0004 169#define SK_LED 0x0006 170#define SK_ISR 0x0008 /* interrupt source */ 171#define SK_IMR 0x000C /* interrupt mask */ 172#define SK_IESR 0x0010 /* interrupt hardware error source */ 173#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 174#define SK_ISSR 0x0018 /* special interrupt source */ 175#define SK_XM_IMR0 0x0020 176#define SK_XM_ISR0 0x0028 177#define SK_XM_PHYADDR0 0x0030 178#define SK_XM_PHYDATA0 0x0034 179#define SK_XM_IMR1 0x0040 180#define SK_XM_ISR1 0x0048 181#define SK_XM_PHYADDR1 0x0050 182#define SK_XM_PHYDATA1 0x0054 183#define SK_BMU_RX_CSR0 0x0060 184#define SK_BMU_RX_CSR1 0x0064 185#define SK_BMU_TXS_CSR0 0x0068 186#define SK_BMU_TXA_CSR0 0x006C 187#define SK_BMU_TXS_CSR1 0x0070 188#define SK_BMU_TXA_CSR1 0x0074 189 190/* SK_CSR register */ 191#define SK_CSR_SW_RESET 0x0001 192#define SK_CSR_SW_UNRESET 0x0002 193#define SK_CSR_MASTER_RESET 0x0004 194#define SK_CSR_MASTER_UNRESET 0x0008 195#define SK_CSR_MASTER_STOP 0x0010 196#define SK_CSR_MASTER_DONE 0x0020 197#define SK_CSR_SW_IRQ_CLEAR 0x0040 198#define SK_CSR_SW_IRQ_SET 0x0080 199#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 200#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 201 202/* SK_LED register */ 203#define SK_LED_GREEN_OFF 0x01 204#define SK_LED_GREEN_ON 0x02 205 206/* SK_ISR register */ 207#define SK_ISR_TX2_AS_CHECK 0x00000001 208#define SK_ISR_TX2_AS_EOF 0x00000002 209#define SK_ISR_TX2_AS_EOB 0x00000004 210#define SK_ISR_TX2_S_CHECK 0x00000008 211#define SK_ISR_TX2_S_EOF 0x00000010 212#define SK_ISR_TX2_S_EOB 0x00000020 213#define SK_ISR_TX1_AS_CHECK 0x00000040 214#define SK_ISR_TX1_AS_EOF 0x00000080 215#define SK_ISR_TX1_AS_EOB 0x00000100 216#define SK_ISR_TX1_S_CHECK 0x00000200 217#define SK_ISR_TX1_S_EOF 0x00000400 218#define SK_ISR_TX1_S_EOB 0x00000800 219#define SK_ISR_RX2_CHECK 0x00001000 220#define SK_ISR_RX2_EOF 0x00002000 221#define SK_ISR_RX2_EOB 0x00004000 222#define SK_ISR_RX1_CHECK 0x00008000 223#define SK_ISR_RX1_EOF 0x00010000 224#define SK_ISR_RX1_EOB 0x00020000 225#define SK_ISR_LINK2_OFLOW 0x00040000 226#define SK_ISR_MAC2 0x00080000 227#define SK_ISR_LINK1_OFLOW 0x00100000 228#define SK_ISR_MAC1 0x00200000 229#define SK_ISR_TIMER 0x00400000 230#define SK_ISR_EXTERNAL_REG 0x00800000 231#define SK_ISR_SW 0x01000000 232#define SK_ISR_I2C_RDY 0x02000000 233#define SK_ISR_TX2_TIMEO 0x04000000 234#define SK_ISR_TX1_TIMEO 0x08000000 235#define SK_ISR_RX2_TIMEO 0x10000000 236#define SK_ISR_RX1_TIMEO 0x20000000 237#define SK_ISR_RSVD 0x40000000 238#define SK_ISR_HWERR 0x80000000 239 240/* SK_IMR register */ 241#define SK_IMR_TX2_AS_CHECK 0x00000001 242#define SK_IMR_TX2_AS_EOF 0x00000002 243#define SK_IMR_TX2_AS_EOB 0x00000004 244#define SK_IMR_TX2_S_CHECK 0x00000008 245#define SK_IMR_TX2_S_EOF 0x00000010 246#define SK_IMR_TX2_S_EOB 0x00000020 247#define SK_IMR_TX1_AS_CHECK 0x00000040 248#define SK_IMR_TX1_AS_EOF 0x00000080 249#define SK_IMR_TX1_AS_EOB 0x00000100 250#define SK_IMR_TX1_S_CHECK 0x00000200 251#define SK_IMR_TX1_S_EOF 0x00000400 252#define SK_IMR_TX1_S_EOB 0x00000800 253#define SK_IMR_RX2_CHECK 0x00001000 254#define SK_IMR_RX2_EOF 0x00002000 255#define SK_IMR_RX2_EOB 0x00004000 256#define SK_IMR_RX1_CHECK 0x00008000 257#define SK_IMR_RX1_EOF 0x00010000 258#define SK_IMR_RX1_EOB 0x00020000 259#define SK_IMR_LINK2_OFLOW 0x00040000 260#define SK_IMR_MAC2 0x00080000 261#define SK_IMR_LINK1_OFLOW 0x00100000 262#define SK_IMR_MAC1 0x00200000 263#define SK_IMR_TIMER 0x00400000 264#define SK_IMR_EXTERNAL_REG 0x00800000 265#define SK_IMR_SW 0x01000000 266#define SK_IMR_I2C_RDY 0x02000000 267#define SK_IMR_TX2_TIMEO 0x04000000 268#define SK_IMR_TX1_TIMEO 0x08000000 269#define SK_IMR_RX2_TIMEO 0x10000000 270#define SK_IMR_RX1_TIMEO 0x20000000 271#define SK_IMR_RSVD 0x40000000 272#define SK_IMR_HWERR 0x80000000 273 274#define SK_INTRS1 \ 275 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 276 277#define SK_INTRS2 \ 278 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 279 280/* SK_IESR register */ 281#define SK_IESR_PAR_RX2 0x00000001 282#define SK_IESR_PAR_RX1 0x00000002 283#define SK_IESR_PAR_MAC2 0x00000004 284#define SK_IESR_PAR_MAC1 0x00000008 285#define SK_IESR_PAR_WR_RAM 0x00000010 286#define SK_IESR_PAR_RD_RAM 0x00000020 287#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 288#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 289#define SK_IESR_NO_STS_MAC2 0x00000100 290#define SK_IESR_NO_STS_MAC1 0x00000200 291#define SK_IESR_IRQ_STS 0x00000400 292#define SK_IESR_MASTERERR 0x00000800 293 294/* SK_IEMR register */ 295#define SK_IEMR_PAR_RX2 0x00000001 296#define SK_IEMR_PAR_RX1 0x00000002 297#define SK_IEMR_PAR_MAC2 0x00000004 298#define SK_IEMR_PAR_MAC1 0x00000008 299#define SK_IEMR_PAR_WR_RAM 0x00000010 300#define SK_IEMR_PAR_RD_RAM 0x00000020 301#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 302#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 303#define SK_IEMR_NO_STS_MAC2 0x00000100 304#define SK_IEMR_NO_STS_MAC1 0x00000200 305#define SK_IEMR_IRQ_STS 0x00000400 306#define SK_IEMR_MASTERERR 0x00000800 307 308/* Block 2 */ 309#define SK_MAC0_0 0x0100 310#define SK_MAC0_1 0x0104 311#define SK_MAC1_0 0x0108 312#define SK_MAC1_1 0x010C 313#define SK_MAC2_0 0x0110 314#define SK_MAC2_1 0x0114 315#define SK_CONNTYPE 0x0118 316#define SK_PMDTYPE 0x0119 317#define SK_CONFIG 0x011A 318#define SK_CHIPVER 0x011B 319#define SK_EPROM0 0x011C 320#define SK_EPROM1 0x011D 321#define SK_EPROM2 0x011E 322#define SK_EPROM3 0x011F 323#define SK_EP_ADDR 0x0120 324#define SK_EP_DATA 0x0124 325#define SK_EP_LOADCTL 0x0128 326#define SK_EP_LOADTST 0x0129 327#define SK_TIMERINIT 0x0130 328#define SK_TIMER 0x0134 329#define SK_TIMERCTL 0x0138 330#define SK_TIMERTST 0x0139 331#define SK_IMTIMERINIT 0x0140 332#define SK_IMTIMER 0x0144 333#define SK_IMTIMERCTL 0x0148 334#define SK_IMTIMERTST 0x0149 335#define SK_IMMR 0x014C 336#define SK_IHWEMR 0x0150 337#define SK_TESTCTL1 0x0158 338#define SK_TESTCTL2 0x0159 339#define SK_GPIO 0x015C 340#define SK_I2CHWCTL 0x0160 341#define SK_I2CHWDATA 0x0164 342#define SK_I2CHWIRQ 0x0168 343#define SK_I2CSW 0x016C 344#define SK_BLNKINIT 0x0170 345#define SK_BLNKCOUNT 0x0174 346#define SK_BLNKCTL 0x0178 347#define SK_BLNKSTS 0x0179 348#define SK_BLNKTST 0x017A 349 350#define SK_IMCTL_STOP 0x02 351#define SK_IMCTL_START 0x04 352 353#define SK_IMTIMER_TICKS 54 354#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 355 356/* 357 * The SK_EPROM0 register contains a byte that describes the 358 * amount of SRAM mounted on the NIC. The value also tells if 359 * the chips are 64K or 128K. This affects the RAMbuffer address 360 * offset that we need to use. 361 */ 362#define SK_RAMSIZE_512K_64 0x1 363#define SK_RAMSIZE_1024K_128 0x2 364#define SK_RAMSIZE_1024K_64 0x3 365#define SK_RAMSIZE_2048K_128 0x4 366 367#define SK_RBOFF_0 0x0 368#define SK_RBOFF_80000 0x80000 369 370/* 371 * SK_EEPROM1 contains the PHY type, which may be XMAC for 372 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 373 * PHY. 374 */ 375#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 376#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 377#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 378#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 379#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 380#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 381 382/* 383 * PHY addresses. 384 */ 385#define SK_PHYADDR_XMAC 0x0 386#define SK_PHYADDR_BCOM 0x1 387#define SK_PHYADDR_LONE 0x3 388#define SK_PHYADDR_NAT 0x0 389#define SK_PHYADDR_MARV 0x0 390 391#define SK_CONFIG_SINGLEMAC 0x01 392#define SK_CONFIG_DIS_DSL_CLK 0x02 393 394#define SK_PMD_1000BASELX 0x4C 395#define SK_PMD_1000BASESX 0x53 396#define SK_PMD_1000BASECX 0x43 397#define SK_PMD_1000BASETX 0x54 398 399/* GPIO bits */ 400#define SK_GPIO_DAT0 0x00000001 401#define SK_GPIO_DAT1 0x00000002 402#define SK_GPIO_DAT2 0x00000004 403#define SK_GPIO_DAT3 0x00000008 404#define SK_GPIO_DAT4 0x00000010 405#define SK_GPIO_DAT5 0x00000020 406#define SK_GPIO_DAT6 0x00000040 407#define SK_GPIO_DAT7 0x00000080 408#define SK_GPIO_DAT8 0x00000100 409#define SK_GPIO_DAT9 0x00000200 410#define SK_GPIO_DIR0 0x00010000 411#define SK_GPIO_DIR1 0x00020000 412#define SK_GPIO_DIR2 0x00040000 413#define SK_GPIO_DIR3 0x00080000 414#define SK_GPIO_DIR4 0x00100000 415#define SK_GPIO_DIR5 0x00200000 416#define SK_GPIO_DIR6 0x00400000 417#define SK_GPIO_DIR7 0x00800000 418#define SK_GPIO_DIR8 0x01000000 419#define SK_GPIO_DIR9 0x02000000 420 421/* Block 3 Ram interface and MAC arbiter registers */ 422#define SK_RAMADDR 0x0180 423#define SK_RAMDATA0 0x0184 424#define SK_RAMDATA1 0x0188 425#define SK_TO0 0x0190 426#define SK_TO1 0x0191 427#define SK_TO2 0x0192 428#define SK_TO3 0x0193 429#define SK_TO4 0x0194 430#define SK_TO5 0x0195 431#define SK_TO6 0x0196 432#define SK_TO7 0x0197 433#define SK_TO8 0x0198 434#define SK_TO9 0x0199 435#define SK_TO10 0x019A 436#define SK_TO11 0x019B 437#define SK_RITIMEO_TMR 0x019C 438#define SK_RAMCTL 0x01A0 439#define SK_RITIMER_TST 0x01A2 440 441#define SK_RAMCTL_RESET 0x0001 442#define SK_RAMCTL_UNRESET 0x0002 443#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 444#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 445 446/* Mac arbiter registers */ 447#define SK_MINIT_RX1 0x01B0 448#define SK_MINIT_RX2 0x01B1 449#define SK_MINIT_TX1 0x01B2 450#define SK_MINIT_TX2 0x01B3 451#define SK_MTIMEO_RX1 0x01B4 452#define SK_MTIMEO_RX2 0x01B5 453#define SK_MTIMEO_TX1 0x01B6 454#define SK_MTIEMO_TX2 0x01B7 455#define SK_MACARB_CTL 0x01B8 456#define SK_MTIMER_TST 0x01BA 457#define SK_RCINIT_RX1 0x01C0 458#define SK_RCINIT_RX2 0x01C1 459#define SK_RCINIT_TX1 0x01C2 460#define SK_RCINIT_TX2 0x01C3 461#define SK_RCTIMEO_RX1 0x01C4 462#define SK_RCTIMEO_RX2 0x01C5 463#define SK_RCTIMEO_TX1 0x01C6 464#define SK_RCTIMEO_TX2 0x01C7 465#define SK_RECOVERY_CTL 0x01C8 466#define SK_RCTIMER_TST 0x01CA 467 468/* Packet arbiter registers */ 469#define SK_RXPA1_TINIT 0x01D0 470#define SK_RXPA2_TINIT 0x01D4 471#define SK_TXPA1_TINIT 0x01D8 472#define SK_TXPA2_TINIT 0x01DC 473#define SK_RXPA1_TIMEO 0x01E0 474#define SK_RXPA2_TIMEO 0x01E4 475#define SK_TXPA1_TIMEO 0x01E8 476#define SK_TXPA2_TIMEO 0x01EC 477#define SK_PKTARB_CTL 0x01F0 478#define SK_PKTATB_TST 0x01F2 479 480#define SK_PKTARB_TIMEOUT 0x2000 481 482#define SK_PKTARBCTL_RESET 0x0001 483#define SK_PKTARBCTL_UNRESET 0x0002 484#define SK_PKTARBCTL_RXTO1_OFF 0x0004 485#define SK_PKTARBCTL_RXTO1_ON 0x0008 486#define SK_PKTARBCTL_RXTO2_OFF 0x0010 487#define SK_PKTARBCTL_RXTO2_ON 0x0020 488#define SK_PKTARBCTL_TXTO1_OFF 0x0040 489#define SK_PKTARBCTL_TXTO1_ON 0x0080 490#define SK_PKTARBCTL_TXTO2_OFF 0x0100 491#define SK_PKTARBCTL_TXTO2_ON 0x0200 492#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 493#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 494#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 495#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 496 497#define SK_MINIT_XMAC_B2 54 498#define SK_MINIT_XMAC_C1 63 499 500#define SK_MACARBCTL_RESET 0x0001 501#define SK_MACARBCTL_UNRESET 0x0002 502#define SK_MACARBCTL_FASTOE_OFF 0x0004 503#define SK_MACARBCRL_FASTOE_ON 0x0008 504 505#define SK_RCINIT_XMAC_B2 54 506#define SK_RCINIT_XMAC_C1 0 507 508#define SK_RECOVERYCTL_RX1_OFF 0x0001 509#define SK_RECOVERYCTL_RX1_ON 0x0002 510#define SK_RECOVERYCTL_RX2_OFF 0x0004 511#define SK_RECOVERYCTL_RX2_ON 0x0008 512#define SK_RECOVERYCTL_TX1_OFF 0x0010 513#define SK_RECOVERYCTL_TX1_ON 0x0020 514#define SK_RECOVERYCTL_TX2_OFF 0x0040 515#define SK_RECOVERYCTL_TX2_ON 0x0080 516 517#define SK_RECOVERY_XMAC_B2 \ 518 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 519 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 520 521#define SK_RECOVERY_XMAC_C1 \ 522 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 523 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 524 525/* Block 4 -- TX Arbiter MAC 1 */ 526#define SK_TXAR1_TIMERINIT 0x0200 527#define SK_TXAR1_TIMERVAL 0x0204 528#define SK_TXAR1_LIMITINIT 0x0208 529#define SK_TXAR1_LIMITCNT 0x020C 530#define SK_TXAR1_COUNTERCTL 0x0210 531#define SK_TXAR1_COUNTERTST 0x0212 532#define SK_TXAR1_COUNTERSTS 0x0212 533 534/* Block 5 -- TX Arbiter MAC 2 */ 535#define SK_TXAR2_TIMERINIT 0x0280 536#define SK_TXAR2_TIMERVAL 0x0284 537#define SK_TXAR2_LIMITINIT 0x0288 538#define SK_TXAR2_LIMITCNT 0x028C 539#define SK_TXAR2_COUNTERCTL 0x0290 540#define SK_TXAR2_COUNTERTST 0x0291 541#define SK_TXAR2_COUNTERSTS 0x0292 542 543#define SK_TXARCTL_OFF 0x01 544#define SK_TXARCTL_ON 0x02 545#define SK_TXARCTL_RATECTL_OFF 0x04 546#define SK_TXARCTL_RATECTL_ON 0x08 547#define SK_TXARCTL_ALLOC_OFF 0x10 548#define SK_TXARCTL_ALLOC_ON 0x20 549#define SK_TXARCTL_FSYNC_OFF 0x40 550#define SK_TXARCTL_FSYNC_ON 0x80 551 552/* Block 6 -- External registers */ 553#define SK_EXTREG_BASE 0x300 554#define SK_EXTREG_END 0x37C 555 556/* Block 7 -- PCI config registers */ 557#define SK_PCI_BASE 0x0380 558#define SK_PCI_END 0x03FC 559 560/* Compute offset of mirrored PCI register */ 561#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 562 563/* Block 8 -- RX queue 1 */ 564#define SK_RXQ1_BUFCNT 0x0400 565#define SK_RXQ1_BUFCTL 0x0402 566#define SK_RXQ1_NEXTDESC 0x0404 567#define SK_RXQ1_RXBUF_LO 0x0408 568#define SK_RXQ1_RXBUF_HI 0x040C 569#define SK_RXQ1_RXSTAT 0x0410 570#define SK_RXQ1_TIMESTAMP 0x0414 571#define SK_RXQ1_CSUM1 0x0418 572#define SK_RXQ1_CSUM2 0x041A 573#define SK_RXQ1_CSUM1_START 0x041C 574#define SK_RXQ1_CSUM2_START 0x041E 575#define SK_RXQ1_CURADDR_LO 0x0420 576#define SK_RXQ1_CURADDR_HI 0x0424 577#define SK_RXQ1_CURCNT_LO 0x0428 578#define SK_RXQ1_CURCNT_HI 0x042C 579#define SK_RXQ1_CURBYTES 0x0430 580#define SK_RXQ1_BMU_CSR 0x0434 581#define SK_RXQ1_WATERMARK 0x0438 582#define SK_RXQ1_FLAG 0x043A 583#define SK_RXQ1_TEST1 0x043C 584#define SK_RXQ1_TEST2 0x0440 585#define SK_RXQ1_TEST3 0x0444 586 587/* Block 9 -- RX queue 2 */ 588#define SK_RXQ2_BUFCNT 0x0480 589#define SK_RXQ2_BUFCTL 0x0482 590#define SK_RXQ2_NEXTDESC 0x0484 591#define SK_RXQ2_RXBUF_LO 0x0488 592#define SK_RXQ2_RXBUF_HI 0x048C 593#define SK_RXQ2_RXSTAT 0x0490 594#define SK_RXQ2_TIMESTAMP 0x0494 595#define SK_RXQ2_CSUM1 0x0498 596#define SK_RXQ2_CSUM2 0x049A 597#define SK_RXQ2_CSUM1_START 0x049C 598#define SK_RXQ2_CSUM2_START 0x049E 599#define SK_RXQ2_CURADDR_LO 0x04A0 600#define SK_RXQ2_CURADDR_HI 0x04A4 601#define SK_RXQ2_CURCNT_LO 0x04A8 602#define SK_RXQ2_CURCNT_HI 0x04AC 603#define SK_RXQ2_CURBYTES 0x04B0 604#define SK_RXQ2_BMU_CSR 0x04B4 605#define SK_RXQ2_WATERMARK 0x04B8 606#define SK_RXQ2_FLAG 0x04BA 607#define SK_RXQ2_TEST1 0x04BC 608#define SK_RXQ2_TEST2 0x04C0 609#define SK_RXQ2_TEST3 0x04C4 610 611#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 612#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 613#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 614#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 615#define SK_RXBMU_RX_START 0x00000010 616#define SK_RXBMU_RX_STOP 0x00000020 617#define SK_RXBMU_POLL_OFF 0x00000040 618#define SK_RXBMU_POLL_ON 0x00000080 619#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 620#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 621#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 622#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 623#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 624#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 625#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 626#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 627#define SK_RXBMU_PFI_SM_RESET 0x00010000 628#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 629#define SK_RXBMU_FIFO_RESET 0x00040000 630#define SK_RXBMU_FIFO_UNRESET 0x00080000 631#define SK_RXBMU_DESC_RESET 0x00100000 632#define SK_RXBMU_DESC_UNRESET 0x00200000 633#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 634 635#define SK_RXBMU_ONLINE \ 636 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 637 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 638 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 639 SK_RXBMU_DESC_UNRESET) 640 641#define SK_RXBMU_OFFLINE \ 642 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 643 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 644 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 645 SK_RXBMU_DESC_RESET) 646 647/* Block 12 -- TX sync queue 1 */ 648#define SK_TXQS1_BUFCNT 0x0600 649#define SK_TXQS1_BUFCTL 0x0602 650#define SK_TXQS1_NEXTDESC 0x0604 651#define SK_TXQS1_RXBUF_LO 0x0608 652#define SK_TXQS1_RXBUF_HI 0x060C 653#define SK_TXQS1_RXSTAT 0x0610 654#define SK_TXQS1_CSUM_STARTVAL 0x0614 655#define SK_TXQS1_CSUM_STARTPOS 0x0618 656#define SK_TXQS1_CSUM_WRITEPOS 0x061A 657#define SK_TXQS1_CURADDR_LO 0x0620 658#define SK_TXQS1_CURADDR_HI 0x0624 659#define SK_TXQS1_CURCNT_LO 0x0628 660#define SK_TXQS1_CURCNT_HI 0x062C 661#define SK_TXQS1_CURBYTES 0x0630 662#define SK_TXQS1_BMU_CSR 0x0634 663#define SK_TXQS1_WATERMARK 0x0638 664#define SK_TXQS1_FLAG 0x063A 665#define SK_TXQS1_TEST1 0x063C 666#define SK_TXQS1_TEST2 0x0640 667#define SK_TXQS1_TEST3 0x0644 668 669/* Block 13 -- TX async queue 1 */ 670#define SK_TXQA1_BUFCNT 0x0680 671#define SK_TXQA1_BUFCTL 0x0682 672#define SK_TXQA1_NEXTDESC 0x0684 673#define SK_TXQA1_RXBUF_LO 0x0688 674#define SK_TXQA1_RXBUF_HI 0x068C 675#define SK_TXQA1_RXSTAT 0x0690 676#define SK_TXQA1_CSUM_STARTVAL 0x0694 677#define SK_TXQA1_CSUM_STARTPOS 0x0698 678#define SK_TXQA1_CSUM_WRITEPOS 0x069A 679#define SK_TXQA1_CURADDR_LO 0x06A0 680#define SK_TXQA1_CURADDR_HI 0x06A4 681#define SK_TXQA1_CURCNT_LO 0x06A8 682#define SK_TXQA1_CURCNT_HI 0x06AC 683#define SK_TXQA1_CURBYTES 0x06B0 684#define SK_TXQA1_BMU_CSR 0x06B4 685#define SK_TXQA1_WATERMARK 0x06B8 686#define SK_TXQA1_FLAG 0x06BA 687#define SK_TXQA1_TEST1 0x06BC 688#define SK_TXQA1_TEST2 0x06C0 689#define SK_TXQA1_TEST3 0x06C4 690 691/* Block 14 -- TX sync queue 2 */ 692#define SK_TXQS2_BUFCNT 0x0700 693#define SK_TXQS2_BUFCTL 0x0702 694#define SK_TXQS2_NEXTDESC 0x0704 695#define SK_TXQS2_RXBUF_LO 0x0708 696#define SK_TXQS2_RXBUF_HI 0x070C 697#define SK_TXQS2_RXSTAT 0x0710 698#define SK_TXQS2_CSUM_STARTVAL 0x0714 699#define SK_TXQS2_CSUM_STARTPOS 0x0718 700#define SK_TXQS2_CSUM_WRITEPOS 0x071A 701#define SK_TXQS2_CURADDR_LO 0x0720 702#define SK_TXQS2_CURADDR_HI 0x0724 703#define SK_TXQS2_CURCNT_LO 0x0728 704#define SK_TXQS2_CURCNT_HI 0x072C 705#define SK_TXQS2_CURBYTES 0x0730 706#define SK_TXQS2_BMU_CSR 0x0734 707#define SK_TXQS2_WATERMARK 0x0738 708#define SK_TXQS2_FLAG 0x073A 709#define SK_TXQS2_TEST1 0x073C 710#define SK_TXQS2_TEST2 0x0740 711#define SK_TXQS2_TEST3 0x0744 712 713/* Block 15 -- TX async queue 2 */ 714#define SK_TXQA2_BUFCNT 0x0780 715#define SK_TXQA2_BUFCTL 0x0782 716#define SK_TXQA2_NEXTDESC 0x0784 717#define SK_TXQA2_RXBUF_LO 0x0788 718#define SK_TXQA2_RXBUF_HI 0x078C 719#define SK_TXQA2_RXSTAT 0x0790 720#define SK_TXQA2_CSUM_STARTVAL 0x0794 721#define SK_TXQA2_CSUM_STARTPOS 0x0798 722#define SK_TXQA2_CSUM_WRITEPOS 0x079A 723#define SK_TXQA2_CURADDR_LO 0x07A0 724#define SK_TXQA2_CURADDR_HI 0x07A4 725#define SK_TXQA2_CURCNT_LO 0x07A8 726#define SK_TXQA2_CURCNT_HI 0x07AC 727#define SK_TXQA2_CURBYTES 0x07B0 728#define SK_TXQA2_BMU_CSR 0x07B4 729#define SK_TXQA2_WATERMARK 0x07B8 730#define SK_TXQA2_FLAG 0x07BA 731#define SK_TXQA2_TEST1 0x07BC 732#define SK_TXQA2_TEST2 0x07C0 733#define SK_TXQA2_TEST3 0x07C4 734 735#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 736#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 737#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 738#define SK_TXBMU_TX_START 0x00000010 739#define SK_TXBMU_TX_STOP 0x00000020 740#define SK_TXBMU_POLL_OFF 0x00000040 741#define SK_TXBMU_POLL_ON 0x00000080 742#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 743#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 744#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 745#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 746#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 747#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 748#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 749#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 750#define SK_TXBMU_PFI_SM_RESET 0x00010000 751#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 752#define SK_TXBMU_FIFO_RESET 0x00040000 753#define SK_TXBMU_FIFO_UNRESET 0x00080000 754#define SK_TXBMU_DESC_RESET 0x00100000 755#define SK_TXBMU_DESC_UNRESET 0x00200000 756#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 757 758#define SK_TXBMU_ONLINE \ 759 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 760 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 761 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 762 SK_TXBMU_DESC_UNRESET) 763 764#define SK_TXBMU_OFFLINE \ 765 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 766 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 767 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 768 SK_TXBMU_DESC_RESET) 769 770/* Block 16 -- Receive RAMbuffer 1 */ 771#define SK_RXRB1_START 0x0800 772#define SK_RXRB1_END 0x0804 773#define SK_RXRB1_WR_PTR 0x0808 774#define SK_RXRB1_RD_PTR 0x080C 775#define SK_RXRB1_UTHR_PAUSE 0x0810 776#define SK_RXRB1_LTHR_PAUSE 0x0814 777#define SK_RXRB1_UTHR_HIPRIO 0x0818 778#define SK_RXRB1_UTHR_LOPRIO 0x081C 779#define SK_RXRB1_PKTCNT 0x0820 780#define SK_RXRB1_LVL 0x0824 781#define SK_RXRB1_CTLTST 0x0828 782 783/* Block 17 -- Receive RAMbuffer 2 */ 784#define SK_RXRB2_START 0x0880 785#define SK_RXRB2_END 0x0884 786#define SK_RXRB2_WR_PTR 0x0888 787#define SK_RXRB2_RD_PTR 0x088C 788#define SK_RXRB2_UTHR_PAUSE 0x0890 789#define SK_RXRB2_LTHR_PAUSE 0x0894 790#define SK_RXRB2_UTHR_HIPRIO 0x0898 791#define SK_RXRB2_UTHR_LOPRIO 0x089C 792#define SK_RXRB2_PKTCNT 0x08A0 793#define SK_RXRB2_LVL 0x08A4 794#define SK_RXRB2_CTLTST 0x08A8 795 796/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 797#define SK_TXRBS1_START 0x0A00 798#define SK_TXRBS1_END 0x0A04 799#define SK_TXRBS1_WR_PTR 0x0A08 800#define SK_TXRBS1_RD_PTR 0x0A0C 801#define SK_TXRBS1_PKTCNT 0x0A20 802#define SK_TXRBS1_LVL 0x0A24 803#define SK_TXRBS1_CTLTST 0x0A28 804 805/* Block 21 -- Async. Transmit RAMbuffer 1 */ 806#define SK_TXRBA1_START 0x0A80 807#define SK_TXRBA1_END 0x0A84 808#define SK_TXRBA1_WR_PTR 0x0A88 809#define SK_TXRBA1_RD_PTR 0x0A8C 810#define SK_TXRBA1_PKTCNT 0x0AA0 811#define SK_TXRBA1_LVL 0x0AA4 812#define SK_TXRBA1_CTLTST 0x0AA8 813 814/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 815#define SK_TXRBS2_START 0x0B00 816#define SK_TXRBS2_END 0x0B04 817#define SK_TXRBS2_WR_PTR 0x0B08 818#define SK_TXRBS2_RD_PTR 0x0B0C 819#define SK_TXRBS2_PKTCNT 0x0B20 820#define SK_TXRBS2_LVL 0x0B24 821#define SK_TXRBS2_CTLTST 0x0B28 822 823/* Block 23 -- Async. Transmit RAMbuffer 2 */ 824#define SK_TXRBA2_START 0x0B80 825#define SK_TXRBA2_END 0x0B84 826#define SK_TXRBA2_WR_PTR 0x0B88 827#define SK_TXRBA2_RD_PTR 0x0B8C 828#define SK_TXRBA2_PKTCNT 0x0BA0 829#define SK_TXRBA2_LVL 0x0BA4 830#define SK_TXRBA2_CTLTST 0x0BA8 831 832#define SK_RBCTL_RESET 0x00000001 833#define SK_RBCTL_UNRESET 0x00000002 834#define SK_RBCTL_OFF 0x00000004 835#define SK_RBCTL_ON 0x00000008 836#define SK_RBCTL_STORENFWD_OFF 0x00000010 837#define SK_RBCTL_STORENFWD_ON 0x00000020 838 839/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 840#define SK_RXF1_END 0x0C00 841#define SK_RXF1_WPTR 0x0C04 842#define SK_RXF1_RPTR 0x0C0C 843#define SK_RXF1_PKTCNT 0x0C10 844#define SK_RXF1_LVL 0x0C14 845#define SK_RXF1_MACCTL 0x0C18 846#define SK_RXF1_CTL 0x0C1C 847#define SK_RXLED1_CNTINIT 0x0C20 848#define SK_RXLED1_COUNTER 0x0C24 849#define SK_RXLED1_CTL 0x0C28 850#define SK_RXLED1_TST 0x0C29 851#define SK_LINK_SYNC1_CINIT 0x0C30 852#define SK_LINK_SYNC1_COUNTER 0x0C34 853#define SK_LINK_SYNC1_CTL 0x0C38 854#define SK_LINK_SYNC1_TST 0x0C39 855#define SK_LINKLED1_CTL 0x0C3C 856 857#define SK_FIFO_END 0x3F 858 859/* Receive MAC FIFO 1 (Yukon Only) */ 860#define SK_RXMF1_END 0x0C40 861#define SK_RXMF1_THRESHOLD 0x0C44 862#define SK_RXMF1_CTRL_TEST 0x0C48 863#define SK_RXMF1_WRITE_PTR 0x0C60 864#define SK_RXMF1_WRITE_LEVEL 0x0C68 865#define SK_RXMF1_READ_PTR 0x0C70 866#define SK_RXMF1_READ_LEVEL 0x0C78 867 868#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 869#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 870#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 871#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 872#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 873#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 874#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 875#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 876#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 877#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 878#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 879#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 880 881/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 882#define SK_RXF2_END 0x0C80 883#define SK_RXF2_WPTR 0x0C84 884#define SK_RXF2_RPTR 0x0C8C 885#define SK_RXF2_PKTCNT 0x0C90 886#define SK_RXF2_LVL 0x0C94 887#define SK_RXF2_MACCTL 0x0C98 888#define SK_RXF2_CTL 0x0C9C 889#define SK_RXLED2_CNTINIT 0x0CA0 890#define SK_RXLED2_COUNTER 0x0CA4 891#define SK_RXLED2_CTL 0x0CA8 892#define SK_RXLED2_TST 0x0CA9 893#define SK_LINK_SYNC2_CINIT 0x0CB0 894#define SK_LINK_SYNC2_COUNTER 0x0CB4 895#define SK_LINK_SYNC2_CTL 0x0CB8 896#define SK_LINK_SYNC2_TST 0x0CB9 897#define SK_LINKLED2_CTL 0x0CBC 898 899#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 900#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 901#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 902#define SK_RXMACCTL_RSTAMP_ON 0x00000008 903#define SK_RXMACCTL_FLUSH_OFF 0x00000010 904#define SK_RXMACCTL_FLUSH_ON 0x00000020 905#define SK_RXMACCTL_PAUSE_OFF 0x00000040 906#define SK_RXMACCTL_PAUSE_ON 0x00000080 907#define SK_RXMACCTL_AFULL_OFF 0x00000100 908#define SK_RXMACCTL_AFULL_ON 0x00000200 909#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 910#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 911#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 912#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 913#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 914#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 915 916#define SK_RXLEDCTL_ENABLE 0x0001 917#define SK_RXLEDCTL_COUNTER_STOP 0x0002 918#define SK_RXLEDCTL_COUNTER_START 0x0004 919 920#define SK_LINKLED_OFF 0x0001 921#define SK_LINKLED_ON 0x0002 922#define SK_LINKLED_LINKSYNC_OFF 0x0004 923#define SK_LINKLED_LINKSYNC_ON 0x0008 924#define SK_LINKLED_BLINK_OFF 0x0010 925#define SK_LINKLED_BLINK_ON 0x0020 926 927/* Block 26 -- TX MAC FIFO 1 regisrers */ 928#define SK_TXF1_END 0x0D00 929#define SK_TXF1_WPTR 0x0D04 930#define SK_TXF1_RPTR 0x0D0C 931#define SK_TXF1_PKTCNT 0x0D10 932#define SK_TXF1_LVL 0x0D14 933#define SK_TXF1_MACCTL 0x0D18 934#define SK_TXF1_CTL 0x0D1C 935#define SK_TXLED1_CNTINIT 0x0D20 936#define SK_TXLED1_COUNTER 0x0D24 937#define SK_TXLED1_CTL 0x0D28 938#define SK_TXLED1_TST 0x0D29 939 940/* Receive MAC FIFO 1 (Yukon Only) */ 941#define SK_TXMF1_END 0x0D40 942#define SK_TXMF1_THRESHOLD 0x0D44 943#define SK_TXMF1_CTRL_TEST 0x0D48 944#define SK_TXMF1_WRITE_PTR 0x0D60 945#define SK_TXMF1_WRITE_SHADOW 0x0D64 946#define SK_TXMF1_WRITE_LEVEL 0x0D68 947#define SK_TXMF1_READ_PTR 0x0D70 948#define SK_TXMF1_RESTART_PTR 0x0D74 949#define SK_TXMF1_READ_LEVEL 0x0D78 950 951#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 952#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 953#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 954#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 955#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 956#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 957#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 958#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 959#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 960#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 961#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 962#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 963#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 964 965/* Block 27 -- TX MAC FIFO 2 regisrers */ 966#define SK_TXF2_END 0x0D80 967#define SK_TXF2_WPTR 0x0D84 968#define SK_TXF2_RPTR 0x0D8C 969#define SK_TXF2_PKTCNT 0x0D90 970#define SK_TXF2_LVL 0x0D94 971#define SK_TXF2_MACCTL 0x0D98 972#define SK_TXF2_CTL 0x0D9C 973#define SK_TXLED2_CNTINIT 0x0DA0 974#define SK_TXLED2_COUNTER 0x0DA4 975#define SK_TXLED2_CTL 0x0DA8 976#define SK_TXLED2_TST 0x0DA9 977 978#define SK_TXMACCTL_XMAC_RESET 0x00000001 979#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 980#define SK_TXMACCTL_LOOP_OFF 0x00000004 981#define SK_TXMACCTL_LOOP_ON 0x00000008 982#define SK_TXMACCTL_FLUSH_OFF 0x00000010 983#define SK_TXMACCTL_FLUSH_ON 0x00000020 984#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 985#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 986#define SK_TXMACCTL_AFULL_OFF 0x00000100 987#define SK_TXMACCTL_AFULL_ON 0x00000200 988#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 989#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 990#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 991#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 992#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 993#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 994 995#define SK_TXLEDCTL_ENABLE 0x0001 996#define SK_TXLEDCTL_COUNTER_STOP 0x0002 997#define SK_TXLEDCTL_COUNTER_START 0x0004 998 999#define SK_FIFO_RESET 0x00000001 1000#define SK_FIFO_UNRESET 0x00000002 1001#define SK_FIFO_OFF 0x00000004 1002#define SK_FIFO_ON 0x00000008 1003 1004/* Block 28 -- Descriptor Poll Timer */ 1005#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1006#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1007 1008#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1009#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1010#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1011 1012#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1013#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1014#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1015#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1016 1017/* Block 29 -- reserved */ 1018 1019/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1020#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1021#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1022#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1023#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1024#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1025#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1026#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1027#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1028#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1029#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1030#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1031#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1032#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1033#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1034#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1035#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1036#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1037#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1038#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1039#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1040#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1041#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1042#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1043#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1044#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1045#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1046#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1047#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1048#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1049 1050#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1051#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1052#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1053#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1054#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1055#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1056 1057#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1058#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1059#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1060#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1061#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1062#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1063#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1064#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1065#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1066#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1067#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1068#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1069#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1070#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1071#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1072#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1073#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1074#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1075#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1076#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1077#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1078#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1079#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1080 1081#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1082 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1083#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1084 SK_GPHY_HWCFG_M_2 ) 1085#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1086 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1087 1088#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1089#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1090#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1091#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1092#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1093#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1094 1095#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1096#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1097 1098/* Block 31 -- reserved */ 1099 1100/* Block 32-33 -- Pattern Ram */ 1101#define SK_WOL_PRAM 0x1000 1102 1103/* Block 0x22 - 0x3f -- reserved */ 1104 1105/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1106#define SK_XMAC1_BASE 0x2000 1107 1108/* Block 0x50 to 0x5F -- MARV 1 registers */ 1109#define SK_MARV1_BASE 0x2800 1110 1111/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1112#define SK_XMAC2_BASE 0x3000 1113 1114/* Block 0x70 to 0x7F -- MARV 2 registers */ 1115#define SK_MARV2_BASE 0x3800 1116 1117/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1118#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1119 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1120 1121#if 0 1122#define SK_XM_READ_4(sc, reg) \ 1123 ((sk_win_read_2(sc->sk_softc, \ 1124 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1125 ((sk_win_read_2(sc->sk_softc, \ 1126 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1127 1128#define SK_XM_WRITE_4(sc, reg, val) \ 1129 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1130 ((val) & 0xFFFF)); \ 1131 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1132 ((val) >> 16) & 0xFFFF) 1133#else 1134#define SK_XM_READ_4(sc, reg) \ 1135 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1136 1137#define SK_XM_WRITE_4(sc, reg, val) \ 1138 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1139#endif 1140 1141#define SK_XM_READ_2(sc, reg) \ 1142 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1143 1144#define SK_XM_WRITE_2(sc, reg, val) \ 1145 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1146 1147#define SK_XM_SETBIT_4(sc, reg, x) \ 1148 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1149 1150#define SK_XM_CLRBIT_4(sc, reg, x) \ 1151 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1152 1153#define SK_XM_SETBIT_2(sc, reg, x) \ 1154 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1155 1156#define SK_XM_CLRBIT_2(sc, reg, x) \ 1157 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1158 1159/* Compute relative offset of an MARV register in the MARV window(s). */ 1160#define SK_YU_REG(sc, reg) \ 1161 ((reg) + SK_MARV1_BASE + \ 1162 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1163 1164#define SK_YU_READ_4(sc, reg) \ 1165 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1166 1167#define SK_YU_READ_2(sc, reg) \ 1168 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1169 1170#define SK_YU_WRITE_4(sc, reg, val) \ 1171 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1172 1173#define SK_YU_WRITE_2(sc, reg, val) \ 1174 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1175 1176#define SK_YU_SETBIT_4(sc, reg, x) \ 1177 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1178 1179#define SK_YU_CLRBIT_4(sc, reg, x) \ 1180 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1181 1182#define SK_YU_SETBIT_2(sc, reg, x) \ 1183 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1184 1185#define SK_YU_CLRBIT_2(sc, reg, x) \ 1186 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1187 1188/* 1189 * The default FIFO threshold on the XMAC II is 4 bytes. On 1190 * dual port NICs, this often leads to transmit underruns, so we 1191 * bump the threshold a little. 1192 */ 1193#define SK_XM_TX_FIFOTHRESH 512 1194 1195#define SK_PCI_VENDOR_ID 0x0000 1196#define SK_PCI_DEVICE_ID 0x0002 1197#define SK_PCI_COMMAND 0x0004 1198#define SK_PCI_STATUS 0x0006 1199#define SK_PCI_REVID 0x0008 1200#define SK_PCI_CLASSCODE 0x0009 1201#define SK_PCI_CACHELEN 0x000C 1202#define SK_PCI_LATENCY_TIMER 0x000D 1203#define SK_PCI_HEADER_TYPE 0x000E 1204#define SK_PCI_LOMEM 0x0010 1205#define SK_PCI_LOIO 0x0014 1206#define SK_PCI_SUBVEN_ID 0x002C 1207#define SK_PCI_SYBSYS_ID 0x002E 1208#define SK_PCI_BIOSROM 0x0030 1209#define SK_PCI_INTLINE 0x003C 1210#define SK_PCI_INTPIN 0x003D 1211#define SK_PCI_MINGNT 0x003E 1212#define SK_PCI_MINLAT 0x003F 1213 1214/* device specific PCI registers */ 1215#define SK_PCI_OURREG1 0x0040 1216#define SK_PCI_OURREG2 0x0044 1217#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1218#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1219#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1220#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1221#define SK_PCI_PME_EVENT 0x004F 1222#define SK_PCI_VPD_CAPID 0x0050 1223#define SK_PCI_VPD_NEXTPTR 0x0051 1224#define SK_PCI_VPD_ADDR 0x0052 1225#define SK_PCI_VPD_DATA 0x0054 1226 1227#define SK_PSTATE_MASK 0x0003 1228#define SK_PSTATE_D0 0x0000 1229#define SK_PSTATE_D1 0x0001 1230#define SK_PSTATE_D2 0x0002 1231#define SK_PSTATE_D3 0x0003 1232#define SK_PME_EN 0x0010 1233#define SK_PME_STATUS 0x8000 1234 1235/* 1236 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1237 * read is complete. Set to 1 to initiate a write, will become 0 1238 * when write is finished. 1239 */ 1240#define SK_VPD_FLAG 0x8000 1241 1242/* VPD structures */ 1243struct vpd_res { 1244 u_int8_t vr_id; 1245 u_int8_t vr_len; 1246 u_int8_t vr_pad; 1247}; 1248 1249struct vpd_key { 1250 char vk_key[2]; 1251 u_int8_t vk_len; 1252}; 1253 1254#define VPD_RES_ID 0x82 /* ID string */ 1255#define VPD_RES_READ 0x90 /* start of read only area */ 1256#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1257#define VPD_RES_END 0x78 /* end tag */ 1258 1259#define CSR_WRITE_4(sc, reg, val) \ 1260 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1261#define CSR_WRITE_2(sc, reg, val) \ 1262 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1263#define CSR_WRITE_1(sc, reg, val) \ 1264 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1265 1266#define CSR_READ_4(sc, reg) \ 1267 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1268#define CSR_READ_2(sc, reg) \ 1269 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1270#define CSR_READ_1(sc, reg) \ 1271 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1272 1273struct sk_type { 1274 u_int16_t sk_vid; 1275 u_int16_t sk_did; 1276 char *sk_name; 1277}; 1278 1279/* RX queue descriptor data structure */ 1280struct sk_rx_desc { 1281 u_int32_t sk_ctl; 1282 u_int32_t sk_next; 1283 u_int32_t sk_data_lo; 1284 u_int32_t sk_data_hi; 1285 u_int32_t sk_xmac_rxstat; 1286 u_int32_t sk_timestamp; 1287 u_int16_t sk_csum2; 1288 u_int16_t sk_csum1; 1289 u_int16_t sk_csum2_start; 1290 u_int16_t sk_csum1_start; 1291}; 1292 1293#define SK_OPCODE_DEFAULT 0x00550000 1294#define SK_OPCODE_CSUM 0x00560000 1295 1296#define SK_RXCTL_LEN 0x0000FFFF 1297#define SK_RXCTL_OPCODE 0x00FF0000 1298#define SK_RXCTL_TSTAMP_VALID 0x01000000 1299#define SK_RXCTL_STATUS_VALID 0x02000000 1300#define SK_RXCTL_DEV0 0x04000000 1301#define SK_RXCTL_EOF_INTR 0x08000000 1302#define SK_RXCTL_EOB_INTR 0x10000000 1303#define SK_RXCTL_LASTFRAG 0x20000000 1304#define SK_RXCTL_FIRSTFRAG 0x40000000 1305#define SK_RXCTL_OWN 0x80000000 1306 1307#define SK_RXSTAT \ 1308 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1309 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1310 1311struct sk_tx_desc { 1312 u_int32_t sk_ctl; 1313 u_int32_t sk_next; 1314 u_int32_t sk_data_lo; 1315 u_int32_t sk_data_hi; 1316 u_int32_t sk_xmac_txstat; 1317 u_int16_t sk_rsvd0; 1318 u_int16_t sk_csum_startval; 1319 u_int16_t sk_csum_startpos; 1320 u_int16_t sk_csum_writepos; 1321 u_int32_t sk_rsvd1; 1322}; 1323 1324#define SK_TXCTL_LEN 0x0000FFFF 1325#define SK_TXCTL_OPCODE 0x00FF0000 1326#define SK_TXCTL_SW 0x01000000 1327#define SK_TXCTL_NOCRC 0x02000000 1328#define SK_TXCTL_STORENFWD 0x04000000 1329#define SK_TXCTL_EOF_INTR 0x08000000 1330#define SK_TXCTL_EOB_INTR 0x10000000 1331#define SK_TXCTL_LASTFRAG 0x20000000 1332#define SK_TXCTL_FIRSTFRAG 0x40000000 1333#define SK_TXCTL_OWN 0x80000000 1334 1335#define SK_TXSTAT \ 1336 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1337 1338#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1339#define SK_TXBYTES SK_RXBYTES 1340 1341#define SK_TX_RING_CNT 512 1342#define SK_RX_RING_CNT 256 1343 1344/* 1345 * Jumbo buffer stuff. Note that we must allocate more jumbo 1346 * buffers than there are descriptors in the receive ring. This 1347 * is because we don't know how long it will take for a packet 1348 * to be released after we hand it off to the upper protocol 1349 * layers. To be safe, we allocate 1.5 times the number of 1350 * receive descriptors. 1351 */ 1352#define SK_JUMBO_FRAMELEN 9018 1353#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1354#define SK_JSLOTS 384 1355 1356#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1357#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1358 (SK_JRAWLEN % sizeof(u_int64_t)))) 1359#define SK_JPAGESZ PAGE_SIZE 1360#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1361#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1362 1363struct sk_jpool_entry { 1364 int slot; 1365 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1366}; 1367 1368struct sk_chain { 1369 void *sk_desc; 1370 struct mbuf *sk_mbuf; 1371 struct sk_chain *sk_next; 1372}; 1373 1374struct sk_chain_data { 1375 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1376 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1377 int sk_tx_prod; 1378 int sk_tx_cons; 1379 int sk_tx_cnt; 1380 int sk_rx_prod; 1381 int sk_rx_cons; 1382 int sk_rx_cnt; 1383 /* Stick the jumbo mem management stuff here too. */ 1384 caddr_t sk_jslots[SK_JSLOTS]; 1385 void *sk_jumbo_buf; 1386 1387}; 1388 1389struct sk_ring_data { 1390 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1391 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1392}; 1393 1394struct sk_bcom_hack { 1395 int reg; 1396 int val; 1397}; 1398 1399#define SK_INC(x, y) (x) = (x + 1) % y 1400 1401/* Forward decl. */ 1402struct sk_if_softc; 1403 1404/* Softc for the GEnesis controller. */ 1405struct sk_softc { 1406 bus_space_handle_t sk_bhandle; /* bus space handle */ 1407 bus_space_tag_t sk_btag; /* bus space tag */ 1408 void *sk_intrhand; /* irq handler handle */ 1409 struct resource *sk_irq; /* IRQ resource handle */ 1410 struct resource *sk_res; /* I/O or shared mem handle */ 1411 u_int8_t sk_unit; /* controller number */ 1412 u_int8_t sk_type; 1413 char *sk_vpd_prodname; 1414 char *sk_vpd_readonly; 1415 u_int32_t sk_rboff; /* RAMbuffer offset */ 1416 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1417 u_int32_t sk_pmd; /* physical media type */ 1418 u_int32_t sk_intrmask; 1419 struct sk_if_softc *sk_if[2]; 1420 device_t sk_devs[2]; 1421 struct mtx sk_mtx; 1422}; 1423 1424#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1425#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1426#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1427#define SK_IF_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mtx) 1428#define SK_IF_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mtx) 1429 1430/* Softc for each logical interface */ 1431struct sk_if_softc { 1432 struct arpcom arpcom; /* interface info */ 1433 device_t sk_miibus; 1434 u_int8_t sk_unit; /* interface number */ 1435 u_int8_t sk_port; /* port # on controller */ 1436 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1437 u_int32_t sk_rx_ramstart; 1438 u_int32_t sk_rx_ramend; 1439 u_int32_t sk_tx_ramstart; 1440 u_int32_t sk_tx_ramend; 1441 int sk_phytype; 1442 int sk_phyaddr; 1443 device_t sk_dev; 1444 int sk_cnt; 1445 int sk_link; 1446 struct callout_handle sk_tick_ch; 1447 struct sk_chain_data sk_cdata; 1448 struct sk_ring_data *sk_rdata; 1449 struct sk_softc *sk_softc; /* parent controller */ 1450 int sk_tx_bmu; /* TX BMU register */ 1451 int sk_if_flags; 1452 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1453 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1454}; 1455 1456#define SK_MAXUNIT 256 1457#define SK_TIMEOUT 1000 1458#define ETHER_ALIGN 2 1459 1460#ifdef __alpha__ 1461#undef vtophys 1462#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1463#endif 1464