if_skreg.h revision 122258
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 122258 2003-11-07 22:04:26Z peter $ 35 */ 36 37/* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart */ 54#define SK_GENESIS 0 55#define SK_YUKON 1 56 57/* 58 * SysKonnect PCI vendor ID 59 */ 60#define VENDORID_SK 0x1148 61 62/* 63 * SK-NET gigabit ethernet device IDs 64 */ 65#define DEVICEID_SK_V1 0x4300 66#define DEVICEID_SK_V2 0x4320 67 68/* 69 * 3Com PCI vendor ID 70 */ 71#define VENDORID_3COM 0x10b7 72 73/* 74 * 3Com gigabit ethernet device ID 75 */ 76#define DEVICEID_3COM_3C940 0x1700 77 78/* 79 * Linksys PCI vendor ID 80 */ 81#define VENDORID_LINKSYS 0x1737 82 83/* 84 * Linksys gigabit ethernet device ID 85 */ 86#define DEVICEID_LINKSYS_EG1032 0x1032 87 88/* 89 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 90 * but internally it has a 16K register space. This 16K space is 91 * divided into 128-byte blocks. The first 128 bytes of the I/O 92 * window represent the first block, which is permanently mapped 93 * at the start of the window. The other 127 blocks can be mapped 94 * to the second 128 bytes of the I/O window by setting the desired 95 * block value in the RAP register in block 0. Not all of the 127 96 * blocks are actually used. Most registers are 32 bits wide, but 97 * there are a few 16-bit and 8-bit ones as well. 98 */ 99 100 101/* Start of remappable register window. */ 102#define SK_WIN_BASE 0x0080 103 104/* Size of a window */ 105#define SK_WIN_LEN 0x80 106 107#define SK_WIN_MASK 0x3F80 108#define SK_REG_MASK 0x7F 109 110/* Compute the window of a given register (for the RAP register) */ 111#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 112 113/* Compute the relative offset of a register within the window */ 114#define SK_REG(reg) ((reg) & SK_REG_MASK) 115 116#define SK_PORT_A 0 117#define SK_PORT_B 1 118 119/* 120 * Compute offset of port-specific register. Since there are two 121 * ports, there are two of some GEnesis modules (e.g. two sets of 122 * DMA queues, two sets of FIFO control registers, etc...). Normally, 123 * the block for port 0 is at offset 0x0 and the block for port 1 is 124 * at offset 0x80 (i.e. the next page over). However for the transmit 125 * BMUs and RAMbuffers, there are two blocks for each port: one for 126 * the sync transmit queue and one for the async queue (which we don't 127 * use). However instead of ordering them like this: 128 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 129 * SysKonnect has instead ordered them like this: 130 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 131 * This means that when referencing the TX BMU and RAMbuffer registers, 132 * we have to double the block offset (0x80 * 2) in order to reach the 133 * second queue. This prevents us from using the same formula 134 * (sk_port * 0x80) to compute the offsets for all of the port-specific 135 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 136 * The simplest thing is to provide an extra argument to these macros: 137 * the 'skip' parameter. The 'skip' value is the number of extra pages 138 * for skip when computing the port0/port1 offsets. For most registers, 139 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 140 */ 141#define SK_IF_READ_4(sc_if, skip, reg) \ 142 sk_win_read_4(sc_if->sk_softc, reg + \ 143 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 144#define SK_IF_READ_2(sc_if, skip, reg) \ 145 sk_win_read_2(sc_if->sk_softc, reg + \ 146 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 147#define SK_IF_READ_1(sc_if, skip, reg) \ 148 sk_win_read_1(sc_if->sk_softc, reg + \ 149 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 150 151#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 152 sk_win_write_4(sc_if->sk_softc, \ 153 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 154#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 155 sk_win_write_2(sc_if->sk_softc, \ 156 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 157#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 158 sk_win_write_1(sc_if->sk_softc, \ 159 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 160 161/* Block 0 registers, permanently mapped at iobase. */ 162#define SK_RAP 0x0000 163#define SK_CSR 0x0004 164#define SK_LED 0x0006 165#define SK_ISR 0x0008 /* interrupt source */ 166#define SK_IMR 0x000C /* interrupt mask */ 167#define SK_IESR 0x0010 /* interrupt hardware error source */ 168#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 169#define SK_ISSR 0x0018 /* special interrupt source */ 170#define SK_XM_IMR0 0x0020 171#define SK_XM_ISR0 0x0028 172#define SK_XM_PHYADDR0 0x0030 173#define SK_XM_PHYDATA0 0x0034 174#define SK_XM_IMR1 0x0040 175#define SK_XM_ISR1 0x0048 176#define SK_XM_PHYADDR1 0x0050 177#define SK_XM_PHYDATA1 0x0054 178#define SK_BMU_RX_CSR0 0x0060 179#define SK_BMU_RX_CSR1 0x0064 180#define SK_BMU_TXS_CSR0 0x0068 181#define SK_BMU_TXA_CSR0 0x006C 182#define SK_BMU_TXS_CSR1 0x0070 183#define SK_BMU_TXA_CSR1 0x0074 184 185/* SK_CSR register */ 186#define SK_CSR_SW_RESET 0x0001 187#define SK_CSR_SW_UNRESET 0x0002 188#define SK_CSR_MASTER_RESET 0x0004 189#define SK_CSR_MASTER_UNRESET 0x0008 190#define SK_CSR_MASTER_STOP 0x0010 191#define SK_CSR_MASTER_DONE 0x0020 192#define SK_CSR_SW_IRQ_CLEAR 0x0040 193#define SK_CSR_SW_IRQ_SET 0x0080 194#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 195#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 196 197/* SK_LED register */ 198#define SK_LED_GREEN_OFF 0x01 199#define SK_LED_GREEN_ON 0x02 200 201/* SK_ISR register */ 202#define SK_ISR_TX2_AS_CHECK 0x00000001 203#define SK_ISR_TX2_AS_EOF 0x00000002 204#define SK_ISR_TX2_AS_EOB 0x00000004 205#define SK_ISR_TX2_S_CHECK 0x00000008 206#define SK_ISR_TX2_S_EOF 0x00000010 207#define SK_ISR_TX2_S_EOB 0x00000020 208#define SK_ISR_TX1_AS_CHECK 0x00000040 209#define SK_ISR_TX1_AS_EOF 0x00000080 210#define SK_ISR_TX1_AS_EOB 0x00000100 211#define SK_ISR_TX1_S_CHECK 0x00000200 212#define SK_ISR_TX1_S_EOF 0x00000400 213#define SK_ISR_TX1_S_EOB 0x00000800 214#define SK_ISR_RX2_CHECK 0x00001000 215#define SK_ISR_RX2_EOF 0x00002000 216#define SK_ISR_RX2_EOB 0x00004000 217#define SK_ISR_RX1_CHECK 0x00008000 218#define SK_ISR_RX1_EOF 0x00010000 219#define SK_ISR_RX1_EOB 0x00020000 220#define SK_ISR_LINK2_OFLOW 0x00040000 221#define SK_ISR_MAC2 0x00080000 222#define SK_ISR_LINK1_OFLOW 0x00100000 223#define SK_ISR_MAC1 0x00200000 224#define SK_ISR_TIMER 0x00400000 225#define SK_ISR_EXTERNAL_REG 0x00800000 226#define SK_ISR_SW 0x01000000 227#define SK_ISR_I2C_RDY 0x02000000 228#define SK_ISR_TX2_TIMEO 0x04000000 229#define SK_ISR_TX1_TIMEO 0x08000000 230#define SK_ISR_RX2_TIMEO 0x10000000 231#define SK_ISR_RX1_TIMEO 0x20000000 232#define SK_ISR_RSVD 0x40000000 233#define SK_ISR_HWERR 0x80000000 234 235/* SK_IMR register */ 236#define SK_IMR_TX2_AS_CHECK 0x00000001 237#define SK_IMR_TX2_AS_EOF 0x00000002 238#define SK_IMR_TX2_AS_EOB 0x00000004 239#define SK_IMR_TX2_S_CHECK 0x00000008 240#define SK_IMR_TX2_S_EOF 0x00000010 241#define SK_IMR_TX2_S_EOB 0x00000020 242#define SK_IMR_TX1_AS_CHECK 0x00000040 243#define SK_IMR_TX1_AS_EOF 0x00000080 244#define SK_IMR_TX1_AS_EOB 0x00000100 245#define SK_IMR_TX1_S_CHECK 0x00000200 246#define SK_IMR_TX1_S_EOF 0x00000400 247#define SK_IMR_TX1_S_EOB 0x00000800 248#define SK_IMR_RX2_CHECK 0x00001000 249#define SK_IMR_RX2_EOF 0x00002000 250#define SK_IMR_RX2_EOB 0x00004000 251#define SK_IMR_RX1_CHECK 0x00008000 252#define SK_IMR_RX1_EOF 0x00010000 253#define SK_IMR_RX1_EOB 0x00020000 254#define SK_IMR_LINK2_OFLOW 0x00040000 255#define SK_IMR_MAC2 0x00080000 256#define SK_IMR_LINK1_OFLOW 0x00100000 257#define SK_IMR_MAC1 0x00200000 258#define SK_IMR_TIMER 0x00400000 259#define SK_IMR_EXTERNAL_REG 0x00800000 260#define SK_IMR_SW 0x01000000 261#define SK_IMR_I2C_RDY 0x02000000 262#define SK_IMR_TX2_TIMEO 0x04000000 263#define SK_IMR_TX1_TIMEO 0x08000000 264#define SK_IMR_RX2_TIMEO 0x10000000 265#define SK_IMR_RX1_TIMEO 0x20000000 266#define SK_IMR_RSVD 0x40000000 267#define SK_IMR_HWERR 0x80000000 268 269#define SK_INTRS1 \ 270 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 271 272#define SK_INTRS2 \ 273 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 274 275/* SK_IESR register */ 276#define SK_IESR_PAR_RX2 0x00000001 277#define SK_IESR_PAR_RX1 0x00000002 278#define SK_IESR_PAR_MAC2 0x00000004 279#define SK_IESR_PAR_MAC1 0x00000008 280#define SK_IESR_PAR_WR_RAM 0x00000010 281#define SK_IESR_PAR_RD_RAM 0x00000020 282#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 283#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 284#define SK_IESR_NO_STS_MAC2 0x00000100 285#define SK_IESR_NO_STS_MAC1 0x00000200 286#define SK_IESR_IRQ_STS 0x00000400 287#define SK_IESR_MASTERERR 0x00000800 288 289/* SK_IEMR register */ 290#define SK_IEMR_PAR_RX2 0x00000001 291#define SK_IEMR_PAR_RX1 0x00000002 292#define SK_IEMR_PAR_MAC2 0x00000004 293#define SK_IEMR_PAR_MAC1 0x00000008 294#define SK_IEMR_PAR_WR_RAM 0x00000010 295#define SK_IEMR_PAR_RD_RAM 0x00000020 296#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 297#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 298#define SK_IEMR_NO_STS_MAC2 0x00000100 299#define SK_IEMR_NO_STS_MAC1 0x00000200 300#define SK_IEMR_IRQ_STS 0x00000400 301#define SK_IEMR_MASTERERR 0x00000800 302 303/* Block 2 */ 304#define SK_MAC0_0 0x0100 305#define SK_MAC0_1 0x0104 306#define SK_MAC1_0 0x0108 307#define SK_MAC1_1 0x010C 308#define SK_MAC2_0 0x0110 309#define SK_MAC2_1 0x0114 310#define SK_CONNTYPE 0x0118 311#define SK_PMDTYPE 0x0119 312#define SK_CONFIG 0x011A 313#define SK_CHIPVER 0x011B 314#define SK_EPROM0 0x011C 315#define SK_EPROM1 0x011D 316#define SK_EPROM2 0x011E 317#define SK_EPROM3 0x011F 318#define SK_EP_ADDR 0x0120 319#define SK_EP_DATA 0x0124 320#define SK_EP_LOADCTL 0x0128 321#define SK_EP_LOADTST 0x0129 322#define SK_TIMERINIT 0x0130 323#define SK_TIMER 0x0134 324#define SK_TIMERCTL 0x0138 325#define SK_TIMERTST 0x0139 326#define SK_IMTIMERINIT 0x0140 327#define SK_IMTIMER 0x0144 328#define SK_IMTIMERCTL 0x0148 329#define SK_IMTIMERTST 0x0149 330#define SK_IMMR 0x014C 331#define SK_IHWEMR 0x0150 332#define SK_TESTCTL1 0x0158 333#define SK_TESTCTL2 0x0159 334#define SK_GPIO 0x015C 335#define SK_I2CHWCTL 0x0160 336#define SK_I2CHWDATA 0x0164 337#define SK_I2CHWIRQ 0x0168 338#define SK_I2CSW 0x016C 339#define SK_BLNKINIT 0x0170 340#define SK_BLNKCOUNT 0x0174 341#define SK_BLNKCTL 0x0178 342#define SK_BLNKSTS 0x0179 343#define SK_BLNKTST 0x017A 344 345#define SK_IMCTL_STOP 0x02 346#define SK_IMCTL_START 0x04 347 348#define SK_IMTIMER_TICKS 54 349#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 350 351/* 352 * The SK_EPROM0 register contains a byte that describes the 353 * amount of SRAM mounted on the NIC. The value also tells if 354 * the chips are 64K or 128K. This affects the RAMbuffer address 355 * offset that we need to use. 356 */ 357#define SK_RAMSIZE_512K_64 0x1 358#define SK_RAMSIZE_1024K_128 0x2 359#define SK_RAMSIZE_1024K_64 0x3 360#define SK_RAMSIZE_2048K_128 0x4 361 362#define SK_RBOFF_0 0x0 363#define SK_RBOFF_80000 0x80000 364 365/* 366 * SK_EEPROM1 contains the PHY type, which may be XMAC for 367 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 368 * PHY. 369 */ 370#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 371#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 372#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 373#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 374#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 375#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 376 377/* 378 * PHY addresses. 379 */ 380#define SK_PHYADDR_XMAC 0x0 381#define SK_PHYADDR_BCOM 0x1 382#define SK_PHYADDR_LONE 0x3 383#define SK_PHYADDR_NAT 0x0 384#define SK_PHYADDR_MARV 0x0 385 386#define SK_CONFIG_SINGLEMAC 0x01 387#define SK_CONFIG_DIS_DSL_CLK 0x02 388 389#define SK_PMD_1000BASELX 0x4C 390#define SK_PMD_1000BASESX 0x53 391#define SK_PMD_1000BASECX 0x43 392#define SK_PMD_1000BASETX 0x54 393 394/* GPIO bits */ 395#define SK_GPIO_DAT0 0x00000001 396#define SK_GPIO_DAT1 0x00000002 397#define SK_GPIO_DAT2 0x00000004 398#define SK_GPIO_DAT3 0x00000008 399#define SK_GPIO_DAT4 0x00000010 400#define SK_GPIO_DAT5 0x00000020 401#define SK_GPIO_DAT6 0x00000040 402#define SK_GPIO_DAT7 0x00000080 403#define SK_GPIO_DAT8 0x00000100 404#define SK_GPIO_DAT9 0x00000200 405#define SK_GPIO_DIR0 0x00010000 406#define SK_GPIO_DIR1 0x00020000 407#define SK_GPIO_DIR2 0x00040000 408#define SK_GPIO_DIR3 0x00080000 409#define SK_GPIO_DIR4 0x00100000 410#define SK_GPIO_DIR5 0x00200000 411#define SK_GPIO_DIR6 0x00400000 412#define SK_GPIO_DIR7 0x00800000 413#define SK_GPIO_DIR8 0x01000000 414#define SK_GPIO_DIR9 0x02000000 415 416/* Block 3 Ram interface and MAC arbiter registers */ 417#define SK_RAMADDR 0x0180 418#define SK_RAMDATA0 0x0184 419#define SK_RAMDATA1 0x0188 420#define SK_TO0 0x0190 421#define SK_TO1 0x0191 422#define SK_TO2 0x0192 423#define SK_TO3 0x0193 424#define SK_TO4 0x0194 425#define SK_TO5 0x0195 426#define SK_TO6 0x0196 427#define SK_TO7 0x0197 428#define SK_TO8 0x0198 429#define SK_TO9 0x0199 430#define SK_TO10 0x019A 431#define SK_TO11 0x019B 432#define SK_RITIMEO_TMR 0x019C 433#define SK_RAMCTL 0x01A0 434#define SK_RITIMER_TST 0x01A2 435 436#define SK_RAMCTL_RESET 0x0001 437#define SK_RAMCTL_UNRESET 0x0002 438#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 439#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 440 441/* Mac arbiter registers */ 442#define SK_MINIT_RX1 0x01B0 443#define SK_MINIT_RX2 0x01B1 444#define SK_MINIT_TX1 0x01B2 445#define SK_MINIT_TX2 0x01B3 446#define SK_MTIMEO_RX1 0x01B4 447#define SK_MTIMEO_RX2 0x01B5 448#define SK_MTIMEO_TX1 0x01B6 449#define SK_MTIEMO_TX2 0x01B7 450#define SK_MACARB_CTL 0x01B8 451#define SK_MTIMER_TST 0x01BA 452#define SK_RCINIT_RX1 0x01C0 453#define SK_RCINIT_RX2 0x01C1 454#define SK_RCINIT_TX1 0x01C2 455#define SK_RCINIT_TX2 0x01C3 456#define SK_RCTIMEO_RX1 0x01C4 457#define SK_RCTIMEO_RX2 0x01C5 458#define SK_RCTIMEO_TX1 0x01C6 459#define SK_RCTIMEO_TX2 0x01C7 460#define SK_RECOVERY_CTL 0x01C8 461#define SK_RCTIMER_TST 0x01CA 462 463/* Packet arbiter registers */ 464#define SK_RXPA1_TINIT 0x01D0 465#define SK_RXPA2_TINIT 0x01D4 466#define SK_TXPA1_TINIT 0x01D8 467#define SK_TXPA2_TINIT 0x01DC 468#define SK_RXPA1_TIMEO 0x01E0 469#define SK_RXPA2_TIMEO 0x01E4 470#define SK_TXPA1_TIMEO 0x01E8 471#define SK_TXPA2_TIMEO 0x01EC 472#define SK_PKTARB_CTL 0x01F0 473#define SK_PKTATB_TST 0x01F2 474 475#define SK_PKTARB_TIMEOUT 0x2000 476 477#define SK_PKTARBCTL_RESET 0x0001 478#define SK_PKTARBCTL_UNRESET 0x0002 479#define SK_PKTARBCTL_RXTO1_OFF 0x0004 480#define SK_PKTARBCTL_RXTO1_ON 0x0008 481#define SK_PKTARBCTL_RXTO2_OFF 0x0010 482#define SK_PKTARBCTL_RXTO2_ON 0x0020 483#define SK_PKTARBCTL_TXTO1_OFF 0x0040 484#define SK_PKTARBCTL_TXTO1_ON 0x0080 485#define SK_PKTARBCTL_TXTO2_OFF 0x0100 486#define SK_PKTARBCTL_TXTO2_ON 0x0200 487#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 488#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 489#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 490#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 491 492#define SK_MINIT_XMAC_B2 54 493#define SK_MINIT_XMAC_C1 63 494 495#define SK_MACARBCTL_RESET 0x0001 496#define SK_MACARBCTL_UNRESET 0x0002 497#define SK_MACARBCTL_FASTOE_OFF 0x0004 498#define SK_MACARBCRL_FASTOE_ON 0x0008 499 500#define SK_RCINIT_XMAC_B2 54 501#define SK_RCINIT_XMAC_C1 0 502 503#define SK_RECOVERYCTL_RX1_OFF 0x0001 504#define SK_RECOVERYCTL_RX1_ON 0x0002 505#define SK_RECOVERYCTL_RX2_OFF 0x0004 506#define SK_RECOVERYCTL_RX2_ON 0x0008 507#define SK_RECOVERYCTL_TX1_OFF 0x0010 508#define SK_RECOVERYCTL_TX1_ON 0x0020 509#define SK_RECOVERYCTL_TX2_OFF 0x0040 510#define SK_RECOVERYCTL_TX2_ON 0x0080 511 512#define SK_RECOVERY_XMAC_B2 \ 513 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 514 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 515 516#define SK_RECOVERY_XMAC_C1 \ 517 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 518 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 519 520/* Block 4 -- TX Arbiter MAC 1 */ 521#define SK_TXAR1_TIMERINIT 0x0200 522#define SK_TXAR1_TIMERVAL 0x0204 523#define SK_TXAR1_LIMITINIT 0x0208 524#define SK_TXAR1_LIMITCNT 0x020C 525#define SK_TXAR1_COUNTERCTL 0x0210 526#define SK_TXAR1_COUNTERTST 0x0212 527#define SK_TXAR1_COUNTERSTS 0x0212 528 529/* Block 5 -- TX Arbiter MAC 2 */ 530#define SK_TXAR2_TIMERINIT 0x0280 531#define SK_TXAR2_TIMERVAL 0x0284 532#define SK_TXAR2_LIMITINIT 0x0288 533#define SK_TXAR2_LIMITCNT 0x028C 534#define SK_TXAR2_COUNTERCTL 0x0290 535#define SK_TXAR2_COUNTERTST 0x0291 536#define SK_TXAR2_COUNTERSTS 0x0292 537 538#define SK_TXARCTL_OFF 0x01 539#define SK_TXARCTL_ON 0x02 540#define SK_TXARCTL_RATECTL_OFF 0x04 541#define SK_TXARCTL_RATECTL_ON 0x08 542#define SK_TXARCTL_ALLOC_OFF 0x10 543#define SK_TXARCTL_ALLOC_ON 0x20 544#define SK_TXARCTL_FSYNC_OFF 0x40 545#define SK_TXARCTL_FSYNC_ON 0x80 546 547/* Block 6 -- External registers */ 548#define SK_EXTREG_BASE 0x300 549#define SK_EXTREG_END 0x37C 550 551/* Block 7 -- PCI config registers */ 552#define SK_PCI_BASE 0x0380 553#define SK_PCI_END 0x03FC 554 555/* Compute offset of mirrored PCI register */ 556#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 557 558/* Block 8 -- RX queue 1 */ 559#define SK_RXQ1_BUFCNT 0x0400 560#define SK_RXQ1_BUFCTL 0x0402 561#define SK_RXQ1_NEXTDESC 0x0404 562#define SK_RXQ1_RXBUF_LO 0x0408 563#define SK_RXQ1_RXBUF_HI 0x040C 564#define SK_RXQ1_RXSTAT 0x0410 565#define SK_RXQ1_TIMESTAMP 0x0414 566#define SK_RXQ1_CSUM1 0x0418 567#define SK_RXQ1_CSUM2 0x041A 568#define SK_RXQ1_CSUM1_START 0x041C 569#define SK_RXQ1_CSUM2_START 0x041E 570#define SK_RXQ1_CURADDR_LO 0x0420 571#define SK_RXQ1_CURADDR_HI 0x0424 572#define SK_RXQ1_CURCNT_LO 0x0428 573#define SK_RXQ1_CURCNT_HI 0x042C 574#define SK_RXQ1_CURBYTES 0x0430 575#define SK_RXQ1_BMU_CSR 0x0434 576#define SK_RXQ1_WATERMARK 0x0438 577#define SK_RXQ1_FLAG 0x043A 578#define SK_RXQ1_TEST1 0x043C 579#define SK_RXQ1_TEST2 0x0440 580#define SK_RXQ1_TEST3 0x0444 581 582/* Block 9 -- RX queue 2 */ 583#define SK_RXQ2_BUFCNT 0x0480 584#define SK_RXQ2_BUFCTL 0x0482 585#define SK_RXQ2_NEXTDESC 0x0484 586#define SK_RXQ2_RXBUF_LO 0x0488 587#define SK_RXQ2_RXBUF_HI 0x048C 588#define SK_RXQ2_RXSTAT 0x0490 589#define SK_RXQ2_TIMESTAMP 0x0494 590#define SK_RXQ2_CSUM1 0x0498 591#define SK_RXQ2_CSUM2 0x049A 592#define SK_RXQ2_CSUM1_START 0x049C 593#define SK_RXQ2_CSUM2_START 0x049E 594#define SK_RXQ2_CURADDR_LO 0x04A0 595#define SK_RXQ2_CURADDR_HI 0x04A4 596#define SK_RXQ2_CURCNT_LO 0x04A8 597#define SK_RXQ2_CURCNT_HI 0x04AC 598#define SK_RXQ2_CURBYTES 0x04B0 599#define SK_RXQ2_BMU_CSR 0x04B4 600#define SK_RXQ2_WATERMARK 0x04B8 601#define SK_RXQ2_FLAG 0x04BA 602#define SK_RXQ2_TEST1 0x04BC 603#define SK_RXQ2_TEST2 0x04C0 604#define SK_RXQ2_TEST3 0x04C4 605 606#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 607#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 608#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 609#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 610#define SK_RXBMU_RX_START 0x00000010 611#define SK_RXBMU_RX_STOP 0x00000020 612#define SK_RXBMU_POLL_OFF 0x00000040 613#define SK_RXBMU_POLL_ON 0x00000080 614#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 615#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 616#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 617#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 618#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 619#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 620#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 621#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 622#define SK_RXBMU_PFI_SM_RESET 0x00010000 623#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 624#define SK_RXBMU_FIFO_RESET 0x00040000 625#define SK_RXBMU_FIFO_UNRESET 0x00080000 626#define SK_RXBMU_DESC_RESET 0x00100000 627#define SK_RXBMU_DESC_UNRESET 0x00200000 628#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 629 630#define SK_RXBMU_ONLINE \ 631 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 632 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 633 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 634 SK_RXBMU_DESC_UNRESET) 635 636#define SK_RXBMU_OFFLINE \ 637 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 638 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 639 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 640 SK_RXBMU_DESC_RESET) 641 642/* Block 12 -- TX sync queue 1 */ 643#define SK_TXQS1_BUFCNT 0x0600 644#define SK_TXQS1_BUFCTL 0x0602 645#define SK_TXQS1_NEXTDESC 0x0604 646#define SK_TXQS1_RXBUF_LO 0x0608 647#define SK_TXQS1_RXBUF_HI 0x060C 648#define SK_TXQS1_RXSTAT 0x0610 649#define SK_TXQS1_CSUM_STARTVAL 0x0614 650#define SK_TXQS1_CSUM_STARTPOS 0x0618 651#define SK_TXQS1_CSUM_WRITEPOS 0x061A 652#define SK_TXQS1_CURADDR_LO 0x0620 653#define SK_TXQS1_CURADDR_HI 0x0624 654#define SK_TXQS1_CURCNT_LO 0x0628 655#define SK_TXQS1_CURCNT_HI 0x062C 656#define SK_TXQS1_CURBYTES 0x0630 657#define SK_TXQS1_BMU_CSR 0x0634 658#define SK_TXQS1_WATERMARK 0x0638 659#define SK_TXQS1_FLAG 0x063A 660#define SK_TXQS1_TEST1 0x063C 661#define SK_TXQS1_TEST2 0x0640 662#define SK_TXQS1_TEST3 0x0644 663 664/* Block 13 -- TX async queue 1 */ 665#define SK_TXQA1_BUFCNT 0x0680 666#define SK_TXQA1_BUFCTL 0x0682 667#define SK_TXQA1_NEXTDESC 0x0684 668#define SK_TXQA1_RXBUF_LO 0x0688 669#define SK_TXQA1_RXBUF_HI 0x068C 670#define SK_TXQA1_RXSTAT 0x0690 671#define SK_TXQA1_CSUM_STARTVAL 0x0694 672#define SK_TXQA1_CSUM_STARTPOS 0x0698 673#define SK_TXQA1_CSUM_WRITEPOS 0x069A 674#define SK_TXQA1_CURADDR_LO 0x06A0 675#define SK_TXQA1_CURADDR_HI 0x06A4 676#define SK_TXQA1_CURCNT_LO 0x06A8 677#define SK_TXQA1_CURCNT_HI 0x06AC 678#define SK_TXQA1_CURBYTES 0x06B0 679#define SK_TXQA1_BMU_CSR 0x06B4 680#define SK_TXQA1_WATERMARK 0x06B8 681#define SK_TXQA1_FLAG 0x06BA 682#define SK_TXQA1_TEST1 0x06BC 683#define SK_TXQA1_TEST2 0x06C0 684#define SK_TXQA1_TEST3 0x06C4 685 686/* Block 14 -- TX sync queue 2 */ 687#define SK_TXQS2_BUFCNT 0x0700 688#define SK_TXQS2_BUFCTL 0x0702 689#define SK_TXQS2_NEXTDESC 0x0704 690#define SK_TXQS2_RXBUF_LO 0x0708 691#define SK_TXQS2_RXBUF_HI 0x070C 692#define SK_TXQS2_RXSTAT 0x0710 693#define SK_TXQS2_CSUM_STARTVAL 0x0714 694#define SK_TXQS2_CSUM_STARTPOS 0x0718 695#define SK_TXQS2_CSUM_WRITEPOS 0x071A 696#define SK_TXQS2_CURADDR_LO 0x0720 697#define SK_TXQS2_CURADDR_HI 0x0724 698#define SK_TXQS2_CURCNT_LO 0x0728 699#define SK_TXQS2_CURCNT_HI 0x072C 700#define SK_TXQS2_CURBYTES 0x0730 701#define SK_TXQS2_BMU_CSR 0x0734 702#define SK_TXQS2_WATERMARK 0x0738 703#define SK_TXQS2_FLAG 0x073A 704#define SK_TXQS2_TEST1 0x073C 705#define SK_TXQS2_TEST2 0x0740 706#define SK_TXQS2_TEST3 0x0744 707 708/* Block 15 -- TX async queue 2 */ 709#define SK_TXQA2_BUFCNT 0x0780 710#define SK_TXQA2_BUFCTL 0x0782 711#define SK_TXQA2_NEXTDESC 0x0784 712#define SK_TXQA2_RXBUF_LO 0x0788 713#define SK_TXQA2_RXBUF_HI 0x078C 714#define SK_TXQA2_RXSTAT 0x0790 715#define SK_TXQA2_CSUM_STARTVAL 0x0794 716#define SK_TXQA2_CSUM_STARTPOS 0x0798 717#define SK_TXQA2_CSUM_WRITEPOS 0x079A 718#define SK_TXQA2_CURADDR_LO 0x07A0 719#define SK_TXQA2_CURADDR_HI 0x07A4 720#define SK_TXQA2_CURCNT_LO 0x07A8 721#define SK_TXQA2_CURCNT_HI 0x07AC 722#define SK_TXQA2_CURBYTES 0x07B0 723#define SK_TXQA2_BMU_CSR 0x07B4 724#define SK_TXQA2_WATERMARK 0x07B8 725#define SK_TXQA2_FLAG 0x07BA 726#define SK_TXQA2_TEST1 0x07BC 727#define SK_TXQA2_TEST2 0x07C0 728#define SK_TXQA2_TEST3 0x07C4 729 730#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 731#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 732#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 733#define SK_TXBMU_TX_START 0x00000010 734#define SK_TXBMU_TX_STOP 0x00000020 735#define SK_TXBMU_POLL_OFF 0x00000040 736#define SK_TXBMU_POLL_ON 0x00000080 737#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 738#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 739#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 740#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 741#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 742#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 743#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 744#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 745#define SK_TXBMU_PFI_SM_RESET 0x00010000 746#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 747#define SK_TXBMU_FIFO_RESET 0x00040000 748#define SK_TXBMU_FIFO_UNRESET 0x00080000 749#define SK_TXBMU_DESC_RESET 0x00100000 750#define SK_TXBMU_DESC_UNRESET 0x00200000 751#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 752 753#define SK_TXBMU_ONLINE \ 754 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 755 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 756 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 757 SK_TXBMU_DESC_UNRESET) 758 759#define SK_TXBMU_OFFLINE \ 760 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 761 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 762 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 763 SK_TXBMU_DESC_RESET) 764 765/* Block 16 -- Receive RAMbuffer 1 */ 766#define SK_RXRB1_START 0x0800 767#define SK_RXRB1_END 0x0804 768#define SK_RXRB1_WR_PTR 0x0808 769#define SK_RXRB1_RD_PTR 0x080C 770#define SK_RXRB1_UTHR_PAUSE 0x0810 771#define SK_RXRB1_LTHR_PAUSE 0x0814 772#define SK_RXRB1_UTHR_HIPRIO 0x0818 773#define SK_RXRB1_UTHR_LOPRIO 0x081C 774#define SK_RXRB1_PKTCNT 0x0820 775#define SK_RXRB1_LVL 0x0824 776#define SK_RXRB1_CTLTST 0x0828 777 778/* Block 17 -- Receive RAMbuffer 2 */ 779#define SK_RXRB2_START 0x0880 780#define SK_RXRB2_END 0x0884 781#define SK_RXRB2_WR_PTR 0x0888 782#define SK_RXRB2_RD_PTR 0x088C 783#define SK_RXRB2_UTHR_PAUSE 0x0890 784#define SK_RXRB2_LTHR_PAUSE 0x0894 785#define SK_RXRB2_UTHR_HIPRIO 0x0898 786#define SK_RXRB2_UTHR_LOPRIO 0x089C 787#define SK_RXRB2_PKTCNT 0x08A0 788#define SK_RXRB2_LVL 0x08A4 789#define SK_RXRB2_CTLTST 0x08A8 790 791/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 792#define SK_TXRBS1_START 0x0A00 793#define SK_TXRBS1_END 0x0A04 794#define SK_TXRBS1_WR_PTR 0x0A08 795#define SK_TXRBS1_RD_PTR 0x0A0C 796#define SK_TXRBS1_PKTCNT 0x0A20 797#define SK_TXRBS1_LVL 0x0A24 798#define SK_TXRBS1_CTLTST 0x0A28 799 800/* Block 21 -- Async. Transmit RAMbuffer 1 */ 801#define SK_TXRBA1_START 0x0A80 802#define SK_TXRBA1_END 0x0A84 803#define SK_TXRBA1_WR_PTR 0x0A88 804#define SK_TXRBA1_RD_PTR 0x0A8C 805#define SK_TXRBA1_PKTCNT 0x0AA0 806#define SK_TXRBA1_LVL 0x0AA4 807#define SK_TXRBA1_CTLTST 0x0AA8 808 809/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 810#define SK_TXRBS2_START 0x0B00 811#define SK_TXRBS2_END 0x0B04 812#define SK_TXRBS2_WR_PTR 0x0B08 813#define SK_TXRBS2_RD_PTR 0x0B0C 814#define SK_TXRBS2_PKTCNT 0x0B20 815#define SK_TXRBS2_LVL 0x0B24 816#define SK_TXRBS2_CTLTST 0x0B28 817 818/* Block 23 -- Async. Transmit RAMbuffer 2 */ 819#define SK_TXRBA2_START 0x0B80 820#define SK_TXRBA2_END 0x0B84 821#define SK_TXRBA2_WR_PTR 0x0B88 822#define SK_TXRBA2_RD_PTR 0x0B8C 823#define SK_TXRBA2_PKTCNT 0x0BA0 824#define SK_TXRBA2_LVL 0x0BA4 825#define SK_TXRBA2_CTLTST 0x0BA8 826 827#define SK_RBCTL_RESET 0x00000001 828#define SK_RBCTL_UNRESET 0x00000002 829#define SK_RBCTL_OFF 0x00000004 830#define SK_RBCTL_ON 0x00000008 831#define SK_RBCTL_STORENFWD_OFF 0x00000010 832#define SK_RBCTL_STORENFWD_ON 0x00000020 833 834/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 835#define SK_RXF1_END 0x0C00 836#define SK_RXF1_WPTR 0x0C04 837#define SK_RXF1_RPTR 0x0C0C 838#define SK_RXF1_PKTCNT 0x0C10 839#define SK_RXF1_LVL 0x0C14 840#define SK_RXF1_MACCTL 0x0C18 841#define SK_RXF1_CTL 0x0C1C 842#define SK_RXLED1_CNTINIT 0x0C20 843#define SK_RXLED1_COUNTER 0x0C24 844#define SK_RXLED1_CTL 0x0C28 845#define SK_RXLED1_TST 0x0C29 846#define SK_LINK_SYNC1_CINIT 0x0C30 847#define SK_LINK_SYNC1_COUNTER 0x0C34 848#define SK_LINK_SYNC1_CTL 0x0C38 849#define SK_LINK_SYNC1_TST 0x0C39 850#define SK_LINKLED1_CTL 0x0C3C 851 852#define SK_FIFO_END 0x3F 853 854/* Receive MAC FIFO 1 (Yukon Only) */ 855#define SK_RXMF1_END 0x0C40 856#define SK_RXMF1_THRESHOLD 0x0C44 857#define SK_RXMF1_CTRL_TEST 0x0C48 858#define SK_RXMF1_WRITE_PTR 0x0C60 859#define SK_RXMF1_WRITE_LEVEL 0x0C68 860#define SK_RXMF1_READ_PTR 0x0C70 861#define SK_RXMF1_READ_LEVEL 0x0C78 862 863#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 864#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 865#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 866#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 867#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 868#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 869#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 870#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 871#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 872#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 873#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 874#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 875 876/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 877#define SK_RXF2_END 0x0C80 878#define SK_RXF2_WPTR 0x0C84 879#define SK_RXF2_RPTR 0x0C8C 880#define SK_RXF2_PKTCNT 0x0C90 881#define SK_RXF2_LVL 0x0C94 882#define SK_RXF2_MACCTL 0x0C98 883#define SK_RXF2_CTL 0x0C9C 884#define SK_RXLED2_CNTINIT 0x0CA0 885#define SK_RXLED2_COUNTER 0x0CA4 886#define SK_RXLED2_CTL 0x0CA8 887#define SK_RXLED2_TST 0x0CA9 888#define SK_LINK_SYNC2_CINIT 0x0CB0 889#define SK_LINK_SYNC2_COUNTER 0x0CB4 890#define SK_LINK_SYNC2_CTL 0x0CB8 891#define SK_LINK_SYNC2_TST 0x0CB9 892#define SK_LINKLED2_CTL 0x0CBC 893 894#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 895#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 896#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 897#define SK_RXMACCTL_RSTAMP_ON 0x00000008 898#define SK_RXMACCTL_FLUSH_OFF 0x00000010 899#define SK_RXMACCTL_FLUSH_ON 0x00000020 900#define SK_RXMACCTL_PAUSE_OFF 0x00000040 901#define SK_RXMACCTL_PAUSE_ON 0x00000080 902#define SK_RXMACCTL_AFULL_OFF 0x00000100 903#define SK_RXMACCTL_AFULL_ON 0x00000200 904#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 905#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 906#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 907#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 908#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 909#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 910 911#define SK_RXLEDCTL_ENABLE 0x0001 912#define SK_RXLEDCTL_COUNTER_STOP 0x0002 913#define SK_RXLEDCTL_COUNTER_START 0x0004 914 915#define SK_LINKLED_OFF 0x0001 916#define SK_LINKLED_ON 0x0002 917#define SK_LINKLED_LINKSYNC_OFF 0x0004 918#define SK_LINKLED_LINKSYNC_ON 0x0008 919#define SK_LINKLED_BLINK_OFF 0x0010 920#define SK_LINKLED_BLINK_ON 0x0020 921 922/* Block 26 -- TX MAC FIFO 1 regisrers */ 923#define SK_TXF1_END 0x0D00 924#define SK_TXF1_WPTR 0x0D04 925#define SK_TXF1_RPTR 0x0D0C 926#define SK_TXF1_PKTCNT 0x0D10 927#define SK_TXF1_LVL 0x0D14 928#define SK_TXF1_MACCTL 0x0D18 929#define SK_TXF1_CTL 0x0D1C 930#define SK_TXLED1_CNTINIT 0x0D20 931#define SK_TXLED1_COUNTER 0x0D24 932#define SK_TXLED1_CTL 0x0D28 933#define SK_TXLED1_TST 0x0D29 934 935/* Receive MAC FIFO 1 (Yukon Only) */ 936#define SK_TXMF1_END 0x0D40 937#define SK_TXMF1_THRESHOLD 0x0D44 938#define SK_TXMF1_CTRL_TEST 0x0D48 939#define SK_TXMF1_WRITE_PTR 0x0D60 940#define SK_TXMF1_WRITE_SHADOW 0x0D64 941#define SK_TXMF1_WRITE_LEVEL 0x0D68 942#define SK_TXMF1_READ_PTR 0x0D70 943#define SK_TXMF1_RESTART_PTR 0x0D74 944#define SK_TXMF1_READ_LEVEL 0x0D78 945 946#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 947#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 948#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 949#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 950#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 951#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 952#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 953#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 954#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 955#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 956#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 957#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 958#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 959 960/* Block 27 -- TX MAC FIFO 2 regisrers */ 961#define SK_TXF2_END 0x0D80 962#define SK_TXF2_WPTR 0x0D84 963#define SK_TXF2_RPTR 0x0D8C 964#define SK_TXF2_PKTCNT 0x0D90 965#define SK_TXF2_LVL 0x0D94 966#define SK_TXF2_MACCTL 0x0D98 967#define SK_TXF2_CTL 0x0D9C 968#define SK_TXLED2_CNTINIT 0x0DA0 969#define SK_TXLED2_COUNTER 0x0DA4 970#define SK_TXLED2_CTL 0x0DA8 971#define SK_TXLED2_TST 0x0DA9 972 973#define SK_TXMACCTL_XMAC_RESET 0x00000001 974#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 975#define SK_TXMACCTL_LOOP_OFF 0x00000004 976#define SK_TXMACCTL_LOOP_ON 0x00000008 977#define SK_TXMACCTL_FLUSH_OFF 0x00000010 978#define SK_TXMACCTL_FLUSH_ON 0x00000020 979#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 980#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 981#define SK_TXMACCTL_AFULL_OFF 0x00000100 982#define SK_TXMACCTL_AFULL_ON 0x00000200 983#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 984#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 985#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 986#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 987#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 988#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 989 990#define SK_TXLEDCTL_ENABLE 0x0001 991#define SK_TXLEDCTL_COUNTER_STOP 0x0002 992#define SK_TXLEDCTL_COUNTER_START 0x0004 993 994#define SK_FIFO_RESET 0x00000001 995#define SK_FIFO_UNRESET 0x00000002 996#define SK_FIFO_OFF 0x00000004 997#define SK_FIFO_ON 0x00000008 998 999/* Block 28 -- Descriptor Poll Timer */ 1000#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1001#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1002 1003#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1004#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1005#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1006 1007#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1008#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1009#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1010#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1011 1012/* Block 29 -- reserved */ 1013 1014/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1015#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1016#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1017#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1018#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1019#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1020#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1021#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1022#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1023#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1024#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1025#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1026#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1027#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1028#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1029#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1030#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1031#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1032#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1033#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1034#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1035#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1036#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1037#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1038#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1039#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1040#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1041#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1042#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1043#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1044 1045#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1046#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1047#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1048#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1049#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1050#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1051 1052#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1053#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1054#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1055#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1056#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1057#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1058#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1059#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1060#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1061#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1062#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1063#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1064#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1065#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1066#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1067#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1068#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1069#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1070#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1071#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1072#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1073#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1074#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1075 1076#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1077 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1078#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1079 SK_GPHY_HWCFG_M_2 ) 1080#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1081 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1082 1083#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1084#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1085#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1086#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1087#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1088#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1089 1090#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1091#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1092 1093/* Block 31 -- reserved */ 1094 1095/* Block 32-33 -- Pattern Ram */ 1096#define SK_WOL_PRAM 0x1000 1097 1098/* Block 0x22 - 0x3f -- reserved */ 1099 1100/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1101#define SK_XMAC1_BASE 0x2000 1102 1103/* Block 0x50 to 0x5F -- MARV 1 registers */ 1104#define SK_MARV1_BASE 0x2800 1105 1106/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1107#define SK_XMAC2_BASE 0x3000 1108 1109/* Block 0x70 to 0x7F -- MARV 2 registers */ 1110#define SK_MARV2_BASE 0x3800 1111 1112/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1113#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1114 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1115 1116#if 0 1117#define SK_XM_READ_4(sc, reg) \ 1118 ((sk_win_read_2(sc->sk_softc, \ 1119 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1120 ((sk_win_read_2(sc->sk_softc, \ 1121 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1122 1123#define SK_XM_WRITE_4(sc, reg, val) \ 1124 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1125 ((val) & 0xFFFF)); \ 1126 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1127 ((val) >> 16) & 0xFFFF) 1128#else 1129#define SK_XM_READ_4(sc, reg) \ 1130 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1131 1132#define SK_XM_WRITE_4(sc, reg, val) \ 1133 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1134#endif 1135 1136#define SK_XM_READ_2(sc, reg) \ 1137 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1138 1139#define SK_XM_WRITE_2(sc, reg, val) \ 1140 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1141 1142#define SK_XM_SETBIT_4(sc, reg, x) \ 1143 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1144 1145#define SK_XM_CLRBIT_4(sc, reg, x) \ 1146 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1147 1148#define SK_XM_SETBIT_2(sc, reg, x) \ 1149 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1150 1151#define SK_XM_CLRBIT_2(sc, reg, x) \ 1152 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1153 1154/* Compute relative offset of an MARV register in the MARV window(s). */ 1155#define SK_YU_REG(sc, reg) \ 1156 ((reg) + SK_MARV1_BASE + \ 1157 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1158 1159#define SK_YU_READ_4(sc, reg) \ 1160 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1161 1162#define SK_YU_READ_2(sc, reg) \ 1163 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1164 1165#define SK_YU_WRITE_4(sc, reg, val) \ 1166 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1167 1168#define SK_YU_WRITE_2(sc, reg, val) \ 1169 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1170 1171#define SK_YU_SETBIT_4(sc, reg, x) \ 1172 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1173 1174#define SK_YU_CLRBIT_4(sc, reg, x) \ 1175 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1176 1177#define SK_YU_SETBIT_2(sc, reg, x) \ 1178 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1179 1180#define SK_YU_CLRBIT_2(sc, reg, x) \ 1181 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1182 1183/* 1184 * The default FIFO threshold on the XMAC II is 4 bytes. On 1185 * dual port NICs, this often leads to transmit underruns, so we 1186 * bump the threshold a little. 1187 */ 1188#define SK_XM_TX_FIFOTHRESH 512 1189 1190#define SK_PCI_VENDOR_ID 0x0000 1191#define SK_PCI_DEVICE_ID 0x0002 1192#define SK_PCI_COMMAND 0x0004 1193#define SK_PCI_STATUS 0x0006 1194#define SK_PCI_REVID 0x0008 1195#define SK_PCI_CLASSCODE 0x0009 1196#define SK_PCI_CACHELEN 0x000C 1197#define SK_PCI_LATENCY_TIMER 0x000D 1198#define SK_PCI_HEADER_TYPE 0x000E 1199#define SK_PCI_LOMEM 0x0010 1200#define SK_PCI_LOIO 0x0014 1201#define SK_PCI_SUBVEN_ID 0x002C 1202#define SK_PCI_SYBSYS_ID 0x002E 1203#define SK_PCI_BIOSROM 0x0030 1204#define SK_PCI_INTLINE 0x003C 1205#define SK_PCI_INTPIN 0x003D 1206#define SK_PCI_MINGNT 0x003E 1207#define SK_PCI_MINLAT 0x003F 1208 1209/* device specific PCI registers */ 1210#define SK_PCI_OURREG1 0x0040 1211#define SK_PCI_OURREG2 0x0044 1212#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1213#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1214#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1215#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1216#define SK_PCI_PME_EVENT 0x004F 1217#define SK_PCI_VPD_CAPID 0x0050 1218#define SK_PCI_VPD_NEXTPTR 0x0051 1219#define SK_PCI_VPD_ADDR 0x0052 1220#define SK_PCI_VPD_DATA 0x0054 1221 1222#define SK_PSTATE_MASK 0x0003 1223#define SK_PSTATE_D0 0x0000 1224#define SK_PSTATE_D1 0x0001 1225#define SK_PSTATE_D2 0x0002 1226#define SK_PSTATE_D3 0x0003 1227#define SK_PME_EN 0x0010 1228#define SK_PME_STATUS 0x8000 1229 1230/* 1231 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1232 * read is complete. Set to 1 to initiate a write, will become 0 1233 * when write is finished. 1234 */ 1235#define SK_VPD_FLAG 0x8000 1236 1237/* VPD structures */ 1238struct vpd_res { 1239 u_int8_t vr_id; 1240 u_int8_t vr_len; 1241 u_int8_t vr_pad; 1242}; 1243 1244struct vpd_key { 1245 char vk_key[2]; 1246 u_int8_t vk_len; 1247}; 1248 1249#define VPD_RES_ID 0x82 /* ID string */ 1250#define VPD_RES_READ 0x90 /* start of read only area */ 1251#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1252#define VPD_RES_END 0x78 /* end tag */ 1253 1254#define CSR_WRITE_4(sc, reg, val) \ 1255 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1256#define CSR_WRITE_2(sc, reg, val) \ 1257 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1258#define CSR_WRITE_1(sc, reg, val) \ 1259 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1260 1261#define CSR_READ_4(sc, reg) \ 1262 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1263#define CSR_READ_2(sc, reg) \ 1264 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1265#define CSR_READ_1(sc, reg) \ 1266 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1267 1268struct sk_type { 1269 u_int16_t sk_vid; 1270 u_int16_t sk_did; 1271 char *sk_name; 1272}; 1273 1274/* RX queue descriptor data structure */ 1275struct sk_rx_desc { 1276 u_int32_t sk_ctl; 1277 u_int32_t sk_next; 1278 u_int32_t sk_data_lo; 1279 u_int32_t sk_data_hi; 1280 u_int32_t sk_xmac_rxstat; 1281 u_int32_t sk_timestamp; 1282 u_int16_t sk_csum2; 1283 u_int16_t sk_csum1; 1284 u_int16_t sk_csum2_start; 1285 u_int16_t sk_csum1_start; 1286}; 1287 1288#define SK_OPCODE_DEFAULT 0x00550000 1289#define SK_OPCODE_CSUM 0x00560000 1290 1291#define SK_RXCTL_LEN 0x0000FFFF 1292#define SK_RXCTL_OPCODE 0x00FF0000 1293#define SK_RXCTL_TSTAMP_VALID 0x01000000 1294#define SK_RXCTL_STATUS_VALID 0x02000000 1295#define SK_RXCTL_DEV0 0x04000000 1296#define SK_RXCTL_EOF_INTR 0x08000000 1297#define SK_RXCTL_EOB_INTR 0x10000000 1298#define SK_RXCTL_LASTFRAG 0x20000000 1299#define SK_RXCTL_FIRSTFRAG 0x40000000 1300#define SK_RXCTL_OWN 0x80000000 1301 1302#define SK_RXSTAT \ 1303 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1304 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1305 1306struct sk_tx_desc { 1307 u_int32_t sk_ctl; 1308 u_int32_t sk_next; 1309 u_int32_t sk_data_lo; 1310 u_int32_t sk_data_hi; 1311 u_int32_t sk_xmac_txstat; 1312 u_int16_t sk_rsvd0; 1313 u_int16_t sk_csum_startval; 1314 u_int16_t sk_csum_startpos; 1315 u_int16_t sk_csum_writepos; 1316 u_int32_t sk_rsvd1; 1317}; 1318 1319#define SK_TXCTL_LEN 0x0000FFFF 1320#define SK_TXCTL_OPCODE 0x00FF0000 1321#define SK_TXCTL_SW 0x01000000 1322#define SK_TXCTL_NOCRC 0x02000000 1323#define SK_TXCTL_STORENFWD 0x04000000 1324#define SK_TXCTL_EOF_INTR 0x08000000 1325#define SK_TXCTL_EOB_INTR 0x10000000 1326#define SK_TXCTL_LASTFRAG 0x20000000 1327#define SK_TXCTL_FIRSTFRAG 0x40000000 1328#define SK_TXCTL_OWN 0x80000000 1329 1330#define SK_TXSTAT \ 1331 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1332 1333#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1334#define SK_TXBYTES SK_RXBYTES 1335 1336#define SK_TX_RING_CNT 512 1337#define SK_RX_RING_CNT 256 1338 1339/* 1340 * Jumbo buffer stuff. Note that we must allocate more jumbo 1341 * buffers than there are descriptors in the receive ring. This 1342 * is because we don't know how long it will take for a packet 1343 * to be released after we hand it off to the upper protocol 1344 * layers. To be safe, we allocate 1.5 times the number of 1345 * receive descriptors. 1346 */ 1347#define SK_JUMBO_FRAMELEN 9018 1348#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1349#define SK_JSLOTS 384 1350 1351#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1352#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1353 (SK_JRAWLEN % sizeof(u_int64_t)))) 1354#define SK_JPAGESZ PAGE_SIZE 1355#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1356#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1357 1358struct sk_jpool_entry { 1359 int slot; 1360 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1361}; 1362 1363struct sk_chain { 1364 void *sk_desc; 1365 struct mbuf *sk_mbuf; 1366 struct sk_chain *sk_next; 1367}; 1368 1369struct sk_chain_data { 1370 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1371 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1372 int sk_tx_prod; 1373 int sk_tx_cons; 1374 int sk_tx_cnt; 1375 int sk_rx_prod; 1376 int sk_rx_cons; 1377 int sk_rx_cnt; 1378 /* Stick the jumbo mem management stuff here too. */ 1379 caddr_t sk_jslots[SK_JSLOTS]; 1380 void *sk_jumbo_buf; 1381 1382}; 1383 1384struct sk_ring_data { 1385 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1386 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1387}; 1388 1389struct sk_bcom_hack { 1390 int reg; 1391 int val; 1392}; 1393 1394#define SK_INC(x, y) (x) = (x + 1) % y 1395 1396/* Forward decl. */ 1397struct sk_if_softc; 1398 1399/* Softc for the GEnesis controller. */ 1400struct sk_softc { 1401 bus_space_handle_t sk_bhandle; /* bus space handle */ 1402 bus_space_tag_t sk_btag; /* bus space tag */ 1403 void *sk_intrhand; /* irq handler handle */ 1404 struct resource *sk_irq; /* IRQ resource handle */ 1405 struct resource *sk_res; /* I/O or shared mem handle */ 1406 u_int8_t sk_unit; /* controller number */ 1407 u_int8_t sk_type; 1408 char *sk_vpd_prodname; 1409 char *sk_vpd_readonly; 1410 u_int32_t sk_rboff; /* RAMbuffer offset */ 1411 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1412 u_int32_t sk_pmd; /* physical media type */ 1413 u_int32_t sk_intrmask; 1414 struct sk_if_softc *sk_if[2]; 1415 device_t sk_devs[2]; 1416 struct mtx sk_mtx; 1417}; 1418 1419#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1420#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1421#define SK_IF_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mtx) 1422#define SK_IF_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mtx) 1423 1424/* Softc for each logical interface */ 1425struct sk_if_softc { 1426 struct arpcom arpcom; /* interface info */ 1427 device_t sk_miibus; 1428 u_int8_t sk_unit; /* interface number */ 1429 u_int8_t sk_port; /* port # on controller */ 1430 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1431 u_int32_t sk_rx_ramstart; 1432 u_int32_t sk_rx_ramend; 1433 u_int32_t sk_tx_ramstart; 1434 u_int32_t sk_tx_ramend; 1435 int sk_phytype; 1436 int sk_phyaddr; 1437 device_t sk_dev; 1438 int sk_cnt; 1439 int sk_link; 1440 struct callout_handle sk_tick_ch; 1441 struct sk_chain_data sk_cdata; 1442 struct sk_ring_data *sk_rdata; 1443 struct sk_softc *sk_softc; /* parent controller */ 1444 int sk_tx_bmu; /* TX BMU register */ 1445 int sk_if_flags; 1446 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1447 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1448}; 1449 1450#define SK_MAXUNIT 256 1451#define SK_TIMEOUT 1000 1452#define ETHER_ALIGN 2 1453 1454#ifdef __alpha__ 1455#undef vtophys 1456#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1457#endif 1458