efx_regs_pci.h revision 283514
155714Skris/*- 255714Skris * Copyright (c) 2007-2015 Solarflare Communications Inc. 355714Skris * All rights reserved. 455714Skris * 555714Skris * Redistribution and use in source and binary forms, with or without 655714Skris * modification, are permitted provided that the following conditions are met: 755714Skris * 855714Skris * 1. Redistributions of source code must retain the above copyright notice, 955714Skris * this list of conditions and the following disclaimer. 1055714Skris * 2. Redistributions in binary form must reproduce the above copyright notice, 1155714Skris * this list of conditions and the following disclaimer in the documentation 1255714Skris * and/or other materials provided with the distribution. 1355714Skris * 1455714Skris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1555714Skris * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 1655714Skris * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 1755714Skris * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 1855714Skris * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 1955714Skris * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2055714Skris * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2155714Skris * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2255714Skris * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2355714Skris * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 2455714Skris * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2555714Skris * 2655714Skris * The views and conclusions contained in the software and documentation are 2755714Skris * those of the authors and should not be interpreted as representing official 2855714Skris * policies, either expressed or implied, of the FreeBSD Project. 2955714Skris * 3055714Skris * $FreeBSD: head/sys/dev/sfxge/common/efx_regs_pci.h 283514 2015-05-25 08:34:55Z arybchik $ 3155714Skris */ 3255714Skris 3355714Skris#ifndef _SYS_EFX_REGS_PCI_H 3455714Skris#define _SYS_EFX_REGS_PCI_H 3555714Skris 3655714Skris#ifdef __cplusplus 3755714Skrisextern "C" { 3855714Skris#endif 3955714Skris 4055714Skris/* 4155714Skris * PC_VEND_ID_REG(16bit): 4255714Skris * Vendor ID register 4355714Skris */ 4455714Skris 4555714Skris#define PCR_AZ_VEND_ID_REG 0x00000000 4655714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 4755714Skris 4855714Skris#define PCRF_AZ_VEND_ID_LBN 0 4955714Skris#define PCRF_AZ_VEND_ID_WIDTH 16 5055714Skris 5155714Skris 5255714Skris/* 5355714Skris * PC_DEV_ID_REG(16bit): 5455714Skris * Device ID register 5555714Skris */ 5655714Skris 5755714Skris#define PCR_AZ_DEV_ID_REG 0x00000002 5855714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 5955714Skris 60109998Smarkm#define PCRF_AZ_DEV_ID_LBN 0 61109998Smarkm#define PCRF_AZ_DEV_ID_WIDTH 16 62109998Smarkm 63109998Smarkm 64109998Smarkm/* 65109998Smarkm * PC_CMD_REG(16bit): 66109998Smarkm * Command register 67109998Smarkm */ 68109998Smarkm 69109998Smarkm#define PCR_AZ_CMD_REG 0x00000004 70109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 71109998Smarkm 72109998Smarkm#define PCRF_AZ_INTX_DIS_LBN 10 73109998Smarkm#define PCRF_AZ_INTX_DIS_WIDTH 1 74109998Smarkm#define PCRF_AZ_FB2B_EN_LBN 9 75109998Smarkm#define PCRF_AZ_FB2B_EN_WIDTH 1 76109998Smarkm#define PCRF_AZ_SERR_EN_LBN 8 77109998Smarkm#define PCRF_AZ_SERR_EN_WIDTH 1 78109998Smarkm#define PCRF_AZ_IDSEL_CTL_LBN 7 79109998Smarkm#define PCRF_AZ_IDSEL_CTL_WIDTH 1 80109998Smarkm#define PCRF_AZ_PERR_EN_LBN 6 81109998Smarkm#define PCRF_AZ_PERR_EN_WIDTH 1 82109998Smarkm#define PCRF_AZ_VGA_PAL_SNP_LBN 5 83109998Smarkm#define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 84109998Smarkm#define PCRF_AZ_MWI_EN_LBN 4 85109998Smarkm#define PCRF_AZ_MWI_EN_WIDTH 1 86109998Smarkm#define PCRF_AZ_SPEC_CYC_LBN 3 87109998Smarkm#define PCRF_AZ_SPEC_CYC_WIDTH 1 88109998Smarkm#define PCRF_AZ_MST_EN_LBN 2 89109998Smarkm#define PCRF_AZ_MST_EN_WIDTH 1 90109998Smarkm#define PCRF_AZ_MEM_EN_LBN 1 91109998Smarkm#define PCRF_AZ_MEM_EN_WIDTH 1 92109998Smarkm#define PCRF_AZ_IO_EN_LBN 0 93109998Smarkm#define PCRF_AZ_IO_EN_WIDTH 1 94109998Smarkm 95109998Smarkm 96109998Smarkm/* 97109998Smarkm * PC_STAT_REG(16bit): 98109998Smarkm * Status register 99109998Smarkm */ 100109998Smarkm 101109998Smarkm#define PCR_AZ_STAT_REG 0x00000006 102109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 103109998Smarkm 104109998Smarkm#define PCRF_AZ_DET_PERR_LBN 15 105109998Smarkm#define PCRF_AZ_DET_PERR_WIDTH 1 106109998Smarkm#define PCRF_AZ_SIG_SERR_LBN 14 107109998Smarkm#define PCRF_AZ_SIG_SERR_WIDTH 1 108109998Smarkm#define PCRF_AZ_GOT_MABRT_LBN 13 109109998Smarkm#define PCRF_AZ_GOT_MABRT_WIDTH 1 110109998Smarkm#define PCRF_AZ_GOT_TABRT_LBN 12 111109998Smarkm#define PCRF_AZ_GOT_TABRT_WIDTH 1 112109998Smarkm#define PCRF_AZ_SIG_TABRT_LBN 11 113160814Ssimon#define PCRF_AZ_SIG_TABRT_WIDTH 1 114160814Ssimon#define PCRF_AZ_DEVSEL_TIM_LBN 9 115160814Ssimon#define PCRF_AZ_DEVSEL_TIM_WIDTH 2 116160814Ssimon#define PCRF_AZ_MDAT_PERR_LBN 8 117160814Ssimon#define PCRF_AZ_MDAT_PERR_WIDTH 1 11855714Skris#define PCRF_AZ_FB2B_CAP_LBN 7 119109998Smarkm#define PCRF_AZ_FB2B_CAP_WIDTH 1 120109998Smarkm#define PCRF_AZ_66MHZ_CAP_LBN 5 121109998Smarkm#define PCRF_AZ_66MHZ_CAP_WIDTH 1 12255714Skris#define PCRF_AZ_CAP_LIST_LBN 4 123109998Smarkm#define PCRF_AZ_CAP_LIST_WIDTH 1 124109998Smarkm#define PCRF_AZ_INTX_STAT_LBN 3 12555714Skris#define PCRF_AZ_INTX_STAT_WIDTH 1 12655714Skris 12759191Skris 128160814Ssimon/* 129160814Ssimon * PC_REV_ID_REG(8bit): 130160814Ssimon * Class code & revision ID register 13155714Skris */ 13259191Skris 13355714Skris#define PCR_AZ_REV_ID_REG 0x00000008 134160814Ssimon/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 13559191Skris 13659191Skris#define PCRF_AZ_REV_ID_LBN 0 13759191Skris#define PCRF_AZ_REV_ID_WIDTH 8 13855714Skris 13959191Skris 14059191Skris/* 141160814Ssimon * PC_CC_REG(24bit): 142160814Ssimon * Class code register 143160814Ssimon */ 144160814Ssimon 145160814Ssimon#define PCR_AZ_CC_REG 0x00000009 146160814Ssimon/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 147160814Ssimon 148160814Ssimon#define PCRF_AZ_BASE_CC_LBN 16 14955714Skris#define PCRF_AZ_BASE_CC_WIDTH 8 15055714Skris#define PCRF_AZ_SUB_CC_LBN 8 15155714Skris#define PCRF_AZ_SUB_CC_WIDTH 8 15255714Skris#define PCRF_AZ_PROG_IF_LBN 0 15355714Skris#define PCRF_AZ_PROG_IF_WIDTH 8 15455714Skris 15555714Skris 15655714Skris/* 15755714Skris * PC_CACHE_LSIZE_REG(8bit): 15855714Skris * Cache line size 15955714Skris */ 160100928Snectar 161100928Snectar#define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 162100928Snectar/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 163100928Snectar 164100928Snectar#define PCRF_AZ_CACHE_LSIZE_LBN 0 165100928Snectar#define PCRF_AZ_CACHE_LSIZE_WIDTH 8 16655714Skris 16755714Skris 16855714Skris/* 16955714Skris * PC_MST_LAT_REG(8bit): 17059191Skris * Master latency timer register 17159191Skris */ 17255714Skris 17355714Skris#define PCR_AZ_MST_LAT_REG 0x0000000d 17455714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 17559191Skris 17659191Skris#define PCRF_AZ_MST_LAT_LBN 0 17759191Skris#define PCRF_AZ_MST_LAT_WIDTH 8 178109998Smarkm 17959191Skris 18059191Skris/* 18155714Skris * PC_HDR_TYPE_REG(8bit): 18255714Skris * Header type register 18355714Skris */ 18455714Skris 18555714Skris#define PCR_AZ_HDR_TYPE_REG 0x0000000e 18655714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 18755714Skris 18855714Skris#define PCRF_AZ_MULT_FUNC_LBN 7 18955714Skris#define PCRF_AZ_MULT_FUNC_WIDTH 1 19055714Skris#define PCRF_AZ_TYPE_LBN 0 19172613Skris#define PCRF_AZ_TYPE_WIDTH 7 19255714Skris 19372613Skris 19455714Skris/* 19555714Skris * PC_BIST_REG(8bit): 19655714Skris * BIST register 19755714Skris */ 19855714Skris 19955714Skris#define PCR_AZ_BIST_REG 0x0000000f 20055714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 20155714Skris 20255714Skris#define PCRF_AZ_BIST_LBN 0 20355714Skris#define PCRF_AZ_BIST_WIDTH 8 20455714Skris 20555714Skris 20655714Skris/* 20755714Skris * PC_BAR0_REG(32bit): 20889837Skris * Primary function base address register 0 20955714Skris */ 21055714Skris 21155714Skris#define PCR_AZ_BAR0_REG 0x00000010 21255714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 21355714Skris 21455714Skris#define PCRF_AZ_BAR0_LBN 4 21555714Skris#define PCRF_AZ_BAR0_WIDTH 28 21655714Skris#define PCRF_AZ_BAR0_PREF_LBN 3 21755714Skris#define PCRF_AZ_BAR0_PREF_WIDTH 1 21855714Skris#define PCRF_AZ_BAR0_TYPE_LBN 1 21955714Skris#define PCRF_AZ_BAR0_TYPE_WIDTH 2 22055714Skris#define PCRF_AZ_BAR0_IOM_LBN 0 22155714Skris#define PCRF_AZ_BAR0_IOM_WIDTH 1 22255714Skris 22355714Skris 22455714Skris/* 22555714Skris * PC_BAR1_REG(32bit): 22655714Skris * Primary function base address register 1, BAR1 is not implemented so read only. 22755714Skris */ 22855714Skris 22955714Skris#define PCR_DZ_BAR1_REG 0x00000014 23055714Skris/* hunta0=pci_f0_config */ 23155714Skris 23255714Skris#define PCRF_DZ_BAR1_LBN 0 23355714Skris#define PCRF_DZ_BAR1_WIDTH 32 23455714Skris 23555714Skris 23655714Skris/* 23755714Skris * PC_BAR2_LO_REG(32bit): 23855714Skris * Primary function base address register 2 low bits 23955714Skris */ 24055714Skris 24155714Skris#define PCR_AZ_BAR2_LO_REG 0x00000018 24255714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 24355714Skris 24455714Skris#define PCRF_AZ_BAR2_LO_LBN 4 24555714Skris#define PCRF_AZ_BAR2_LO_WIDTH 28 24655714Skris#define PCRF_AZ_BAR2_PREF_LBN 3 24755714Skris#define PCRF_AZ_BAR2_PREF_WIDTH 1 24855714Skris#define PCRF_AZ_BAR2_TYPE_LBN 1 24955714Skris#define PCRF_AZ_BAR2_TYPE_WIDTH 2 25055714Skris#define PCRF_AZ_BAR2_IOM_LBN 0 25155714Skris#define PCRF_AZ_BAR2_IOM_WIDTH 1 25255714Skris 25368651Skris 25455714Skris/* 25555714Skris * PC_BAR2_HI_REG(32bit): 25655714Skris * Primary function base address register 2 high bits 257109998Smarkm */ 258109998Smarkm 259109998Smarkm#define PCR_AZ_BAR2_HI_REG 0x0000001c 260109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 261109998Smarkm 262109998Smarkm#define PCRF_AZ_BAR2_HI_LBN 0 263109998Smarkm#define PCRF_AZ_BAR2_HI_WIDTH 32 264109998Smarkm 26555714Skris 26655714Skris/* 26755714Skris * PC_BAR4_LO_REG(32bit): 26855714Skris * Primary function base address register 2 low bits 26955714Skris */ 27055714Skris 27155714Skris#define PCR_CZ_BAR4_LO_REG 0x00000020 27255714Skris/* sienaa0,hunta0=pci_f0_config */ 27355714Skris 27455714Skris#define PCRF_CZ_BAR4_LO_LBN 4 27555714Skris#define PCRF_CZ_BAR4_LO_WIDTH 28 27655714Skris#define PCRF_CZ_BAR4_PREF_LBN 3 27755714Skris#define PCRF_CZ_BAR4_PREF_WIDTH 1 27855714Skris#define PCRF_CZ_BAR4_TYPE_LBN 1 27955714Skris#define PCRF_CZ_BAR4_TYPE_WIDTH 2 28055714Skris#define PCRF_CZ_BAR4_IOM_LBN 0 28155714Skris#define PCRF_CZ_BAR4_IOM_WIDTH 1 28255714Skris 283109998Smarkm 284109998Smarkm/* 285109998Smarkm * PC_BAR4_HI_REG(32bit): 286109998Smarkm * Primary function base address register 2 high bits 287109998Smarkm */ 288160814Ssimon 289109998Smarkm#define PCR_CZ_BAR4_HI_REG 0x00000024 290160814Ssimon/* sienaa0,hunta0=pci_f0_config */ 29155714Skris 292109998Smarkm#define PCRF_CZ_BAR4_HI_LBN 0 29355714Skris#define PCRF_CZ_BAR4_HI_WIDTH 32 29455714Skris 295109998Smarkm 296160814Ssimon/* 297160814Ssimon * PC_SS_VEND_ID_REG(16bit): 298160814Ssimon * Sub-system vendor ID register 299160814Ssimon */ 300160814Ssimon 301160814Ssimon#define PCR_AZ_SS_VEND_ID_REG 0x0000002c 30259191Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 30359191Skris 304160814Ssimon#define PCRF_AZ_SS_VEND_ID_LBN 0 305109998Smarkm#define PCRF_AZ_SS_VEND_ID_WIDTH 16 306109998Smarkm 30755714Skris 30855714Skris/* 30955714Skris * PC_SS_ID_REG(16bit): 31055714Skris * Sub-system ID register 31155714Skris */ 31255714Skris 31355714Skris#define PCR_AZ_SS_ID_REG 0x0000002e 31455714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 31555714Skris 31655714Skris#define PCRF_AZ_SS_ID_LBN 0 31755714Skris#define PCRF_AZ_SS_ID_WIDTH 16 31855714Skris 319109998Smarkm 32055714Skris/* 32155714Skris * PC_EXPROM_BAR_REG(32bit): 322109998Smarkm * Expansion ROM base address register 32355714Skris */ 32455714Skris 32555714Skris#define PCR_AZ_EXPROM_BAR_REG 0x00000030 32655714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 32755714Skris 32855714Skris#define PCRF_AZ_EXPROM_BAR_LBN 11 32955714Skris#define PCRF_AZ_EXPROM_BAR_WIDTH 21 33055714Skris#define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 33155714Skris#define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 33268651Skris#define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 33355714Skris#define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 33455714Skris#define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 33555714Skris#define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 33655714Skris#define PCRF_AZ_EXPROM_EN_LBN 0 33755714Skris#define PCRF_AZ_EXPROM_EN_WIDTH 1 33855714Skris 33955714Skris 34055714Skris/* 341109998Smarkm * PC_CAP_PTR_REG(8bit): 34255714Skris * Capability pointer register 34355714Skris */ 34455714Skris 34555714Skris#define PCR_AZ_CAP_PTR_REG 0x00000034 34655714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 34755714Skris 34855714Skris#define PCRF_AZ_CAP_PTR_LBN 0 34955714Skris#define PCRF_AZ_CAP_PTR_WIDTH 8 35055714Skris 35155714Skris 35255714Skris/* 35355714Skris * PC_INT_LINE_REG(8bit): 35455714Skris * Interrupt line register 35555714Skris */ 35655714Skris 35755714Skris#define PCR_AZ_INT_LINE_REG 0x0000003c 35855714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 35955714Skris 36055714Skris#define PCRF_AZ_INT_LINE_LBN 0 36155714Skris#define PCRF_AZ_INT_LINE_WIDTH 8 36255714Skris 36355714Skris 36455714Skris/* 36555714Skris * PC_INT_PIN_REG(8bit): 366109998Smarkm * Interrupt pin register 367109998Smarkm */ 368109998Smarkm 369109998Smarkm#define PCR_AZ_INT_PIN_REG 0x0000003d 370109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 371109998Smarkm 37259191Skris#define PCRF_AZ_INT_PIN_LBN 0 373109998Smarkm#define PCRF_AZ_INT_PIN_WIDTH 8 374109998Smarkm#define PCFE_DZ_INTPIN_INTD 4 375109998Smarkm#define PCFE_DZ_INTPIN_INTC 3 376109998Smarkm#define PCFE_DZ_INTPIN_INTB 2 377109998Smarkm#define PCFE_DZ_INTPIN_INTA 1 378109998Smarkm 37959191Skris 380109998Smarkm/* 38159191Skris * PC_PM_CAP_ID_REG(8bit): 382109998Smarkm * Power management capability ID 383109998Smarkm */ 384109998Smarkm 385109998Smarkm#define PCR_AZ_PM_CAP_ID_REG 0x00000040 386109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 387109998Smarkm 388109998Smarkm#define PCRF_AZ_PM_CAP_ID_LBN 0 389109998Smarkm#define PCRF_AZ_PM_CAP_ID_WIDTH 8 390109998Smarkm 391109998Smarkm 392109998Smarkm/* 39359191Skris * PC_PM_NXT_PTR_REG(8bit): 394109998Smarkm * Power management next item pointer 395109998Smarkm */ 396109998Smarkm 397109998Smarkm#define PCR_AZ_PM_NXT_PTR_REG 0x00000041 398109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 399109998Smarkm 400109998Smarkm#define PCRF_AZ_PM_NXT_PTR_LBN 0 401109998Smarkm#define PCRF_AZ_PM_NXT_PTR_WIDTH 8 402109998Smarkm 403109998Smarkm 404109998Smarkm/* 405109998Smarkm * PC_PM_CAP_REG(16bit): 406109998Smarkm * Power management capabilities register 407109998Smarkm */ 408109998Smarkm 409109998Smarkm#define PCR_AZ_PM_CAP_REG 0x00000042 410109998Smarkm/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 411109998Smarkm 412109998Smarkm#define PCRF_AZ_PM_PME_SUPT_LBN 11 413109998Smarkm#define PCRF_AZ_PM_PME_SUPT_WIDTH 5 41459191Skris#define PCRF_AZ_PM_D2_SUPT_LBN 10 415109998Smarkm#define PCRF_AZ_PM_D2_SUPT_WIDTH 1 416109998Smarkm#define PCRF_AZ_PM_D1_SUPT_LBN 9 417109998Smarkm#define PCRF_AZ_PM_D1_SUPT_WIDTH 1 418160814Ssimon#define PCRF_AZ_PM_AUX_CURR_LBN 6 419109998Smarkm#define PCRF_AZ_PM_AUX_CURR_WIDTH 3 420109998Smarkm#define PCRF_AZ_PM_DSI_LBN 5 421109998Smarkm#define PCRF_AZ_PM_DSI_WIDTH 1 422109998Smarkm#define PCRF_AZ_PM_PME_CLK_LBN 3 423160814Ssimon#define PCRF_AZ_PM_PME_CLK_WIDTH 1 424109998Smarkm#define PCRF_AZ_PM_PME_VER_LBN 0 425109998Smarkm#define PCRF_AZ_PM_PME_VER_WIDTH 3 42659191Skris 427109998Smarkm 428160814Ssimon/* 42959191Skris * PC_PM_CS_REG(16bit): 43059191Skris * Power management control & status register 43159191Skris */ 432109998Smarkm 433160814Ssimon#define PCR_AZ_PM_CS_REG 0x00000044 43459191Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 43559191Skris 43655714Skris#define PCRF_AZ_PM_PME_STAT_LBN 15 43755714Skris#define PCRF_AZ_PM_PME_STAT_WIDTH 1 43855714Skris#define PCRF_AZ_PM_DAT_SCALE_LBN 13 43955714Skris#define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 44055714Skris#define PCRF_AZ_PM_DAT_SEL_LBN 9 44155714Skris#define PCRF_AZ_PM_DAT_SEL_WIDTH 4 44255714Skris#define PCRF_AZ_PM_PME_EN_LBN 8 44355714Skris#define PCRF_AZ_PM_PME_EN_WIDTH 1 44455714Skris#define PCRF_CZ_NO_SOFT_RESET_LBN 3 44555714Skris#define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 44655714Skris#define PCRF_AZ_PM_PWR_ST_LBN 0 44755714Skris#define PCRF_AZ_PM_PWR_ST_WIDTH 2 44855714Skris 44955714Skris 45055714Skris/* 45155714Skris * PC_MSI_CAP_ID_REG(8bit): 45255714Skris * MSI capability ID 45355714Skris */ 45455714Skris 45555714Skris#define PCR_AZ_MSI_CAP_ID_REG 0x00000050 456160814Ssimon/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 457160814Ssimon 458160814Ssimon#define PCRF_AZ_MSI_CAP_ID_LBN 0 459109998Smarkm#define PCRF_AZ_MSI_CAP_ID_WIDTH 8 46055714Skris 46155714Skris 46255714Skris/* 46355714Skris * PC_MSI_NXT_PTR_REG(8bit): 46455714Skris * MSI next item pointer 46555714Skris */ 46655714Skris 46755714Skris#define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 46855714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 46955714Skris 47055714Skris#define PCRF_AZ_MSI_NXT_PTR_LBN 0 47155714Skris#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 47255714Skris 47355714Skris 47455714Skris/* 47555714Skris * PC_MSI_CTL_REG(16bit): 47655714Skris * MSI control register 47755714Skris */ 47855714Skris 47955714Skris#define PCR_AZ_MSI_CTL_REG 0x00000052 48055714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 48155714Skris 48255714Skris#define PCRF_AZ_MSI_64_EN_LBN 7 48355714Skris#define PCRF_AZ_MSI_64_EN_WIDTH 1 48455714Skris#define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 48555714Skris#define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 48655714Skris#define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 48755714Skris#define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 48855714Skris#define PCRF_AZ_MSI_EN_LBN 0 48955714Skris#define PCRF_AZ_MSI_EN_WIDTH 1 49055714Skris 49155714Skris 49255714Skris/* 49355714Skris * PC_MSI_ADR_LO_REG(32bit): 49455714Skris * MSI low 32 bits address register 49555714Skris */ 49655714Skris 49755714Skris#define PCR_AZ_MSI_ADR_LO_REG 0x00000054 49855714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 49955714Skris 50055714Skris#define PCRF_AZ_MSI_ADR_LO_LBN 2 501120631Snectar#define PCRF_AZ_MSI_ADR_LO_WIDTH 30 502120631Snectar 503120631Snectar 504120631Snectar/* 505120631Snectar * PC_MSI_ADR_HI_REG(32bit): 50668651Skris * MSI high 32 bits address register 50755714Skris */ 50855714Skris 50955714Skris#define PCR_AZ_MSI_ADR_HI_REG 0x00000058 51055714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 51155714Skris 51255714Skris#define PCRF_AZ_MSI_ADR_HI_LBN 0 51355714Skris#define PCRF_AZ_MSI_ADR_HI_WIDTH 32 51455714Skris 51555714Skris 51655714Skris/* 51755714Skris * PC_MSI_DAT_REG(16bit): 51855714Skris * MSI data register 51955714Skris */ 52055714Skris 52155714Skris#define PCR_AZ_MSI_DAT_REG 0x0000005c 52255714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 52355714Skris 52455714Skris#define PCRF_AZ_MSI_DAT_LBN 0 52555714Skris#define PCRF_AZ_MSI_DAT_WIDTH 16 52655714Skris 52755714Skris 52855714Skris/* 529160814Ssimon * PC_PCIE_CAP_LIST_REG(16bit): 53055714Skris * PCIe capability list register 53155714Skris */ 532160814Ssimon 53355714Skris#define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 53455714Skris/* falcona0,falconb0=pci_f0_config */ 535160814Ssimon 53655714Skris#define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 53789837Skris/* sienaa0,hunta0=pci_f0_config */ 53889837Skris 53989837Skris#define PCRF_AZ_PCIE_NXT_PTR_LBN 8 540160814Ssimon#define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 54189837Skris#define PCRF_AZ_PCIE_CAP_ID_LBN 0 54255714Skris#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 54355714Skris 54455714Skris 54555714Skris/* 54655714Skris * PC_PCIE_CAP_REG(16bit): 54755714Skris * PCIe capability register 54855714Skris */ 54955714Skris 55055714Skris#define PCR_AB_PCIE_CAP_REG 0x00000062 55155714Skris/* falcona0,falconb0=pci_f0_config */ 552160814Ssimon 55389837Skris#define PCR_CZ_PCIE_CAP_REG 0x00000072 55489837Skris/* sienaa0,hunta0=pci_f0_config */ 55589837Skris 55689837Skris#define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 55789837Skris#define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 55889837Skris#define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 55989837Skris#define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 56089837Skris#define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 56189837Skris#define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 56289837Skris#define PCRF_AZ_PCIE_CAP_VER_LBN 0 56389837Skris#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 564109998Smarkm 56555714Skris 56655714Skris/* 56755714Skris * PC_DEV_CAP_REG(32bit): 56855714Skris * PCIe device capabilities register 56955714Skris */ 57055714Skris 57155714Skris#define PCR_AB_DEV_CAP_REG 0x00000064 57255714Skris/* falcona0,falconb0=pci_f0_config */ 57355714Skris 57455714Skris#define PCR_CZ_DEV_CAP_REG 0x00000074 57555714Skris/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 57655714Skris 57755714Skris#define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 57855714Skris#define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 57955714Skris#define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 58055714Skris#define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 58155714Skris#define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 58255714Skris#define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 58355714Skris#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 58455714Skris#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 58555714Skris#define PCRF_AB_PWR_IND_LBN 14 58655714Skris#define PCRF_AB_PWR_IND_WIDTH 1 58755714Skris#define PCRF_AB_ATTN_IND_LBN 13 58855714Skris#define PCRF_AB_ATTN_IND_WIDTH 1 58955714Skris#define PCRF_AB_ATTN_BUTTON_LBN 12 59055714Skris#define PCRF_AB_ATTN_BUTTON_WIDTH 1 59155714Skris#define PCRF_AZ_ENDPT_L1_LAT_LBN 9 59255714Skris#define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 59355714Skris#define PCRF_AZ_ENDPT_L0_LAT_LBN 6 59455714Skris#define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 59555714Skris#define PCRF_AZ_TAG_FIELD_LBN 5 59655714Skris#define PCRF_AZ_TAG_FIELD_WIDTH 1 59755714Skris#define PCRF_AZ_PHAN_FUNC_LBN 3 59855714Skris#define PCRF_AZ_PHAN_FUNC_WIDTH 2 59955714Skris#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 60055714Skris#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 60155714Skris 60255714Skris 60355714Skris/* 60455714Skris * PC_DEV_CTL_REG(16bit): 60555714Skris * PCIe device control register 60655714Skris */ 60755714Skris 60855714Skris#define PCR_AB_DEV_CTL_REG 0x00000068 60955714Skris/* falcona0,falconb0=pci_f0_config */ 61055714Skris 61155714Skris#define PCR_CZ_DEV_CTL_REG 0x00000078 61255714Skris/* sienaa0,hunta0=pci_f0_config */ 61355714Skris 61455714Skris#define PCRF_CZ_FN_LEVEL_RESET_LBN 15 61555714Skris#define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 61655714Skris#define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 61755714Skris#define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 61855714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 61955714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 62055714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 62155714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 62255714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 62355714Skris#define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 62455714Skris#define PCRF_AZ_EN_NO_SNOOP_LBN 11 62555714Skris#define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 62655714Skris#define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 62755714Skris#define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 62855714Skris#define PCRF_AZ_PHAN_FUNC_EN_LBN 9 62955714Skris#define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 63055714Skris#define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 63155714Skris#define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 63259191Skris#define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 63359191Skris#define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 634160814Ssimon#define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 63559191Skris#define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 63659191Skris#define PCFE_AZ_MAX_PAYL_SIZE_4096 5 63759191Skris#define PCFE_AZ_MAX_PAYL_SIZE_2048 4 63859191Skris#define PCFE_AZ_MAX_PAYL_SIZE_1024 3 63959191Skris#define PCFE_AZ_MAX_PAYL_SIZE_512 2 64059191Skris#define PCFE_AZ_MAX_PAYL_SIZE_256 1 64159191Skris#define PCFE_AZ_MAX_PAYL_SIZE_128 0 64259191Skris#define PCRF_AZ_EN_RELAX_ORDER_LBN 4 64359191Skris#define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 64459191Skris#define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 64559191Skris#define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 64659191Skris#define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 64759191Skris#define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 64859191Skris#define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 649160814Ssimon#define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 65059191Skris#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 65159191Skris#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 65259191Skris 65359191Skris 65459191Skris/* 65559191Skris * PC_DEV_STAT_REG(16bit): 65659191Skris * PCIe device status register 65759191Skris */ 65859191Skris 65959191Skris#define PCR_AB_DEV_STAT_REG 0x0000006a 66059191Skris/* falcona0,falconb0=pci_f0_config */ 66159191Skris 66259191Skris#define PCR_CZ_DEV_STAT_REG 0x0000007a 66359191Skris/* sienaa0,hunta0=pci_f0_config */ 664160814Ssimon 66555714Skris#define PCRF_AZ_TRNS_PEND_LBN 5 66655714Skris#define PCRF_AZ_TRNS_PEND_WIDTH 1 66755714Skris#define PCRF_AZ_AUX_PWR_DET_LBN 4 66855714Skris#define PCRF_AZ_AUX_PWR_DET_WIDTH 1 669160814Ssimon#define PCRF_AZ_UNSUP_REQ_DET_LBN 3 67055714Skris#define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 671160814Ssimon#define PCRF_AZ_FATAL_ERR_DET_LBN 2 67255714Skris#define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 67355714Skris#define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 674160814Ssimon#define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 67555714Skris#define PCRF_AZ_CORR_ERR_DET_LBN 0 67655714Skris#define PCRF_AZ_CORR_ERR_DET_WIDTH 1 67755714Skris 67855714Skris 679160814Ssimon/* 68055714Skris * PC_LNK_CAP_REG(32bit): 68155714Skris * PCIe link capabilities register 68255714Skris */ 68355714Skris 684160814Ssimon#define PCR_AB_LNK_CAP_REG 0x0000006c 68555714Skris/* falcona0,falconb0=pci_f0_config */ 686160814Ssimon 68755714Skris#define PCR_CZ_LNK_CAP_REG 0x0000007c 68855714Skris/* sienaa0,hunta0=pci_f0_config */ 689160814Ssimon 69055714Skris#define PCRF_AZ_PORT_NUM_LBN 24 69155714Skris#define PCRF_AZ_PORT_NUM_WIDTH 8 69255714Skris#define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 69355714Skris#define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 69455714Skris#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 69555714Skris#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 69655714Skris#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 69755714Skris#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 69855714Skris#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 69955714Skris#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 70055714Skris#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 70155714Skris#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 70255714Skris#define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 70355714Skris#define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 704160814Ssimon#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 70555714Skris#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 70655714Skris#define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 70755714Skris#define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 70855714Skris#define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 70955714Skris#define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 71055714Skris#define PCRF_AZ_MAX_LNK_SP_LBN 0 71155714Skris#define PCRF_AZ_MAX_LNK_SP_WIDTH 4 712160814Ssimon 71355714Skris 71455714Skris/* 71555714Skris * PC_LNK_CTL_REG(16bit): 71655714Skris * PCIe link control register 717160814Ssimon */ 71855714Skris 719109998Smarkm#define PCR_AB_LNK_CTL_REG 0x00000070 720109998Smarkm/* falcona0,falconb0=pci_f0_config */ 721109998Smarkm 722109998Smarkm#define PCR_CZ_LNK_CTL_REG 0x00000080 723109998Smarkm/* sienaa0,hunta0=pci_f0_config */ 724109998Smarkm 725109998Smarkm#define PCRF_AZ_EXT_SYNC_LBN 7 72655714Skris#define PCRF_AZ_EXT_SYNC_WIDTH 1 72755714Skris#define PCRF_AZ_COMM_CLK_CFG_LBN 6 72855714Skris#define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 729160814Ssimon#define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 73055714Skris#define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 73155714Skris#define PCRF_CZ_LNK_RETRAIN_LBN 5 73255714Skris#define PCRF_CZ_LNK_RETRAIN_WIDTH 1 73355714Skris#define PCRF_AZ_LNK_DIS_LBN 4 73455714Skris#define PCRF_AZ_LNK_DIS_WIDTH 1 73555714Skris#define PCRF_AZ_RD_COM_BDRY_LBN 3 73655714Skris#define PCRF_AZ_RD_COM_BDRY_WIDTH 1 73755714Skris#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 73855714Skris#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 73955714Skris 74055714Skris 74155714Skris/* 74255714Skris * PC_LNK_STAT_REG(16bit): 74355714Skris * PCIe link status register 74455714Skris */ 745160814Ssimon 74655714Skris#define PCR_AB_LNK_STAT_REG 0x00000072 74755714Skris/* falcona0,falconb0=pci_f0_config */ 74855714Skris 74955714Skris#define PCR_CZ_LNK_STAT_REG 0x00000082 75055714Skris/* sienaa0,hunta0=pci_f0_config */ 75155714Skris 75255714Skris#define PCRF_AZ_SLOT_CLK_CFG_LBN 12 75355714Skris#define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 75459191Skris#define PCRF_AZ_LNK_TRAIN_LBN 11 75559191Skris#define PCRF_AZ_LNK_TRAIN_WIDTH 1 75659191Skris#define PCRF_AB_TRAIN_ERR_LBN 10 75755714Skris#define PCRF_AB_TRAIN_ERR_WIDTH 1 75855714Skris#define PCRF_AZ_LNK_WIDTH_LBN 4 75955714Skris#define PCRF_AZ_LNK_WIDTH_WIDTH 6 76055714Skris#define PCRF_AZ_LNK_SP_LBN 0 76155714Skris#define PCRF_AZ_LNK_SP_WIDTH 4 762160814Ssimon 76355714Skris 76455714Skris/* 76555714Skris * PC_SLOT_CAP_REG(32bit): 76655714Skris * PCIe slot capabilities register 76755714Skris */ 76855714Skris 76955714Skris#define PCR_AB_SLOT_CAP_REG 0x00000074 77055714Skris/* falcona0,falconb0=pci_f0_config */ 77155714Skris 77255714Skris#define PCRF_AB_SLOT_NUM_LBN 19 77355714Skris#define PCRF_AB_SLOT_NUM_WIDTH 13 77455714Skris#define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 77555714Skris#define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 77655714Skris#define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 77755714Skris#define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 77855714Skris#define PCRF_AB_SLOT_HP_CAP_LBN 6 77955714Skris#define PCRF_AB_SLOT_HP_CAP_WIDTH 1 78055714Skris#define PCRF_AB_SLOT_HP_SURP_LBN 5 78155714Skris#define PCRF_AB_SLOT_HP_SURP_WIDTH 1 78255714Skris#define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 78355714Skris#define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 78455714Skris#define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 78555714Skris#define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 78655714Skris#define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 78755714Skris#define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 78855714Skris#define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 78955714Skris#define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 79055714Skris#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 791160814Ssimon#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 79255714Skris 79355714Skris 79455714Skris/* 79555714Skris * PC_SLOT_CTL_REG(16bit): 79655714Skris * PCIe slot control register 79755714Skris */ 79855714Skris 79955714Skris#define PCR_AB_SLOT_CTL_REG 0x00000078 80055714Skris/* falcona0,falconb0=pci_f0_config */ 80155714Skris 80255714Skris#define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 80355714Skris#define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 80455714Skris#define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 80555714Skris#define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 80655714Skris#define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 80755714Skris#define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 80855714Skris#define PCRF_AB_SLOT_HP_INT_EN_LBN 5 809160814Ssimon#define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 81055714Skris#define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 81155714Skris#define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 81255714Skris#define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 81355714Skris#define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 81455714Skris#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 81555714Skris#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 81655714Skris#define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 81755714Skris#define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 81855714Skris#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 81955714Skris#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 82055714Skris 82155714Skris 82255714Skris/* 82355714Skris * PC_SLOT_STAT_REG(16bit): 82455714Skris * PCIe slot status register 82555714Skris */ 82655714Skris 82755714Skris#define PCR_AB_SLOT_STAT_REG 0x0000007a 82855714Skris/* falcona0,falconb0=pci_f0_config */ 82955714Skris 83055714Skris#define PCRF_AB_PRES_DET_ST_LBN 6 83155714Skris#define PCRF_AB_PRES_DET_ST_WIDTH 1 83255714Skris#define PCRF_AB_MRL_SENS_ST_LBN 5 83355714Skris#define PCRF_AB_MRL_SENS_ST_WIDTH 1 83455714Skris#define PCRF_AB_SLOT_PWR_IND_LBN 4 83555714Skris#define PCRF_AB_SLOT_PWR_IND_WIDTH 1 83655714Skris#define PCRF_AB_SLOT_ATTN_IND_LBN 3 83755714Skris#define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 83855714Skris#define PCRF_AB_SLOT_MRL_SENS_LBN 2 83955714Skris#define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 84055714Skris#define PCRF_AB_PWR_FLTDET_LBN 1 84155714Skris#define PCRF_AB_PWR_FLTDET_WIDTH 1 84255714Skris#define PCRF_AB_ATTN_BUTDET_LBN 0 84355714Skris#define PCRF_AB_ATTN_BUTDET_WIDTH 1 84455714Skris 84555714Skris 84655714Skris/* 84755714Skris * PC_MSIX_CAP_ID_REG(8bit): 84855714Skris * MSIX Capability ID 84955714Skris */ 85055714Skris 85155714Skris#define PCR_BB_MSIX_CAP_ID_REG 0x00000090 85255714Skris/* falconb0=pci_f0_config */ 853160814Ssimon 85455714Skris#define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 85555714Skris/* sienaa0,hunta0=pci_f0_config */ 85655714Skris 85755714Skris#define PCRF_BZ_MSIX_CAP_ID_LBN 0 85876866Skris#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 85955714Skris 86055714Skris 86155714Skris/* 86255714Skris * PC_MSIX_NXT_PTR_REG(8bit): 86355714Skris * MSIX Capability Next Capability Ptr 86455714Skris */ 86555714Skris 86655714Skris#define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 86755714Skris/* falconb0=pci_f0_config */ 86855714Skris 86955714Skris#define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 87055714Skris/* sienaa0,hunta0=pci_f0_config */ 87155714Skris 87255714Skris#define PCRF_BZ_MSIX_NXT_PTR_LBN 0 87355714Skris#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 87476866Skris 87555714Skris 87676866Skris/* 87776866Skris * PC_MSIX_CTL_REG(16bit): 878160814Ssimon * MSIX control register 87976866Skris */ 88076866Skris 88176866Skris#define PCR_BB_MSIX_CTL_REG 0x00000092 88255714Skris/* falconb0=pci_f0_config */ 88355714Skris 88455714Skris#define PCR_CZ_MSIX_CTL_REG 0x000000b2 88555714Skris/* sienaa0,hunta0=pci_f0_config */ 88655714Skris 88755714Skris#define PCRF_BZ_MSIX_EN_LBN 15 88855714Skris#define PCRF_BZ_MSIX_EN_WIDTH 1 88976866Skris#define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 89055714Skris#define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 89155714Skris#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 89255714Skris#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 89355714Skris 89455714Skris 89555714Skris/* 89655714Skris * PC_MSIX_TBL_BASE_REG(32bit): 89755714Skris * MSIX Capability Vector Table Base 89855714Skris */ 89955714Skris 90055714Skris#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 90155714Skris/* falconb0=pci_f0_config */ 90255714Skris 90355714Skris#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 90455714Skris/* sienaa0,hunta0=pci_f0_config */ 90555714Skris 90655714Skris#define PCRF_BZ_MSIX_TBL_OFF_LBN 3 90755714Skris#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 90855714Skris#define PCRF_BZ_MSIX_TBL_BIR_LBN 0 90955714Skris#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 91055714Skris 91155714Skris 91255714Skris/* 91355714Skris * PC_DEV_CAP2_REG(32bit): 91455714Skris * PCIe Device Capabilities 2 91555714Skris */ 91655714Skris 91755714Skris#define PCR_CZ_DEV_CAP2_REG 0x00000094 91855714Skris/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 91955714Skris 92055714Skris#define PCRF_DZ_OBFF_SUPPORTED_LBN 18 92155714Skris#define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 92255714Skris#define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 92355714Skris#define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 92455714Skris#define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 92555714Skris#define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 92655714Skris#define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 92755714Skris#define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 928100928Snectar#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 929100928Snectar#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 930100928Snectar#define PCRF_CZ_CMPL_TIMEOUT_LBN 0 931100928Snectar#define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 93255714Skris#define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 93355714Skris#define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 93455714Skris#define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 935109998Smarkm#define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 93655714Skris#define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 937109998Smarkm#define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 938109998Smarkm#define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 939109998Smarkm#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 940109998Smarkm#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 941109998Smarkm 942109998Smarkm 943109998Smarkm/* 94455714Skris * PC_DEV_CTL2_REG(16bit): 94555714Skris * PCIe Device Control 2 94655714Skris */ 94755714Skris 94855714Skris#define PCR_CZ_DEV_CTL2_REG 0x00000098 94955714Skris/* sienaa0,hunta0=pci_f0_config */ 95055714Skris 95155714Skris#define PCRF_DZ_OBFF_ENABLE_LBN 13 95255714Skris#define PCRF_DZ_OBFF_ENABLE_WIDTH 2 95355714Skris#define PCRF_DZ_LTR_ENABLE_LBN 10 954109998Smarkm#define PCRF_DZ_LTR_ENABLE_WIDTH 1 955109998Smarkm#define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 956109998Smarkm#define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 957109998Smarkm#define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 958109998Smarkm#define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 95955714Skris#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 96055714Skris#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 96155714Skris#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 96255714Skris#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 963109998Smarkm 964109998Smarkm 965109998Smarkm/* 966109998Smarkm * PC_MSIX_PBA_BASE_REG(32bit): 967109998Smarkm * MSIX Capability PBA Base 968109998Smarkm */ 969160814Ssimon 970160814Ssimon#define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 971160814Ssimon/* falconb0=pci_f0_config */ 972160814Ssimon 973160814Ssimon#define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 974160814Ssimon/* sienaa0,hunta0=pci_f0_config */ 975160814Ssimon 97655714Skris#define PCRF_BZ_MSIX_PBA_OFF_LBN 3 97755714Skris#define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 97855714Skris#define PCRF_BZ_MSIX_PBA_BIR_LBN 0 97955714Skris#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 98055714Skris 981160814Ssimon 98259191Skris/* 98359191Skris * PC_LNK_CAP2_REG(32bit): 98459191Skris * PCIe Link Capability 2 985109998Smarkm */ 986109998Smarkm 987109998Smarkm#define PCR_DZ_LNK_CAP2_REG 0x0000009c 988109998Smarkm/* hunta0=pci_f0_config */ 98959191Skris 99059191Skris#define PCRF_DZ_LNK_SPEED_SUP_LBN 1 99159191Skris#define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 99259191Skris 99359191Skris 99459191Skris/* 99559191Skris * PC_LNK_CTL2_REG(16bit): 99659191Skris * PCIe Link Control 2 99759191Skris */ 99859191Skris 999109998Smarkm#define PCR_CZ_LNK_CTL2_REG 0x000000a0 100055714Skris/* sienaa0,hunta0=pci_f0_config */ 100155714Skris 100255714Skris#define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 100355714Skris#define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 100455714Skris#define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 100555714Skris#define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 100655714Skris#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 100755714Skris#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 100855714Skris#define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 100955714Skris#define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 101055714Skris#define PCRF_CZ_SELECT_DEEMPH_LBN 6 1011109998Smarkm#define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 1012109998Smarkm#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 1013109998Smarkm#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 1014109998Smarkm#define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 101555714Skris#define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 1016109998Smarkm#define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 1017109998Smarkm#define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 1018109998Smarkm#define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 1019109998Smarkm#define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 1020109998Smarkm#define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 1021109998Smarkm 1022109998Smarkm 102355714Skris/* 102455714Skris * PC_LNK_STAT2_REG(16bit): 102555714Skris * PCIe Link Status 2 102655714Skris */ 102755714Skris 102855714Skris#define PCR_CZ_LNK_STAT2_REG 0x000000a2 102955714Skris/* sienaa0,hunta0=pci_f0_config */ 103055714Skris 103155714Skris#define PCRF_CZ_CURRENT_DEEMPH_LBN 0 103255714Skris#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 103355714Skris 103455714Skris 103555714Skris/* 103655714Skris * PC_VPD_CAP_ID_REG(8bit): 103755714Skris * VPD data register 103855714Skris */ 103955714Skris 104055714Skris#define PCR_AB_VPD_CAP_ID_REG 0x000000b0 104155714Skris/* falcona0,falconb0=pci_f0_config */ 104255714Skris 104355714Skris#define PCRF_AB_VPD_CAP_ID_LBN 0 104455714Skris#define PCRF_AB_VPD_CAP_ID_WIDTH 8 104555714Skris 104655714Skris 104755714Skris/* 104855714Skris * PC_VPD_NXT_PTR_REG(8bit): 104955714Skris * VPD next item pointer 105055714Skris */ 105155714Skris 105255714Skris#define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 105355714Skris/* falcona0,falconb0=pci_f0_config */ 105455714Skris 105555714Skris#define PCRF_AB_VPD_NXT_PTR_LBN 0 105655714Skris#define PCRF_AB_VPD_NXT_PTR_WIDTH 8 105755714Skris 105855714Skris 105955714Skris/* 106055714Skris * PC_VPD_ADDR_REG(16bit): 106155714Skris * VPD address register 106255714Skris */ 106355714Skris 106455714Skris#define PCR_AB_VPD_ADDR_REG 0x000000b2 106555714Skris/* falcona0,falconb0=pci_f0_config */ 106655714Skris 106755714Skris#define PCRF_AB_VPD_FLAG_LBN 15 106855714Skris#define PCRF_AB_VPD_FLAG_WIDTH 1 1069160814Ssimon#define PCRF_AB_VPD_ADDR_LBN 0 107059191Skris#define PCRF_AB_VPD_ADDR_WIDTH 15 107159191Skris 107259191Skris 1073109998Smarkm/* 1074109998Smarkm * PC_VPD_CAP_DATA_REG(32bit): 1075109998Smarkm * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1076109998Smarkm */ 107759191Skris 107859191Skris#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 107959191Skris/* falcona0,falconb0=pci_f0_config */ 108059191Skris 108159191Skris#define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 108268651Skris/* sienaa0,hunta0=pci_f0_config */ 108355714Skris 108455714Skris#define PCRF_AZ_VPD_DATA_LBN 0 108555714Skris#define PCRF_AZ_VPD_DATA_WIDTH 32 108655714Skris 108755714Skris 108855714Skris/* 108955714Skris * PC_VPD_CAP_CTL_REG(8bit): 109055714Skris * VPD control and capabilities register 109155714Skris */ 109255714Skris 109368651Skris#define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 109468651Skris/* sienaa0,hunta0=pci_f0_config */ 109555714Skris 109655714Skris#define PCRF_CZ_VPD_FLAG_LBN 31 109755714Skris#define PCRF_CZ_VPD_FLAG_WIDTH 1 109855714Skris#define PCRF_CZ_VPD_ADDR_LBN 16 109955714Skris#define PCRF_CZ_VPD_ADDR_WIDTH 15 110055714Skris#define PCRF_CZ_VPD_NXT_PTR_LBN 8 110155714Skris#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 110255714Skris#define PCRF_CZ_VPD_CAP_ID_LBN 0 110355714Skris#define PCRF_CZ_VPD_CAP_ID_WIDTH 8 110455714Skris 110555714Skris 110655714Skris/* 1107160814Ssimon * PC_AER_CAP_HDR_REG(32bit): 110855714Skris * AER capability header register 1109111147Snectar */ 111055714Skris 1111111147Snectar#define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1112111147Snectar/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1113111147Snectar 1114111147Snectar#define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1115111147Snectar#define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1116111147Snectar#define PCRF_AZ_AERCAPHDR_VER_LBN 16 1117111147Snectar#define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1118111147Snectar#define PCRF_AZ_AERCAPHDR_ID_LBN 0 1119111147Snectar#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 112055714Skris 112155714Skris 112255714Skris/* 112355714Skris * PC_AER_UNCORR_ERR_STAT_REG(32bit): 112455714Skris * AER Uncorrectable error status register 112555714Skris */ 112655714Skris 112755714Skris#define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1128111147Snectar/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 112955714Skris 1130111147Snectar#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1131111147Snectar#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1132111147Snectar#define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1133111147Snectar#define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1134111147Snectar#define PCRF_AZ_MALF_TLP_STAT_LBN 18 1135111147Snectar#define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1136111147Snectar#define PCRF_AZ_RX_OVF_STAT_LBN 17 1137111147Snectar#define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1138111147Snectar#define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 113955714Skris#define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 114055714Skris#define PCRF_AZ_COMP_ABRT_STAT_LBN 15 114155714Skris#define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 114255714Skris#define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 114355714Skris#define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1144160814Ssimon#define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 114555714Skris#define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 114655714Skris#define PCRF_AZ_PSON_TLP_STAT_LBN 12 114755714Skris#define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 114855714Skris#define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 114955714Skris#define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 115055714Skris#define PCRF_AB_TRAIN_ERR_STAT_LBN 0 115155714Skris#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 115255714Skris 115355714Skris 115455714Skris/* 115555714Skris * PC_AER_UNCORR_ERR_MASK_REG(32bit): 115655714Skris * AER Uncorrectable error mask register 115755714Skris */ 115859191Skris 115959191Skris#define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 116055714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 116155714Skris 116255714Skris#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 116355714Skris#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 116455714Skris#define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1165160814Ssimon#define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 1166160814Ssimon#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1167160814Ssimon#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1168160814Ssimon#define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1169160814Ssimon#define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1170160814Ssimon#define PCRF_AZ_MALF_TLP_MASK_LBN 18 1171160814Ssimon#define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1172160814Ssimon#define PCRF_AZ_RX_OVF_MASK_LBN 17 1173160814Ssimon#define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1174160814Ssimon#define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1175160814Ssimon#define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1176160814Ssimon#define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1177160814Ssimon#define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1178160814Ssimon#define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1179160814Ssimon#define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 118055714Skris#define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 118155714Skris#define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 118255714Skris#define PCRF_AZ_PSON_TLP_MASK_LBN 12 118359191Skris#define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 118455714Skris#define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 118555714Skris#define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 118655714Skris#define PCRF_AB_TRAIN_ERR_MASK_LBN 0 118755714Skris#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 118855714Skris 1189160814Ssimon 1190160814Ssimon/* 1191160814Ssimon * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1192160814Ssimon * AER Uncorrectable error severity register 1193160814Ssimon */ 1194160814Ssimon 1195160814Ssimon#define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1196160814Ssimon/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1197160814Ssimon 119855714Skris#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 119955714Skris#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 120055714Skris#define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1201160814Ssimon#define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 120255714Skris#define PCRF_AZ_MALF_TLP_SEV_LBN 18 120355714Skris#define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 120455714Skris#define PCRF_AZ_RX_OVF_SEV_LBN 17 120555714Skris#define PCRF_AZ_RX_OVF_SEV_WIDTH 1 120655714Skris#define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 120755714Skris#define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 120855714Skris#define PCRF_AZ_COMP_ABRT_SEV_LBN 15 120955714Skris#define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 121055714Skris#define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 121155714Skris#define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 121255714Skris#define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 121355714Skris#define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 121455714Skris#define PCRF_AZ_PSON_TLP_SEV_LBN 12 121555714Skris#define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1216172429Ssimon#define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1217172429Ssimon#define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 121855714Skris#define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1219172429Ssimon#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1220172429Ssimon 122155714Skris 1222172429Ssimon/* 1223172429Ssimon * PC_AER_CORR_ERR_STAT_REG(32bit): 1224172429Ssimon * AER Correctable error status register 1225172429Ssimon */ 122655714Skris 1227172429Ssimon#define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1228172429Ssimon/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 122955714Skris 1230172429Ssimon#define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 123155714Skris#define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 123255714Skris#define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 123355714Skris#define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 123455714Skris#define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 123555714Skris#define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1236160814Ssimon#define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1237160814Ssimon#define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 123855714Skris#define PCRF_AZ_BAD_TLP_STAT_LBN 6 123955714Skris#define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 124055714Skris#define PCRF_AZ_RX_ERR_STAT_LBN 0 124155714Skris#define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1242109998Smarkm 1243109998Smarkm 1244109998Smarkm/* 124555714Skris * PC_AER_CORR_ERR_MASK_REG(32bit): 124655714Skris * AER Correctable error status register 124755714Skris */ 124855714Skris 124955714Skris#define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 125055714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 125155714Skris 1252109998Smarkm#define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1253109998Smarkm#define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1254109998Smarkm#define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1255109998Smarkm#define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1256160814Ssimon#define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1257160814Ssimon#define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 125855714Skris#define PCRF_AZ_BAD_DLLP_MASK_LBN 7 125955714Skris#define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 126055714Skris#define PCRF_AZ_BAD_TLP_MASK_LBN 6 126155714Skris#define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 126255714Skris#define PCRF_AZ_RX_ERR_MASK_LBN 0 126355714Skris#define PCRF_AZ_RX_ERR_MASK_WIDTH 1 126455714Skris 126555714Skris 126655714Skris/* 126755714Skris * PC_AER_CAP_CTL_REG(32bit): 126855714Skris * AER capability and control register 126955714Skris */ 127055714Skris 127155714Skris#define PCR_AZ_AER_CAP_CTL_REG 0x00000118 127255714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 127355714Skris 127455714Skris#define PCRF_AZ_ECRC_CHK_EN_LBN 8 127555714Skris#define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 127655714Skris#define PCRF_AZ_ECRC_CHK_CAP_LBN 7 127768651Skris#define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 127855714Skris#define PCRF_AZ_ECRC_GEN_EN_LBN 6 127955714Skris#define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 128055714Skris#define PCRF_AZ_ECRC_GEN_CAP_LBN 5 128155714Skris#define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 128255714Skris#define PCRF_AZ_1ST_ERR_PTR_LBN 0 128355714Skris#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 128455714Skris 128555714Skris 128655714Skris/* 128755714Skris * PC_AER_HDR_LOG_REG(128bit): 128855714Skris * AER Header log register 128955714Skris */ 129055714Skris 129155714Skris#define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 129255714Skris/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 129355714Skris 129455714Skris#define PCRF_AZ_HDR_LOG_LBN 0 129555714Skris#define PCRF_AZ_HDR_LOG_WIDTH 128 129655714Skris 129755714Skris 129855714Skris/* 129955714Skris * PC_DEVSN_CAP_HDR_REG(32bit): 130055714Skris * Device serial number capability header register 130155714Skris */ 130255714Skris 130355714Skris#define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 130455714Skris/* sienaa0,hunta0=pci_f0_config */ 130555714Skris 130655714Skris#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1307160814Ssimon#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 130855714Skris#define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 130955714Skris#define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 131055714Skris#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 131155714Skris#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 131255714Skris 131355714Skris 131455714Skris/* 131555714Skris * PC_DEVSN_DWORD0_REG(32bit): 131655714Skris * Device serial number DWORD0 131755714Skris */ 131855714Skris 1319109998Smarkm#define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1320109998Smarkm/* sienaa0,hunta0=pci_f0_config */ 1321109998Smarkm 1322109998Smarkm#define PCRF_CZ_DEVSN_DWORD0_LBN 0 1323109998Smarkm#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1324160814Ssimon 132555714Skris 132655714Skris/* 132755714Skris * PC_DEVSN_DWORD1_REG(32bit): 132855714Skris * Device serial number DWORD0 132955714Skris */ 133055714Skris 133155714Skris#define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 133255714Skris/* sienaa0,hunta0=pci_f0_config */ 1333109998Smarkm 1334109998Smarkm#define PCRF_CZ_DEVSN_DWORD1_LBN 0 1335109998Smarkm#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1336109998Smarkm 1337109998Smarkm 1338109998Smarkm/* 1339109998Smarkm * PC_ARI_CAP_HDR_REG(32bit): 134055714Skris * ARI capability header register 134155714Skris */ 134255714Skris 134355714Skris#define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 134455714Skris/* sienaa0,hunta0=pci_f0_config */ 134555714Skris 134655714Skris#define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 134755714Skris#define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 134855714Skris#define PCRF_CZ_ARICAPHDR_VER_LBN 16 134955714Skris#define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 135055714Skris#define PCRF_CZ_ARICAPHDR_ID_LBN 0 135155714Skris#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 135255714Skris 135355714Skris 135455714Skris/* 135568651Skris * PC_ARI_CAP_REG(16bit): 135655714Skris * ARI Capabilities 135755714Skris */ 135855714Skris 135955714Skris#define PCR_CZ_ARI_CAP_REG 0x00000154 136055714Skris/* sienaa0,hunta0=pci_f0_config */ 136155714Skris 136255714Skris#define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 136355714Skris#define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 136455714Skris#define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 136555714Skris#define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 136655714Skris#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 136755714Skris#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 136855714Skris 136955714Skris 137055714Skris/* 137155714Skris * PC_ARI_CTL_REG(16bit): 1372109998Smarkm * ARI Control 1373109998Smarkm */ 1374109998Smarkm 1375109998Smarkm#define PCR_CZ_ARI_CTL_REG 0x00000156 137655714Skris/* sienaa0,hunta0=pci_f0_config */ 137755714Skris 137855714Skris#define PCRF_CZ_ARI_FN_GRP_LBN 4 137955714Skris#define PCRF_CZ_ARI_FN_GRP_WIDTH 3 138055714Skris#define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 138155714Skris#define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 138255714Skris#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 138355714Skris#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 138455714Skris 138555714Skris 138655714Skris/* 138755714Skris * PC_SEC_PCIE_CAP_REG(32bit): 138855714Skris * Secondary PCIE Capability Register 138955714Skris */ 1390109998Smarkm 139155714Skris#define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 139255714Skris/* hunta0=pci_f0_config */ 1393109998Smarkm 139455714Skris#define PCRF_DZ_SEC_NXT_PTR_LBN 20 1395109998Smarkm#define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1396109998Smarkm#define PCRF_DZ_SEC_VERSION_LBN 16 139755714Skris#define PCRF_DZ_SEC_VERSION_WIDTH 4 1398160814Ssimon#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 139955714Skris#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1400160814Ssimon 1401109998Smarkm 140255714Skris/* 140355714Skris * PC_SRIOV_CAP_HDR_REG(32bit): 140455714Skris * SRIOV capability header register 140555714Skris */ 1406109998Smarkm 140755714Skris#define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1408109998Smarkm/* sienaa0=pci_f0_config */ 1409160814Ssimon 1410160814Ssimon#define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 141155714Skris/* hunta0=pci_f0_config */ 1412109998Smarkm 1413109998Smarkm#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 141455714Skris#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 141555714Skris#define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 141655714Skris#define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 141755714Skris#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 141855714Skris#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 141955714Skris 142055714Skris 142155714Skris/* 142255714Skris * PC_SRIOV_CAP_REG(32bit): 142355714Skris * SRIOV Capabilities 142455714Skris */ 142555714Skris 142655714Skris#define PCR_CC_SRIOV_CAP_REG 0x00000164 142755714Skris/* sienaa0=pci_f0_config */ 1428160814Ssimon 1429160814Ssimon#define PCR_DZ_SRIOV_CAP_REG 0x00000184 1430160814Ssimon/* hunta0=pci_f0_config */ 1431160814Ssimon 143255714Skris#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 143355714Skris#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 143455714Skris#define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 143555714Skris#define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 143655714Skris#define PCRF_CZ_VF_MIGR_CAP_LBN 0 143755714Skris#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 143855714Skris 143955714Skris 144055714Skris/* 144155714Skris * PC_LINK_CONTROL3_REG(32bit): 144255714Skris * Link Control 3. 144355714Skris */ 144455714Skris 144555714Skris#define PCR_DZ_LINK_CONTROL3_REG 0x00000164 144655714Skris/* hunta0=pci_f0_config */ 144755714Skris 144855714Skris#define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 144955714Skris#define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 145055714Skris#define PCRF_DZ_PERFORM_EQL_LBN 0 1451109998Smarkm#define PCRF_DZ_PERFORM_EQL_WIDTH 1 145255714Skris 145355714Skris 145455714Skris/* 145555714Skris * PC_LANE_ERROR_STAT_REG(32bit): 145655714Skris * Lane Error Status Register. 145755714Skris */ 145855714Skris 145955714Skris#define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 146055714Skris/* hunta0=pci_f0_config */ 146155714Skris 146255714Skris#define PCRF_DZ_LANE_STATUS_LBN 0 146355714Skris#define PCRF_DZ_LANE_STATUS_WIDTH 8 1464109998Smarkm 146555714Skris 146668651Skris/* 1467109998Smarkm * PC_SRIOV_CTL_REG(16bit): 146855714Skris * SRIOV Control 146955714Skris */ 147055714Skris 147155714Skris#define PCR_CC_SRIOV_CTL_REG 0x00000168 147255714Skris/* sienaa0=pci_f0_config */ 147355714Skris 147455714Skris#define PCR_DZ_SRIOV_CTL_REG 0x00000188 147555714Skris/* hunta0=pci_f0_config */ 147655714Skris 147755714Skris#define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 147855714Skris#define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 147955714Skris#define PCRF_CZ_VF_MSE_LBN 3 148055714Skris#define PCRF_CZ_VF_MSE_WIDTH 1 148155714Skris#define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 148255714Skris#define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 148355714Skris#define PCRF_CZ_VF_MIGR_EN_LBN 1 148455714Skris#define PCRF_CZ_VF_MIGR_EN_WIDTH 1 148555714Skris#define PCRF_CZ_VF_EN_LBN 0 148655714Skris#define PCRF_CZ_VF_EN_WIDTH 1 148755714Skris 1488160814Ssimon 1489160814Ssimon/* 1490160814Ssimon * PC_SRIOV_STAT_REG(16bit): 1491109998Smarkm * SRIOV Status 1492109998Smarkm */ 1493109998Smarkm 1494109998Smarkm#define PCR_CC_SRIOV_STAT_REG 0x0000016a 1495109998Smarkm/* sienaa0=pci_f0_config */ 1496109998Smarkm 1497109998Smarkm#define PCR_DZ_SRIOV_STAT_REG 0x0000018a 1498109998Smarkm/* hunta0=pci_f0_config */ 1499109998Smarkm 150055714Skris#define PCRF_CZ_VF_MIGR_STAT_LBN 0 150155714Skris#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1502109998Smarkm 1503109998Smarkm 1504109998Smarkm/* 1505109998Smarkm * PC_LANE01_EQU_CONTROL_REG(32bit): 150655714Skris * Lanes 0,1 Equalization Control Register. 1507109998Smarkm */ 150855714Skris 150955714Skris#define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 151055714Skris/* hunta0=pci_f0_config */ 151155714Skris 151255714Skris#define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 151355714Skris#define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 151455714Skris#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 151555714Skris#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 151655714Skris 151755714Skris 151855714Skris/* 151955714Skris * PC_SRIOV_INITIALVFS_REG(16bit): 1520109998Smarkm * SRIOV Initial VFs 152155714Skris */ 152255714Skris 1523109998Smarkm#define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1524109998Smarkm/* sienaa0=pci_f0_config */ 1525109998Smarkm 152668651Skris#define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c 152755714Skris/* hunta0=pci_f0_config */ 152855714Skris 152955714Skris#define PCRF_CZ_VF_INITIALVFS_LBN 0 153055714Skris#define PCRF_CZ_VF_INITIALVFS_WIDTH 16 153155714Skris 153255714Skris 153355714Skris/* 153455714Skris * PC_SRIOV_TOTALVFS_REG(10bit): 153555714Skris * SRIOV Total VFs 153655714Skris */ 153755714Skris 153855714Skris#define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1539109998Smarkm/* sienaa0=pci_f0_config */ 154055714Skris 154155714Skris#define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e 1542109998Smarkm/* hunta0=pci_f0_config */ 154355714Skris 154455714Skris#define PCRF_CZ_VF_TOTALVFS_LBN 0 154555714Skris#define PCRF_CZ_VF_TOTALVFS_WIDTH 16 154655714Skris 154755714Skris 154855714Skris/* 154955714Skris * PC_SRIOV_NUMVFS_REG(16bit): 155055714Skris * SRIOV Number of VFs 155155714Skris */ 155255714Skris 1553160814Ssimon#define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 155455714Skris/* sienaa0=pci_f0_config */ 155555714Skris 155655714Skris#define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 155755714Skris/* hunta0=pci_f0_config */ 155855714Skris 155955714Skris#define PCRF_CZ_VF_NUMVFS_LBN 0 156055714Skris#define PCRF_CZ_VF_NUMVFS_WIDTH 16 156155714Skris 156255714Skris 1563160814Ssimon/* 1564160814Ssimon * PC_LANE23_EQU_CONTROL_REG(32bit): 1565160814Ssimon * Lanes 2,3 Equalization Control Register. 1566160814Ssimon */ 1567160814Ssimon 1568160814Ssimon#define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1569160814Ssimon/* hunta0=pci_f0_config */ 157055714Skris 157155714Skris#define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 157255714Skris#define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 157355714Skris#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 157455714Skris#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1575109998Smarkm 157655714Skris 157755714Skris/* 157855714Skris * PC_SRIOV_FN_DPND_LNK_REG(16bit): 157955714Skris * SRIOV Function dependency link 158055714Skris */ 158155714Skris 1582109998Smarkm#define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 158355714Skris/* sienaa0=pci_f0_config */ 158455714Skris 158555714Skris#define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 158655714Skris/* hunta0=pci_f0_config */ 158755714Skris 158855714Skris#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 158955714Skris#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1590160814Ssimon 1591160814Ssimon 1592160814Ssimon/* 159355714Skris * PC_SRIOV_1STVF_OFFSET_REG(16bit): 159455714Skris * SRIOV First VF Offset 159555714Skris */ 159655714Skris 159755714Skris#define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 159855714Skris/* sienaa0=pci_f0_config */ 159955714Skris 160055714Skris#define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 160155714Skris/* hunta0=pci_f0_config */ 160255714Skris 160355714Skris#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 160455714Skris#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 160555714Skris 160655714Skris 1607160814Ssimon/* 1608160814Ssimon * PC_LANE45_EQU_CONTROL_REG(32bit): 160955714Skris * Lanes 4,5 Equalization Control Register. 161055714Skris */ 161155714Skris 161255714Skris#define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 161355714Skris/* hunta0=pci_f0_config */ 161455714Skris 161555714Skris#define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 161655714Skris#define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 161755714Skris#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 161855714Skris#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 161955714Skris 162055714Skris 162155714Skris/* 162255714Skris * PC_SRIOV_VFSTRIDE_REG(16bit): 162355714Skris * SRIOV VF Stride 162455714Skris */ 162555714Skris 162655714Skris#define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 162755714Skris/* sienaa0=pci_f0_config */ 162855714Skris 162955714Skris#define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 163055714Skris/* hunta0=pci_f0_config */ 163155714Skris 163255714Skris#define PCRF_CZ_VF_VFSTRIDE_LBN 0 163355714Skris#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 163455714Skris 163555714Skris 163655714Skris/* 163755714Skris * PC_LANE67_EQU_CONTROL_REG(32bit): 163855714Skris * Lanes 6,7 Equalization Control Register. 163955714Skris */ 164055714Skris 164155714Skris#define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 164255714Skris/* hunta0=pci_f0_config */ 164355714Skris 164455714Skris#define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 164555714Skris#define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 164655714Skris#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 164755714Skris#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 164855714Skris 164955714Skris 165055714Skris/* 165155714Skris * PC_SRIOV_DEVID_REG(16bit): 165255714Skris * SRIOV VF Device ID 165355714Skris */ 165455714Skris 165555714Skris#define PCR_CC_SRIOV_DEVID_REG 0x0000017a 165655714Skris/* sienaa0=pci_f0_config */ 165755714Skris 165855714Skris#define PCR_DZ_SRIOV_DEVID_REG 0x0000019a 165955714Skris/* hunta0=pci_f0_config */ 1660109998Smarkm 1661109998Smarkm#define PCRF_CZ_VF_DEVID_LBN 0 1662109998Smarkm#define PCRF_CZ_VF_DEVID_WIDTH 16 1663109998Smarkm 1664109998Smarkm 1665160814Ssimon/* 1666160814Ssimon * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1667160814Ssimon * SRIOV Supported Page Sizes 1668160814Ssimon */ 1669160814Ssimon 1670160814Ssimon#define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1671160814Ssimon/* sienaa0=pci_f0_config */ 1672160814Ssimon 1673160814Ssimon#define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c 1674160814Ssimon/* hunta0=pci_f0_config */ 1675160814Ssimon 1676160814Ssimon#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1677160814Ssimon#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1678160814Ssimon 1679160814Ssimon 1680160814Ssimon/* 1681160814Ssimon * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1682160814Ssimon * SRIOV System Page Size 1683160814Ssimon */ 1684160814Ssimon 1685160814Ssimon#define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1686160814Ssimon/* sienaa0=pci_f0_config */ 1687160814Ssimon 1688160814Ssimon#define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 1689160814Ssimon/* hunta0=pci_f0_config */ 1690160814Ssimon 1691160814Ssimon#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1692160814Ssimon#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1693160814Ssimon 1694160814Ssimon 1695160814Ssimon/* 1696160814Ssimon * PC_SRIOV_BAR0_REG(32bit): 1697160814Ssimon * SRIOV VF Bar0 1698160814Ssimon */ 1699160814Ssimon 1700160814Ssimon#define PCR_CC_SRIOV_BAR0_REG 0x00000184 1701160814Ssimon/* sienaa0=pci_f0_config */ 1702160814Ssimon 1703160814Ssimon#define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 1704160814Ssimon/* hunta0=pci_f0_config */ 1705160814Ssimon 1706160814Ssimon#define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1707160814Ssimon#define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1708160814Ssimon#define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1709160814Ssimon#define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1710160814Ssimon#define PCRF_DZ_VF_BAR0_PREF_LBN 3 1711160814Ssimon#define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1712160814Ssimon#define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1713160814Ssimon#define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1714160814Ssimon#define PCRF_DZ_VF_BAR0_IOM_LBN 0 1715160814Ssimon#define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 1716160814Ssimon 1717160814Ssimon 171855714Skris/* 171955714Skris * PC_SRIOV_BAR1_REG(32bit): 172055714Skris * SRIOV Bar1 172155714Skris */ 172255714Skris 1723160814Ssimon#define PCR_CC_SRIOV_BAR1_REG 0x00000188 1724160814Ssimon/* sienaa0=pci_f0_config */ 1725160814Ssimon 1726160814Ssimon#define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 1727160814Ssimon/* hunta0=pci_f0_config */ 1728160814Ssimon 1729160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1730160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1731160814Ssimon#define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1732160814Ssimon#define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1733160814Ssimon 1734160814Ssimon 1735160814Ssimon/* 1736160814Ssimon * PC_SRIOV_BAR2_REG(32bit): 1737160814Ssimon * SRIOV Bar2 1738160814Ssimon */ 1739160814Ssimon 1740160814Ssimon#define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1741160814Ssimon/* sienaa0=pci_f0_config */ 1742160814Ssimon 1743160814Ssimon#define PCR_DZ_SRIOV_BAR2_REG 0x000001ac 1744160814Ssimon/* hunta0=pci_f0_config */ 1745160814Ssimon 1746160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1747160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1748160814Ssimon#define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1749160814Ssimon#define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1750160814Ssimon#define PCRF_DZ_VF_BAR2_PREF_LBN 3 1751160814Ssimon#define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1752160814Ssimon#define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1753160814Ssimon#define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1754160814Ssimon#define PCRF_DZ_VF_BAR2_IOM_LBN 0 1755160814Ssimon#define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 1756160814Ssimon 1757160814Ssimon 1758160814Ssimon/* 1759160814Ssimon * PC_SRIOV_BAR3_REG(32bit): 1760160814Ssimon * SRIOV Bar3 1761160814Ssimon */ 1762160814Ssimon 1763160814Ssimon#define PCR_CC_SRIOV_BAR3_REG 0x00000190 1764160814Ssimon/* sienaa0=pci_f0_config */ 1765160814Ssimon 1766160814Ssimon#define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 1767160814Ssimon/* hunta0=pci_f0_config */ 1768160814Ssimon 1769160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1770160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1771160814Ssimon#define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1772160814Ssimon#define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1773160814Ssimon 1774160814Ssimon 1775160814Ssimon/* 1776160814Ssimon * PC_SRIOV_BAR4_REG(32bit): 1777160814Ssimon * SRIOV Bar4 1778160814Ssimon */ 1779160814Ssimon 1780160814Ssimon#define PCR_CC_SRIOV_BAR4_REG 0x00000194 1781160814Ssimon/* sienaa0=pci_f0_config */ 1782160814Ssimon 1783160814Ssimon#define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 1784160814Ssimon/* hunta0=pci_f0_config */ 1785160814Ssimon 178655714Skris/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 178755714Skris/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 178855714Skris#define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 178955714Skris#define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 179055714Skris 179155714Skris 179255714Skris/* 179355714Skris * PC_SRIOV_BAR5_REG(32bit): 179455714Skris * SRIOV Bar5 179555714Skris */ 179659191Skris 179755714Skris#define PCR_CC_SRIOV_BAR5_REG 0x00000198 179855714Skris/* sienaa0=pci_f0_config */ 179955714Skris 1800160814Ssimon#define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 1801160814Ssimon/* hunta0=pci_f0_config */ 1802160814Ssimon 1803160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1804160814Ssimon/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1805160814Ssimon#define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1806160814Ssimon#define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1807160814Ssimon 1808160814Ssimon 1809160814Ssimon/* 1810160814Ssimon * PC_SRIOV_RSVD_REG(16bit): 1811160814Ssimon * Reserved register 1812160814Ssimon */ 1813160814Ssimon 1814160814Ssimon#define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1815160814Ssimon/* hunta0=pci_f0_config */ 1816160814Ssimon 1817160814Ssimon#define PCRF_DZ_VF_RSVD_LBN 0 1818160814Ssimon#define PCRF_DZ_VF_RSVD_WIDTH 16 1819160814Ssimon 182055714Skris 182155714Skris/* 182255714Skris * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 182355714Skris * SRIOV VF Migration State Array Offset 182455714Skris */ 182555714Skris 182655714Skris#define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 182755714Skris/* sienaa0=pci_f0_config */ 182855714Skris 182955714Skris#define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc 183055714Skris/* hunta0=pci_f0_config */ 183155714Skris 1832109998Smarkm#define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1833109998Smarkm#define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1834109998Smarkm#define PCRF_CZ_VF_MIGR_BIR_LBN 0 1835109998Smarkm#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1836109998Smarkm 183755714Skris 183855714Skris/* 1839109998Smarkm * PC_TPH_CAP_HDR_REG(32bit): 184055714Skris * TPH Capability Header Register 184155714Skris */ 184255714Skris 1843160814Ssimon#define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 184455714Skris/* hunta0=pci_f0_config */ 184555714Skris 184655714Skris#define PCRF_DZ_TPH_NXT_PTR_LBN 20 184755714Skris#define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 184855714Skris#define PCRF_DZ_TPH_VERSION_LBN 16 184955714Skris#define PCRF_DZ_TPH_VERSION_WIDTH 4 185055714Skris#define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 185155714Skris#define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 185255714Skris 185355714Skris 185455714Skris/* 185555714Skris * PC_TPH_REQ_CAP_REG(32bit): 185655714Skris * TPH Requester Capability Register 185755714Skris */ 185855714Skris 185955714Skris#define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 186055714Skris/* hunta0=pci_f0_config */ 186155714Skris 186255714Skris#define PCRF_DZ_ST_TBLE_SIZE_LBN 16 186355714Skris#define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 186455714Skris#define PCRF_DZ_ST_TBLE_LOC_LBN 9 186555714Skris#define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 186655714Skris#define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1867160814Ssimon#define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1868160814Ssimon#define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1869160814Ssimon#define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 187055714Skris#define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 187155714Skris#define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1872109998Smarkm#define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 187355714Skris#define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 187455714Skris 187555714Skris 187655714Skris/* 187755714Skris * PC_TPH_REQ_CTL_REG(32bit): 187855714Skris * TPH Requester Control Register 187955714Skris */ 188055714Skris 188155714Skris#define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 188255714Skris/* hunta0=pci_f0_config */ 188355714Skris 188455714Skris#define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1885100928Snectar#define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1886100928Snectar#define PCRF_DZ_TPH_ST_MODE_LBN 0 1887109998Smarkm#define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1888100928Snectar 188955714Skris 189055714Skris/* 189155714Skris * PC_LTR_CAP_HDR_REG(32bit): 189255714Skris * Latency Tolerance Reporting Cap Header Reg 189355714Skris */ 189455714Skris 189555714Skris#define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 189655714Skris/* hunta0=pci_f0_config */ 189755714Skris 189855714Skris#define PCRF_DZ_LTR_NXT_PTR_LBN 20 189955714Skris#define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 190055714Skris#define PCRF_DZ_LTR_VERSION_LBN 16 190155714Skris#define PCRF_DZ_LTR_VERSION_WIDTH 4 190255714Skris#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 190355714Skris#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1904160814Ssimon 190555714Skris 190655714Skris/* 190755714Skris * PC_LTR_MAX_SNOOP_REG(32bit): 190855714Skris * LTR Maximum Snoop/No Snoop Register 190955714Skris */ 191055714Skris 191155714Skris#define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 191255714Skris/* hunta0=pci_f0_config */ 191355714Skris 191455714Skris#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 191555714Skris#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 191655714Skris#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 191755714Skris#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 191855714Skris#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 191955714Skris#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 192055714Skris#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 192155714Skris#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 192255714Skris 192355714Skris 192455714Skris/* 192555714Skris * PC_ACK_LAT_TMR_REG(32bit): 192655714Skris * ACK latency timer & replay timer register 192755714Skris */ 192855714Skris 192955714Skris#define PCR_AC_ACK_LAT_TMR_REG 0x00000700 193055714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 193155714Skris 193255714Skris#define PCRF_AC_RT_LBN 16 193355714Skris#define PCRF_AC_RT_WIDTH 16 193455714Skris#define PCRF_AC_ALT_LBN 0 193555714Skris#define PCRF_AC_ALT_WIDTH 16 193655714Skris 193755714Skris 193855714Skris/* 193955714Skris * PC_OTHER_MSG_REG(32bit): 194055714Skris * Other message register 1941160814Ssimon */ 194255714Skris 194355714Skris#define PCR_AC_OTHER_MSG_REG 0x00000704 194455714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 194555714Skris 194655714Skris#define PCRF_AC_OM_CRPT3_LBN 24 194755714Skris#define PCRF_AC_OM_CRPT3_WIDTH 8 194855714Skris#define PCRF_AC_OM_CRPT2_LBN 16 194955714Skris#define PCRF_AC_OM_CRPT2_WIDTH 8 195055714Skris#define PCRF_AC_OM_CRPT1_LBN 8 195155714Skris#define PCRF_AC_OM_CRPT1_WIDTH 8 195255714Skris#define PCRF_AC_OM_CRPT0_LBN 0 195355714Skris#define PCRF_AC_OM_CRPT0_WIDTH 8 195455714Skris 195555714Skris 195655714Skris/* 195755714Skris * PC_FORCE_LNK_REG(24bit): 195855714Skris * Port force link register 195955714Skris */ 196055714Skris 196155714Skris#define PCR_AC_FORCE_LNK_REG 0x00000708 196255714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 196355714Skris 196455714Skris#define PCRF_AC_LFS_LBN 16 196555714Skris#define PCRF_AC_LFS_WIDTH 6 196655714Skris#define PCRF_AC_FL_LBN 15 196755714Skris#define PCRF_AC_FL_WIDTH 1 196855714Skris#define PCRF_AC_LN_LBN 0 196955714Skris#define PCRF_AC_LN_WIDTH 8 197055714Skris 197155714Skris 197255714Skris/* 197355714Skris * PC_ACK_FREQ_REG(32bit): 197455714Skris * ACK frequency register 197555714Skris */ 197655714Skris 197755714Skris#define PCR_AC_ACK_FREQ_REG 0x0000070c 197855714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 197955714Skris 1980109998Smarkm#define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 1981109998Smarkm#define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 198255714Skris#define PCRF_AC_L1_ENTR_LAT_LBN 27 198355714Skris#define PCRF_AC_L1_ENTR_LAT_WIDTH 3 198455714Skris#define PCRF_AC_L0_ENTR_LAT_LBN 24 198555714Skris#define PCRF_AC_L0_ENTR_LAT_WIDTH 3 198655714Skris#define PCRF_CC_COMM_NFTS_LBN 16 198755714Skris#define PCRF_CC_COMM_NFTS_WIDTH 8 198855714Skris#define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 198955714Skris#define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 199055714Skris#define PCRF_AC_MAX_FTS_LBN 8 199155714Skris#define PCRF_AC_MAX_FTS_WIDTH 8 199255714Skris#define PCRF_AC_ACK_FREQ_LBN 0 199355714Skris#define PCRF_AC_ACK_FREQ_WIDTH 8 199455714Skris 199555714Skris 199655714Skris/* 199755714Skris * PC_PORT_LNK_CTL_REG(32bit): 199855714Skris * Port link control register 199955714Skris */ 2000109998Smarkm 2001109998Smarkm#define PCR_AC_PORT_LNK_CTL_REG 0x00000710 200255714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 200355714Skris 200455714Skris#define PCRF_AB_LRE_LBN 27 200555714Skris#define PCRF_AB_LRE_WIDTH 1 200655714Skris#define PCRF_AB_ESYNC_LBN 26 200755714Skris#define PCRF_AB_ESYNC_WIDTH 1 200855714Skris#define PCRF_AB_CRPT_LBN 25 200955714Skris#define PCRF_AB_CRPT_WIDTH 1 201055714Skris#define PCRF_AB_XB_LBN 24 201155714Skris#define PCRF_AB_XB_WIDTH 1 201255714Skris#define PCRF_AC_LC_LBN 16 201355714Skris#define PCRF_AC_LC_WIDTH 6 201455714Skris#define PCRF_AC_LDR_LBN 8 201555714Skris#define PCRF_AC_LDR_WIDTH 4 201655714Skris#define PCRF_AC_FLM_LBN 7 201755714Skris#define PCRF_AC_FLM_WIDTH 1 201855714Skris#define PCRF_AC_LKD_LBN 6 201955714Skris#define PCRF_AC_LKD_WIDTH 1 202055714Skris#define PCRF_AC_DLE_LBN 5 202155714Skris#define PCRF_AC_DLE_WIDTH 1 202255714Skris#define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 202355714Skris#define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 202455714Skris#define PCRF_AC_RA_LBN 3 202555714Skris#define PCRF_AC_RA_WIDTH 1 202655714Skris#define PCRF_AC_LE_LBN 2 202755714Skris#define PCRF_AC_LE_WIDTH 1 202855714Skris#define PCRF_AC_SD_LBN 1 202955714Skris#define PCRF_AC_SD_WIDTH 1 203055714Skris#define PCRF_AC_OMR_LBN 0 203155714Skris#define PCRF_AC_OMR_WIDTH 1 203255714Skris 203355714Skris 203455714Skris/* 203555714Skris * PC_LN_SKEW_REG(32bit): 203655714Skris * Lane skew register 203755714Skris */ 203855714Skris 203955714Skris#define PCR_AC_LN_SKEW_REG 0x00000714 204055714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 204155714Skris 204255714Skris#define PCRF_AC_DIS_LBN 31 204355714Skris#define PCRF_AC_DIS_WIDTH 1 204455714Skris#define PCRF_AB_RST_LBN 30 204555714Skris#define PCRF_AB_RST_WIDTH 1 204655714Skris#define PCRF_AC_AD_LBN 25 204755714Skris#define PCRF_AC_AD_WIDTH 1 204855714Skris#define PCRF_AC_FCD_LBN 24 204955714Skris#define PCRF_AC_FCD_WIDTH 1 205055714Skris#define PCRF_AC_LS2_LBN 16 205155714Skris#define PCRF_AC_LS2_WIDTH 8 205255714Skris#define PCRF_AC_LS1_LBN 8 205355714Skris#define PCRF_AC_LS1_WIDTH 8 205455714Skris#define PCRF_AC_LS0_LBN 0 205555714Skris#define PCRF_AC_LS0_WIDTH 8 205655714Skris 205755714Skris 205855714Skris/* 205955714Skris * PC_SYM_NUM_REG(16bit): 206055714Skris * Symbol number register 206155714Skris */ 206255714Skris 206355714Skris#define PCR_AC_SYM_NUM_REG 0x00000718 206455714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 206555714Skris 206655714Skris#define PCRF_CC_MAX_FUNCTIONS_LBN 29 206755714Skris#define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 206855714Skris#define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 206955714Skris#define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 207055714Skris#define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 207155714Skris#define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 207255714Skris#define PCRF_CC_REPLAY_TMR_MOD_LBN 14 207355714Skris#define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 207455714Skris#define PCRF_AB_ES_LBN 12 2075160814Ssimon#define PCRF_AB_ES_WIDTH 3 2076160814Ssimon#define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 2077160814Ssimon#define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 2078160814Ssimon#define PCRF_CC_NUM_SKP_SYMS_LBN 8 2079160814Ssimon#define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 2080160814Ssimon#define PCRF_AB_TS2_LBN 4 2081160814Ssimon#define PCRF_AB_TS2_WIDTH 4 2082160814Ssimon#define PCRF_AC_TS1_LBN 0 2083160814Ssimon#define PCRF_AC_TS1_WIDTH 4 2084160814Ssimon 2085160814Ssimon 2086160814Ssimon/* 208755714Skris * PC_SYM_TMR_FLT_MSK_REG(16bit): 208855714Skris * Symbol timer and Filter Mask Register 208955714Skris */ 209055714Skris 209155714Skris#define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 209255714Skris/* sienaa0=pci_f0_config */ 2093160814Ssimon 209455714Skris#define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 209555714Skris#define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 209655714Skris#define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 209755714Skris#define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 209855714Skris#define PCRF_CC_SI1_LBN 8 209955714Skris#define PCRF_CC_SI1_WIDTH 3 210055714Skris#define PCRF_CC_SKIP_INT_VAL_LBN 0 210155714Skris#define PCRF_CC_SKIP_INT_VAL_WIDTH 11 210255714Skris#define PCRF_CC_SI0_LBN 0 210355714Skris#define PCRF_CC_SI0_WIDTH 8 210455714Skris 210555714Skris 210655714Skris/* 210755714Skris * PC_SYM_TMR_REG(16bit): 210855714Skris * Symbol timer register 210955714Skris */ 211055714Skris 211155714Skris#define PCR_AB_SYM_TMR_REG 0x0000071c 211255714Skris/* falcona0,falconb0=pci_f0_config */ 211355714Skris 2114109998Smarkm#define PCRF_AB_ET_LBN 11 2115109998Smarkm#define PCRF_AB_ET_WIDTH 4 2116109998Smarkm#define PCRF_AB_SI1_LBN 8 2117109998Smarkm#define PCRF_AB_SI1_WIDTH 3 2118109998Smarkm#define PCRF_AB_SI0_LBN 0 211955714Skris#define PCRF_AB_SI0_WIDTH 8 212055714Skris 212155714Skris 212255714Skris/* 212355714Skris * PC_FLT_MSK_REG(32bit): 212455714Skris * Filter Mask Register 2 212555714Skris */ 212655714Skris 212755714Skris#define PCR_CC_FLT_MSK_REG 0x00000720 212855714Skris/* sienaa0=pci_f0_config */ 212955714Skris 213055714Skris#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2131111147Snectar#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 213255714Skris 213355714Skris 213455714Skris/* 213555714Skris * PC_PHY_STAT_REG(32bit): 213655714Skris * PHY status register 213776866Skris */ 213876866Skris 213976866Skris#define PCR_AB_PHY_STAT_REG 0x00000720 214076866Skris/* falcona0,falconb0=pci_f0_config */ 214155714Skris 214255714Skris#define PCR_CC_PHY_STAT_REG 0x00000810 214355714Skris/* sienaa0=pci_f0_config */ 214455714Skris 214555714Skris#define PCRF_AC_SSL_LBN 3 214655714Skris#define PCRF_AC_SSL_WIDTH 1 214755714Skris#define PCRF_AC_SSR_LBN 2 214855714Skris#define PCRF_AC_SSR_WIDTH 1 214955714Skris#define PCRF_AC_SSCL_LBN 1 2150109998Smarkm#define PCRF_AC_SSCL_WIDTH 1 2151109998Smarkm#define PCRF_AC_SSCD_LBN 0 2152109998Smarkm#define PCRF_AC_SSCD_WIDTH 1 215355714Skris 2154109998Smarkm 2155109998Smarkm/* 215655714Skris * PC_PHY_CTL_REG(32bit): 215755714Skris * PHY control register 215855714Skris */ 2159109998Smarkm 216055714Skris#define PCR_AB_PHY_CTL_REG 0x00000724 216155714Skris/* falcona0,falconb0=pci_f0_config */ 216255714Skris 216355714Skris#define PCR_CC_PHY_CTL_REG 0x00000814 216455714Skris/* sienaa0=pci_f0_config */ 216555714Skris 2166109998Smarkm#define PCRF_AC_BD_LBN 31 216755714Skris#define PCRF_AC_BD_WIDTH 1 216855714Skris#define PCRF_AC_CDS_LBN 30 216955714Skris#define PCRF_AC_CDS_WIDTH 1 217055714Skris#define PCRF_AC_DWRAP_LB_LBN 29 217155714Skris#define PCRF_AC_DWRAP_LB_WIDTH 1 217255714Skris#define PCRF_AC_EBD_LBN 28 217355714Skris#define PCRF_AC_EBD_WIDTH 1 217455714Skris#define PCRF_AC_SNR_LBN 27 217555714Skris#define PCRF_AC_SNR_WIDTH 1 217655714Skris#define PCRF_AC_RX_NOT_DET_LBN 2 217755714Skris#define PCRF_AC_RX_NOT_DET_WIDTH 1 217855714Skris#define PCRF_AC_FORCE_LOS_VAL_LBN 1 217955714Skris#define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 218055714Skris#define PCRF_AC_FORCE_LOS_EN_LBN 0 218155714Skris#define PCRF_AC_FORCE_LOS_EN_WIDTH 1 218255714Skris 218355714Skris 218455714Skris/* 2185109998Smarkm * PC_DEBUG0_REG(32bit): 2186109998Smarkm * Debug register 0 2187109998Smarkm */ 2188109998Smarkm 2189109998Smarkm#define PCR_AC_DEBUG0_REG 0x00000728 2190109998Smarkm/* falcona0,falconb0,sienaa0=pci_f0_config */ 2191109998Smarkm 2192109998Smarkm#define PCRF_AC_CDI03_LBN 24 2193109998Smarkm#define PCRF_AC_CDI03_WIDTH 8 2194109998Smarkm#define PCRF_AC_CDI0_LBN 0 2195109998Smarkm#define PCRF_AC_CDI0_WIDTH 32 219655714Skris#define PCRF_AC_CDI02_LBN 16 2197160814Ssimon#define PCRF_AC_CDI02_WIDTH 8 2198160814Ssimon#define PCRF_AC_CDI01_LBN 8 219955714Skris#define PCRF_AC_CDI01_WIDTH 8 220055714Skris#define PCRF_AC_CDI00_LBN 0 220155714Skris#define PCRF_AC_CDI00_WIDTH 8 220255714Skris 220355714Skris 220455714Skris/* 220555714Skris * PC_DEBUG1_REG(32bit): 220655714Skris * Debug register 1 220755714Skris */ 220855714Skris 220955714Skris#define PCR_AC_DEBUG1_REG 0x0000072c 221055714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 221155714Skris 221255714Skris#define PCRF_AC_CDI13_LBN 24 221355714Skris#define PCRF_AC_CDI13_WIDTH 8 221455714Skris#define PCRF_AC_CDI1_LBN 0 221555714Skris#define PCRF_AC_CDI1_WIDTH 32 221655714Skris#define PCRF_AC_CDI12_LBN 16 221755714Skris#define PCRF_AC_CDI12_WIDTH 8 221855714Skris#define PCRF_AC_CDI11_LBN 8 221955714Skris#define PCRF_AC_CDI11_WIDTH 8 222055714Skris#define PCRF_AC_CDI10_LBN 0 222155714Skris#define PCRF_AC_CDI10_WIDTH 8 222255714Skris 222355714Skris 222455714Skris/* 222555714Skris * PC_XPFCC_STAT_REG(24bit): 222655714Skris * documentation to be written for sum_PC_XPFCC_STAT_REG 222755714Skris */ 222855714Skris 222955714Skris#define PCR_AC_XPFCC_STAT_REG 0x00000730 223055714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 223155714Skris 223255714Skris#define PCRF_AC_XPDC_LBN 12 223355714Skris#define PCRF_AC_XPDC_WIDTH 8 223455714Skris#define PCRF_AC_XPHC_LBN 0 223555714Skris#define PCRF_AC_XPHC_WIDTH 12 223655714Skris 223755714Skris 223855714Skris/* 223955714Skris * PC_XNPFCC_STAT_REG(24bit): 224068651Skris * documentation to be written for sum_PC_XNPFCC_STAT_REG 224155714Skris */ 224255714Skris 224355714Skris#define PCR_AC_XNPFCC_STAT_REG 0x00000734 224455714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 224555714Skris 224668651Skris#define PCRF_AC_XNPDC_LBN 12 224755714Skris#define PCRF_AC_XNPDC_WIDTH 8 224855714Skris#define PCRF_AC_XNPHC_LBN 0 2249160814Ssimon#define PCRF_AC_XNPHC_WIDTH 12 225055714Skris 225155714Skris 225255714Skris/* 225355714Skris * PC_XCFCC_STAT_REG(24bit): 225455714Skris * documentation to be written for sum_PC_XCFCC_STAT_REG 225555714Skris */ 225655714Skris 225755714Skris#define PCR_AC_XCFCC_STAT_REG 0x00000738 225855714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 225955714Skris 2260160814Ssimon#define PCRF_AC_XCDC_LBN 12 226155714Skris#define PCRF_AC_XCDC_WIDTH 8 226255714Skris#define PCRF_AC_XCHC_LBN 0 226355714Skris#define PCRF_AC_XCHC_WIDTH 12 2264160814Ssimon 226555714Skris 226655714Skris/* 226755714Skris * PC_Q_STAT_REG(8bit): 226855714Skris * documentation to be written for sum_PC_Q_STAT_REG 226955714Skris */ 227055714Skris 227155714Skris#define PCR_AC_Q_STAT_REG 0x0000073c 227255714Skris/* falcona0,falconb0,sienaa0=pci_f0_config */ 227355714Skris 227455714Skris#define PCRF_AC_RQNE_LBN 2 227555714Skris#define PCRF_AC_RQNE_WIDTH 1 227655714Skris#define PCRF_AC_XRNE_LBN 1 227755714Skris#define PCRF_AC_XRNE_WIDTH 1 227855714Skris#define PCRF_AC_RCNR_LBN 0 227955714Skris#define PCRF_AC_RCNR_WIDTH 1 228055714Skris 2281160814Ssimon 228255714Skris/* 228355714Skris * PC_VC_XMIT_ARB1_REG(32bit): 228455714Skris * VC Transmit Arbitration Register 1 228555714Skris */ 228655714Skris 2287160814Ssimon#define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2288160814Ssimon/* sienaa0=pci_f0_config */ 2289160814Ssimon 2290160814Ssimon 2291160814Ssimon 2292160814Ssimon/* 2293160814Ssimon * PC_VC_XMIT_ARB2_REG(32bit): 2294160814Ssimon * VC Transmit Arbitration Register 2 2295160814Ssimon */ 2296160814Ssimon 229755714Skris#define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2298160814Ssimon/* sienaa0=pci_f0_config */ 2299160814Ssimon 2300160814Ssimon 2301160814Ssimon 2302160814Ssimon/* 2303160814Ssimon * PC_VC0_P_RQ_CTL_REG(32bit): 2304160814Ssimon * VC0 Posted Receive Queue Control 2305160814Ssimon */ 2306160814Ssimon 2307160814Ssimon#define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2308160814Ssimon/* sienaa0=pci_f0_config */ 2309160814Ssimon 2310160814Ssimon 2311160814Ssimon 2312160814Ssimon/* 231355714Skris * PC_VC0_NP_RQ_CTL_REG(32bit): 231455714Skris * VC0 Non-Posted Receive Queue Control 231555714Skris */ 231655714Skris 231755714Skris#define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 231855714Skris/* sienaa0=pci_f0_config */ 231955714Skris 232055714Skris 232155714Skris 232255714Skris/* 232355714Skris * PC_VC0_C_RQ_CTL_REG(32bit): 232455714Skris * VC0 Completion Receive Queue Control 232555714Skris */ 232655714Skris 232755714Skris#define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 232855714Skris/* sienaa0=pci_f0_config */ 232955714Skris 233055714Skris 233155714Skris 233255714Skris/* 233355714Skris * PC_GEN2_REG(32bit): 233455714Skris * Gen2 Register 233555714Skris */ 233655714Skris 233755714Skris#define PCR_CC_GEN2_REG 0x0000080c 233855714Skris/* sienaa0=pci_f0_config */ 233955714Skris 234055714Skris#define PCRF_CC_SET_DE_EMPHASIS_LBN 20 234155714Skris#define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 234255714Skris#define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 234355714Skris#define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 234455714Skris#define PCRF_CC_CFG_TX_SWING_LBN 18 234555714Skris#define PCRF_CC_CFG_TX_SWING_WIDTH 1 234655714Skris#define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 234755714Skris#define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 234855714Skris#define PCRF_CC_LANE_ENABLE_LBN 8 234955714Skris#define PCRF_CC_LANE_ENABLE_WIDTH 9 235055714Skris#define PCRF_CC_NUM_FTS_LBN 0 235155714Skris#define PCRF_CC_NUM_FTS_WIDTH 8 235255714Skris 235355714Skris 235455714Skris#ifdef __cplusplus 235555714Skris} 235668651Skris#endif 235768651Skris 235868651Skris#endif /* _SYS_EFX_REGS_PCI_H */ 235968651Skris