efx_ev.c revision 310930
1/*- 2 * Copyright (c) 2007-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/sfxge/common/efx_ev.c 310930 2016-12-31 11:12:26Z arybchik $"); 33 34#include "efx.h" 35#include "efx_impl.h" 36#if EFSYS_OPT_MON_MCDI 37#include "mcdi_mon.h" 38#endif 39 40#if EFSYS_OPT_QSTATS 41#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 42 do { \ 43 (_eep)->ee_stat[_stat]++; \ 44 _NOTE(CONSTANTCONDITION) \ 45 } while (B_FALSE) 46#else 47#define EFX_EV_QSTAT_INCR(_eep, _stat) 48#endif 49 50#define EFX_EV_PRESENT(_qword) \ 51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 53 54 55 56#if EFSYS_OPT_SIENA 57 58static __checkReturn efx_rc_t 59siena_ev_init( 60 __in efx_nic_t *enp); 61 62static void 63siena_ev_fini( 64 __in efx_nic_t *enp); 65 66static __checkReturn efx_rc_t 67siena_ev_qcreate( 68 __in efx_nic_t *enp, 69 __in unsigned int index, 70 __in efsys_mem_t *esmp, 71 __in size_t n, 72 __in uint32_t id, 73 __in uint32_t us, 74 __in efx_evq_t *eep); 75 76static void 77siena_ev_qdestroy( 78 __in efx_evq_t *eep); 79 80static __checkReturn efx_rc_t 81siena_ev_qprime( 82 __in efx_evq_t *eep, 83 __in unsigned int count); 84 85static void 86siena_ev_qpoll( 87 __in efx_evq_t *eep, 88 __inout unsigned int *countp, 89 __in const efx_ev_callbacks_t *eecp, 90 __in_opt void *arg); 91 92static void 93siena_ev_qpost( 94 __in efx_evq_t *eep, 95 __in uint16_t data); 96 97static __checkReturn efx_rc_t 98siena_ev_qmoderate( 99 __in efx_evq_t *eep, 100 __in unsigned int us); 101 102#if EFSYS_OPT_QSTATS 103static void 104siena_ev_qstats_update( 105 __in efx_evq_t *eep, 106 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 107 108#endif 109 110#endif /* EFSYS_OPT_SIENA */ 111 112#if EFSYS_OPT_SIENA 113static const efx_ev_ops_t __efx_ev_siena_ops = { 114 siena_ev_init, /* eevo_init */ 115 siena_ev_fini, /* eevo_fini */ 116 siena_ev_qcreate, /* eevo_qcreate */ 117 siena_ev_qdestroy, /* eevo_qdestroy */ 118 siena_ev_qprime, /* eevo_qprime */ 119 siena_ev_qpost, /* eevo_qpost */ 120 siena_ev_qmoderate, /* eevo_qmoderate */ 121#if EFSYS_OPT_QSTATS 122 siena_ev_qstats_update, /* eevo_qstats_update */ 123#endif 124}; 125#endif /* EFSYS_OPT_SIENA */ 126 127#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 128static const efx_ev_ops_t __efx_ev_ef10_ops = { 129 ef10_ev_init, /* eevo_init */ 130 ef10_ev_fini, /* eevo_fini */ 131 ef10_ev_qcreate, /* eevo_qcreate */ 132 ef10_ev_qdestroy, /* eevo_qdestroy */ 133 ef10_ev_qprime, /* eevo_qprime */ 134 ef10_ev_qpost, /* eevo_qpost */ 135 ef10_ev_qmoderate, /* eevo_qmoderate */ 136#if EFSYS_OPT_QSTATS 137 ef10_ev_qstats_update, /* eevo_qstats_update */ 138#endif 139}; 140#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 141 142 143 __checkReturn efx_rc_t 144efx_ev_init( 145 __in efx_nic_t *enp) 146{ 147 const efx_ev_ops_t *eevop; 148 efx_rc_t rc; 149 150 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 151 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 152 153 if (enp->en_mod_flags & EFX_MOD_EV) { 154 rc = EINVAL; 155 goto fail1; 156 } 157 158 switch (enp->en_family) { 159#if EFSYS_OPT_SIENA 160 case EFX_FAMILY_SIENA: 161 eevop = &__efx_ev_siena_ops; 162 break; 163#endif /* EFSYS_OPT_SIENA */ 164 165#if EFSYS_OPT_HUNTINGTON 166 case EFX_FAMILY_HUNTINGTON: 167 eevop = &__efx_ev_ef10_ops; 168 break; 169#endif /* EFSYS_OPT_HUNTINGTON */ 170 171#if EFSYS_OPT_MEDFORD 172 case EFX_FAMILY_MEDFORD: 173 eevop = &__efx_ev_ef10_ops; 174 break; 175#endif /* EFSYS_OPT_MEDFORD */ 176 177 default: 178 EFSYS_ASSERT(0); 179 rc = ENOTSUP; 180 goto fail1; 181 } 182 183 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 184 185 if ((rc = eevop->eevo_init(enp)) != 0) 186 goto fail2; 187 188 enp->en_eevop = eevop; 189 enp->en_mod_flags |= EFX_MOD_EV; 190 return (0); 191 192fail2: 193 EFSYS_PROBE(fail2); 194 195fail1: 196 EFSYS_PROBE1(fail1, efx_rc_t, rc); 197 198 enp->en_eevop = NULL; 199 enp->en_mod_flags &= ~EFX_MOD_EV; 200 return (rc); 201} 202 203 void 204efx_ev_fini( 205 __in efx_nic_t *enp) 206{ 207 const efx_ev_ops_t *eevop = enp->en_eevop; 208 209 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 211 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 212 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 213 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 214 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 215 216 eevop->eevo_fini(enp); 217 218 enp->en_eevop = NULL; 219 enp->en_mod_flags &= ~EFX_MOD_EV; 220} 221 222 223 __checkReturn efx_rc_t 224efx_ev_qcreate( 225 __in efx_nic_t *enp, 226 __in unsigned int index, 227 __in efsys_mem_t *esmp, 228 __in size_t n, 229 __in uint32_t id, 230 __in uint32_t us, 231 __deref_out efx_evq_t **eepp) 232{ 233 const efx_ev_ops_t *eevop = enp->en_eevop; 234 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 235 efx_evq_t *eep; 236 efx_rc_t rc; 237 238 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 239 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 240 241 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 242 243 /* Allocate an EVQ object */ 244 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 245 if (eep == NULL) { 246 rc = ENOMEM; 247 goto fail1; 248 } 249 250 eep->ee_magic = EFX_EVQ_MAGIC; 251 eep->ee_enp = enp; 252 eep->ee_index = index; 253 eep->ee_mask = n - 1; 254 eep->ee_esmp = esmp; 255 256 /* 257 * Set outputs before the queue is created because interrupts may be 258 * raised for events immediately after the queue is created, before the 259 * function call below returns. See bug58606. 260 * 261 * The eepp pointer passed in by the client must therefore point to data 262 * shared with the client's event processing context. 263 */ 264 enp->en_ev_qcount++; 265 *eepp = eep; 266 267 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, eep)) != 0) 268 goto fail2; 269 270 return (0); 271 272fail2: 273 EFSYS_PROBE(fail2); 274 275 *eepp = NULL; 276 enp->en_ev_qcount--; 277 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 278fail1: 279 EFSYS_PROBE1(fail1, efx_rc_t, rc); 280 return (rc); 281} 282 283 void 284efx_ev_qdestroy( 285 __in efx_evq_t *eep) 286{ 287 efx_nic_t *enp = eep->ee_enp; 288 const efx_ev_ops_t *eevop = enp->en_eevop; 289 290 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 291 292 EFSYS_ASSERT(enp->en_ev_qcount != 0); 293 --enp->en_ev_qcount; 294 295 eevop->eevo_qdestroy(eep); 296 297 /* Free the EVQ object */ 298 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 299} 300 301 __checkReturn efx_rc_t 302efx_ev_qprime( 303 __in efx_evq_t *eep, 304 __in unsigned int count) 305{ 306 efx_nic_t *enp = eep->ee_enp; 307 const efx_ev_ops_t *eevop = enp->en_eevop; 308 efx_rc_t rc; 309 310 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 311 312 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 313 rc = EINVAL; 314 goto fail1; 315 } 316 317 if ((rc = eevop->eevo_qprime(eep, count)) != 0) 318 goto fail2; 319 320 return (0); 321 322fail2: 323 EFSYS_PROBE(fail2); 324fail1: 325 EFSYS_PROBE1(fail1, efx_rc_t, rc); 326 return (rc); 327} 328 329 __checkReturn boolean_t 330efx_ev_qpending( 331 __in efx_evq_t *eep, 332 __in unsigned int count) 333{ 334 size_t offset; 335 efx_qword_t qword; 336 337 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 338 339 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 340 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 341 342 return (EFX_EV_PRESENT(qword)); 343} 344 345#if EFSYS_OPT_EV_PREFETCH 346 347 void 348efx_ev_qprefetch( 349 __in efx_evq_t *eep, 350 __in unsigned int count) 351{ 352 unsigned int offset; 353 354 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 355 356 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 357 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 358} 359 360#endif /* EFSYS_OPT_EV_PREFETCH */ 361 362 void 363efx_ev_qpoll( 364 __in efx_evq_t *eep, 365 __inout unsigned int *countp, 366 __in const efx_ev_callbacks_t *eecp, 367 __in_opt void *arg) 368{ 369 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 370 371 /* 372 * FIXME: Huntington will require support for hardware event batching 373 * and merging, which will need a different ev_qpoll implementation. 374 * 375 * Without those features the Falcon/Siena code can be used unchanged. 376 */ 377 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); 378 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); 379 380 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); 381 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); 382 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); 383 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == 384 FSE_AZ_EV_CODE_DRV_GEN_EV); 385#if EFSYS_OPT_MCDI 386 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == 387 FSE_AZ_EV_CODE_MCDI_EVRESPONSE); 388#endif 389 siena_ev_qpoll(eep, countp, eecp, arg); 390} 391 392 void 393efx_ev_qpost( 394 __in efx_evq_t *eep, 395 __in uint16_t data) 396{ 397 efx_nic_t *enp = eep->ee_enp; 398 const efx_ev_ops_t *eevop = enp->en_eevop; 399 400 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 401 402 EFSYS_ASSERT(eevop != NULL && 403 eevop->eevo_qpost != NULL); 404 405 eevop->eevo_qpost(eep, data); 406} 407 408 __checkReturn efx_rc_t 409efx_ev_usecs_to_ticks( 410 __in efx_nic_t *enp, 411 __in unsigned int us, 412 __out unsigned int *ticksp) 413{ 414 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 415 unsigned int ticks; 416 417 /* Convert microseconds to a timer tick count */ 418 if (us == 0) 419 ticks = 0; 420 else if (us * 1000 < encp->enc_evq_timer_quantum_ns) 421 ticks = 1; /* Never round down to zero */ 422 else 423 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns; 424 425 *ticksp = ticks; 426 return (0); 427} 428 429 __checkReturn efx_rc_t 430efx_ev_qmoderate( 431 __in efx_evq_t *eep, 432 __in unsigned int us) 433{ 434 efx_nic_t *enp = eep->ee_enp; 435 const efx_ev_ops_t *eevop = enp->en_eevop; 436 efx_rc_t rc; 437 438 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 439 440 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) 441 goto fail1; 442 443 return (0); 444 445fail1: 446 EFSYS_PROBE1(fail1, efx_rc_t, rc); 447 return (rc); 448} 449 450#if EFSYS_OPT_QSTATS 451 void 452efx_ev_qstats_update( 453 __in efx_evq_t *eep, 454 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 455 456{ efx_nic_t *enp = eep->ee_enp; 457 const efx_ev_ops_t *eevop = enp->en_eevop; 458 459 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 460 461 eevop->eevo_qstats_update(eep, stat); 462} 463 464#endif /* EFSYS_OPT_QSTATS */ 465 466#if EFSYS_OPT_SIENA 467 468static __checkReturn efx_rc_t 469siena_ev_init( 470 __in efx_nic_t *enp) 471{ 472 efx_oword_t oword; 473 474 /* 475 * Program the event queue for receive and transmit queue 476 * flush events. 477 */ 478 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 479 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 480 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 481 482 return (0); 483 484} 485 486static __checkReturn boolean_t 487siena_ev_rx_not_ok( 488 __in efx_evq_t *eep, 489 __in efx_qword_t *eqp, 490 __in uint32_t label, 491 __in uint32_t id, 492 __inout uint16_t *flagsp) 493{ 494 boolean_t ignore = B_FALSE; 495 496 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 497 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 498 EFSYS_PROBE(tobe_disc); 499 /* 500 * Assume this is a unicast address mismatch, unless below 501 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 502 * EV_RX_PAUSE_FRM_ERR is set. 503 */ 504 (*flagsp) |= EFX_ADDR_MISMATCH; 505 } 506 507 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 508 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 509 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 510 (*flagsp) |= EFX_DISCARD; 511 512#if EFSYS_OPT_RX_SCATTER 513 /* 514 * Lookout for payload queue ran dry errors and ignore them. 515 * 516 * Sadly for the header/data split cases, the descriptor 517 * pointer in this event refers to the header queue and 518 * therefore cannot be easily detected as duplicate. 519 * So we drop these and rely on the receive processing seeing 520 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 521 * the partially received packet. 522 */ 523 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 524 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 525 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 526 ignore = B_TRUE; 527#endif /* EFSYS_OPT_RX_SCATTER */ 528 } 529 530 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 531 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 532 EFSYS_PROBE(crc_err); 533 (*flagsp) &= ~EFX_ADDR_MISMATCH; 534 (*flagsp) |= EFX_DISCARD; 535 } 536 537 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 538 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 539 EFSYS_PROBE(pause_frm_err); 540 (*flagsp) &= ~EFX_ADDR_MISMATCH; 541 (*flagsp) |= EFX_DISCARD; 542 } 543 544 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 545 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 546 EFSYS_PROBE(owner_id_err); 547 (*flagsp) |= EFX_DISCARD; 548 } 549 550 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 551 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 552 EFSYS_PROBE(ipv4_err); 553 (*flagsp) &= ~EFX_CKSUM_IPV4; 554 } 555 556 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 557 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 558 EFSYS_PROBE(udp_chk_err); 559 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 560 } 561 562 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 563 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 564 565 /* 566 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 567 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 568 * condition. 569 */ 570 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 571 } 572 573 return (ignore); 574} 575 576static __checkReturn boolean_t 577siena_ev_rx( 578 __in efx_evq_t *eep, 579 __in efx_qword_t *eqp, 580 __in const efx_ev_callbacks_t *eecp, 581 __in_opt void *arg) 582{ 583 uint32_t id; 584 uint32_t size; 585 uint32_t label; 586 boolean_t ok; 587#if EFSYS_OPT_RX_SCATTER 588 boolean_t sop; 589 boolean_t jumbo_cont; 590#endif /* EFSYS_OPT_RX_SCATTER */ 591 uint32_t hdr_type; 592 boolean_t is_v6; 593 uint16_t flags; 594 boolean_t ignore; 595 boolean_t should_abort; 596 597 EFX_EV_QSTAT_INCR(eep, EV_RX); 598 599 /* Basic packet information */ 600 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 601 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 602 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 603 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 604 605#if EFSYS_OPT_RX_SCATTER 606 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 607 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 608#endif /* EFSYS_OPT_RX_SCATTER */ 609 610 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 611 612 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 613 614 /* 615 * If packet is marked as OK and packet type is TCP/IP or 616 * UDP/IP or other IP, then we can rely on the hardware checksums. 617 */ 618 switch (hdr_type) { 619 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 620 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 621 if (is_v6) { 622 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 623 flags |= EFX_PKT_IPV6; 624 } else { 625 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 626 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 627 } 628 break; 629 630 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 631 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 632 if (is_v6) { 633 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 634 flags |= EFX_PKT_IPV6; 635 } else { 636 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 637 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 638 } 639 break; 640 641 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 642 if (is_v6) { 643 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 644 flags = EFX_PKT_IPV6; 645 } else { 646 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 647 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 648 } 649 break; 650 651 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 652 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 653 flags = 0; 654 break; 655 656 default: 657 EFSYS_ASSERT(B_FALSE); 658 flags = 0; 659 break; 660 } 661 662#if EFSYS_OPT_RX_SCATTER 663 /* Report scatter and header/lookahead split buffer flags */ 664 if (sop) 665 flags |= EFX_PKT_START; 666 if (jumbo_cont) 667 flags |= EFX_PKT_CONT; 668#endif /* EFSYS_OPT_RX_SCATTER */ 669 670 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 671 if (!ok) { 672 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags); 673 if (ignore) { 674 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 675 uint32_t, size, uint16_t, flags); 676 677 return (B_FALSE); 678 } 679 } 680 681 /* If we're not discarding the packet then it is ok */ 682 if (~flags & EFX_DISCARD) 683 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 684 685 /* Detect multicast packets that didn't match the filter */ 686 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 687 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 688 689 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 690 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 691 } else { 692 EFSYS_PROBE(mcast_mismatch); 693 flags |= EFX_ADDR_MISMATCH; 694 } 695 } else { 696 flags |= EFX_PKT_UNICAST; 697 } 698 699 /* 700 * The packet parser in Siena can abort parsing packets under 701 * certain error conditions, setting the PKT_NOT_PARSED bit 702 * (which clears PKT_OK). If this is set, then don't trust 703 * the PKT_TYPE field. 704 */ 705 if (!ok) { 706 uint32_t parse_err; 707 708 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 709 if (parse_err != 0) 710 flags |= EFX_CHECK_VLAN; 711 } 712 713 if (~flags & EFX_CHECK_VLAN) { 714 uint32_t pkt_type; 715 716 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 717 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 718 flags |= EFX_PKT_VLAN_TAGGED; 719 } 720 721 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 722 uint32_t, size, uint16_t, flags); 723 724 EFSYS_ASSERT(eecp->eec_rx != NULL); 725 should_abort = eecp->eec_rx(arg, label, id, size, flags); 726 727 return (should_abort); 728} 729 730static __checkReturn boolean_t 731siena_ev_tx( 732 __in efx_evq_t *eep, 733 __in efx_qword_t *eqp, 734 __in const efx_ev_callbacks_t *eecp, 735 __in_opt void *arg) 736{ 737 uint32_t id; 738 uint32_t label; 739 boolean_t should_abort; 740 741 EFX_EV_QSTAT_INCR(eep, EV_TX); 742 743 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 744 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 745 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 746 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 747 748 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 749 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 750 751 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 752 753 EFSYS_ASSERT(eecp->eec_tx != NULL); 754 should_abort = eecp->eec_tx(arg, label, id); 755 756 return (should_abort); 757 } 758 759 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 760 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 761 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 762 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 763 764 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 765 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 766 767 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 768 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 769 770 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 771 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 772 773 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 774 return (B_FALSE); 775} 776 777static __checkReturn boolean_t 778siena_ev_global( 779 __in efx_evq_t *eep, 780 __in efx_qword_t *eqp, 781 __in const efx_ev_callbacks_t *eecp, 782 __in_opt void *arg) 783{ 784 _NOTE(ARGUNUSED(eqp, eecp, arg)) 785 786 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 787 788 return (B_FALSE); 789} 790 791static __checkReturn boolean_t 792siena_ev_driver( 793 __in efx_evq_t *eep, 794 __in efx_qword_t *eqp, 795 __in const efx_ev_callbacks_t *eecp, 796 __in_opt void *arg) 797{ 798 boolean_t should_abort; 799 800 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 801 should_abort = B_FALSE; 802 803 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 804 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 805 uint32_t txq_index; 806 807 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 808 809 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 810 811 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 812 813 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 814 should_abort = eecp->eec_txq_flush_done(arg, txq_index); 815 816 break; 817 } 818 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 819 uint32_t rxq_index; 820 uint32_t failed; 821 822 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 823 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 824 825 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 826 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 827 828 if (failed) { 829 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 830 831 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 832 833 should_abort = eecp->eec_rxq_flush_failed(arg, 834 rxq_index); 835 } else { 836 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 837 838 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 839 840 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 841 } 842 843 break; 844 } 845 case FSE_AZ_EVQ_INIT_DONE_EV: 846 EFSYS_ASSERT(eecp->eec_initialized != NULL); 847 should_abort = eecp->eec_initialized(arg); 848 849 break; 850 851 case FSE_AZ_EVQ_NOT_EN_EV: 852 EFSYS_PROBE(evq_not_en); 853 break; 854 855 case FSE_AZ_SRM_UPD_DONE_EV: { 856 uint32_t code; 857 858 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 859 860 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 861 862 EFSYS_ASSERT(eecp->eec_sram != NULL); 863 should_abort = eecp->eec_sram(arg, code); 864 865 break; 866 } 867 case FSE_AZ_WAKE_UP_EV: { 868 uint32_t id; 869 870 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 871 872 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 873 should_abort = eecp->eec_wake_up(arg, id); 874 875 break; 876 } 877 case FSE_AZ_TX_PKT_NON_TCP_UDP: 878 EFSYS_PROBE(tx_pkt_non_tcp_udp); 879 break; 880 881 case FSE_AZ_TIMER_EV: { 882 uint32_t id; 883 884 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 885 886 EFSYS_ASSERT(eecp->eec_timer != NULL); 887 should_abort = eecp->eec_timer(arg, id); 888 889 break; 890 } 891 case FSE_AZ_RX_DSC_ERROR_EV: 892 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 893 894 EFSYS_PROBE(rx_dsc_error); 895 896 EFSYS_ASSERT(eecp->eec_exception != NULL); 897 should_abort = eecp->eec_exception(arg, 898 EFX_EXCEPTION_RX_DSC_ERROR, 0); 899 900 break; 901 902 case FSE_AZ_TX_DSC_ERROR_EV: 903 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 904 905 EFSYS_PROBE(tx_dsc_error); 906 907 EFSYS_ASSERT(eecp->eec_exception != NULL); 908 should_abort = eecp->eec_exception(arg, 909 EFX_EXCEPTION_TX_DSC_ERROR, 0); 910 911 break; 912 913 default: 914 break; 915 } 916 917 return (should_abort); 918} 919 920static __checkReturn boolean_t 921siena_ev_drv_gen( 922 __in efx_evq_t *eep, 923 __in efx_qword_t *eqp, 924 __in const efx_ev_callbacks_t *eecp, 925 __in_opt void *arg) 926{ 927 uint32_t data; 928 boolean_t should_abort; 929 930 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 931 932 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 933 if (data >= ((uint32_t)1 << 16)) { 934 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 935 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 936 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 937 return (B_TRUE); 938 } 939 940 EFSYS_ASSERT(eecp->eec_software != NULL); 941 should_abort = eecp->eec_software(arg, (uint16_t)data); 942 943 return (should_abort); 944} 945 946#if EFSYS_OPT_MCDI 947 948static __checkReturn boolean_t 949siena_ev_mcdi( 950 __in efx_evq_t *eep, 951 __in efx_qword_t *eqp, 952 __in const efx_ev_callbacks_t *eecp, 953 __in_opt void *arg) 954{ 955 efx_nic_t *enp = eep->ee_enp; 956 unsigned int code; 957 boolean_t should_abort = B_FALSE; 958 959 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 960 961 if (enp->en_family != EFX_FAMILY_SIENA) 962 goto out; 963 964 EFSYS_ASSERT(eecp->eec_link_change != NULL); 965 EFSYS_ASSERT(eecp->eec_exception != NULL); 966#if EFSYS_OPT_MON_STATS 967 EFSYS_ASSERT(eecp->eec_monitor != NULL); 968#endif 969 970 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 971 972 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 973 switch (code) { 974 case MCDI_EVENT_CODE_BADSSERT: 975 efx_mcdi_ev_death(enp, EINTR); 976 break; 977 978 case MCDI_EVENT_CODE_CMDDONE: 979 efx_mcdi_ev_cpl(enp, 980 MCDI_EV_FIELD(eqp, CMDDONE_SEQ), 981 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), 982 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); 983 break; 984 985 case MCDI_EVENT_CODE_LINKCHANGE: { 986 efx_link_mode_t link_mode; 987 988 siena_phy_link_ev(enp, eqp, &link_mode); 989 should_abort = eecp->eec_link_change(arg, link_mode); 990 break; 991 } 992 case MCDI_EVENT_CODE_SENSOREVT: { 993#if EFSYS_OPT_MON_STATS 994 efx_mon_stat_t id; 995 efx_mon_stat_value_t value; 996 efx_rc_t rc; 997 998 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) 999 should_abort = eecp->eec_monitor(arg, id, value); 1000 else if (rc == ENOTSUP) { 1001 should_abort = eecp->eec_exception(arg, 1002 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 1003 MCDI_EV_FIELD(eqp, DATA)); 1004 } else 1005 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 1006#else 1007 should_abort = B_FALSE; 1008#endif 1009 break; 1010 } 1011 case MCDI_EVENT_CODE_SCHEDERR: 1012 /* Informational only */ 1013 break; 1014 1015 case MCDI_EVENT_CODE_REBOOT: 1016 efx_mcdi_ev_death(enp, EIO); 1017 break; 1018 1019 case MCDI_EVENT_CODE_MAC_STATS_DMA: 1020#if EFSYS_OPT_MAC_STATS 1021 if (eecp->eec_mac_stats != NULL) { 1022 eecp->eec_mac_stats(arg, 1023 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 1024 } 1025#endif 1026 break; 1027 1028 case MCDI_EVENT_CODE_FWALERT: { 1029 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 1030 1031 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 1032 should_abort = eecp->eec_exception(arg, 1033 EFX_EXCEPTION_FWALERT_SRAM, 1034 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 1035 else 1036 should_abort = eecp->eec_exception(arg, 1037 EFX_EXCEPTION_UNKNOWN_FWALERT, 1038 MCDI_EV_FIELD(eqp, DATA)); 1039 break; 1040 } 1041 1042 default: 1043 EFSYS_PROBE1(mc_pcol_error, int, code); 1044 break; 1045 } 1046 1047out: 1048 return (should_abort); 1049} 1050 1051#endif /* EFSYS_OPT_MCDI */ 1052 1053static __checkReturn efx_rc_t 1054siena_ev_qprime( 1055 __in efx_evq_t *eep, 1056 __in unsigned int count) 1057{ 1058 efx_nic_t *enp = eep->ee_enp; 1059 uint32_t rptr; 1060 efx_dword_t dword; 1061 1062 rptr = count & eep->ee_mask; 1063 1064 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 1065 1066 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 1067 &dword, B_FALSE); 1068 1069 return (0); 1070} 1071 1072#define EFX_EV_BATCH 8 1073 1074static void 1075siena_ev_qpoll( 1076 __in efx_evq_t *eep, 1077 __inout unsigned int *countp, 1078 __in const efx_ev_callbacks_t *eecp, 1079 __in_opt void *arg) 1080{ 1081 efx_qword_t ev[EFX_EV_BATCH]; 1082 unsigned int batch; 1083 unsigned int total; 1084 unsigned int count; 1085 unsigned int index; 1086 size_t offset; 1087 1088 EFSYS_ASSERT(countp != NULL); 1089 EFSYS_ASSERT(eecp != NULL); 1090 1091 count = *countp; 1092 do { 1093 /* Read up until the end of the batch period */ 1094 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 1095 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1096 for (total = 0; total < batch; ++total) { 1097 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 1098 1099 if (!EFX_EV_PRESENT(ev[total])) 1100 break; 1101 1102 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 1103 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 1104 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 1105 1106 offset += sizeof (efx_qword_t); 1107 } 1108 1109#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 1110 /* 1111 * Prefetch the next batch when we get within PREFETCH_PERIOD 1112 * of a completed batch. If the batch is smaller, then prefetch 1113 * immediately. 1114 */ 1115 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 1116 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1117#endif /* EFSYS_OPT_EV_PREFETCH */ 1118 1119 /* Process the batch of events */ 1120 for (index = 0; index < total; ++index) { 1121 boolean_t should_abort; 1122 uint32_t code; 1123 1124#if EFSYS_OPT_EV_PREFETCH 1125 /* Prefetch if we've now reached the batch period */ 1126 if (total == batch && 1127 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 1128 offset = (count + batch) & eep->ee_mask; 1129 offset *= sizeof (efx_qword_t); 1130 1131 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1132 } 1133#endif /* EFSYS_OPT_EV_PREFETCH */ 1134 1135 EFX_EV_QSTAT_INCR(eep, EV_ALL); 1136 1137 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 1138 switch (code) { 1139 case FSE_AZ_EV_CODE_RX_EV: 1140 should_abort = eep->ee_rx(eep, 1141 &(ev[index]), eecp, arg); 1142 break; 1143 case FSE_AZ_EV_CODE_TX_EV: 1144 should_abort = eep->ee_tx(eep, 1145 &(ev[index]), eecp, arg); 1146 break; 1147 case FSE_AZ_EV_CODE_DRIVER_EV: 1148 should_abort = eep->ee_driver(eep, 1149 &(ev[index]), eecp, arg); 1150 break; 1151 case FSE_AZ_EV_CODE_DRV_GEN_EV: 1152 should_abort = eep->ee_drv_gen(eep, 1153 &(ev[index]), eecp, arg); 1154 break; 1155#if EFSYS_OPT_MCDI 1156 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: 1157 should_abort = eep->ee_mcdi(eep, 1158 &(ev[index]), eecp, arg); 1159 break; 1160#endif 1161 case FSE_AZ_EV_CODE_GLOBAL_EV: 1162 if (eep->ee_global) { 1163 should_abort = eep->ee_global(eep, 1164 &(ev[index]), eecp, arg); 1165 break; 1166 } 1167 /* else fallthrough */ 1168 default: 1169 EFSYS_PROBE3(bad_event, 1170 unsigned int, eep->ee_index, 1171 uint32_t, 1172 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), 1173 uint32_t, 1174 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); 1175 1176 EFSYS_ASSERT(eecp->eec_exception != NULL); 1177 (void) eecp->eec_exception(arg, 1178 EFX_EXCEPTION_EV_ERROR, code); 1179 should_abort = B_TRUE; 1180 } 1181 if (should_abort) { 1182 /* Ignore subsequent events */ 1183 total = index + 1; 1184 break; 1185 } 1186 } 1187 1188 /* 1189 * Now that the hardware has most likely moved onto dma'ing 1190 * into the next cache line, clear the processed events. Take 1191 * care to only clear out events that we've processed 1192 */ 1193 EFX_SET_QWORD(ev[0]); 1194 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1195 for (index = 0; index < total; ++index) { 1196 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 1197 offset += sizeof (efx_qword_t); 1198 } 1199 1200 count += total; 1201 1202 } while (total == batch); 1203 1204 *countp = count; 1205} 1206 1207static void 1208siena_ev_qpost( 1209 __in efx_evq_t *eep, 1210 __in uint16_t data) 1211{ 1212 efx_nic_t *enp = eep->ee_enp; 1213 efx_qword_t ev; 1214 efx_oword_t oword; 1215 1216 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 1217 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 1218 1219 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 1220 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 1221 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 1222 1223 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 1224} 1225 1226static __checkReturn efx_rc_t 1227siena_ev_qmoderate( 1228 __in efx_evq_t *eep, 1229 __in unsigned int us) 1230{ 1231 efx_nic_t *enp = eep->ee_enp; 1232 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1233 unsigned int locked; 1234 efx_dword_t dword; 1235 efx_rc_t rc; 1236 1237 if (us > encp->enc_evq_timer_max_us) { 1238 rc = EINVAL; 1239 goto fail1; 1240 } 1241 1242 /* If the value is zero then disable the timer */ 1243 if (us == 0) { 1244 EFX_POPULATE_DWORD_2(dword, 1245 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 1246 FRF_CZ_TC_TIMER_VAL, 0); 1247 } else { 1248 unsigned int ticks; 1249 1250 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0) 1251 goto fail2; 1252 1253 EFSYS_ASSERT(ticks > 0); 1254 EFX_POPULATE_DWORD_2(dword, 1255 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 1256 FRF_CZ_TC_TIMER_VAL, ticks - 1); 1257 } 1258 1259 locked = (eep->ee_index == 0) ? 1 : 0; 1260 1261 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 1262 eep->ee_index, &dword, locked); 1263 1264 return (0); 1265 1266fail2: 1267 EFSYS_PROBE(fail2); 1268fail1: 1269 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1270 1271 return (rc); 1272} 1273 1274static __checkReturn efx_rc_t 1275siena_ev_qcreate( 1276 __in efx_nic_t *enp, 1277 __in unsigned int index, 1278 __in efsys_mem_t *esmp, 1279 __in size_t n, 1280 __in uint32_t id, 1281 __in uint32_t us, 1282 __in efx_evq_t *eep) 1283{ 1284 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1285 uint32_t size; 1286 efx_oword_t oword; 1287 efx_rc_t rc; 1288 1289 _NOTE(ARGUNUSED(esmp)) 1290 1291 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); 1292 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); 1293 1294 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { 1295 rc = EINVAL; 1296 goto fail1; 1297 } 1298 if (index >= encp->enc_evq_limit) { 1299 rc = EINVAL; 1300 goto fail2; 1301 } 1302#if EFSYS_OPT_RX_SCALE 1303 if (enp->en_intr.ei_type == EFX_INTR_LINE && 1304 index >= EFX_MAXRSS_LEGACY) { 1305 rc = EINVAL; 1306 goto fail3; 1307 } 1308#endif 1309 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 1310 size++) 1311 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 1312 break; 1313 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1314 rc = EINVAL; 1315 goto fail4; 1316 } 1317 1318 /* Set up the handler table */ 1319 eep->ee_rx = siena_ev_rx; 1320 eep->ee_tx = siena_ev_tx; 1321 eep->ee_driver = siena_ev_driver; 1322 eep->ee_global = siena_ev_global; 1323 eep->ee_drv_gen = siena_ev_drv_gen; 1324#if EFSYS_OPT_MCDI 1325 eep->ee_mcdi = siena_ev_mcdi; 1326#endif /* EFSYS_OPT_MCDI */ 1327 1328 /* Set up the new event queue */ 1329 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 1330 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); 1331 1332 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 1333 FRF_AZ_EVQ_BUF_BASE_ID, id); 1334 1335 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); 1336 1337 /* Set initial interrupt moderation */ 1338 siena_ev_qmoderate(eep, us); 1339 1340 return (0); 1341 1342fail4: 1343 EFSYS_PROBE(fail4); 1344#if EFSYS_OPT_RX_SCALE 1345fail3: 1346 EFSYS_PROBE(fail3); 1347#endif 1348fail2: 1349 EFSYS_PROBE(fail2); 1350fail1: 1351 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1352 1353 return (rc); 1354} 1355 1356#endif /* EFSYS_OPT_SIENA */ 1357 1358#if EFSYS_OPT_QSTATS 1359#if EFSYS_OPT_NAMES 1360/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */ 1361static const char * const __efx_ev_qstat_name[] = { 1362 "all", 1363 "rx", 1364 "rx_ok", 1365 "rx_frm_trunc", 1366 "rx_tobe_disc", 1367 "rx_pause_frm_err", 1368 "rx_buf_owner_id_err", 1369 "rx_ipv4_hdr_chksum_err", 1370 "rx_tcp_udp_chksum_err", 1371 "rx_eth_crc_err", 1372 "rx_ip_frag_err", 1373 "rx_mcast_pkt", 1374 "rx_mcast_hash_match", 1375 "rx_tcp_ipv4", 1376 "rx_tcp_ipv6", 1377 "rx_udp_ipv4", 1378 "rx_udp_ipv6", 1379 "rx_other_ipv4", 1380 "rx_other_ipv6", 1381 "rx_non_ip", 1382 "rx_batch", 1383 "tx", 1384 "tx_wq_ff_full", 1385 "tx_pkt_err", 1386 "tx_pkt_too_big", 1387 "tx_unexpected", 1388 "global", 1389 "global_mnt", 1390 "driver", 1391 "driver_srm_upd_done", 1392 "driver_tx_descq_fls_done", 1393 "driver_rx_descq_fls_done", 1394 "driver_rx_descq_fls_failed", 1395 "driver_rx_dsc_error", 1396 "driver_tx_dsc_error", 1397 "drv_gen", 1398 "mcdi_response", 1399}; 1400/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1401 1402 const char * 1403efx_ev_qstat_name( 1404 __in efx_nic_t *enp, 1405 __in unsigned int id) 1406{ 1407 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1408 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1409 1410 return (__efx_ev_qstat_name[id]); 1411} 1412#endif /* EFSYS_OPT_NAMES */ 1413#endif /* EFSYS_OPT_QSTATS */ 1414 1415#if EFSYS_OPT_SIENA 1416 1417#if EFSYS_OPT_QSTATS 1418static void 1419siena_ev_qstats_update( 1420 __in efx_evq_t *eep, 1421 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1422{ 1423 unsigned int id; 1424 1425 for (id = 0; id < EV_NQSTATS; id++) { 1426 efsys_stat_t *essp = &stat[id]; 1427 1428 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1429 eep->ee_stat[id] = 0; 1430 } 1431} 1432#endif /* EFSYS_OPT_QSTATS */ 1433 1434static void 1435siena_ev_qdestroy( 1436 __in efx_evq_t *eep) 1437{ 1438 efx_nic_t *enp = eep->ee_enp; 1439 efx_oword_t oword; 1440 1441 /* Purge event queue */ 1442 EFX_ZERO_OWORD(oword); 1443 1444 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1445 eep->ee_index, &oword, B_TRUE); 1446 1447 EFX_ZERO_OWORD(oword); 1448 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE); 1449} 1450 1451static void 1452siena_ev_fini( 1453 __in efx_nic_t *enp) 1454{ 1455 _NOTE(ARGUNUSED(enp)) 1456} 1457 1458#endif /* EFSYS_OPT_SIENA */ 1459