efx_ev.c revision 301127
1/*- 2 * Copyright (c) 2007-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_ev.c 301127 2016-06-01 14:16:16Z arybchik $"); 33 34#include "efx.h" 35#include "efx_impl.h" 36#if EFSYS_OPT_MON_MCDI 37#include "mcdi_mon.h" 38#endif 39 40#if EFSYS_OPT_QSTATS 41#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 42 do { \ 43 (_eep)->ee_stat[_stat]++; \ 44 _NOTE(CONSTANTCONDITION) \ 45 } while (B_FALSE) 46#else 47#define EFX_EV_QSTAT_INCR(_eep, _stat) 48#endif 49 50#define EFX_EV_PRESENT(_qword) \ 51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 53 54 55 56#if EFSYS_OPT_SIENA 57 58static __checkReturn efx_rc_t 59siena_ev_init( 60 __in efx_nic_t *enp); 61 62static void 63siena_ev_fini( 64 __in efx_nic_t *enp); 65 66static __checkReturn efx_rc_t 67siena_ev_qcreate( 68 __in efx_nic_t *enp, 69 __in unsigned int index, 70 __in efsys_mem_t *esmp, 71 __in size_t n, 72 __in uint32_t id, 73 __in uint32_t us, 74 __in efx_evq_t *eep); 75 76static void 77siena_ev_qdestroy( 78 __in efx_evq_t *eep); 79 80static __checkReturn efx_rc_t 81siena_ev_qprime( 82 __in efx_evq_t *eep, 83 __in unsigned int count); 84 85static void 86siena_ev_qpoll( 87 __in efx_evq_t *eep, 88 __inout unsigned int *countp, 89 __in const efx_ev_callbacks_t *eecp, 90 __in_opt void *arg); 91 92static void 93siena_ev_qpost( 94 __in efx_evq_t *eep, 95 __in uint16_t data); 96 97static __checkReturn efx_rc_t 98siena_ev_qmoderate( 99 __in efx_evq_t *eep, 100 __in unsigned int us); 101 102#if EFSYS_OPT_QSTATS 103static void 104siena_ev_qstats_update( 105 __in efx_evq_t *eep, 106 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 107 108#endif 109 110#endif /* EFSYS_OPT_SIENA */ 111 112#if EFSYS_OPT_SIENA 113static const efx_ev_ops_t __efx_ev_siena_ops = { 114 siena_ev_init, /* eevo_init */ 115 siena_ev_fini, /* eevo_fini */ 116 siena_ev_qcreate, /* eevo_qcreate */ 117 siena_ev_qdestroy, /* eevo_qdestroy */ 118 siena_ev_qprime, /* eevo_qprime */ 119 siena_ev_qpost, /* eevo_qpost */ 120 siena_ev_qmoderate, /* eevo_qmoderate */ 121#if EFSYS_OPT_QSTATS 122 siena_ev_qstats_update, /* eevo_qstats_update */ 123#endif 124}; 125#endif /* EFSYS_OPT_SIENA */ 126 127#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 128static const efx_ev_ops_t __efx_ev_ef10_ops = { 129 ef10_ev_init, /* eevo_init */ 130 ef10_ev_fini, /* eevo_fini */ 131 ef10_ev_qcreate, /* eevo_qcreate */ 132 ef10_ev_qdestroy, /* eevo_qdestroy */ 133 ef10_ev_qprime, /* eevo_qprime */ 134 ef10_ev_qpost, /* eevo_qpost */ 135 ef10_ev_qmoderate, /* eevo_qmoderate */ 136#if EFSYS_OPT_QSTATS 137 ef10_ev_qstats_update, /* eevo_qstats_update */ 138#endif 139}; 140#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 141 142 143 __checkReturn efx_rc_t 144efx_ev_init( 145 __in efx_nic_t *enp) 146{ 147 const efx_ev_ops_t *eevop; 148 efx_rc_t rc; 149 150 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 151 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 152 153 if (enp->en_mod_flags & EFX_MOD_EV) { 154 rc = EINVAL; 155 goto fail1; 156 } 157 158 switch (enp->en_family) { 159#if EFSYS_OPT_SIENA 160 case EFX_FAMILY_SIENA: 161 eevop = &__efx_ev_siena_ops; 162 break; 163#endif /* EFSYS_OPT_SIENA */ 164 165#if EFSYS_OPT_HUNTINGTON 166 case EFX_FAMILY_HUNTINGTON: 167 eevop = &__efx_ev_ef10_ops; 168 break; 169#endif /* EFSYS_OPT_HUNTINGTON */ 170 171#if EFSYS_OPT_MEDFORD 172 case EFX_FAMILY_MEDFORD: 173 eevop = &__efx_ev_ef10_ops; 174 break; 175#endif /* EFSYS_OPT_MEDFORD */ 176 177 default: 178 EFSYS_ASSERT(0); 179 rc = ENOTSUP; 180 goto fail1; 181 } 182 183 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 184 185 if ((rc = eevop->eevo_init(enp)) != 0) 186 goto fail2; 187 188 enp->en_eevop = eevop; 189 enp->en_mod_flags |= EFX_MOD_EV; 190 return (0); 191 192fail2: 193 EFSYS_PROBE(fail2); 194 195fail1: 196 EFSYS_PROBE1(fail1, efx_rc_t, rc); 197 198 enp->en_eevop = NULL; 199 enp->en_mod_flags &= ~EFX_MOD_EV; 200 return (rc); 201} 202 203 void 204efx_ev_fini( 205 __in efx_nic_t *enp) 206{ 207 const efx_ev_ops_t *eevop = enp->en_eevop; 208 209 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 211 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 212 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 213 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 214 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 215 216 eevop->eevo_fini(enp); 217 218 enp->en_eevop = NULL; 219 enp->en_mod_flags &= ~EFX_MOD_EV; 220} 221 222 223 __checkReturn efx_rc_t 224efx_ev_qcreate( 225 __in efx_nic_t *enp, 226 __in unsigned int index, 227 __in efsys_mem_t *esmp, 228 __in size_t n, 229 __in uint32_t id, 230 __in uint32_t us, 231 __deref_out efx_evq_t **eepp) 232{ 233 const efx_ev_ops_t *eevop = enp->en_eevop; 234 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 235 efx_evq_t *eep; 236 efx_rc_t rc; 237 238 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 239 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 240 241 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 242 243 /* Allocate an EVQ object */ 244 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 245 if (eep == NULL) { 246 rc = ENOMEM; 247 goto fail1; 248 } 249 250 eep->ee_magic = EFX_EVQ_MAGIC; 251 eep->ee_enp = enp; 252 eep->ee_index = index; 253 eep->ee_mask = n - 1; 254 eep->ee_esmp = esmp; 255 256 /* 257 * Set outputs before the queue is created because interrupts may be 258 * raised for events immediately after the queue is created, before the 259 * function call below returns. See bug58606. 260 * 261 * The eepp pointer passed in by the client must therefore point to data 262 * shared with the client's event processing context. 263 */ 264 enp->en_ev_qcount++; 265 *eepp = eep; 266 267 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, eep)) != 0) 268 goto fail2; 269 270 return (0); 271 272fail2: 273 EFSYS_PROBE(fail2); 274 275 *eepp = NULL; 276 enp->en_ev_qcount--; 277 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 278fail1: 279 EFSYS_PROBE1(fail1, efx_rc_t, rc); 280 return (rc); 281} 282 283 void 284efx_ev_qdestroy( 285 __in efx_evq_t *eep) 286{ 287 efx_nic_t *enp = eep->ee_enp; 288 const efx_ev_ops_t *eevop = enp->en_eevop; 289 290 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 291 292 EFSYS_ASSERT(enp->en_ev_qcount != 0); 293 --enp->en_ev_qcount; 294 295 eevop->eevo_qdestroy(eep); 296 297 /* Free the EVQ object */ 298 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 299} 300 301 __checkReturn efx_rc_t 302efx_ev_qprime( 303 __in efx_evq_t *eep, 304 __in unsigned int count) 305{ 306 efx_nic_t *enp = eep->ee_enp; 307 const efx_ev_ops_t *eevop = enp->en_eevop; 308 efx_rc_t rc; 309 310 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 311 312 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 313 rc = EINVAL; 314 goto fail1; 315 } 316 317 if ((rc = eevop->eevo_qprime(eep, count)) != 0) 318 goto fail2; 319 320 return (0); 321 322fail2: 323 EFSYS_PROBE(fail2); 324fail1: 325 EFSYS_PROBE1(fail1, efx_rc_t, rc); 326 return (rc); 327} 328 329 __checkReturn boolean_t 330efx_ev_qpending( 331 __in efx_evq_t *eep, 332 __in unsigned int count) 333{ 334 size_t offset; 335 efx_qword_t qword; 336 337 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 338 339 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 340 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 341 342 return (EFX_EV_PRESENT(qword)); 343} 344 345#if EFSYS_OPT_EV_PREFETCH 346 347 void 348efx_ev_qprefetch( 349 __in efx_evq_t *eep, 350 __in unsigned int count) 351{ 352 unsigned int offset; 353 354 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 355 356 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 357 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 358} 359 360#endif /* EFSYS_OPT_EV_PREFETCH */ 361 362 void 363efx_ev_qpoll( 364 __in efx_evq_t *eep, 365 __inout unsigned int *countp, 366 __in const efx_ev_callbacks_t *eecp, 367 __in_opt void *arg) 368{ 369 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 370 371 /* 372 * FIXME: Huntington will require support for hardware event batching 373 * and merging, which will need a different ev_qpoll implementation. 374 * 375 * Without those features the Falcon/Siena code can be used unchanged. 376 */ 377 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); 378 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); 379 380 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); 381 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); 382 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); 383 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == 384 FSE_AZ_EV_CODE_DRV_GEN_EV); 385#if EFSYS_OPT_MCDI 386 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == 387 FSE_AZ_EV_CODE_MCDI_EVRESPONSE); 388#endif 389 siena_ev_qpoll(eep, countp, eecp, arg); 390} 391 392 void 393efx_ev_qpost( 394 __in efx_evq_t *eep, 395 __in uint16_t data) 396{ 397 efx_nic_t *enp = eep->ee_enp; 398 const efx_ev_ops_t *eevop = enp->en_eevop; 399 400 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 401 402 EFSYS_ASSERT(eevop != NULL && 403 eevop->eevo_qpost != NULL); 404 405 eevop->eevo_qpost(eep, data); 406} 407 408 __checkReturn efx_rc_t 409efx_ev_qmoderate( 410 __in efx_evq_t *eep, 411 __in unsigned int us) 412{ 413 efx_nic_t *enp = eep->ee_enp; 414 const efx_ev_ops_t *eevop = enp->en_eevop; 415 efx_rc_t rc; 416 417 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 418 419 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) 420 goto fail1; 421 422 return (0); 423 424fail1: 425 EFSYS_PROBE1(fail1, efx_rc_t, rc); 426 return (rc); 427} 428 429#if EFSYS_OPT_QSTATS 430 void 431efx_ev_qstats_update( 432 __in efx_evq_t *eep, 433 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 434 435{ efx_nic_t *enp = eep->ee_enp; 436 const efx_ev_ops_t *eevop = enp->en_eevop; 437 438 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 439 440 eevop->eevo_qstats_update(eep, stat); 441} 442 443#endif /* EFSYS_OPT_QSTATS */ 444 445#if EFSYS_OPT_SIENA 446 447static __checkReturn efx_rc_t 448siena_ev_init( 449 __in efx_nic_t *enp) 450{ 451 efx_oword_t oword; 452 453 /* 454 * Program the event queue for receive and transmit queue 455 * flush events. 456 */ 457 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 458 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 459 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 460 461 return (0); 462 463} 464 465static __checkReturn boolean_t 466siena_ev_rx_not_ok( 467 __in efx_evq_t *eep, 468 __in efx_qword_t *eqp, 469 __in uint32_t label, 470 __in uint32_t id, 471 __inout uint16_t *flagsp) 472{ 473 boolean_t ignore = B_FALSE; 474 475 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 476 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 477 EFSYS_PROBE(tobe_disc); 478 /* 479 * Assume this is a unicast address mismatch, unless below 480 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 481 * EV_RX_PAUSE_FRM_ERR is set. 482 */ 483 (*flagsp) |= EFX_ADDR_MISMATCH; 484 } 485 486 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 487 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 488 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 489 (*flagsp) |= EFX_DISCARD; 490 491#if EFSYS_OPT_RX_SCATTER 492 /* 493 * Lookout for payload queue ran dry errors and ignore them. 494 * 495 * Sadly for the header/data split cases, the descriptor 496 * pointer in this event refers to the header queue and 497 * therefore cannot be easily detected as duplicate. 498 * So we drop these and rely on the receive processing seeing 499 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 500 * the partially received packet. 501 */ 502 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 503 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 504 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 505 ignore = B_TRUE; 506#endif /* EFSYS_OPT_RX_SCATTER */ 507 } 508 509 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 510 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 511 EFSYS_PROBE(crc_err); 512 (*flagsp) &= ~EFX_ADDR_MISMATCH; 513 (*flagsp) |= EFX_DISCARD; 514 } 515 516 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 517 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 518 EFSYS_PROBE(pause_frm_err); 519 (*flagsp) &= ~EFX_ADDR_MISMATCH; 520 (*flagsp) |= EFX_DISCARD; 521 } 522 523 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 524 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 525 EFSYS_PROBE(owner_id_err); 526 (*flagsp) |= EFX_DISCARD; 527 } 528 529 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 530 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 531 EFSYS_PROBE(ipv4_err); 532 (*flagsp) &= ~EFX_CKSUM_IPV4; 533 } 534 535 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 536 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 537 EFSYS_PROBE(udp_chk_err); 538 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 539 } 540 541 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 542 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 543 544 /* 545 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 546 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 547 * condition. 548 */ 549 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 550 } 551 552 return (ignore); 553} 554 555static __checkReturn boolean_t 556siena_ev_rx( 557 __in efx_evq_t *eep, 558 __in efx_qword_t *eqp, 559 __in const efx_ev_callbacks_t *eecp, 560 __in_opt void *arg) 561{ 562 uint32_t id; 563 uint32_t size; 564 uint32_t label; 565 boolean_t ok; 566#if EFSYS_OPT_RX_SCATTER 567 boolean_t sop; 568 boolean_t jumbo_cont; 569#endif /* EFSYS_OPT_RX_SCATTER */ 570 uint32_t hdr_type; 571 boolean_t is_v6; 572 uint16_t flags; 573 boolean_t ignore; 574 boolean_t should_abort; 575 576 EFX_EV_QSTAT_INCR(eep, EV_RX); 577 578 /* Basic packet information */ 579 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 580 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 581 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 582 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 583 584#if EFSYS_OPT_RX_SCATTER 585 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 586 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 587#endif /* EFSYS_OPT_RX_SCATTER */ 588 589 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 590 591 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 592 593 /* 594 * If packet is marked as OK and packet type is TCP/IP or 595 * UDP/IP or other IP, then we can rely on the hardware checksums. 596 */ 597 switch (hdr_type) { 598 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 599 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 600 if (is_v6) { 601 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 602 flags |= EFX_PKT_IPV6; 603 } else { 604 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 605 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 606 } 607 break; 608 609 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 610 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 611 if (is_v6) { 612 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 613 flags |= EFX_PKT_IPV6; 614 } else { 615 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 616 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 617 } 618 break; 619 620 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 621 if (is_v6) { 622 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 623 flags = EFX_PKT_IPV6; 624 } else { 625 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 626 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 627 } 628 break; 629 630 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 631 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 632 flags = 0; 633 break; 634 635 default: 636 EFSYS_ASSERT(B_FALSE); 637 flags = 0; 638 break; 639 } 640 641#if EFSYS_OPT_RX_SCATTER 642 /* Report scatter and header/lookahead split buffer flags */ 643 if (sop) 644 flags |= EFX_PKT_START; 645 if (jumbo_cont) 646 flags |= EFX_PKT_CONT; 647#endif /* EFSYS_OPT_RX_SCATTER */ 648 649 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 650 if (!ok) { 651 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags); 652 if (ignore) { 653 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 654 uint32_t, size, uint16_t, flags); 655 656 return (B_FALSE); 657 } 658 } 659 660 /* If we're not discarding the packet then it is ok */ 661 if (~flags & EFX_DISCARD) 662 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 663 664 /* Detect multicast packets that didn't match the filter */ 665 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 666 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 667 668 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 669 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 670 } else { 671 EFSYS_PROBE(mcast_mismatch); 672 flags |= EFX_ADDR_MISMATCH; 673 } 674 } else { 675 flags |= EFX_PKT_UNICAST; 676 } 677 678 /* 679 * The packet parser in Siena can abort parsing packets under 680 * certain error conditions, setting the PKT_NOT_PARSED bit 681 * (which clears PKT_OK). If this is set, then don't trust 682 * the PKT_TYPE field. 683 */ 684 if (!ok) { 685 uint32_t parse_err; 686 687 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 688 if (parse_err != 0) 689 flags |= EFX_CHECK_VLAN; 690 } 691 692 if (~flags & EFX_CHECK_VLAN) { 693 uint32_t pkt_type; 694 695 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 696 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 697 flags |= EFX_PKT_VLAN_TAGGED; 698 } 699 700 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 701 uint32_t, size, uint16_t, flags); 702 703 EFSYS_ASSERT(eecp->eec_rx != NULL); 704 should_abort = eecp->eec_rx(arg, label, id, size, flags); 705 706 return (should_abort); 707} 708 709static __checkReturn boolean_t 710siena_ev_tx( 711 __in efx_evq_t *eep, 712 __in efx_qword_t *eqp, 713 __in const efx_ev_callbacks_t *eecp, 714 __in_opt void *arg) 715{ 716 uint32_t id; 717 uint32_t label; 718 boolean_t should_abort; 719 720 EFX_EV_QSTAT_INCR(eep, EV_TX); 721 722 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 723 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 724 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 725 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 726 727 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 728 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 729 730 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 731 732 EFSYS_ASSERT(eecp->eec_tx != NULL); 733 should_abort = eecp->eec_tx(arg, label, id); 734 735 return (should_abort); 736 } 737 738 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 739 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 740 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 741 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 742 743 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 744 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 745 746 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 747 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 748 749 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 750 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 751 752 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 753 return (B_FALSE); 754} 755 756static __checkReturn boolean_t 757siena_ev_global( 758 __in efx_evq_t *eep, 759 __in efx_qword_t *eqp, 760 __in const efx_ev_callbacks_t *eecp, 761 __in_opt void *arg) 762{ 763 _NOTE(ARGUNUSED(eqp, eecp, arg)) 764 765 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 766 767 return (B_FALSE); 768} 769 770static __checkReturn boolean_t 771siena_ev_driver( 772 __in efx_evq_t *eep, 773 __in efx_qword_t *eqp, 774 __in const efx_ev_callbacks_t *eecp, 775 __in_opt void *arg) 776{ 777 boolean_t should_abort; 778 779 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 780 should_abort = B_FALSE; 781 782 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 783 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 784 uint32_t txq_index; 785 786 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 787 788 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 789 790 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 791 792 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 793 should_abort = eecp->eec_txq_flush_done(arg, txq_index); 794 795 break; 796 } 797 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 798 uint32_t rxq_index; 799 uint32_t failed; 800 801 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 802 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 803 804 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 805 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 806 807 if (failed) { 808 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 809 810 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 811 812 should_abort = eecp->eec_rxq_flush_failed(arg, 813 rxq_index); 814 } else { 815 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 816 817 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 818 819 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 820 } 821 822 break; 823 } 824 case FSE_AZ_EVQ_INIT_DONE_EV: 825 EFSYS_ASSERT(eecp->eec_initialized != NULL); 826 should_abort = eecp->eec_initialized(arg); 827 828 break; 829 830 case FSE_AZ_EVQ_NOT_EN_EV: 831 EFSYS_PROBE(evq_not_en); 832 break; 833 834 case FSE_AZ_SRM_UPD_DONE_EV: { 835 uint32_t code; 836 837 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 838 839 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 840 841 EFSYS_ASSERT(eecp->eec_sram != NULL); 842 should_abort = eecp->eec_sram(arg, code); 843 844 break; 845 } 846 case FSE_AZ_WAKE_UP_EV: { 847 uint32_t id; 848 849 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 850 851 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 852 should_abort = eecp->eec_wake_up(arg, id); 853 854 break; 855 } 856 case FSE_AZ_TX_PKT_NON_TCP_UDP: 857 EFSYS_PROBE(tx_pkt_non_tcp_udp); 858 break; 859 860 case FSE_AZ_TIMER_EV: { 861 uint32_t id; 862 863 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 864 865 EFSYS_ASSERT(eecp->eec_timer != NULL); 866 should_abort = eecp->eec_timer(arg, id); 867 868 break; 869 } 870 case FSE_AZ_RX_DSC_ERROR_EV: 871 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 872 873 EFSYS_PROBE(rx_dsc_error); 874 875 EFSYS_ASSERT(eecp->eec_exception != NULL); 876 should_abort = eecp->eec_exception(arg, 877 EFX_EXCEPTION_RX_DSC_ERROR, 0); 878 879 break; 880 881 case FSE_AZ_TX_DSC_ERROR_EV: 882 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 883 884 EFSYS_PROBE(tx_dsc_error); 885 886 EFSYS_ASSERT(eecp->eec_exception != NULL); 887 should_abort = eecp->eec_exception(arg, 888 EFX_EXCEPTION_TX_DSC_ERROR, 0); 889 890 break; 891 892 default: 893 break; 894 } 895 896 return (should_abort); 897} 898 899static __checkReturn boolean_t 900siena_ev_drv_gen( 901 __in efx_evq_t *eep, 902 __in efx_qword_t *eqp, 903 __in const efx_ev_callbacks_t *eecp, 904 __in_opt void *arg) 905{ 906 uint32_t data; 907 boolean_t should_abort; 908 909 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 910 911 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 912 if (data >= ((uint32_t)1 << 16)) { 913 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 914 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 915 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 916 return (B_TRUE); 917 } 918 919 EFSYS_ASSERT(eecp->eec_software != NULL); 920 should_abort = eecp->eec_software(arg, (uint16_t)data); 921 922 return (should_abort); 923} 924 925#if EFSYS_OPT_MCDI 926 927static __checkReturn boolean_t 928siena_ev_mcdi( 929 __in efx_evq_t *eep, 930 __in efx_qword_t *eqp, 931 __in const efx_ev_callbacks_t *eecp, 932 __in_opt void *arg) 933{ 934 efx_nic_t *enp = eep->ee_enp; 935 unsigned code; 936 boolean_t should_abort = B_FALSE; 937 938 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 939 940 if (enp->en_family != EFX_FAMILY_SIENA) 941 goto out; 942 943 EFSYS_ASSERT(eecp->eec_link_change != NULL); 944 EFSYS_ASSERT(eecp->eec_exception != NULL); 945#if EFSYS_OPT_MON_STATS 946 EFSYS_ASSERT(eecp->eec_monitor != NULL); 947#endif 948 949 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 950 951 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 952 switch (code) { 953 case MCDI_EVENT_CODE_BADSSERT: 954 efx_mcdi_ev_death(enp, EINTR); 955 break; 956 957 case MCDI_EVENT_CODE_CMDDONE: 958 efx_mcdi_ev_cpl(enp, 959 MCDI_EV_FIELD(eqp, CMDDONE_SEQ), 960 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), 961 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); 962 break; 963 964 case MCDI_EVENT_CODE_LINKCHANGE: { 965 efx_link_mode_t link_mode; 966 967 siena_phy_link_ev(enp, eqp, &link_mode); 968 should_abort = eecp->eec_link_change(arg, link_mode); 969 break; 970 } 971 case MCDI_EVENT_CODE_SENSOREVT: { 972#if EFSYS_OPT_MON_STATS 973 efx_mon_stat_t id; 974 efx_mon_stat_value_t value; 975 efx_rc_t rc; 976 977 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) 978 should_abort = eecp->eec_monitor(arg, id, value); 979 else if (rc == ENOTSUP) { 980 should_abort = eecp->eec_exception(arg, 981 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 982 MCDI_EV_FIELD(eqp, DATA)); 983 } else 984 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 985#else 986 should_abort = B_FALSE; 987#endif 988 break; 989 } 990 case MCDI_EVENT_CODE_SCHEDERR: 991 /* Informational only */ 992 break; 993 994 case MCDI_EVENT_CODE_REBOOT: 995 efx_mcdi_ev_death(enp, EIO); 996 break; 997 998 case MCDI_EVENT_CODE_MAC_STATS_DMA: 999#if EFSYS_OPT_MAC_STATS 1000 if (eecp->eec_mac_stats != NULL) { 1001 eecp->eec_mac_stats(arg, 1002 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 1003 } 1004#endif 1005 break; 1006 1007 case MCDI_EVENT_CODE_FWALERT: { 1008 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 1009 1010 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 1011 should_abort = eecp->eec_exception(arg, 1012 EFX_EXCEPTION_FWALERT_SRAM, 1013 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 1014 else 1015 should_abort = eecp->eec_exception(arg, 1016 EFX_EXCEPTION_UNKNOWN_FWALERT, 1017 MCDI_EV_FIELD(eqp, DATA)); 1018 break; 1019 } 1020 1021 default: 1022 EFSYS_PROBE1(mc_pcol_error, int, code); 1023 break; 1024 } 1025 1026out: 1027 return (should_abort); 1028} 1029 1030#endif /* EFSYS_OPT_MCDI */ 1031 1032static __checkReturn efx_rc_t 1033siena_ev_qprime( 1034 __in efx_evq_t *eep, 1035 __in unsigned int count) 1036{ 1037 efx_nic_t *enp = eep->ee_enp; 1038 uint32_t rptr; 1039 efx_dword_t dword; 1040 1041 rptr = count & eep->ee_mask; 1042 1043 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 1044 1045 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 1046 &dword, B_FALSE); 1047 1048 return (0); 1049} 1050 1051#define EFX_EV_BATCH 8 1052 1053static void 1054siena_ev_qpoll( 1055 __in efx_evq_t *eep, 1056 __inout unsigned int *countp, 1057 __in const efx_ev_callbacks_t *eecp, 1058 __in_opt void *arg) 1059{ 1060 efx_qword_t ev[EFX_EV_BATCH]; 1061 unsigned int batch; 1062 unsigned int total; 1063 unsigned int count; 1064 unsigned int index; 1065 size_t offset; 1066 1067 EFSYS_ASSERT(countp != NULL); 1068 EFSYS_ASSERT(eecp != NULL); 1069 1070 count = *countp; 1071 do { 1072 /* Read up until the end of the batch period */ 1073 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 1074 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1075 for (total = 0; total < batch; ++total) { 1076 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 1077 1078 if (!EFX_EV_PRESENT(ev[total])) 1079 break; 1080 1081 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 1082 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 1083 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 1084 1085 offset += sizeof (efx_qword_t); 1086 } 1087 1088#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 1089 /* 1090 * Prefetch the next batch when we get within PREFETCH_PERIOD 1091 * of a completed batch. If the batch is smaller, then prefetch 1092 * immediately. 1093 */ 1094 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 1095 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1096#endif /* EFSYS_OPT_EV_PREFETCH */ 1097 1098 /* Process the batch of events */ 1099 for (index = 0; index < total; ++index) { 1100 boolean_t should_abort; 1101 uint32_t code; 1102 1103#if EFSYS_OPT_EV_PREFETCH 1104 /* Prefetch if we've now reached the batch period */ 1105 if (total == batch && 1106 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 1107 offset = (count + batch) & eep->ee_mask; 1108 offset *= sizeof (efx_qword_t); 1109 1110 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1111 } 1112#endif /* EFSYS_OPT_EV_PREFETCH */ 1113 1114 EFX_EV_QSTAT_INCR(eep, EV_ALL); 1115 1116 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 1117 switch (code) { 1118 case FSE_AZ_EV_CODE_RX_EV: 1119 should_abort = eep->ee_rx(eep, 1120 &(ev[index]), eecp, arg); 1121 break; 1122 case FSE_AZ_EV_CODE_TX_EV: 1123 should_abort = eep->ee_tx(eep, 1124 &(ev[index]), eecp, arg); 1125 break; 1126 case FSE_AZ_EV_CODE_DRIVER_EV: 1127 should_abort = eep->ee_driver(eep, 1128 &(ev[index]), eecp, arg); 1129 break; 1130 case FSE_AZ_EV_CODE_DRV_GEN_EV: 1131 should_abort = eep->ee_drv_gen(eep, 1132 &(ev[index]), eecp, arg); 1133 break; 1134#if EFSYS_OPT_MCDI 1135 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: 1136 should_abort = eep->ee_mcdi(eep, 1137 &(ev[index]), eecp, arg); 1138 break; 1139#endif 1140 case FSE_AZ_EV_CODE_GLOBAL_EV: 1141 if (eep->ee_global) { 1142 should_abort = eep->ee_global(eep, 1143 &(ev[index]), eecp, arg); 1144 break; 1145 } 1146 /* else fallthrough */ 1147 default: 1148 EFSYS_PROBE3(bad_event, 1149 unsigned int, eep->ee_index, 1150 uint32_t, 1151 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), 1152 uint32_t, 1153 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); 1154 1155 EFSYS_ASSERT(eecp->eec_exception != NULL); 1156 (void) eecp->eec_exception(arg, 1157 EFX_EXCEPTION_EV_ERROR, code); 1158 should_abort = B_TRUE; 1159 } 1160 if (should_abort) { 1161 /* Ignore subsequent events */ 1162 total = index + 1; 1163 break; 1164 } 1165 } 1166 1167 /* 1168 * Now that the hardware has most likely moved onto dma'ing 1169 * into the next cache line, clear the processed events. Take 1170 * care to only clear out events that we've processed 1171 */ 1172 EFX_SET_QWORD(ev[0]); 1173 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1174 for (index = 0; index < total; ++index) { 1175 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 1176 offset += sizeof (efx_qword_t); 1177 } 1178 1179 count += total; 1180 1181 } while (total == batch); 1182 1183 *countp = count; 1184} 1185 1186static void 1187siena_ev_qpost( 1188 __in efx_evq_t *eep, 1189 __in uint16_t data) 1190{ 1191 efx_nic_t *enp = eep->ee_enp; 1192 efx_qword_t ev; 1193 efx_oword_t oword; 1194 1195 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 1196 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 1197 1198 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 1199 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 1200 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 1201 1202 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 1203} 1204 1205static __checkReturn efx_rc_t 1206siena_ev_qmoderate( 1207 __in efx_evq_t *eep, 1208 __in unsigned int us) 1209{ 1210 efx_nic_t *enp = eep->ee_enp; 1211 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1212 unsigned int locked; 1213 efx_dword_t dword; 1214 efx_rc_t rc; 1215 1216 if (us > encp->enc_evq_timer_max_us) { 1217 rc = EINVAL; 1218 goto fail1; 1219 } 1220 1221 /* If the value is zero then disable the timer */ 1222 if (us == 0) { 1223 EFX_POPULATE_DWORD_2(dword, 1224 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 1225 FRF_CZ_TC_TIMER_VAL, 0); 1226 } else { 1227 uint32_t timer_val; 1228 1229 /* Calculate the timer value in quanta */ 1230 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; 1231 1232 /* Moderation value is base 0 so we need to deduct 1 */ 1233 if (timer_val > 0) 1234 timer_val--; 1235 1236 EFX_POPULATE_DWORD_2(dword, 1237 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 1238 FRF_CZ_TC_TIMER_VAL, timer_val); 1239 } 1240 1241 locked = (eep->ee_index == 0) ? 1 : 0; 1242 1243 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 1244 eep->ee_index, &dword, locked); 1245 1246 return (0); 1247 1248fail1: 1249 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1250 1251 return (rc); 1252} 1253 1254static __checkReturn efx_rc_t 1255siena_ev_qcreate( 1256 __in efx_nic_t *enp, 1257 __in unsigned int index, 1258 __in efsys_mem_t *esmp, 1259 __in size_t n, 1260 __in uint32_t id, 1261 __in uint32_t us, 1262 __in efx_evq_t *eep) 1263{ 1264 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1265 uint32_t size; 1266 efx_oword_t oword; 1267 efx_rc_t rc; 1268 1269 _NOTE(ARGUNUSED(esmp)) 1270 1271 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); 1272 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); 1273 1274 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { 1275 rc = EINVAL; 1276 goto fail1; 1277 } 1278 if (index >= encp->enc_evq_limit) { 1279 rc = EINVAL; 1280 goto fail2; 1281 } 1282#if EFSYS_OPT_RX_SCALE 1283 if (enp->en_intr.ei_type == EFX_INTR_LINE && 1284 index >= EFX_MAXRSS_LEGACY) { 1285 rc = EINVAL; 1286 goto fail3; 1287 } 1288#endif 1289 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 1290 size++) 1291 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 1292 break; 1293 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1294 rc = EINVAL; 1295 goto fail4; 1296 } 1297 1298 /* Set up the handler table */ 1299 eep->ee_rx = siena_ev_rx; 1300 eep->ee_tx = siena_ev_tx; 1301 eep->ee_driver = siena_ev_driver; 1302 eep->ee_global = siena_ev_global; 1303 eep->ee_drv_gen = siena_ev_drv_gen; 1304#if EFSYS_OPT_MCDI 1305 eep->ee_mcdi = siena_ev_mcdi; 1306#endif /* EFSYS_OPT_MCDI */ 1307 1308 /* Set up the new event queue */ 1309 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 1310 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); 1311 1312 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 1313 FRF_AZ_EVQ_BUF_BASE_ID, id); 1314 1315 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); 1316 1317 /* Set initial interrupt moderation */ 1318 siena_ev_qmoderate(eep, us); 1319 1320 return (0); 1321 1322fail4: 1323 EFSYS_PROBE(fail4); 1324#if EFSYS_OPT_RX_SCALE 1325fail3: 1326 EFSYS_PROBE(fail3); 1327#endif 1328fail2: 1329 EFSYS_PROBE(fail2); 1330fail1: 1331 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1332 1333 return (rc); 1334} 1335 1336#endif /* EFSYS_OPT_SIENA */ 1337 1338#if EFSYS_OPT_QSTATS 1339#if EFSYS_OPT_NAMES 1340/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */ 1341static const char *__efx_ev_qstat_name[] = { 1342 "all", 1343 "rx", 1344 "rx_ok", 1345 "rx_frm_trunc", 1346 "rx_tobe_disc", 1347 "rx_pause_frm_err", 1348 "rx_buf_owner_id_err", 1349 "rx_ipv4_hdr_chksum_err", 1350 "rx_tcp_udp_chksum_err", 1351 "rx_eth_crc_err", 1352 "rx_ip_frag_err", 1353 "rx_mcast_pkt", 1354 "rx_mcast_hash_match", 1355 "rx_tcp_ipv4", 1356 "rx_tcp_ipv6", 1357 "rx_udp_ipv4", 1358 "rx_udp_ipv6", 1359 "rx_other_ipv4", 1360 "rx_other_ipv6", 1361 "rx_non_ip", 1362 "rx_batch", 1363 "tx", 1364 "tx_wq_ff_full", 1365 "tx_pkt_err", 1366 "tx_pkt_too_big", 1367 "tx_unexpected", 1368 "global", 1369 "global_mnt", 1370 "driver", 1371 "driver_srm_upd_done", 1372 "driver_tx_descq_fls_done", 1373 "driver_rx_descq_fls_done", 1374 "driver_rx_descq_fls_failed", 1375 "driver_rx_dsc_error", 1376 "driver_tx_dsc_error", 1377 "drv_gen", 1378 "mcdi_response", 1379}; 1380/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1381 1382 const char * 1383efx_ev_qstat_name( 1384 __in efx_nic_t *enp, 1385 __in unsigned int id) 1386{ 1387 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1388 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1389 1390 return (__efx_ev_qstat_name[id]); 1391} 1392#endif /* EFSYS_OPT_NAMES */ 1393#endif /* EFSYS_OPT_QSTATS */ 1394 1395#if EFSYS_OPT_SIENA 1396 1397#if EFSYS_OPT_QSTATS 1398static void 1399siena_ev_qstats_update( 1400 __in efx_evq_t *eep, 1401 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1402{ 1403 unsigned int id; 1404 1405 for (id = 0; id < EV_NQSTATS; id++) { 1406 efsys_stat_t *essp = &stat[id]; 1407 1408 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1409 eep->ee_stat[id] = 0; 1410 } 1411} 1412#endif /* EFSYS_OPT_QSTATS */ 1413 1414static void 1415siena_ev_qdestroy( 1416 __in efx_evq_t *eep) 1417{ 1418 efx_nic_t *enp = eep->ee_enp; 1419 efx_oword_t oword; 1420 1421 /* Purge event queue */ 1422 EFX_ZERO_OWORD(oword); 1423 1424 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1425 eep->ee_index, &oword, B_TRUE); 1426 1427 EFX_ZERO_OWORD(oword); 1428 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE); 1429} 1430 1431static void 1432siena_ev_fini( 1433 __in efx_nic_t *enp) 1434{ 1435 _NOTE(ARGUNUSED(enp)) 1436} 1437 1438#endif /* EFSYS_OPT_SIENA */ 1439