efx_ev.c revision 299320
1/*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_ev.c 299320 2016-05-10 07:01:06Z arybchik $"); 33 34#include "efx.h" 35#include "efx_impl.h" 36#if EFSYS_OPT_MON_MCDI 37#include "mcdi_mon.h" 38#endif 39 40#if EFSYS_OPT_QSTATS 41#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 42 do { \ 43 (_eep)->ee_stat[_stat]++; \ 44 _NOTE(CONSTANTCONDITION) \ 45 } while (B_FALSE) 46#else 47#define EFX_EV_QSTAT_INCR(_eep, _stat) 48#endif 49 50#define EFX_EV_PRESENT(_qword) \ 51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 53 54 55 56#if EFSYS_OPT_SIENA 57 58static __checkReturn efx_rc_t 59falconsiena_ev_init( 60 __in efx_nic_t *enp); 61 62static void 63falconsiena_ev_fini( 64 __in efx_nic_t *enp); 65 66static __checkReturn efx_rc_t 67falconsiena_ev_qcreate( 68 __in efx_nic_t *enp, 69 __in unsigned int index, 70 __in efsys_mem_t *esmp, 71 __in size_t n, 72 __in uint32_t id, 73 __in efx_evq_t *eep); 74 75static void 76falconsiena_ev_qdestroy( 77 __in efx_evq_t *eep); 78 79static __checkReturn efx_rc_t 80falconsiena_ev_qprime( 81 __in efx_evq_t *eep, 82 __in unsigned int count); 83 84static void 85falconsiena_ev_qpoll( 86 __in efx_evq_t *eep, 87 __inout unsigned int *countp, 88 __in const efx_ev_callbacks_t *eecp, 89 __in_opt void *arg); 90 91static void 92falconsiena_ev_qpost( 93 __in efx_evq_t *eep, 94 __in uint16_t data); 95 96static __checkReturn efx_rc_t 97falconsiena_ev_qmoderate( 98 __in efx_evq_t *eep, 99 __in unsigned int us); 100 101#if EFSYS_OPT_QSTATS 102static void 103falconsiena_ev_qstats_update( 104 __in efx_evq_t *eep, 105 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 106 107#endif 108 109#endif /* EFSYS_OPT_SIENA */ 110 111#if EFSYS_OPT_SIENA 112static efx_ev_ops_t __efx_ev_siena_ops = { 113 falconsiena_ev_init, /* eevo_init */ 114 falconsiena_ev_fini, /* eevo_fini */ 115 falconsiena_ev_qcreate, /* eevo_qcreate */ 116 falconsiena_ev_qdestroy, /* eevo_qdestroy */ 117 falconsiena_ev_qprime, /* eevo_qprime */ 118 falconsiena_ev_qpost, /* eevo_qpost */ 119 falconsiena_ev_qmoderate, /* eevo_qmoderate */ 120#if EFSYS_OPT_QSTATS 121 falconsiena_ev_qstats_update, /* eevo_qstats_update */ 122#endif 123}; 124#endif /* EFSYS_OPT_SIENA */ 125 126#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 127static efx_ev_ops_t __efx_ev_ef10_ops = { 128 ef10_ev_init, /* eevo_init */ 129 ef10_ev_fini, /* eevo_fini */ 130 ef10_ev_qcreate, /* eevo_qcreate */ 131 ef10_ev_qdestroy, /* eevo_qdestroy */ 132 ef10_ev_qprime, /* eevo_qprime */ 133 ef10_ev_qpost, /* eevo_qpost */ 134 ef10_ev_qmoderate, /* eevo_qmoderate */ 135#if EFSYS_OPT_QSTATS 136 ef10_ev_qstats_update, /* eevo_qstats_update */ 137#endif 138}; 139#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 140 141 142 __checkReturn efx_rc_t 143efx_ev_init( 144 __in efx_nic_t *enp) 145{ 146 efx_ev_ops_t *eevop; 147 efx_rc_t rc; 148 149 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 150 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 151 152 if (enp->en_mod_flags & EFX_MOD_EV) { 153 rc = EINVAL; 154 goto fail1; 155 } 156 157 switch (enp->en_family) { 158#if EFSYS_OPT_SIENA 159 case EFX_FAMILY_SIENA: 160 eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops; 161 break; 162#endif /* EFSYS_OPT_SIENA */ 163 164#if EFSYS_OPT_HUNTINGTON 165 case EFX_FAMILY_HUNTINGTON: 166 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops; 167 break; 168#endif /* EFSYS_OPT_HUNTINGTON */ 169 170#if EFSYS_OPT_MEDFORD 171 case EFX_FAMILY_MEDFORD: 172 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops; 173 break; 174#endif /* EFSYS_OPT_MEDFORD */ 175 176 default: 177 EFSYS_ASSERT(0); 178 rc = ENOTSUP; 179 goto fail1; 180 } 181 182 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 183 184 if ((rc = eevop->eevo_init(enp)) != 0) 185 goto fail2; 186 187 enp->en_eevop = eevop; 188 enp->en_mod_flags |= EFX_MOD_EV; 189 return (0); 190 191fail2: 192 EFSYS_PROBE(fail2); 193 194fail1: 195 EFSYS_PROBE1(fail1, efx_rc_t, rc); 196 197 enp->en_eevop = NULL; 198 enp->en_mod_flags &= ~EFX_MOD_EV; 199 return (rc); 200} 201 202 void 203efx_ev_fini( 204 __in efx_nic_t *enp) 205{ 206 efx_ev_ops_t *eevop = enp->en_eevop; 207 208 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 209 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 211 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 212 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 213 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 214 215 eevop->eevo_fini(enp); 216 217 enp->en_eevop = NULL; 218 enp->en_mod_flags &= ~EFX_MOD_EV; 219} 220 221 222 __checkReturn efx_rc_t 223efx_ev_qcreate( 224 __in efx_nic_t *enp, 225 __in unsigned int index, 226 __in efsys_mem_t *esmp, 227 __in size_t n, 228 __in uint32_t id, 229 __deref_out efx_evq_t **eepp) 230{ 231 efx_ev_ops_t *eevop = enp->en_eevop; 232 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 233 efx_evq_t *eep; 234 efx_rc_t rc; 235 236 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 237 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 238 239 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 240 241 /* Allocate an EVQ object */ 242 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 243 if (eep == NULL) { 244 rc = ENOMEM; 245 goto fail1; 246 } 247 248 eep->ee_magic = EFX_EVQ_MAGIC; 249 eep->ee_enp = enp; 250 eep->ee_index = index; 251 eep->ee_mask = n - 1; 252 eep->ee_esmp = esmp; 253 254 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0) 255 goto fail2; 256 257 enp->en_ev_qcount++; 258 *eepp = eep; 259 260 return (0); 261 262fail2: 263 EFSYS_PROBE(fail2); 264 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 265fail1: 266 EFSYS_PROBE1(fail1, efx_rc_t, rc); 267 return (rc); 268} 269 270 void 271efx_ev_qdestroy( 272 __in efx_evq_t *eep) 273{ 274 efx_nic_t *enp = eep->ee_enp; 275 efx_ev_ops_t *eevop = enp->en_eevop; 276 277 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 278 279 EFSYS_ASSERT(enp->en_ev_qcount != 0); 280 --enp->en_ev_qcount; 281 282 eevop->eevo_qdestroy(eep); 283 284 /* Free the EVQ object */ 285 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 286} 287 288 __checkReturn efx_rc_t 289efx_ev_qprime( 290 __in efx_evq_t *eep, 291 __in unsigned int count) 292{ 293 efx_nic_t *enp = eep->ee_enp; 294 efx_ev_ops_t *eevop = enp->en_eevop; 295 efx_rc_t rc; 296 297 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 298 299 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 300 rc = EINVAL; 301 goto fail1; 302 } 303 304 if ((rc = eevop->eevo_qprime(eep, count)) != 0) 305 goto fail2; 306 307 return (0); 308 309fail2: 310 EFSYS_PROBE(fail2); 311fail1: 312 EFSYS_PROBE1(fail1, efx_rc_t, rc); 313 return (rc); 314} 315 316 __checkReturn boolean_t 317efx_ev_qpending( 318 __in efx_evq_t *eep, 319 __in unsigned int count) 320{ 321 size_t offset; 322 efx_qword_t qword; 323 324 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 325 326 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 327 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 328 329 return (EFX_EV_PRESENT(qword)); 330} 331 332#if EFSYS_OPT_EV_PREFETCH 333 334 void 335efx_ev_qprefetch( 336 __in efx_evq_t *eep, 337 __in unsigned int count) 338{ 339 efx_nic_t *enp = eep->ee_enp; 340 unsigned int offset; 341 342 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 343 344 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 345 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 346} 347 348#endif /* EFSYS_OPT_EV_PREFETCH */ 349 350 void 351efx_ev_qpoll( 352 __in efx_evq_t *eep, 353 __inout unsigned int *countp, 354 __in const efx_ev_callbacks_t *eecp, 355 __in_opt void *arg) 356{ 357 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 358 359 /* 360 * FIXME: Huntington will require support for hardware event batching 361 * and merging, which will need a different ev_qpoll implementation. 362 * 363 * Without those features the Falcon/Siena code can be used unchanged. 364 */ 365 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); 366 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); 367 368 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); 369 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); 370 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); 371 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == 372 FSE_AZ_EV_CODE_DRV_GEN_EV); 373#if EFSYS_OPT_MCDI 374 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == 375 FSE_AZ_EV_CODE_MCDI_EVRESPONSE); 376#endif 377 falconsiena_ev_qpoll(eep, countp, eecp, arg); 378} 379 380 void 381efx_ev_qpost( 382 __in efx_evq_t *eep, 383 __in uint16_t data) 384{ 385 efx_nic_t *enp = eep->ee_enp; 386 efx_ev_ops_t *eevop = enp->en_eevop; 387 388 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 389 390 EFSYS_ASSERT(eevop != NULL && 391 eevop->eevo_qpost != NULL); 392 393 eevop->eevo_qpost(eep, data); 394} 395 396 __checkReturn efx_rc_t 397efx_ev_qmoderate( 398 __in efx_evq_t *eep, 399 __in unsigned int us) 400{ 401 efx_nic_t *enp = eep->ee_enp; 402 efx_ev_ops_t *eevop = enp->en_eevop; 403 efx_rc_t rc; 404 405 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 406 407 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) 408 goto fail1; 409 410 return (0); 411 412fail1: 413 EFSYS_PROBE1(fail1, efx_rc_t, rc); 414 return (rc); 415} 416 417#if EFSYS_OPT_QSTATS 418 void 419efx_ev_qstats_update( 420 __in efx_evq_t *eep, 421 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 422 423{ efx_nic_t *enp = eep->ee_enp; 424 efx_ev_ops_t *eevop = enp->en_eevop; 425 426 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 427 428 eevop->eevo_qstats_update(eep, stat); 429} 430 431#endif /* EFSYS_OPT_QSTATS */ 432 433#if EFSYS_OPT_SIENA 434 435static __checkReturn efx_rc_t 436falconsiena_ev_init( 437 __in efx_nic_t *enp) 438{ 439 efx_oword_t oword; 440 441 /* 442 * Program the event queue for receive and transmit queue 443 * flush events. 444 */ 445 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 446 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 447 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 448 449 return (0); 450 451} 452 453static __checkReturn boolean_t 454falconsiena_ev_rx_not_ok( 455 __in efx_evq_t *eep, 456 __in efx_qword_t *eqp, 457 __in uint32_t label, 458 __in uint32_t id, 459 __inout uint16_t *flagsp) 460{ 461 boolean_t ignore = B_FALSE; 462 463 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 464 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 465 EFSYS_PROBE(tobe_disc); 466 /* 467 * Assume this is a unicast address mismatch, unless below 468 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 469 * EV_RX_PAUSE_FRM_ERR is set. 470 */ 471 (*flagsp) |= EFX_ADDR_MISMATCH; 472 } 473 474 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 475 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 476 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 477 (*flagsp) |= EFX_DISCARD; 478 479#if EFSYS_OPT_RX_SCATTER 480 /* 481 * Lookout for payload queue ran dry errors and ignore them. 482 * 483 * Sadly for the header/data split cases, the descriptor 484 * pointer in this event refers to the header queue and 485 * therefore cannot be easily detected as duplicate. 486 * So we drop these and rely on the receive processing seeing 487 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 488 * the partially received packet. 489 */ 490 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 491 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 492 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 493 ignore = B_TRUE; 494#endif /* EFSYS_OPT_RX_SCATTER */ 495 } 496 497 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 498 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 499 EFSYS_PROBE(crc_err); 500 (*flagsp) &= ~EFX_ADDR_MISMATCH; 501 (*flagsp) |= EFX_DISCARD; 502 } 503 504 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 505 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 506 EFSYS_PROBE(pause_frm_err); 507 (*flagsp) &= ~EFX_ADDR_MISMATCH; 508 (*flagsp) |= EFX_DISCARD; 509 } 510 511 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 512 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 513 EFSYS_PROBE(owner_id_err); 514 (*flagsp) |= EFX_DISCARD; 515 } 516 517 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 518 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 519 EFSYS_PROBE(ipv4_err); 520 (*flagsp) &= ~EFX_CKSUM_IPV4; 521 } 522 523 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 524 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 525 EFSYS_PROBE(udp_chk_err); 526 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 527 } 528 529 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 530 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 531 532 /* 533 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 534 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 535 * condition. 536 */ 537 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 538 } 539 540 return (ignore); 541} 542 543static __checkReturn boolean_t 544falconsiena_ev_rx( 545 __in efx_evq_t *eep, 546 __in efx_qword_t *eqp, 547 __in const efx_ev_callbacks_t *eecp, 548 __in_opt void *arg) 549{ 550 efx_nic_t *enp = eep->ee_enp; 551 uint32_t id; 552 uint32_t size; 553 uint32_t label; 554 boolean_t ok; 555#if EFSYS_OPT_RX_SCATTER 556 boolean_t sop; 557 boolean_t jumbo_cont; 558#endif /* EFSYS_OPT_RX_SCATTER */ 559 uint32_t hdr_type; 560 boolean_t is_v6; 561 uint16_t flags; 562 boolean_t ignore; 563 boolean_t should_abort; 564 565 EFX_EV_QSTAT_INCR(eep, EV_RX); 566 567 /* Basic packet information */ 568 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 569 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 570 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 571 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 572 573#if EFSYS_OPT_RX_SCATTER 574 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 575 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 576#endif /* EFSYS_OPT_RX_SCATTER */ 577 578 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 579 580 is_v6 = (enp->en_family != EFX_FAMILY_FALCON && 581 EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 582 583 /* 584 * If packet is marked as OK and packet type is TCP/IP or 585 * UDP/IP or other IP, then we can rely on the hardware checksums. 586 */ 587 switch (hdr_type) { 588 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 589 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 590 if (is_v6) { 591 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 592 flags |= EFX_PKT_IPV6; 593 } else { 594 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 595 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 596 } 597 break; 598 599 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 600 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 601 if (is_v6) { 602 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 603 flags |= EFX_PKT_IPV6; 604 } else { 605 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 606 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 607 } 608 break; 609 610 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 611 if (is_v6) { 612 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 613 flags = EFX_PKT_IPV6; 614 } else { 615 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 616 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 617 } 618 break; 619 620 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 621 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 622 flags = 0; 623 break; 624 625 default: 626 EFSYS_ASSERT(B_FALSE); 627 flags = 0; 628 break; 629 } 630 631#if EFSYS_OPT_RX_SCATTER 632 /* Report scatter and header/lookahead split buffer flags */ 633 if (sop) 634 flags |= EFX_PKT_START; 635 if (jumbo_cont) 636 flags |= EFX_PKT_CONT; 637#endif /* EFSYS_OPT_RX_SCATTER */ 638 639 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 640 if (!ok) { 641 ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags); 642 if (ignore) { 643 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 644 uint32_t, size, uint16_t, flags); 645 646 return (B_FALSE); 647 } 648 } 649 650 /* If we're not discarding the packet then it is ok */ 651 if (~flags & EFX_DISCARD) 652 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 653 654 /* Detect multicast packets that didn't match the filter */ 655 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 656 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 657 658 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 659 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 660 } else { 661 EFSYS_PROBE(mcast_mismatch); 662 flags |= EFX_ADDR_MISMATCH; 663 } 664 } else { 665 flags |= EFX_PKT_UNICAST; 666 } 667 668 /* 669 * The packet parser in Siena can abort parsing packets under 670 * certain error conditions, setting the PKT_NOT_PARSED bit 671 * (which clears PKT_OK). If this is set, then don't trust 672 * the PKT_TYPE field. 673 */ 674 if (enp->en_family != EFX_FAMILY_FALCON && !ok) { 675 uint32_t parse_err; 676 677 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 678 if (parse_err != 0) 679 flags |= EFX_CHECK_VLAN; 680 } 681 682 if (~flags & EFX_CHECK_VLAN) { 683 uint32_t pkt_type; 684 685 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 686 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 687 flags |= EFX_PKT_VLAN_TAGGED; 688 } 689 690 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 691 uint32_t, size, uint16_t, flags); 692 693 EFSYS_ASSERT(eecp->eec_rx != NULL); 694 should_abort = eecp->eec_rx(arg, label, id, size, flags); 695 696 return (should_abort); 697} 698 699static __checkReturn boolean_t 700falconsiena_ev_tx( 701 __in efx_evq_t *eep, 702 __in efx_qword_t *eqp, 703 __in const efx_ev_callbacks_t *eecp, 704 __in_opt void *arg) 705{ 706 uint32_t id; 707 uint32_t label; 708 boolean_t should_abort; 709 710 EFX_EV_QSTAT_INCR(eep, EV_TX); 711 712 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 713 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 714 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 715 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 716 717 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 718 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 719 720 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 721 722 EFSYS_ASSERT(eecp->eec_tx != NULL); 723 should_abort = eecp->eec_tx(arg, label, id); 724 725 return (should_abort); 726 } 727 728 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 729 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 730 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 731 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 732 733 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 734 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 735 736 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 737 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 738 739 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 740 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 741 742 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 743 return (B_FALSE); 744} 745 746static __checkReturn boolean_t 747falconsiena_ev_global( 748 __in efx_evq_t *eep, 749 __in efx_qword_t *eqp, 750 __in const efx_ev_callbacks_t *eecp, 751 __in_opt void *arg) 752{ 753 efx_nic_t *enp = eep->ee_enp; 754 efx_port_t *epp = &(enp->en_port); 755 boolean_t should_abort; 756 757 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 758 should_abort = B_FALSE; 759 760 /* Check for a link management event */ 761 if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) { 762 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT); 763 764 EFSYS_PROBE(xg_mgt); 765 766 epp->ep_mac_poll_needed = B_TRUE; 767 } 768 769 return (should_abort); 770} 771 772static __checkReturn boolean_t 773falconsiena_ev_driver( 774 __in efx_evq_t *eep, 775 __in efx_qword_t *eqp, 776 __in const efx_ev_callbacks_t *eecp, 777 __in_opt void *arg) 778{ 779 boolean_t should_abort; 780 781 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 782 should_abort = B_FALSE; 783 784 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 785 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 786 uint32_t txq_index; 787 788 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 789 790 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 791 792 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 793 794 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 795 should_abort = eecp->eec_txq_flush_done(arg, txq_index); 796 797 break; 798 } 799 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 800 uint32_t rxq_index; 801 uint32_t failed; 802 803 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 804 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 805 806 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 807 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 808 809 if (failed) { 810 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 811 812 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 813 814 should_abort = eecp->eec_rxq_flush_failed(arg, 815 rxq_index); 816 } else { 817 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 818 819 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 820 821 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 822 } 823 824 break; 825 } 826 case FSE_AZ_EVQ_INIT_DONE_EV: 827 EFSYS_ASSERT(eecp->eec_initialized != NULL); 828 should_abort = eecp->eec_initialized(arg); 829 830 break; 831 832 case FSE_AZ_EVQ_NOT_EN_EV: 833 EFSYS_PROBE(evq_not_en); 834 break; 835 836 case FSE_AZ_SRM_UPD_DONE_EV: { 837 uint32_t code; 838 839 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 840 841 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 842 843 EFSYS_ASSERT(eecp->eec_sram != NULL); 844 should_abort = eecp->eec_sram(arg, code); 845 846 break; 847 } 848 case FSE_AZ_WAKE_UP_EV: { 849 uint32_t id; 850 851 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 852 853 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 854 should_abort = eecp->eec_wake_up(arg, id); 855 856 break; 857 } 858 case FSE_AZ_TX_PKT_NON_TCP_UDP: 859 EFSYS_PROBE(tx_pkt_non_tcp_udp); 860 break; 861 862 case FSE_AZ_TIMER_EV: { 863 uint32_t id; 864 865 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 866 867 EFSYS_ASSERT(eecp->eec_timer != NULL); 868 should_abort = eecp->eec_timer(arg, id); 869 870 break; 871 } 872 case FSE_AZ_RX_DSC_ERROR_EV: 873 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 874 875 EFSYS_PROBE(rx_dsc_error); 876 877 EFSYS_ASSERT(eecp->eec_exception != NULL); 878 should_abort = eecp->eec_exception(arg, 879 EFX_EXCEPTION_RX_DSC_ERROR, 0); 880 881 break; 882 883 case FSE_AZ_TX_DSC_ERROR_EV: 884 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 885 886 EFSYS_PROBE(tx_dsc_error); 887 888 EFSYS_ASSERT(eecp->eec_exception != NULL); 889 should_abort = eecp->eec_exception(arg, 890 EFX_EXCEPTION_TX_DSC_ERROR, 0); 891 892 break; 893 894 default: 895 break; 896 } 897 898 return (should_abort); 899} 900 901static __checkReturn boolean_t 902falconsiena_ev_drv_gen( 903 __in efx_evq_t *eep, 904 __in efx_qword_t *eqp, 905 __in const efx_ev_callbacks_t *eecp, 906 __in_opt void *arg) 907{ 908 uint32_t data; 909 boolean_t should_abort; 910 911 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 912 913 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 914 if (data >= ((uint32_t)1 << 16)) { 915 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 916 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 917 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 918 return (B_TRUE); 919 } 920 921 EFSYS_ASSERT(eecp->eec_software != NULL); 922 should_abort = eecp->eec_software(arg, (uint16_t)data); 923 924 return (should_abort); 925} 926 927#if EFSYS_OPT_MCDI 928 929static __checkReturn boolean_t 930falconsiena_ev_mcdi( 931 __in efx_evq_t *eep, 932 __in efx_qword_t *eqp, 933 __in const efx_ev_callbacks_t *eecp, 934 __in_opt void *arg) 935{ 936 efx_nic_t *enp = eep->ee_enp; 937 unsigned code; 938 boolean_t should_abort = B_FALSE; 939 940 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 941 942 if (enp->en_family != EFX_FAMILY_SIENA) 943 goto out; 944 945 EFSYS_ASSERT(eecp->eec_link_change != NULL); 946 EFSYS_ASSERT(eecp->eec_exception != NULL); 947#if EFSYS_OPT_MON_STATS 948 EFSYS_ASSERT(eecp->eec_monitor != NULL); 949#endif 950 951 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 952 953 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 954 switch (code) { 955 case MCDI_EVENT_CODE_BADSSERT: 956 efx_mcdi_ev_death(enp, EINTR); 957 break; 958 959 case MCDI_EVENT_CODE_CMDDONE: 960 efx_mcdi_ev_cpl(enp, 961 MCDI_EV_FIELD(eqp, CMDDONE_SEQ), 962 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), 963 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); 964 break; 965 966 case MCDI_EVENT_CODE_LINKCHANGE: { 967 efx_link_mode_t link_mode; 968 969 siena_phy_link_ev(enp, eqp, &link_mode); 970 should_abort = eecp->eec_link_change(arg, link_mode); 971 break; 972 } 973 case MCDI_EVENT_CODE_SENSOREVT: { 974#if EFSYS_OPT_MON_STATS 975 efx_mon_stat_t id; 976 efx_mon_stat_value_t value; 977 efx_rc_t rc; 978 979 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) 980 should_abort = eecp->eec_monitor(arg, id, value); 981 else if (rc == ENOTSUP) { 982 should_abort = eecp->eec_exception(arg, 983 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 984 MCDI_EV_FIELD(eqp, DATA)); 985 } else 986 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 987#else 988 should_abort = B_FALSE; 989#endif 990 break; 991 } 992 case MCDI_EVENT_CODE_SCHEDERR: 993 /* Informational only */ 994 break; 995 996 case MCDI_EVENT_CODE_REBOOT: 997 efx_mcdi_ev_death(enp, EIO); 998 break; 999 1000 case MCDI_EVENT_CODE_MAC_STATS_DMA: 1001#if EFSYS_OPT_MAC_STATS 1002 if (eecp->eec_mac_stats != NULL) { 1003 eecp->eec_mac_stats(arg, 1004 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 1005 } 1006#endif 1007 break; 1008 1009 case MCDI_EVENT_CODE_FWALERT: { 1010 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 1011 1012 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 1013 should_abort = eecp->eec_exception(arg, 1014 EFX_EXCEPTION_FWALERT_SRAM, 1015 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 1016 else 1017 should_abort = eecp->eec_exception(arg, 1018 EFX_EXCEPTION_UNKNOWN_FWALERT, 1019 MCDI_EV_FIELD(eqp, DATA)); 1020 break; 1021 } 1022 1023 default: 1024 EFSYS_PROBE1(mc_pcol_error, int, code); 1025 break; 1026 } 1027 1028out: 1029 return (should_abort); 1030} 1031 1032#endif /* EFSYS_OPT_MCDI */ 1033 1034static __checkReturn efx_rc_t 1035falconsiena_ev_qprime( 1036 __in efx_evq_t *eep, 1037 __in unsigned int count) 1038{ 1039 efx_nic_t *enp = eep->ee_enp; 1040 uint32_t rptr; 1041 efx_dword_t dword; 1042 1043 rptr = count & eep->ee_mask; 1044 1045 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 1046 1047 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 1048 &dword, B_FALSE); 1049 1050 return (0); 1051} 1052 1053#define EFX_EV_BATCH 8 1054 1055static void 1056falconsiena_ev_qpoll( 1057 __in efx_evq_t *eep, 1058 __inout unsigned int *countp, 1059 __in const efx_ev_callbacks_t *eecp, 1060 __in_opt void *arg) 1061{ 1062 efx_qword_t ev[EFX_EV_BATCH]; 1063 unsigned int batch; 1064 unsigned int total; 1065 unsigned int count; 1066 unsigned int index; 1067 size_t offset; 1068 1069 EFSYS_ASSERT(countp != NULL); 1070 EFSYS_ASSERT(eecp != NULL); 1071 1072 count = *countp; 1073 do { 1074 /* Read up until the end of the batch period */ 1075 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 1076 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1077 for (total = 0; total < batch; ++total) { 1078 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 1079 1080 if (!EFX_EV_PRESENT(ev[total])) 1081 break; 1082 1083 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 1084 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 1085 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 1086 1087 offset += sizeof (efx_qword_t); 1088 } 1089 1090#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 1091 /* 1092 * Prefetch the next batch when we get within PREFETCH_PERIOD 1093 * of a completed batch. If the batch is smaller, then prefetch 1094 * immediately. 1095 */ 1096 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 1097 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1098#endif /* EFSYS_OPT_EV_PREFETCH */ 1099 1100 /* Process the batch of events */ 1101 for (index = 0; index < total; ++index) { 1102 boolean_t should_abort; 1103 uint32_t code; 1104 1105#if EFSYS_OPT_EV_PREFETCH 1106 /* Prefetch if we've now reached the batch period */ 1107 if (total == batch && 1108 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 1109 offset = (count + batch) & eep->ee_mask; 1110 offset *= sizeof (efx_qword_t); 1111 1112 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 1113 } 1114#endif /* EFSYS_OPT_EV_PREFETCH */ 1115 1116 EFX_EV_QSTAT_INCR(eep, EV_ALL); 1117 1118 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 1119 switch (code) { 1120 case FSE_AZ_EV_CODE_RX_EV: 1121 should_abort = eep->ee_rx(eep, 1122 &(ev[index]), eecp, arg); 1123 break; 1124 case FSE_AZ_EV_CODE_TX_EV: 1125 should_abort = eep->ee_tx(eep, 1126 &(ev[index]), eecp, arg); 1127 break; 1128 case FSE_AZ_EV_CODE_DRIVER_EV: 1129 should_abort = eep->ee_driver(eep, 1130 &(ev[index]), eecp, arg); 1131 break; 1132 case FSE_AZ_EV_CODE_DRV_GEN_EV: 1133 should_abort = eep->ee_drv_gen(eep, 1134 &(ev[index]), eecp, arg); 1135 break; 1136#if EFSYS_OPT_MCDI 1137 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: 1138 should_abort = eep->ee_mcdi(eep, 1139 &(ev[index]), eecp, arg); 1140 break; 1141#endif 1142 case FSE_AZ_EV_CODE_GLOBAL_EV: 1143 if (eep->ee_global) { 1144 should_abort = eep->ee_global(eep, 1145 &(ev[index]), eecp, arg); 1146 break; 1147 } 1148 /* else fallthrough */ 1149 default: 1150 EFSYS_PROBE3(bad_event, 1151 unsigned int, eep->ee_index, 1152 uint32_t, 1153 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), 1154 uint32_t, 1155 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); 1156 1157 EFSYS_ASSERT(eecp->eec_exception != NULL); 1158 (void) eecp->eec_exception(arg, 1159 EFX_EXCEPTION_EV_ERROR, code); 1160 should_abort = B_TRUE; 1161 } 1162 if (should_abort) { 1163 /* Ignore subsequent events */ 1164 total = index + 1; 1165 break; 1166 } 1167 } 1168 1169 /* 1170 * Now that the hardware has most likely moved onto dma'ing 1171 * into the next cache line, clear the processed events. Take 1172 * care to only clear out events that we've processed 1173 */ 1174 EFX_SET_QWORD(ev[0]); 1175 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 1176 for (index = 0; index < total; ++index) { 1177 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 1178 offset += sizeof (efx_qword_t); 1179 } 1180 1181 count += total; 1182 1183 } while (total == batch); 1184 1185 *countp = count; 1186} 1187 1188static void 1189falconsiena_ev_qpost( 1190 __in efx_evq_t *eep, 1191 __in uint16_t data) 1192{ 1193 efx_nic_t *enp = eep->ee_enp; 1194 efx_qword_t ev; 1195 efx_oword_t oword; 1196 1197 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 1198 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 1199 1200 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 1201 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 1202 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 1203 1204 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 1205} 1206 1207static __checkReturn efx_rc_t 1208falconsiena_ev_qmoderate( 1209 __in efx_evq_t *eep, 1210 __in unsigned int us) 1211{ 1212 efx_nic_t *enp = eep->ee_enp; 1213 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1214 unsigned int locked; 1215 efx_dword_t dword; 1216 efx_rc_t rc; 1217 1218 if (us > encp->enc_evq_timer_max_us) { 1219 rc = EINVAL; 1220 goto fail1; 1221 } 1222 1223 /* If the value is zero then disable the timer */ 1224 if (us == 0) { 1225 if (enp->en_family == EFX_FAMILY_FALCON) 1226 EFX_POPULATE_DWORD_2(dword, 1227 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS, 1228 FRF_AB_TC_TIMER_VAL, 0); 1229 else 1230 EFX_POPULATE_DWORD_2(dword, 1231 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 1232 FRF_CZ_TC_TIMER_VAL, 0); 1233 } else { 1234 uint32_t timer_val; 1235 1236 /* Calculate the timer value in quanta */ 1237 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; 1238 1239 /* Moderation value is base 0 so we need to deduct 1 */ 1240 if (timer_val > 0) 1241 timer_val--; 1242 1243 if (enp->en_family == EFX_FAMILY_FALCON) 1244 EFX_POPULATE_DWORD_2(dword, 1245 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF, 1246 FRF_AB_TIMER_VAL, timer_val); 1247 else 1248 EFX_POPULATE_DWORD_2(dword, 1249 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 1250 FRF_CZ_TC_TIMER_VAL, timer_val); 1251 } 1252 1253 locked = (eep->ee_index == 0) ? 1 : 0; 1254 1255 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 1256 eep->ee_index, &dword, locked); 1257 1258 return (0); 1259 1260fail1: 1261 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1262 1263 return (rc); 1264} 1265 1266static __checkReturn efx_rc_t 1267falconsiena_ev_qcreate( 1268 __in efx_nic_t *enp, 1269 __in unsigned int index, 1270 __in efsys_mem_t *esmp, 1271 __in size_t n, 1272 __in uint32_t id, 1273 __in efx_evq_t *eep) 1274{ 1275 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1276 uint32_t size; 1277 efx_oword_t oword; 1278 efx_rc_t rc; 1279 1280 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); 1281 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); 1282 1283 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) { 1284 rc = EINVAL; 1285 goto fail1; 1286 } 1287 if (index >= encp->enc_evq_limit) { 1288 rc = EINVAL; 1289 goto fail2; 1290 } 1291#if EFSYS_OPT_RX_SCALE 1292 if (enp->en_intr.ei_type == EFX_INTR_LINE && 1293 index >= EFX_MAXRSS_LEGACY) { 1294 rc = EINVAL; 1295 goto fail3; 1296 } 1297#endif 1298 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 1299 size++) 1300 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 1301 break; 1302 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1303 rc = EINVAL; 1304 goto fail4; 1305 } 1306 1307 /* Set up the handler table */ 1308 eep->ee_rx = falconsiena_ev_rx; 1309 eep->ee_tx = falconsiena_ev_tx; 1310 eep->ee_driver = falconsiena_ev_driver; 1311 eep->ee_global = falconsiena_ev_global; 1312 eep->ee_drv_gen = falconsiena_ev_drv_gen; 1313#if EFSYS_OPT_MCDI 1314 eep->ee_mcdi = falconsiena_ev_mcdi; 1315#endif /* EFSYS_OPT_MCDI */ 1316 1317 /* Set up the new event queue */ 1318 if (enp->en_family != EFX_FAMILY_FALCON) { 1319 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 1320 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); 1321 } 1322 1323 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 1324 FRF_AZ_EVQ_BUF_BASE_ID, id); 1325 1326 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); 1327 1328 return (0); 1329 1330fail4: 1331 EFSYS_PROBE(fail4); 1332#if EFSYS_OPT_RX_SCALE 1333fail3: 1334 EFSYS_PROBE(fail3); 1335#endif 1336fail2: 1337 EFSYS_PROBE(fail2); 1338fail1: 1339 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1340 1341 return (rc); 1342} 1343 1344#endif /* EFSYS_OPT_SIENA */ 1345 1346#if EFSYS_OPT_QSTATS 1347#if EFSYS_OPT_NAMES 1348/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */ 1349static const char *__efx_ev_qstat_name[] = { 1350 "all", 1351 "rx", 1352 "rx_ok", 1353 "rx_frm_trunc", 1354 "rx_tobe_disc", 1355 "rx_pause_frm_err", 1356 "rx_buf_owner_id_err", 1357 "rx_ipv4_hdr_chksum_err", 1358 "rx_tcp_udp_chksum_err", 1359 "rx_eth_crc_err", 1360 "rx_ip_frag_err", 1361 "rx_mcast_pkt", 1362 "rx_mcast_hash_match", 1363 "rx_tcp_ipv4", 1364 "rx_tcp_ipv6", 1365 "rx_udp_ipv4", 1366 "rx_udp_ipv6", 1367 "rx_other_ipv4", 1368 "rx_other_ipv6", 1369 "rx_non_ip", 1370 "rx_batch", 1371 "tx", 1372 "tx_wq_ff_full", 1373 "tx_pkt_err", 1374 "tx_pkt_too_big", 1375 "tx_unexpected", 1376 "global", 1377 "global_mnt", 1378 "driver", 1379 "driver_srm_upd_done", 1380 "driver_tx_descq_fls_done", 1381 "driver_rx_descq_fls_done", 1382 "driver_rx_descq_fls_failed", 1383 "driver_rx_dsc_error", 1384 "driver_tx_dsc_error", 1385 "drv_gen", 1386 "mcdi_response", 1387}; 1388/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1389 1390 const char * 1391efx_ev_qstat_name( 1392 __in efx_nic_t *enp, 1393 __in unsigned int id) 1394{ 1395 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1396 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1397 1398 return (__efx_ev_qstat_name[id]); 1399} 1400#endif /* EFSYS_OPT_NAMES */ 1401#endif /* EFSYS_OPT_QSTATS */ 1402 1403#if EFSYS_OPT_SIENA 1404 1405#if EFSYS_OPT_QSTATS 1406static void 1407falconsiena_ev_qstats_update( 1408 __in efx_evq_t *eep, 1409 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1410{ 1411 unsigned int id; 1412 1413 for (id = 0; id < EV_NQSTATS; id++) { 1414 efsys_stat_t *essp = &stat[id]; 1415 1416 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1417 eep->ee_stat[id] = 0; 1418 } 1419} 1420#endif /* EFSYS_OPT_QSTATS */ 1421 1422static void 1423falconsiena_ev_qdestroy( 1424 __in efx_evq_t *eep) 1425{ 1426 efx_nic_t *enp = eep->ee_enp; 1427 efx_oword_t oword; 1428 1429 /* Purge event queue */ 1430 EFX_ZERO_OWORD(oword); 1431 1432 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1433 eep->ee_index, &oword, B_TRUE); 1434 1435 if (enp->en_family != EFX_FAMILY_FALCON) { 1436 EFX_ZERO_OWORD(oword); 1437 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, 1438 eep->ee_index, &oword, B_TRUE); 1439 } 1440} 1441 1442static void 1443falconsiena_ev_fini( 1444 __in efx_nic_t *enp) 1445{ 1446 _NOTE(ARGUNUSED(enp)) 1447} 1448 1449#endif /* EFSYS_OPT_SIENA */ 1450