efx_ev.c revision 277886
1227569Sphilip/*- 2227569Sphilip * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3227569Sphilip * 4227569Sphilip * Redistribution and use in source and binary forms, with or without 5227569Sphilip * modification, are permitted provided that the following conditions 6227569Sphilip * are met: 7227569Sphilip * 1. Redistributions of source code must retain the above copyright 8227569Sphilip * notice, this list of conditions and the following disclaimer. 9227569Sphilip * 2. Redistributions in binary form must reproduce the above copyright 10227569Sphilip * notice, this list of conditions and the following disclaimer in the 11227569Sphilip * documentation and/or other materials provided with the distribution. 12227569Sphilip * 13227569Sphilip * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14227569Sphilip * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15227569Sphilip * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16227569Sphilip * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17227569Sphilip * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18227569Sphilip * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19227569Sphilip * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20227569Sphilip * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21227569Sphilip * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22227569Sphilip * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23227569Sphilip * SUCH DAMAGE. 24227569Sphilip */ 25227569Sphilip 26228078Sphilip#include <sys/cdefs.h> 27228078Sphilip__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/efx_ev.c 277886 2015-01-29 18:54:43Z arybchik $"); 28228078Sphilip 29227569Sphilip#include "efsys.h" 30227569Sphilip#include "efx.h" 31227569Sphilip#include "efx_types.h" 32227569Sphilip#include "efx_regs.h" 33227569Sphilip#include "efx_impl.h" 34227569Sphilip 35227569Sphilip#if EFSYS_OPT_QSTATS 36227569Sphilip#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 37227569Sphilip do { \ 38227569Sphilip (_eep)->ee_stat[_stat]++; \ 39227569Sphilip _NOTE(CONSTANTCONDITION) \ 40227569Sphilip } while (B_FALSE) 41227569Sphilip#else 42227569Sphilip#define EFX_EV_QSTAT_INCR(_eep, _stat) 43227569Sphilip#endif 44227569Sphilip 45227569Sphilip __checkReturn int 46227569Sphilipefx_ev_init( 47227569Sphilip __in efx_nic_t *enp) 48227569Sphilip{ 49227569Sphilip efx_oword_t oword; 50227569Sphilip int rc; 51227569Sphilip 52227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 53227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 54227569Sphilip 55227569Sphilip if (enp->en_mod_flags & EFX_MOD_EV) { 56227569Sphilip rc = EINVAL; 57227569Sphilip goto fail1; 58227569Sphilip } 59227569Sphilip 60227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 61227569Sphilip 62227569Sphilip /* 63227569Sphilip * Program the event queue for receive and transmit queue 64227569Sphilip * flush events. 65227569Sphilip */ 66227569Sphilip EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 67227569Sphilip EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 68227569Sphilip EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 69227569Sphilip 70227569Sphilip enp->en_mod_flags |= EFX_MOD_EV; 71227569Sphilip return (0); 72227569Sphilip 73227569Sphilipfail1: 74227569Sphilip EFSYS_PROBE1(fail1, int, rc); 75227569Sphilip 76227569Sphilip return (rc); 77227569Sphilip} 78227569Sphilip 79227569Sphilipstatic __checkReturn boolean_t 80227569Sphilipefx_ev_rx_not_ok( 81227569Sphilip __in efx_evq_t *eep, 82227569Sphilip __in efx_qword_t *eqp, 83227569Sphilip __in uint32_t label, 84227569Sphilip __in uint32_t id, 85227569Sphilip __inout uint16_t *flagsp) 86227569Sphilip{ 87227569Sphilip boolean_t ignore = B_FALSE; 88227569Sphilip 89227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 90227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 91227569Sphilip EFSYS_PROBE(tobe_disc); 92227569Sphilip /* Assume this is a unicast address mismatch, unless below 93227569Sphilip * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 94227569Sphilip * EV_RX_PAUSE_FRM_ERR is set. 95227569Sphilip */ 96227569Sphilip (*flagsp) |= EFX_ADDR_MISMATCH; 97227569Sphilip } 98227569Sphilip 99227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 100227569Sphilip EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 101227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 102227569Sphilip (*flagsp) |= EFX_DISCARD; 103227569Sphilip 104227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 105227569Sphilip /* Lookout for payload queue ran dry errors and ignore them. 106227569Sphilip * 107227569Sphilip * Sadly for the header/data split cases, the descriptor 108227569Sphilip * pointer in this event refers to the header queue and 109227569Sphilip * therefore cannot be easily detected as duplicate. 110227569Sphilip * So we drop these and rely on the receive processing seeing 111227569Sphilip * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 112227569Sphilip * the partially received packet. 113227569Sphilip */ 114227569Sphilip if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 115227569Sphilip (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 116227569Sphilip (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 117227569Sphilip ignore = B_TRUE; 118227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 119227569Sphilip } 120227569Sphilip 121227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 122227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 123227569Sphilip EFSYS_PROBE(crc_err); 124227569Sphilip (*flagsp) &= ~EFX_ADDR_MISMATCH; 125227569Sphilip (*flagsp) |= EFX_DISCARD; 126227569Sphilip } 127227569Sphilip 128227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 129227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 130227569Sphilip EFSYS_PROBE(pause_frm_err); 131227569Sphilip (*flagsp) &= ~EFX_ADDR_MISMATCH; 132227569Sphilip (*flagsp) |= EFX_DISCARD; 133227569Sphilip } 134227569Sphilip 135227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 136227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 137227569Sphilip EFSYS_PROBE(owner_id_err); 138227569Sphilip (*flagsp) |= EFX_DISCARD; 139227569Sphilip } 140227569Sphilip 141227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 142227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 143227569Sphilip EFSYS_PROBE(ipv4_err); 144227569Sphilip (*flagsp) &= ~EFX_CKSUM_IPV4; 145227569Sphilip } 146227569Sphilip 147227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 148227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 149227569Sphilip EFSYS_PROBE(udp_chk_err); 150227569Sphilip (*flagsp) &= ~EFX_CKSUM_TCPUDP; 151227569Sphilip } 152227569Sphilip 153227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 154227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 155227569Sphilip 156227569Sphilip /* 157227569Sphilip * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 158227569Sphilip * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 159227569Sphilip * condition. 160227569Sphilip */ 161227569Sphilip (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 162227569Sphilip } 163227569Sphilip 164227569Sphilip return (ignore); 165227569Sphilip} 166227569Sphilip 167227569Sphilipstatic __checkReturn boolean_t 168227569Sphilipefx_ev_rx( 169227569Sphilip __in efx_evq_t *eep, 170227569Sphilip __in efx_qword_t *eqp, 171227569Sphilip __in const efx_ev_callbacks_t *eecp, 172227569Sphilip __in_opt void *arg) 173227569Sphilip{ 174227569Sphilip efx_nic_t *enp = eep->ee_enp; 175227569Sphilip uint32_t id; 176227569Sphilip uint32_t size; 177227569Sphilip uint32_t label; 178227569Sphilip boolean_t ok; 179227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 180227569Sphilip boolean_t sop; 181227569Sphilip boolean_t jumbo_cont; 182227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 183227569Sphilip uint32_t hdr_type; 184227569Sphilip boolean_t is_v6; 185227569Sphilip uint16_t flags; 186227569Sphilip boolean_t ignore; 187227569Sphilip boolean_t should_abort; 188227569Sphilip 189227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX); 190227569Sphilip 191227569Sphilip /* Basic packet information */ 192227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 193227569Sphilip size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 194227569Sphilip label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 195227569Sphilip ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 196227569Sphilip 197227569Sphilip#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 198227569Sphilip sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 199227569Sphilip jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 200227569Sphilip#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 201227569Sphilip 202227569Sphilip hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 203227569Sphilip 204227569Sphilip is_v6 = (enp->en_family != EFX_FAMILY_FALCON && 205227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 206227569Sphilip 207227569Sphilip /* 208227569Sphilip * If packet is marked as OK and packet type is TCP/IP or 209227569Sphilip * UDP/IP or other IP, then we can rely on the hardware checksums. 210227569Sphilip */ 211227569Sphilip switch (hdr_type) { 212227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 213227569Sphilip flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 214227569Sphilip if (is_v6) { 215227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 216227569Sphilip flags |= EFX_PKT_IPV6; 217227569Sphilip } else { 218227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 219227569Sphilip flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 220227569Sphilip } 221227569Sphilip break; 222227569Sphilip 223227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 224227569Sphilip flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 225227569Sphilip if (is_v6) { 226227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 227227569Sphilip flags |= EFX_PKT_IPV6; 228227569Sphilip } else { 229227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 230227569Sphilip flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 231227569Sphilip } 232227569Sphilip break; 233227569Sphilip 234227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 235227569Sphilip if (is_v6) { 236227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 237227569Sphilip flags = EFX_PKT_IPV6; 238227569Sphilip } else { 239227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 240227569Sphilip flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 241227569Sphilip } 242227569Sphilip break; 243227569Sphilip 244227569Sphilip case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 245227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 246227569Sphilip flags = 0; 247227569Sphilip break; 248227569Sphilip 249227569Sphilip default: 250227569Sphilip EFSYS_ASSERT(B_FALSE); 251227569Sphilip flags = 0; 252227569Sphilip break; 253227569Sphilip } 254227569Sphilip 255227569Sphilip#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT 256227569Sphilip /* Report scatter and header/lookahead split buffer flags */ 257227569Sphilip if (sop) 258227569Sphilip flags |= EFX_PKT_START; 259227569Sphilip if (jumbo_cont) 260227569Sphilip flags |= EFX_PKT_CONT; 261227569Sphilip#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */ 262227569Sphilip 263227569Sphilip /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 264227569Sphilip if (!ok) { 265227569Sphilip ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags); 266227569Sphilip if (ignore) { 267227569Sphilip EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 268227569Sphilip uint32_t, size, uint16_t, flags); 269227569Sphilip 270227569Sphilip return (B_FALSE); 271227569Sphilip } 272227569Sphilip } 273227569Sphilip 274227569Sphilip /* If we're not discarding the packet then it is ok */ 275227569Sphilip if (~flags & EFX_DISCARD) 276227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 277227569Sphilip 278227569Sphilip /* Detect multicast packets that didn't match the filter */ 279227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 280227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 281227569Sphilip 282227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 283227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 284227569Sphilip } else { 285227569Sphilip EFSYS_PROBE(mcast_mismatch); 286227569Sphilip flags |= EFX_ADDR_MISMATCH; 287227569Sphilip } 288227569Sphilip } else { 289227569Sphilip flags |= EFX_PKT_UNICAST; 290227569Sphilip } 291227569Sphilip 292227569Sphilip /* 293227569Sphilip * The packet parser in Siena can abort parsing packets under 294227569Sphilip * certain error conditions, setting the PKT_NOT_PARSED bit 295227569Sphilip * (which clears PKT_OK). If this is set, then don't trust 296227569Sphilip * the PKT_TYPE field. 297227569Sphilip */ 298227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON && !ok) { 299227569Sphilip uint32_t parse_err; 300227569Sphilip 301227569Sphilip parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 302227569Sphilip if (parse_err != 0) 303227569Sphilip flags |= EFX_CHECK_VLAN; 304227569Sphilip } 305227569Sphilip 306227569Sphilip if (~flags & EFX_CHECK_VLAN) { 307227569Sphilip uint32_t pkt_type; 308227569Sphilip 309227569Sphilip pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 310227569Sphilip if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 311227569Sphilip flags |= EFX_PKT_VLAN_TAGGED; 312227569Sphilip } 313227569Sphilip 314227569Sphilip EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 315227569Sphilip uint32_t, size, uint16_t, flags); 316227569Sphilip 317227569Sphilip EFSYS_ASSERT(eecp->eec_rx != NULL); 318227569Sphilip should_abort = eecp->eec_rx(arg, label, id, size, flags); 319227569Sphilip 320227569Sphilip return (should_abort); 321227569Sphilip} 322227569Sphilip 323227569Sphilipstatic __checkReturn boolean_t 324227569Sphilipefx_ev_tx( 325227569Sphilip __in efx_evq_t *eep, 326227569Sphilip __in efx_qword_t *eqp, 327227569Sphilip __in const efx_ev_callbacks_t *eecp, 328227569Sphilip __in_opt void *arg) 329227569Sphilip{ 330227569Sphilip uint32_t id; 331227569Sphilip uint32_t label; 332227569Sphilip boolean_t should_abort; 333227569Sphilip 334227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX); 335227569Sphilip 336227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 337227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 338227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 339227569Sphilip EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 340227569Sphilip 341227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 342227569Sphilip label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 343227569Sphilip 344227569Sphilip EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 345227569Sphilip 346227569Sphilip EFSYS_ASSERT(eecp->eec_tx != NULL); 347227569Sphilip should_abort = eecp->eec_tx(arg, label, id); 348227569Sphilip 349227569Sphilip return (should_abort); 350227569Sphilip } 351227569Sphilip 352227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 353227569Sphilip EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 354227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 355227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 356227569Sphilip 357227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 358227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 359227569Sphilip 360227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 361227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 362227569Sphilip 363227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 364227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 365227569Sphilip 366227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 367227569Sphilip return (B_FALSE); 368227569Sphilip} 369227569Sphilip 370227569Sphilipstatic __checkReturn boolean_t 371227569Sphilipefx_ev_global( 372227569Sphilip __in efx_evq_t *eep, 373227569Sphilip __in efx_qword_t *eqp, 374227569Sphilip __in const efx_ev_callbacks_t *eecp, 375227569Sphilip __in_opt void *arg) 376227569Sphilip{ 377227569Sphilip efx_nic_t *enp = eep->ee_enp; 378227569Sphilip efx_port_t *epp = &(enp->en_port); 379227569Sphilip boolean_t should_abort; 380227569Sphilip 381227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 382227569Sphilip should_abort = B_FALSE; 383227569Sphilip 384227569Sphilip /* Check for a link management event */ 385227569Sphilip if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) { 386227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT); 387227569Sphilip 388227569Sphilip EFSYS_PROBE(xg_mgt); 389227569Sphilip 390227569Sphilip epp->ep_mac_poll_needed = B_TRUE; 391227569Sphilip } 392227569Sphilip 393227569Sphilip return (should_abort); 394227569Sphilip} 395227569Sphilip 396227569Sphilipstatic __checkReturn boolean_t 397227569Sphilipefx_ev_driver( 398227569Sphilip __in efx_evq_t *eep, 399227569Sphilip __in efx_qword_t *eqp, 400227569Sphilip __in const efx_ev_callbacks_t *eecp, 401227569Sphilip __in_opt void *arg) 402227569Sphilip{ 403227569Sphilip boolean_t should_abort; 404227569Sphilip 405227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 406227569Sphilip should_abort = B_FALSE; 407227569Sphilip 408227569Sphilip switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 409227569Sphilip case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 410264461Sgnn uint32_t txq_index; 411227569Sphilip 412227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 413227569Sphilip 414264461Sgnn txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 415227569Sphilip 416264461Sgnn EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 417227569Sphilip 418227569Sphilip EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 419264461Sgnn should_abort = eecp->eec_txq_flush_done(arg, txq_index); 420227569Sphilip 421227569Sphilip break; 422227569Sphilip } 423227569Sphilip case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 424264461Sgnn uint32_t rxq_index; 425227569Sphilip uint32_t failed; 426227569Sphilip 427264461Sgnn rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 428227569Sphilip failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 429227569Sphilip 430227569Sphilip EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 431227569Sphilip EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 432227569Sphilip 433227569Sphilip if (failed) { 434227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 435227569Sphilip 436264461Sgnn EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 437227569Sphilip 438264461Sgnn should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index); 439227569Sphilip } else { 440227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 441227569Sphilip 442264461Sgnn EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 443227569Sphilip 444264461Sgnn should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 445227569Sphilip } 446227569Sphilip 447227569Sphilip break; 448227569Sphilip } 449227569Sphilip case FSE_AZ_EVQ_INIT_DONE_EV: 450227569Sphilip EFSYS_ASSERT(eecp->eec_initialized != NULL); 451227569Sphilip should_abort = eecp->eec_initialized(arg); 452227569Sphilip 453227569Sphilip break; 454227569Sphilip 455227569Sphilip case FSE_AZ_EVQ_NOT_EN_EV: 456227569Sphilip EFSYS_PROBE(evq_not_en); 457227569Sphilip break; 458227569Sphilip 459227569Sphilip case FSE_AZ_SRM_UPD_DONE_EV: { 460227569Sphilip uint32_t code; 461227569Sphilip 462227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 463227569Sphilip 464227569Sphilip code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 465227569Sphilip 466227569Sphilip EFSYS_ASSERT(eecp->eec_sram != NULL); 467227569Sphilip should_abort = eecp->eec_sram(arg, code); 468227569Sphilip 469227569Sphilip break; 470227569Sphilip } 471227569Sphilip case FSE_AZ_WAKE_UP_EV: { 472227569Sphilip uint32_t id; 473227569Sphilip 474227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 475227569Sphilip 476227569Sphilip EFSYS_ASSERT(eecp->eec_wake_up != NULL); 477227569Sphilip should_abort = eecp->eec_wake_up(arg, id); 478227569Sphilip 479227569Sphilip break; 480227569Sphilip } 481227569Sphilip case FSE_AZ_TX_PKT_NON_TCP_UDP: 482227569Sphilip EFSYS_PROBE(tx_pkt_non_tcp_udp); 483227569Sphilip break; 484227569Sphilip 485227569Sphilip case FSE_AZ_TIMER_EV: { 486227569Sphilip uint32_t id; 487227569Sphilip 488227569Sphilip id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 489227569Sphilip 490227569Sphilip EFSYS_ASSERT(eecp->eec_timer != NULL); 491227569Sphilip should_abort = eecp->eec_timer(arg, id); 492227569Sphilip 493227569Sphilip break; 494227569Sphilip } 495227569Sphilip case FSE_AZ_RX_DSC_ERROR_EV: 496227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 497227569Sphilip 498227569Sphilip EFSYS_PROBE(rx_dsc_error); 499227569Sphilip 500227569Sphilip EFSYS_ASSERT(eecp->eec_exception != NULL); 501227569Sphilip should_abort = eecp->eec_exception(arg, 502227569Sphilip EFX_EXCEPTION_RX_DSC_ERROR, 0); 503227569Sphilip 504227569Sphilip break; 505227569Sphilip 506227569Sphilip case FSE_AZ_TX_DSC_ERROR_EV: 507227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 508227569Sphilip 509227569Sphilip EFSYS_PROBE(tx_dsc_error); 510227569Sphilip 511227569Sphilip EFSYS_ASSERT(eecp->eec_exception != NULL); 512227569Sphilip should_abort = eecp->eec_exception(arg, 513227569Sphilip EFX_EXCEPTION_TX_DSC_ERROR, 0); 514227569Sphilip 515227569Sphilip break; 516227569Sphilip 517227569Sphilip default: 518227569Sphilip break; 519227569Sphilip } 520227569Sphilip 521227569Sphilip return (should_abort); 522227569Sphilip} 523227569Sphilip 524227569Sphilipstatic __checkReturn boolean_t 525227569Sphilipefx_ev_drv_gen( 526227569Sphilip __in efx_evq_t *eep, 527227569Sphilip __in efx_qword_t *eqp, 528227569Sphilip __in const efx_ev_callbacks_t *eecp, 529227569Sphilip __in_opt void *arg) 530227569Sphilip{ 531227569Sphilip uint32_t data; 532227569Sphilip boolean_t should_abort; 533227569Sphilip 534227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 535227569Sphilip 536227569Sphilip data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 537227569Sphilip if (data >= ((uint32_t)1 << 16)) { 538227569Sphilip EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 539227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 540227569Sphilip uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 541227569Sphilip return (B_TRUE); 542227569Sphilip } 543227569Sphilip 544227569Sphilip EFSYS_ASSERT(eecp->eec_software != NULL); 545227569Sphilip should_abort = eecp->eec_software(arg, (uint16_t)data); 546227569Sphilip 547227569Sphilip return (should_abort); 548227569Sphilip} 549227569Sphilip 550227569Sphilip#if EFSYS_OPT_MCDI 551227569Sphilip 552227569Sphilipstatic __checkReturn boolean_t 553227569Sphilipefx_ev_mcdi( 554227569Sphilip __in efx_evq_t *eep, 555227569Sphilip __in efx_qword_t *eqp, 556227569Sphilip __in const efx_ev_callbacks_t *eecp, 557227569Sphilip __in_opt void *arg) 558227569Sphilip{ 559227569Sphilip efx_nic_t *enp = eep->ee_enp; 560227569Sphilip unsigned code; 561227569Sphilip boolean_t should_abort = B_FALSE; 562227569Sphilip 563227569Sphilip EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 564227569Sphilip 565227569Sphilip if (enp->en_family != EFX_FAMILY_SIENA) 566227569Sphilip goto out; 567227569Sphilip 568227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 569227569Sphilip 570227569Sphilip code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 571227569Sphilip switch (code) { 572227569Sphilip case MCDI_EVENT_CODE_BADSSERT: 573227569Sphilip efx_mcdi_ev_death(enp, EINTR); 574227569Sphilip break; 575227569Sphilip 576227569Sphilip case MCDI_EVENT_CODE_CMDDONE: 577227569Sphilip efx_mcdi_ev_cpl(enp, 578227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_SEQ), 579227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_DATALEN), 580227569Sphilip MCDI_EV_FIELD(*eqp, CMDDONE_ERRNO)); 581227569Sphilip break; 582227569Sphilip 583227569Sphilip case MCDI_EVENT_CODE_LINKCHANGE: { 584227569Sphilip efx_link_mode_t link_mode; 585227569Sphilip 586227569Sphilip siena_phy_link_ev(enp, eqp, &link_mode); 587227569Sphilip should_abort = eecp->eec_link_change(arg, link_mode); 588227569Sphilip break; 589227569Sphilip } 590227569Sphilip case MCDI_EVENT_CODE_SENSOREVT: { 591227569Sphilip#if EFSYS_OPT_MON_STATS 592227569Sphilip efx_mon_stat_t id; 593227569Sphilip efx_mon_stat_value_t value; 594227569Sphilip int rc; 595227569Sphilip 596227569Sphilip if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0) 597227569Sphilip should_abort = eecp->eec_monitor(arg, id, value); 598227569Sphilip else if (rc == ENOTSUP) { 599227569Sphilip should_abort = eecp->eec_exception(arg, 600227569Sphilip EFX_EXCEPTION_UNKNOWN_SENSOREVT, 601227569Sphilip MCDI_EV_FIELD(eqp, DATA)); 602227569Sphilip } else 603227569Sphilip EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 604227569Sphilip#else 605227569Sphilip should_abort = B_FALSE; 606227569Sphilip#endif 607227569Sphilip break; 608227569Sphilip } 609227569Sphilip case MCDI_EVENT_CODE_SCHEDERR: 610227569Sphilip /* Informational only */ 611227569Sphilip break; 612227569Sphilip 613227569Sphilip case MCDI_EVENT_CODE_REBOOT: 614227569Sphilip efx_mcdi_ev_death(enp, EIO); 615227569Sphilip break; 616227569Sphilip 617227569Sphilip case MCDI_EVENT_CODE_MAC_STATS_DMA: 618227569Sphilip#if EFSYS_OPT_MAC_STATS 619227569Sphilip if (eecp->eec_mac_stats != NULL) { 620227569Sphilip eecp->eec_mac_stats(arg, 621227569Sphilip MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 622227569Sphilip } 623227569Sphilip#endif 624227569Sphilip break; 625227569Sphilip 626227569Sphilip case MCDI_EVENT_CODE_FWALERT: { 627227569Sphilip uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 628227569Sphilip 629227569Sphilip if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 630227569Sphilip should_abort = eecp->eec_exception(arg, 631227569Sphilip EFX_EXCEPTION_FWALERT_SRAM, 632227569Sphilip MCDI_EV_FIELD(eqp, FWALERT_DATA)); 633227569Sphilip else 634227569Sphilip should_abort = eecp->eec_exception(arg, 635227569Sphilip EFX_EXCEPTION_UNKNOWN_FWALERT, 636227569Sphilip MCDI_EV_FIELD(eqp, DATA)); 637227569Sphilip break; 638227569Sphilip } 639227569Sphilip 640227569Sphilip default: 641227569Sphilip EFSYS_PROBE1(mc_pcol_error, int, code); 642227569Sphilip break; 643227569Sphilip } 644227569Sphilip 645227569Sphilipout: 646227569Sphilip return (should_abort); 647227569Sphilip} 648227569Sphilip 649227569Sphilip#endif /* EFSYS_OPT_SIENA */ 650227569Sphilip 651227569Sphilip __checkReturn int 652227569Sphilipefx_ev_qprime( 653227569Sphilip __in efx_evq_t *eep, 654227569Sphilip __in unsigned int count) 655227569Sphilip{ 656227569Sphilip efx_nic_t *enp = eep->ee_enp; 657227569Sphilip uint32_t rptr; 658227569Sphilip efx_dword_t dword; 659227569Sphilip int rc; 660227569Sphilip 661227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 662227569Sphilip 663227569Sphilip if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 664227569Sphilip rc = EINVAL; 665227569Sphilip goto fail1; 666227569Sphilip } 667227569Sphilip 668227569Sphilip rptr = count & eep->ee_mask; 669227569Sphilip 670227569Sphilip EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 671227569Sphilip 672227569Sphilip EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 673227569Sphilip &dword, B_FALSE); 674227569Sphilip 675227569Sphilip return (0); 676227569Sphilip 677227569Sphilipfail1: 678227569Sphilip EFSYS_PROBE1(fail1, int, rc); 679227569Sphilip 680227569Sphilip return (rc); 681227569Sphilip} 682227569Sphilip 683227569Sphilip __checkReturn boolean_t 684227569Sphilipefx_ev_qpending( 685227569Sphilip __in efx_evq_t *eep, 686227569Sphilip __in unsigned int count) 687227569Sphilip{ 688227569Sphilip size_t offset; 689227569Sphilip efx_qword_t qword; 690227569Sphilip 691227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 692227569Sphilip 693227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 694227569Sphilip EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 695227569Sphilip 696227569Sphilip return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff && 697227569Sphilip EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff); 698227569Sphilip} 699227569Sphilip 700227569Sphilip#if EFSYS_OPT_EV_PREFETCH 701227569Sphilip 702227569Sphilip void 703227569Sphilipefx_ev_qprefetch( 704227569Sphilip __in efx_evq_t *eep, 705227569Sphilip __in unsigned int count) 706227569Sphilip{ 707227569Sphilip unsigned int offset; 708227569Sphilip 709227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 710227569Sphilip 711227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 712227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 713227569Sphilip} 714227569Sphilip 715227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 716227569Sphilip 717227569Sphilip#define EFX_EV_BATCH 8 718227569Sphilip 719227569Sphilip#define EFX_EV_PRESENT(_qword) \ 720227569Sphilip (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 721227569Sphilip EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 722227569Sphilip 723227569Sphilip void 724227569Sphilipefx_ev_qpoll( 725227569Sphilip __in efx_evq_t *eep, 726227569Sphilip __inout unsigned int *countp, 727227569Sphilip __in const efx_ev_callbacks_t *eecp, 728227569Sphilip __in_opt void *arg) 729227569Sphilip{ 730227569Sphilip efx_qword_t ev[EFX_EV_BATCH]; 731227569Sphilip unsigned int batch; 732227569Sphilip unsigned int total; 733227569Sphilip unsigned int count; 734227569Sphilip unsigned int index; 735227569Sphilip size_t offset; 736227569Sphilip 737227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 738227569Sphilip EFSYS_ASSERT(countp != NULL); 739227569Sphilip EFSYS_ASSERT(eecp != NULL); 740227569Sphilip 741227569Sphilip count = *countp; 742227569Sphilip do { 743227569Sphilip /* Read up until the end of the batch period */ 744227569Sphilip batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 745227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 746227569Sphilip for (total = 0; total < batch; ++total) { 747227569Sphilip EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 748227569Sphilip 749227569Sphilip if (!EFX_EV_PRESENT(ev[total])) 750227569Sphilip break; 751227569Sphilip 752227569Sphilip EFSYS_PROBE3(event, unsigned int, eep->ee_index, 753227569Sphilip uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 754227569Sphilip uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 755227569Sphilip 756227569Sphilip offset += sizeof (efx_qword_t); 757227569Sphilip } 758227569Sphilip 759227569Sphilip#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 760227569Sphilip /* 761227569Sphilip * Prefetch the next batch when we get within PREFETCH_PERIOD 762227569Sphilip * of a completed batch. If the batch is smaller, then prefetch 763227569Sphilip * immediately. 764227569Sphilip */ 765227569Sphilip if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 766227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 767227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 768227569Sphilip 769227569Sphilip /* Process the batch of events */ 770227569Sphilip for (index = 0; index < total; ++index) { 771227569Sphilip boolean_t should_abort; 772227569Sphilip uint32_t code; 773227569Sphilip efx_ev_handler_t handler; 774227569Sphilip 775227569Sphilip#if EFSYS_OPT_EV_PREFETCH 776227569Sphilip /* Prefetch if we've now reached the batch period */ 777227569Sphilip if (total == batch && 778227569Sphilip index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 779227569Sphilip offset = (count + batch) & eep->ee_mask; 780227569Sphilip offset *= sizeof (efx_qword_t); 781227569Sphilip 782227569Sphilip EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 783227569Sphilip } 784227569Sphilip#endif /* EFSYS_OPT_EV_PREFETCH */ 785227569Sphilip 786227569Sphilip EFX_EV_QSTAT_INCR(eep, EV_ALL); 787227569Sphilip 788227569Sphilip code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 789227569Sphilip handler = eep->ee_handler[code]; 790227569Sphilip EFSYS_ASSERT(handler != NULL); 791227569Sphilip should_abort = handler(eep, &(ev[index]), eecp, arg); 792227569Sphilip if (should_abort) { 793227569Sphilip /* Ignore subsequent events */ 794227569Sphilip total = index + 1; 795227569Sphilip break; 796227569Sphilip } 797227569Sphilip } 798227569Sphilip 799227569Sphilip /* 800227569Sphilip * Now that the hardware has most likely moved onto dma'ing 801227569Sphilip * into the next cache line, clear the processed events. Take 802227569Sphilip * care to only clear out events that we've processed 803227569Sphilip */ 804227569Sphilip EFX_SET_QWORD(ev[0]); 805227569Sphilip offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 806227569Sphilip for (index = 0; index < total; ++index) { 807227569Sphilip EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 808227569Sphilip offset += sizeof (efx_qword_t); 809227569Sphilip } 810227569Sphilip 811227569Sphilip count += total; 812227569Sphilip 813227569Sphilip } while (total == batch); 814227569Sphilip 815227569Sphilip *countp = count; 816227569Sphilip} 817227569Sphilip 818227569Sphilip void 819227569Sphilipefx_ev_qpost( 820227569Sphilip __in efx_evq_t *eep, 821227569Sphilip __in uint16_t data) 822227569Sphilip{ 823227569Sphilip efx_nic_t *enp = eep->ee_enp; 824227569Sphilip efx_qword_t ev; 825227569Sphilip efx_oword_t oword; 826227569Sphilip 827227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 828227569Sphilip 829227569Sphilip EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 830227569Sphilip FSF_AZ_EV_DATA_DW0, (uint32_t)data); 831227569Sphilip 832227569Sphilip EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 833227569Sphilip EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 834227569Sphilip EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 835227569Sphilip 836227569Sphilip EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 837227569Sphilip} 838227569Sphilip 839227569Sphilip __checkReturn int 840227569Sphilipefx_ev_qmoderate( 841227569Sphilip __in efx_evq_t *eep, 842227569Sphilip __in unsigned int us) 843227569Sphilip{ 844227569Sphilip efx_nic_t *enp = eep->ee_enp; 845227569Sphilip unsigned int locked; 846227569Sphilip efx_dword_t dword; 847227569Sphilip int rc; 848227569Sphilip 849227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 850227569Sphilip 851227569Sphilip if (us > enp->en_nic_cfg.enc_evq_moderation_max) { 852227569Sphilip rc = EINVAL; 853227569Sphilip goto fail1; 854227569Sphilip } 855227569Sphilip 856227569Sphilip /* If the value is zero then disable the timer */ 857227569Sphilip if (us == 0) { 858227569Sphilip if (enp->en_family == EFX_FAMILY_FALCON) 859227569Sphilip EFX_POPULATE_DWORD_2(dword, 860227569Sphilip FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS, 861227569Sphilip FRF_AB_TC_TIMER_VAL, 0); 862227569Sphilip else 863227569Sphilip EFX_POPULATE_DWORD_2(dword, 864227569Sphilip FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 865227569Sphilip FRF_CZ_TC_TIMER_VAL, 0); 866227569Sphilip } else { 867227569Sphilip uint32_t timer_val; 868227569Sphilip 869227569Sphilip /* Calculate the timer value in quanta */ 870227569Sphilip us -= (us % EFX_EV_TIMER_QUANTUM); 871227569Sphilip if (us < EFX_EV_TIMER_QUANTUM) 872227569Sphilip us = EFX_EV_TIMER_QUANTUM; 873227569Sphilip 874227569Sphilip timer_val = us / EFX_EV_TIMER_QUANTUM; 875227569Sphilip 876227569Sphilip /* Moderation value is base 0 so we need to deduct 1 */ 877227569Sphilip if (enp->en_family == EFX_FAMILY_FALCON) 878227569Sphilip EFX_POPULATE_DWORD_2(dword, 879227569Sphilip FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF, 880227569Sphilip FRF_AB_TIMER_VAL, timer_val - 1); 881227569Sphilip else 882227569Sphilip EFX_POPULATE_DWORD_2(dword, 883227569Sphilip FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 884227569Sphilip FRF_CZ_TC_TIMER_VAL, timer_val - 1); 885227569Sphilip } 886227569Sphilip 887227569Sphilip locked = (eep->ee_index == 0) ? 1 : 0; 888227569Sphilip 889227569Sphilip EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 890227569Sphilip eep->ee_index, &dword, locked); 891227569Sphilip 892227569Sphilip return (0); 893227569Sphilip 894227569Sphilipfail1: 895227569Sphilip EFSYS_PROBE1(fail1, int, rc); 896227569Sphilip 897227569Sphilip return (rc); 898227569Sphilip} 899227569Sphilip 900227569Sphilip __checkReturn int 901227569Sphilipefx_ev_qcreate( 902227569Sphilip __in efx_nic_t *enp, 903227569Sphilip __in unsigned int index, 904227569Sphilip __in efsys_mem_t *esmp, 905227569Sphilip __in size_t n, 906227569Sphilip __in uint32_t id, 907227569Sphilip __deref_out efx_evq_t **eepp) 908227569Sphilip{ 909227569Sphilip efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 910227569Sphilip uint32_t size; 911227569Sphilip efx_evq_t *eep; 912227569Sphilip efx_oword_t oword; 913227569Sphilip int rc; 914227569Sphilip 915227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 916227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 917227569Sphilip 918227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 919227569Sphilip 920227569Sphilip if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) { 921227569Sphilip rc = EINVAL; 922227569Sphilip goto fail1; 923227569Sphilip } 924227569Sphilip if (index >= encp->enc_evq_limit) { 925227569Sphilip rc = EINVAL; 926227569Sphilip goto fail2; 927227569Sphilip } 928227569Sphilip#if EFSYS_OPT_RX_SCALE 929227569Sphilip if (enp->en_intr.ei_type == EFX_INTR_LINE && 930227569Sphilip index >= EFX_MAXRSS_LEGACY) { 931227569Sphilip rc = EINVAL; 932227569Sphilip goto fail3; 933227569Sphilip } 934227569Sphilip#endif 935227569Sphilip for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 936227569Sphilip size++) 937227569Sphilip if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 938227569Sphilip break; 939227569Sphilip if (id + (1 << size) >= encp->enc_buftbl_limit) { 940227569Sphilip rc = EINVAL; 941227569Sphilip goto fail4; 942227569Sphilip } 943227569Sphilip 944227569Sphilip /* Allocate an EVQ object */ 945227569Sphilip EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 946227569Sphilip if (eep == NULL) { 947227569Sphilip rc = ENOMEM; 948227569Sphilip goto fail5; 949227569Sphilip } 950227569Sphilip 951227569Sphilip eep->ee_magic = EFX_EVQ_MAGIC; 952227569Sphilip eep->ee_enp = enp; 953227569Sphilip eep->ee_index = index; 954227569Sphilip eep->ee_mask = n - 1; 955227569Sphilip eep->ee_esmp = esmp; 956227569Sphilip 957227569Sphilip /* Set up the handler table */ 958227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx; 959227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx; 960227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver; 961227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global; 962227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen; 963227569Sphilip#if EFSYS_OPT_MCDI 964227569Sphilip eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi; 965227569Sphilip#endif /* EFSYS_OPT_SIENA */ 966227569Sphilip 967227569Sphilip /* Set up the new event queue */ 968227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON) { 969227569Sphilip EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 970227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword); 971227569Sphilip } 972227569Sphilip 973227569Sphilip EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 974227569Sphilip FRF_AZ_EVQ_BUF_BASE_ID, id); 975227569Sphilip 976227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword); 977227569Sphilip 978227569Sphilip enp->en_ev_qcount++; 979227569Sphilip *eepp = eep; 980227569Sphilip return (0); 981227569Sphilip 982227569Sphilipfail5: 983227569Sphilip EFSYS_PROBE(fail5); 984227569Sphilipfail4: 985227569Sphilip EFSYS_PROBE(fail4); 986227569Sphilip#if EFSYS_OPT_RX_SCALE 987227569Sphilipfail3: 988227569Sphilip EFSYS_PROBE(fail3); 989227569Sphilip#endif 990227569Sphilipfail2: 991227569Sphilip EFSYS_PROBE(fail2); 992227569Sphilipfail1: 993227569Sphilip EFSYS_PROBE1(fail1, int, rc); 994227569Sphilip 995227569Sphilip return (rc); 996227569Sphilip} 997227569Sphilip 998277886Sarybchik#if EFSYS_OPT_QSTATS 999227569Sphilip#if EFSYS_OPT_NAMES 1000227569Sphilip/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */ 1001227569Sphilipstatic const char __cs * __cs __efx_ev_qstat_name[] = { 1002227569Sphilip "all", 1003227569Sphilip "rx", 1004227569Sphilip "rx_ok", 1005227569Sphilip "rx_recovery", 1006227569Sphilip "rx_frm_trunc", 1007227569Sphilip "rx_tobe_disc", 1008227569Sphilip "rx_pause_frm_err", 1009227569Sphilip "rx_buf_owner_id_err", 1010227569Sphilip "rx_ipv4_hdr_chksum_err", 1011227569Sphilip "rx_tcp_udp_chksum_err", 1012227569Sphilip "rx_eth_crc_err", 1013227569Sphilip "rx_ip_frag_err", 1014227569Sphilip "rx_mcast_pkt", 1015227569Sphilip "rx_mcast_hash_match", 1016227569Sphilip "rx_tcp_ipv4", 1017227569Sphilip "rx_tcp_ipv6", 1018227569Sphilip "rx_udp_ipv4", 1019227569Sphilip "rx_udp_ipv6", 1020227569Sphilip "rx_other_ipv4", 1021227569Sphilip "rx_other_ipv6", 1022227569Sphilip "rx_non_ip", 1023227569Sphilip "rx_overrun", 1024227569Sphilip "tx", 1025227569Sphilip "tx_wq_ff_full", 1026227569Sphilip "tx_pkt_err", 1027227569Sphilip "tx_pkt_too_big", 1028227569Sphilip "tx_unexpected", 1029227569Sphilip "global", 1030227569Sphilip "global_phy", 1031227569Sphilip "global_mnt", 1032227569Sphilip "global_rx_recovery", 1033227569Sphilip "driver", 1034227569Sphilip "driver_srm_upd_done", 1035227569Sphilip "driver_tx_descq_fls_done", 1036227569Sphilip "driver_rx_descq_fls_done", 1037227569Sphilip "driver_rx_descq_fls_failed", 1038227569Sphilip "driver_rx_dsc_error", 1039227569Sphilip "driver_tx_dsc_error", 1040227569Sphilip "drv_gen", 1041227569Sphilip "mcdi_response", 1042227569Sphilip}; 1043227569Sphilip/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1044227569Sphilip 1045227569Sphilip const char __cs * 1046227569Sphilipefx_ev_qstat_name( 1047227569Sphilip __in efx_nic_t *enp, 1048227569Sphilip __in unsigned int id) 1049227569Sphilip{ 1050227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1051227569Sphilip EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1052227569Sphilip 1053227569Sphilip return (__efx_ev_qstat_name[id]); 1054227569Sphilip} 1055227569Sphilip#endif /* EFSYS_OPT_NAMES */ 1056277886Sarybchik#endif /* EFSYS_OPT_QSTATS */ 1057227569Sphilip 1058227569Sphilip#if EFSYS_OPT_QSTATS 1059227569Sphilip void 1060227569Sphilipefx_ev_qstats_update( 1061227569Sphilip __in efx_evq_t *eep, 1062227569Sphilip __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1063227569Sphilip{ 1064227569Sphilip unsigned int id; 1065227569Sphilip 1066227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1067227569Sphilip 1068227569Sphilip for (id = 0; id < EV_NQSTATS; id++) { 1069227569Sphilip efsys_stat_t *essp = &stat[id]; 1070227569Sphilip 1071227569Sphilip EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1072227569Sphilip eep->ee_stat[id] = 0; 1073227569Sphilip } 1074227569Sphilip} 1075227569Sphilip#endif /* EFSYS_OPT_QSTATS */ 1076227569Sphilip 1077227569Sphilip void 1078227569Sphilipefx_ev_qdestroy( 1079227569Sphilip __in efx_evq_t *eep) 1080227569Sphilip{ 1081227569Sphilip efx_nic_t *enp = eep->ee_enp; 1082227569Sphilip efx_oword_t oword; 1083227569Sphilip 1084227569Sphilip EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1085227569Sphilip 1086227569Sphilip EFSYS_ASSERT(enp->en_ev_qcount != 0); 1087227569Sphilip --enp->en_ev_qcount; 1088227569Sphilip 1089227569Sphilip /* Purge event queue */ 1090227569Sphilip EFX_ZERO_OWORD(oword); 1091227569Sphilip 1092227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1093227569Sphilip eep->ee_index, &oword); 1094227569Sphilip 1095227569Sphilip if (enp->en_family != EFX_FAMILY_FALCON) { 1096227569Sphilip EFX_ZERO_OWORD(oword); 1097227569Sphilip EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, 1098227569Sphilip eep->ee_index, &oword); 1099227569Sphilip } 1100227569Sphilip 1101227569Sphilip /* Free the EVQ object */ 1102227569Sphilip EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 1103227569Sphilip} 1104227569Sphilip 1105227569Sphilip void 1106227569Sphilipefx_ev_fini( 1107227569Sphilip __in efx_nic_t *enp) 1108227569Sphilip{ 1109227569Sphilip EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1110227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 1111227569Sphilip EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 1112227569Sphilip EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 1113227569Sphilip EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 1114227569Sphilip EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 1115227569Sphilip 1116227569Sphilip enp->en_mod_flags &= ~EFX_MOD_EV; 1117227569Sphilip} 1118