efx_ev.c revision 227569
1/*- 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include "efsys.h" 27#include "efx.h" 28#include "efx_types.h" 29#include "efx_regs.h" 30#include "efx_impl.h" 31 32#if EFSYS_OPT_QSTATS 33#define EFX_EV_QSTAT_INCR(_eep, _stat) \ 34 do { \ 35 (_eep)->ee_stat[_stat]++; \ 36 _NOTE(CONSTANTCONDITION) \ 37 } while (B_FALSE) 38#else 39#define EFX_EV_QSTAT_INCR(_eep, _stat) 40#endif 41 42 __checkReturn int 43efx_ev_init( 44 __in efx_nic_t *enp) 45{ 46 efx_oword_t oword; 47 int rc; 48 49 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 50 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 51 52 if (enp->en_mod_flags & EFX_MOD_EV) { 53 rc = EINVAL; 54 goto fail1; 55 } 56 57 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 58 59 /* 60 * Program the event queue for receive and transmit queue 61 * flush events. 62 */ 63 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 64 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 65 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 66 67 enp->en_mod_flags |= EFX_MOD_EV; 68 return (0); 69 70fail1: 71 EFSYS_PROBE1(fail1, int, rc); 72 73 return (rc); 74} 75 76static __checkReturn boolean_t 77efx_ev_rx_not_ok( 78 __in efx_evq_t *eep, 79 __in efx_qword_t *eqp, 80 __in uint32_t label, 81 __in uint32_t id, 82 __inout uint16_t *flagsp) 83{ 84 boolean_t ignore = B_FALSE; 85 86 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 87 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 88 EFSYS_PROBE(tobe_disc); 89 /* Assume this is a unicast address mismatch, unless below 90 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 91 * EV_RX_PAUSE_FRM_ERR is set. 92 */ 93 (*flagsp) |= EFX_ADDR_MISMATCH; 94 } 95 96 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 97 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 98 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 99 (*flagsp) |= EFX_DISCARD; 100 101#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 102 /* Lookout for payload queue ran dry errors and ignore them. 103 * 104 * Sadly for the header/data split cases, the descriptor 105 * pointer in this event refers to the header queue and 106 * therefore cannot be easily detected as duplicate. 107 * So we drop these and rely on the receive processing seeing 108 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 109 * the partially received packet. 110 */ 111 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 112 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 113 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 114 ignore = B_TRUE; 115#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 116 } 117 118 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 119 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 120 EFSYS_PROBE(crc_err); 121 (*flagsp) &= ~EFX_ADDR_MISMATCH; 122 (*flagsp) |= EFX_DISCARD; 123 } 124 125 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 126 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 127 EFSYS_PROBE(pause_frm_err); 128 (*flagsp) &= ~EFX_ADDR_MISMATCH; 129 (*flagsp) |= EFX_DISCARD; 130 } 131 132 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 133 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 134 EFSYS_PROBE(owner_id_err); 135 (*flagsp) |= EFX_DISCARD; 136 } 137 138 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 139 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 140 EFSYS_PROBE(ipv4_err); 141 (*flagsp) &= ~EFX_CKSUM_IPV4; 142 } 143 144 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 145 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 146 EFSYS_PROBE(udp_chk_err); 147 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 148 } 149 150 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 151 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 152 153 /* 154 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 155 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 156 * condition. 157 */ 158 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 159 } 160 161 return (ignore); 162} 163 164static __checkReturn boolean_t 165efx_ev_rx( 166 __in efx_evq_t *eep, 167 __in efx_qword_t *eqp, 168 __in const efx_ev_callbacks_t *eecp, 169 __in_opt void *arg) 170{ 171 efx_nic_t *enp = eep->ee_enp; 172 uint32_t id; 173 uint32_t size; 174 uint32_t label; 175 boolean_t ok; 176#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 177 boolean_t sop; 178 boolean_t jumbo_cont; 179#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 180 uint32_t hdr_type; 181 boolean_t is_v6; 182 uint16_t flags; 183 boolean_t ignore; 184 boolean_t should_abort; 185 186 EFX_EV_QSTAT_INCR(eep, EV_RX); 187 188 /* Basic packet information */ 189 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 190 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 191 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 192 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 193 194#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) 195 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 196 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 197#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ 198 199 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 200 201 is_v6 = (enp->en_family != EFX_FAMILY_FALCON && 202 EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 203 204 /* 205 * If packet is marked as OK and packet type is TCP/IP or 206 * UDP/IP or other IP, then we can rely on the hardware checksums. 207 */ 208 switch (hdr_type) { 209 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 210 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 211 if (is_v6) { 212 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 213 flags |= EFX_PKT_IPV6; 214 } else { 215 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 216 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 217 } 218 break; 219 220 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 221 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 222 if (is_v6) { 223 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 224 flags |= EFX_PKT_IPV6; 225 } else { 226 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 227 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 228 } 229 break; 230 231 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 232 if (is_v6) { 233 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 234 flags = EFX_PKT_IPV6; 235 } else { 236 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 237 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 238 } 239 break; 240 241 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 242 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 243 flags = 0; 244 break; 245 246 default: 247 EFSYS_ASSERT(B_FALSE); 248 flags = 0; 249 break; 250 } 251 252#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT 253 /* Report scatter and header/lookahead split buffer flags */ 254 if (sop) 255 flags |= EFX_PKT_START; 256 if (jumbo_cont) 257 flags |= EFX_PKT_CONT; 258#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */ 259 260 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 261 if (!ok) { 262 ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags); 263 if (ignore) { 264 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 265 uint32_t, size, uint16_t, flags); 266 267 return (B_FALSE); 268 } 269 } 270 271 /* If we're not discarding the packet then it is ok */ 272 if (~flags & EFX_DISCARD) 273 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 274 275 /* Detect multicast packets that didn't match the filter */ 276 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 277 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 278 279 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 280 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 281 } else { 282 EFSYS_PROBE(mcast_mismatch); 283 flags |= EFX_ADDR_MISMATCH; 284 } 285 } else { 286 flags |= EFX_PKT_UNICAST; 287 } 288 289 /* 290 * The packet parser in Siena can abort parsing packets under 291 * certain error conditions, setting the PKT_NOT_PARSED bit 292 * (which clears PKT_OK). If this is set, then don't trust 293 * the PKT_TYPE field. 294 */ 295 if (enp->en_family != EFX_FAMILY_FALCON && !ok) { 296 uint32_t parse_err; 297 298 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 299 if (parse_err != 0) 300 flags |= EFX_CHECK_VLAN; 301 } 302 303 if (~flags & EFX_CHECK_VLAN) { 304 uint32_t pkt_type; 305 306 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 307 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 308 flags |= EFX_PKT_VLAN_TAGGED; 309 } 310 311 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 312 uint32_t, size, uint16_t, flags); 313 314 EFSYS_ASSERT(eecp->eec_rx != NULL); 315 should_abort = eecp->eec_rx(arg, label, id, size, flags); 316 317 return (should_abort); 318} 319 320static __checkReturn boolean_t 321efx_ev_tx( 322 __in efx_evq_t *eep, 323 __in efx_qword_t *eqp, 324 __in const efx_ev_callbacks_t *eecp, 325 __in_opt void *arg) 326{ 327 uint32_t id; 328 uint32_t label; 329 boolean_t should_abort; 330 331 EFX_EV_QSTAT_INCR(eep, EV_TX); 332 333 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 334 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 335 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 336 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 337 338 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 339 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 340 341 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 342 343 EFSYS_ASSERT(eecp->eec_tx != NULL); 344 should_abort = eecp->eec_tx(arg, label, id); 345 346 return (should_abort); 347 } 348 349 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 350 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 351 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 352 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 353 354 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 355 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 356 357 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 358 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 359 360 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 361 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 362 363 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 364 return (B_FALSE); 365} 366 367static __checkReturn boolean_t 368efx_ev_global( 369 __in efx_evq_t *eep, 370 __in efx_qword_t *eqp, 371 __in const efx_ev_callbacks_t *eecp, 372 __in_opt void *arg) 373{ 374 efx_nic_t *enp = eep->ee_enp; 375 efx_port_t *epp = &(enp->en_port); 376 boolean_t should_abort; 377 378 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 379 should_abort = B_FALSE; 380 381 /* Check for a link management event */ 382 if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) { 383 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT); 384 385 EFSYS_PROBE(xg_mgt); 386 387 epp->ep_mac_poll_needed = B_TRUE; 388 } 389 390 return (should_abort); 391} 392 393static __checkReturn boolean_t 394efx_ev_driver( 395 __in efx_evq_t *eep, 396 __in efx_qword_t *eqp, 397 __in const efx_ev_callbacks_t *eecp, 398 __in_opt void *arg) 399{ 400 boolean_t should_abort; 401 402 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 403 should_abort = B_FALSE; 404 405 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 406 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 407 uint32_t label; 408 409 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 410 411 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 412 413 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, label); 414 415 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 416 should_abort = eecp->eec_txq_flush_done(arg, label); 417 418 break; 419 } 420 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 421 uint32_t label; 422 uint32_t failed; 423 424 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 425 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 426 427 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 428 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 429 430 if (failed) { 431 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 432 433 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, label); 434 435 should_abort = eecp->eec_rxq_flush_failed(arg, label); 436 } else { 437 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 438 439 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, label); 440 441 should_abort = eecp->eec_rxq_flush_done(arg, label); 442 } 443 444 break; 445 } 446 case FSE_AZ_EVQ_INIT_DONE_EV: 447 EFSYS_ASSERT(eecp->eec_initialized != NULL); 448 should_abort = eecp->eec_initialized(arg); 449 450 break; 451 452 case FSE_AZ_EVQ_NOT_EN_EV: 453 EFSYS_PROBE(evq_not_en); 454 break; 455 456 case FSE_AZ_SRM_UPD_DONE_EV: { 457 uint32_t code; 458 459 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 460 461 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 462 463 EFSYS_ASSERT(eecp->eec_sram != NULL); 464 should_abort = eecp->eec_sram(arg, code); 465 466 break; 467 } 468 case FSE_AZ_WAKE_UP_EV: { 469 uint32_t id; 470 471 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 472 473 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 474 should_abort = eecp->eec_wake_up(arg, id); 475 476 break; 477 } 478 case FSE_AZ_TX_PKT_NON_TCP_UDP: 479 EFSYS_PROBE(tx_pkt_non_tcp_udp); 480 break; 481 482 case FSE_AZ_TIMER_EV: { 483 uint32_t id; 484 485 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 486 487 EFSYS_ASSERT(eecp->eec_timer != NULL); 488 should_abort = eecp->eec_timer(arg, id); 489 490 break; 491 } 492 case FSE_AZ_RX_DSC_ERROR_EV: 493 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 494 495 EFSYS_PROBE(rx_dsc_error); 496 497 EFSYS_ASSERT(eecp->eec_exception != NULL); 498 should_abort = eecp->eec_exception(arg, 499 EFX_EXCEPTION_RX_DSC_ERROR, 0); 500 501 break; 502 503 case FSE_AZ_TX_DSC_ERROR_EV: 504 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 505 506 EFSYS_PROBE(tx_dsc_error); 507 508 EFSYS_ASSERT(eecp->eec_exception != NULL); 509 should_abort = eecp->eec_exception(arg, 510 EFX_EXCEPTION_TX_DSC_ERROR, 0); 511 512 break; 513 514 default: 515 break; 516 } 517 518 return (should_abort); 519} 520 521static __checkReturn boolean_t 522efx_ev_drv_gen( 523 __in efx_evq_t *eep, 524 __in efx_qword_t *eqp, 525 __in const efx_ev_callbacks_t *eecp, 526 __in_opt void *arg) 527{ 528 uint32_t data; 529 boolean_t should_abort; 530 531 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 532 533 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 534 if (data >= ((uint32_t)1 << 16)) { 535 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 536 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 537 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 538 return (B_TRUE); 539 } 540 541 EFSYS_ASSERT(eecp->eec_software != NULL); 542 should_abort = eecp->eec_software(arg, (uint16_t)data); 543 544 return (should_abort); 545} 546 547#if EFSYS_OPT_MCDI 548 549static __checkReturn boolean_t 550efx_ev_mcdi( 551 __in efx_evq_t *eep, 552 __in efx_qword_t *eqp, 553 __in const efx_ev_callbacks_t *eecp, 554 __in_opt void *arg) 555{ 556 efx_nic_t *enp = eep->ee_enp; 557 unsigned code; 558 boolean_t should_abort = B_FALSE; 559 560 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 561 562 if (enp->en_family != EFX_FAMILY_SIENA) 563 goto out; 564 565 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 566 567 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 568 switch (code) { 569 case MCDI_EVENT_CODE_BADSSERT: 570 efx_mcdi_ev_death(enp, EINTR); 571 break; 572 573 case MCDI_EVENT_CODE_CMDDONE: 574 efx_mcdi_ev_cpl(enp, 575 MCDI_EV_FIELD(*eqp, CMDDONE_SEQ), 576 MCDI_EV_FIELD(*eqp, CMDDONE_DATALEN), 577 MCDI_EV_FIELD(*eqp, CMDDONE_ERRNO)); 578 break; 579 580 case MCDI_EVENT_CODE_LINKCHANGE: { 581 efx_link_mode_t link_mode; 582 583 siena_phy_link_ev(enp, eqp, &link_mode); 584 should_abort = eecp->eec_link_change(arg, link_mode); 585 break; 586 } 587 case MCDI_EVENT_CODE_SENSOREVT: { 588#if EFSYS_OPT_MON_STATS 589 efx_mon_stat_t id; 590 efx_mon_stat_value_t value; 591 int rc; 592 593 if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0) 594 should_abort = eecp->eec_monitor(arg, id, value); 595 else if (rc == ENOTSUP) { 596 should_abort = eecp->eec_exception(arg, 597 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 598 MCDI_EV_FIELD(eqp, DATA)); 599 } else 600 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 601#else 602 should_abort = B_FALSE; 603#endif 604 break; 605 } 606 case MCDI_EVENT_CODE_SCHEDERR: 607 /* Informational only */ 608 break; 609 610 case MCDI_EVENT_CODE_REBOOT: 611 efx_mcdi_ev_death(enp, EIO); 612 break; 613 614 case MCDI_EVENT_CODE_MAC_STATS_DMA: 615#if EFSYS_OPT_MAC_STATS 616 if (eecp->eec_mac_stats != NULL) { 617 eecp->eec_mac_stats(arg, 618 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 619 } 620#endif 621 break; 622 623 case MCDI_EVENT_CODE_FWALERT: { 624 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 625 626 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 627 should_abort = eecp->eec_exception(arg, 628 EFX_EXCEPTION_FWALERT_SRAM, 629 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 630 else 631 should_abort = eecp->eec_exception(arg, 632 EFX_EXCEPTION_UNKNOWN_FWALERT, 633 MCDI_EV_FIELD(eqp, DATA)); 634 break; 635 } 636 637 default: 638 EFSYS_PROBE1(mc_pcol_error, int, code); 639 break; 640 } 641 642out: 643 return (should_abort); 644} 645 646#endif /* EFSYS_OPT_SIENA */ 647 648 __checkReturn int 649efx_ev_qprime( 650 __in efx_evq_t *eep, 651 __in unsigned int count) 652{ 653 efx_nic_t *enp = eep->ee_enp; 654 uint32_t rptr; 655 efx_dword_t dword; 656 int rc; 657 658 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 659 660 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 661 rc = EINVAL; 662 goto fail1; 663 } 664 665 rptr = count & eep->ee_mask; 666 667 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 668 669 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 670 &dword, B_FALSE); 671 672 return (0); 673 674fail1: 675 EFSYS_PROBE1(fail1, int, rc); 676 677 return (rc); 678} 679 680 __checkReturn boolean_t 681efx_ev_qpending( 682 __in efx_evq_t *eep, 683 __in unsigned int count) 684{ 685 size_t offset; 686 efx_qword_t qword; 687 688 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 689 690 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 691 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 692 693 return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff && 694 EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff); 695} 696 697#if EFSYS_OPT_EV_PREFETCH 698 699 void 700efx_ev_qprefetch( 701 __in efx_evq_t *eep, 702 __in unsigned int count) 703{ 704 unsigned int offset; 705 706 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 707 708 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 709 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 710} 711 712#endif /* EFSYS_OPT_EV_PREFETCH */ 713 714#define EFX_EV_BATCH 8 715 716#define EFX_EV_PRESENT(_qword) \ 717 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 718 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 719 720 void 721efx_ev_qpoll( 722 __in efx_evq_t *eep, 723 __inout unsigned int *countp, 724 __in const efx_ev_callbacks_t *eecp, 725 __in_opt void *arg) 726{ 727 efx_qword_t ev[EFX_EV_BATCH]; 728 unsigned int batch; 729 unsigned int total; 730 unsigned int count; 731 unsigned int index; 732 size_t offset; 733 734 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 735 EFSYS_ASSERT(countp != NULL); 736 EFSYS_ASSERT(eecp != NULL); 737 738 count = *countp; 739 do { 740 /* Read up until the end of the batch period */ 741 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 742 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 743 for (total = 0; total < batch; ++total) { 744 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 745 746 if (!EFX_EV_PRESENT(ev[total])) 747 break; 748 749 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 750 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 751 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 752 753 offset += sizeof (efx_qword_t); 754 } 755 756#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 757 /* 758 * Prefetch the next batch when we get within PREFETCH_PERIOD 759 * of a completed batch. If the batch is smaller, then prefetch 760 * immediately. 761 */ 762 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 763 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 764#endif /* EFSYS_OPT_EV_PREFETCH */ 765 766 /* Process the batch of events */ 767 for (index = 0; index < total; ++index) { 768 boolean_t should_abort; 769 uint32_t code; 770 efx_ev_handler_t handler; 771 772#if EFSYS_OPT_EV_PREFETCH 773 /* Prefetch if we've now reached the batch period */ 774 if (total == batch && 775 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 776 offset = (count + batch) & eep->ee_mask; 777 offset *= sizeof (efx_qword_t); 778 779 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 780 } 781#endif /* EFSYS_OPT_EV_PREFETCH */ 782 783 EFX_EV_QSTAT_INCR(eep, EV_ALL); 784 785 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 786 handler = eep->ee_handler[code]; 787 EFSYS_ASSERT(handler != NULL); 788 should_abort = handler(eep, &(ev[index]), eecp, arg); 789 if (should_abort) { 790 /* Ignore subsequent events */ 791 total = index + 1; 792 break; 793 } 794 } 795 796 /* 797 * Now that the hardware has most likely moved onto dma'ing 798 * into the next cache line, clear the processed events. Take 799 * care to only clear out events that we've processed 800 */ 801 EFX_SET_QWORD(ev[0]); 802 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 803 for (index = 0; index < total; ++index) { 804 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 805 offset += sizeof (efx_qword_t); 806 } 807 808 count += total; 809 810 } while (total == batch); 811 812 *countp = count; 813} 814 815 void 816efx_ev_qpost( 817 __in efx_evq_t *eep, 818 __in uint16_t data) 819{ 820 efx_nic_t *enp = eep->ee_enp; 821 efx_qword_t ev; 822 efx_oword_t oword; 823 824 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 825 826 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 827 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 828 829 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 830 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 831 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 832 833 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 834} 835 836 __checkReturn int 837efx_ev_qmoderate( 838 __in efx_evq_t *eep, 839 __in unsigned int us) 840{ 841 efx_nic_t *enp = eep->ee_enp; 842 unsigned int locked; 843 efx_dword_t dword; 844 int rc; 845 846 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 847 848 if (us > enp->en_nic_cfg.enc_evq_moderation_max) { 849 rc = EINVAL; 850 goto fail1; 851 } 852 853 /* If the value is zero then disable the timer */ 854 if (us == 0) { 855 if (enp->en_family == EFX_FAMILY_FALCON) 856 EFX_POPULATE_DWORD_2(dword, 857 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS, 858 FRF_AB_TC_TIMER_VAL, 0); 859 else 860 EFX_POPULATE_DWORD_2(dword, 861 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 862 FRF_CZ_TC_TIMER_VAL, 0); 863 } else { 864 uint32_t timer_val; 865 866 /* Calculate the timer value in quanta */ 867 us -= (us % EFX_EV_TIMER_QUANTUM); 868 if (us < EFX_EV_TIMER_QUANTUM) 869 us = EFX_EV_TIMER_QUANTUM; 870 871 timer_val = us / EFX_EV_TIMER_QUANTUM; 872 873 /* Moderation value is base 0 so we need to deduct 1 */ 874 if (enp->en_family == EFX_FAMILY_FALCON) 875 EFX_POPULATE_DWORD_2(dword, 876 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF, 877 FRF_AB_TIMER_VAL, timer_val - 1); 878 else 879 EFX_POPULATE_DWORD_2(dword, 880 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 881 FRF_CZ_TC_TIMER_VAL, timer_val - 1); 882 } 883 884 locked = (eep->ee_index == 0) ? 1 : 0; 885 886 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 887 eep->ee_index, &dword, locked); 888 889 return (0); 890 891fail1: 892 EFSYS_PROBE1(fail1, int, rc); 893 894 return (rc); 895} 896 897 __checkReturn int 898efx_ev_qcreate( 899 __in efx_nic_t *enp, 900 __in unsigned int index, 901 __in efsys_mem_t *esmp, 902 __in size_t n, 903 __in uint32_t id, 904 __deref_out efx_evq_t **eepp) 905{ 906 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 907 uint32_t size; 908 efx_evq_t *eep; 909 efx_oword_t oword; 910 int rc; 911 912 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 913 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 914 915 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); 916 917 if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) { 918 rc = EINVAL; 919 goto fail1; 920 } 921 if (index >= encp->enc_evq_limit) { 922 rc = EINVAL; 923 goto fail2; 924 } 925#if EFSYS_OPT_RX_SCALE 926 if (enp->en_intr.ei_type == EFX_INTR_LINE && 927 index >= EFX_MAXRSS_LEGACY) { 928 rc = EINVAL; 929 goto fail3; 930 } 931#endif 932 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 933 size++) 934 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS)) 935 break; 936 if (id + (1 << size) >= encp->enc_buftbl_limit) { 937 rc = EINVAL; 938 goto fail4; 939 } 940 941 /* Allocate an EVQ object */ 942 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 943 if (eep == NULL) { 944 rc = ENOMEM; 945 goto fail5; 946 } 947 948 eep->ee_magic = EFX_EVQ_MAGIC; 949 eep->ee_enp = enp; 950 eep->ee_index = index; 951 eep->ee_mask = n - 1; 952 eep->ee_esmp = esmp; 953 954 /* Set up the handler table */ 955 eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx; 956 eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx; 957 eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver; 958 eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global; 959 eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen; 960#if EFSYS_OPT_MCDI 961 eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi; 962#endif /* EFSYS_OPT_SIENA */ 963 964 /* Set up the new event queue */ 965 if (enp->en_family != EFX_FAMILY_FALCON) { 966 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1); 967 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword); 968 } 969 970 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 971 FRF_AZ_EVQ_BUF_BASE_ID, id); 972 973 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword); 974 975 enp->en_ev_qcount++; 976 *eepp = eep; 977 return (0); 978 979fail5: 980 EFSYS_PROBE(fail5); 981fail4: 982 EFSYS_PROBE(fail4); 983#if EFSYS_OPT_RX_SCALE 984fail3: 985 EFSYS_PROBE(fail3); 986#endif 987fail2: 988 EFSYS_PROBE(fail2); 989fail1: 990 EFSYS_PROBE1(fail1, int, rc); 991 992 return (rc); 993} 994 995#if EFSYS_OPT_NAMES 996/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */ 997static const char __cs * __cs __efx_ev_qstat_name[] = { 998 "all", 999 "rx", 1000 "rx_ok", 1001 "rx_recovery", 1002 "rx_frm_trunc", 1003 "rx_tobe_disc", 1004 "rx_pause_frm_err", 1005 "rx_buf_owner_id_err", 1006 "rx_ipv4_hdr_chksum_err", 1007 "rx_tcp_udp_chksum_err", 1008 "rx_eth_crc_err", 1009 "rx_ip_frag_err", 1010 "rx_mcast_pkt", 1011 "rx_mcast_hash_match", 1012 "rx_tcp_ipv4", 1013 "rx_tcp_ipv6", 1014 "rx_udp_ipv4", 1015 "rx_udp_ipv6", 1016 "rx_other_ipv4", 1017 "rx_other_ipv6", 1018 "rx_non_ip", 1019 "rx_overrun", 1020 "tx", 1021 "tx_wq_ff_full", 1022 "tx_pkt_err", 1023 "tx_pkt_too_big", 1024 "tx_unexpected", 1025 "global", 1026 "global_phy", 1027 "global_mnt", 1028 "global_rx_recovery", 1029 "driver", 1030 "driver_srm_upd_done", 1031 "driver_tx_descq_fls_done", 1032 "driver_rx_descq_fls_done", 1033 "driver_rx_descq_fls_failed", 1034 "driver_rx_dsc_error", 1035 "driver_tx_dsc_error", 1036 "drv_gen", 1037 "mcdi_response", 1038}; 1039/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1040 1041 const char __cs * 1042efx_ev_qstat_name( 1043 __in efx_nic_t *enp, 1044 __in unsigned int id) 1045{ 1046 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1047 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1048 1049 return (__efx_ev_qstat_name[id]); 1050} 1051#endif /* EFSYS_OPT_NAMES */ 1052 1053#if EFSYS_OPT_QSTATS 1054 void 1055efx_ev_qstats_update( 1056 __in efx_evq_t *eep, 1057 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1058{ 1059 unsigned int id; 1060 1061 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1062 1063 for (id = 0; id < EV_NQSTATS; id++) { 1064 efsys_stat_t *essp = &stat[id]; 1065 1066 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1067 eep->ee_stat[id] = 0; 1068 } 1069} 1070#endif /* EFSYS_OPT_QSTATS */ 1071 1072 void 1073efx_ev_qdestroy( 1074 __in efx_evq_t *eep) 1075{ 1076 efx_nic_t *enp = eep->ee_enp; 1077 efx_oword_t oword; 1078 1079 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 1080 1081 EFSYS_ASSERT(enp->en_ev_qcount != 0); 1082 --enp->en_ev_qcount; 1083 1084 /* Purge event queue */ 1085 EFX_ZERO_OWORD(oword); 1086 1087 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1088 eep->ee_index, &oword); 1089 1090 if (enp->en_family != EFX_FAMILY_FALCON) { 1091 EFX_ZERO_OWORD(oword); 1092 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, 1093 eep->ee_index, &oword); 1094 } 1095 1096 /* Free the EVQ object */ 1097 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 1098} 1099 1100 void 1101efx_ev_fini( 1102 __in efx_nic_t *enp) 1103{ 1104 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1105 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 1106 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 1107 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 1108 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 1109 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 1110 1111 enp->en_mod_flags &= ~EFX_MOD_EV; 1112} 1113