sdhci_pci.c revision 318496
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 318496 2017-05-18 21:00:50Z marius $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/kernel.h> 33#include <sys/lock.h> 34#include <sys/module.h> 35#include <sys/mutex.h> 36#include <sys/resource.h> 37#include <sys/rman.h> 38#include <sys/sysctl.h> 39#include <sys/taskqueue.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46 47#include <dev/mmc/bridge.h> 48 49#include <dev/sdhci/sdhci.h> 50 51#include "mmcbr_if.h" 52#include "sdhci_if.h" 53 54/* 55 * PCI registers 56 */ 57#define PCI_SDHCI_IFPIO 0x00 58#define PCI_SDHCI_IFDMA 0x01 59#define PCI_SDHCI_IFVENDOR 0x02 60 61#define PCI_SLOT_INFO 0x40 /* 8 bits */ 62#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64 65/* 66 * RICOH specific PCI registers 67 */ 68#define SDHC_PCI_MODE_KEY 0xf9 69#define SDHC_PCI_MODE 0x150 70#define SDHC_PCI_MODE_SD20 0x10 71#define SDHC_PCI_BASE_FREQ_KEY 0xfc 72#define SDHC_PCI_BASE_FREQ 0xe1 73 74static const struct sdhci_device { 75 uint32_t model; 76 uint16_t subvendor; 77 const char *desc; 78 u_int quirks; 79} sdhci_devices[] = { 80 { 0x08221180, 0xffff, "RICOH R5C822 SD", 81 SDHCI_QUIRK_FORCE_DMA }, 82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83 SDHCI_QUIRK_FORCE_DMA | 84 SDHCI_QUIRK_LOWER_FREQUENCY }, 85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88 SDHCI_QUIRK_FORCE_DMA }, 89 { 0x05501524, 0xffff, "ENE CB712 SD", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x05511524, 0xffff, "ENE CB712 SD 2", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07501524, 0xffff, "ENE CB714 SD", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07511524, 0xffff, "ENE CB714 SD 2", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x410111ab, 0xffff, "Marvell CaFe SD", 100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102 SDHCI_QUIRK_32BIT_DMA_SIZE | 103 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 108 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 109 SDHCI_QUIRK_WAIT_WHILE_BUSY | 110 SDHCI_QUIRK_MMC_DDR52 | 111 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 112 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 113 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 114 SDHCI_QUIRK_WAIT_WHILE_BUSY | 115 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 116 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 119 SDHCI_QUIRK_WAIT_WHILE_BUSY | 120 SDHCI_QUIRK_MMC_DDR52 | 121 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 122 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 123 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 124 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 125 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 126 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 127 SDHCI_QUIRK_WAIT_WHILE_BUSY | 128 SDHCI_QUIRK_MMC_DDR52 | 129 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 130 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 131 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 132 SDHCI_QUIRK_WAIT_WHILE_BUSY | 133 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 134 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 135 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 136 SDHCI_QUIRK_WAIT_WHILE_BUSY | 137 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 138 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 139 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 140 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 141 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 142 SDHCI_QUIRK_WAIT_WHILE_BUSY | 143 SDHCI_QUIRK_MMC_DDR52 | 144 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 145 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 146 { 0, 0xffff, NULL, 147 0 } 148}; 149 150struct sdhci_pci_softc { 151 u_int quirks; /* Chip specific quirks */ 152 struct resource *irq_res; /* IRQ resource */ 153 void *intrhand; /* Interrupt handle */ 154 155 int num_slots; /* Number of slots on this controller */ 156 struct sdhci_slot slots[6]; 157 struct resource *mem_res[6]; /* Memory resource */ 158 uint8_t cfg_freq; /* Saved frequency */ 159 uint8_t cfg_mode; /* Saved mode */ 160}; 161 162static int sdhci_enable_msi = 1; 163SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 164 0, "Enable MSI interrupts"); 165 166static uint8_t 167sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 168{ 169 struct sdhci_pci_softc *sc = device_get_softc(dev); 170 171 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 172 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 173 return bus_read_1(sc->mem_res[slot->num], off); 174} 175 176static void 177sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 178 bus_size_t off, uint8_t val) 179{ 180 struct sdhci_pci_softc *sc = device_get_softc(dev); 181 182 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 183 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 184 bus_write_1(sc->mem_res[slot->num], off, val); 185} 186 187static uint16_t 188sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 189{ 190 struct sdhci_pci_softc *sc = device_get_softc(dev); 191 192 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 193 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 194 return bus_read_2(sc->mem_res[slot->num], off); 195} 196 197static void 198sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 199 bus_size_t off, uint16_t val) 200{ 201 struct sdhci_pci_softc *sc = device_get_softc(dev); 202 203 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 204 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 205 bus_write_2(sc->mem_res[slot->num], off, val); 206} 207 208static uint32_t 209sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 210{ 211 struct sdhci_pci_softc *sc = device_get_softc(dev); 212 213 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 214 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 215 return bus_read_4(sc->mem_res[slot->num], off); 216} 217 218static void 219sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 220 bus_size_t off, uint32_t val) 221{ 222 struct sdhci_pci_softc *sc = device_get_softc(dev); 223 224 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 225 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 226 bus_write_4(sc->mem_res[slot->num], off, val); 227} 228 229static void 230sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 231 bus_size_t off, uint32_t *data, bus_size_t count) 232{ 233 struct sdhci_pci_softc *sc = device_get_softc(dev); 234 235 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 236} 237 238static void 239sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 240 bus_size_t off, uint32_t *data, bus_size_t count) 241{ 242 struct sdhci_pci_softc *sc = device_get_softc(dev); 243 244 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 245} 246 247static void sdhci_pci_intr(void *arg); 248 249static void 250sdhci_lower_frequency(device_t dev) 251{ 252 struct sdhci_pci_softc *sc = device_get_softc(dev); 253 254 /* 255 * Enable SD2.0 mode. 256 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 257 */ 258 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 259 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 260 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 261 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 262 263 /* 264 * Some SD/MMC cards don't work with the default base 265 * clock frequency of 200 MHz. Lower it to 50 MHz. 266 */ 267 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 268 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 269 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 270 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 271} 272 273static void 274sdhci_restore_frequency(device_t dev) 275{ 276 struct sdhci_pci_softc *sc = device_get_softc(dev); 277 278 /* Restore mode. */ 279 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 280 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 281 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 282 283 /* Restore frequency. */ 284 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 285 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 286 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 287} 288 289static int 290sdhci_pci_probe(device_t dev) 291{ 292 uint32_t model; 293 uint16_t subvendor; 294 uint8_t class, subclass; 295 int i, result; 296 297 model = (uint32_t)pci_get_device(dev) << 16; 298 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 299 subvendor = pci_get_subvendor(dev); 300 class = pci_get_class(dev); 301 subclass = pci_get_subclass(dev); 302 303 result = ENXIO; 304 for (i = 0; sdhci_devices[i].model != 0; i++) { 305 if (sdhci_devices[i].model == model && 306 (sdhci_devices[i].subvendor == 0xffff || 307 sdhci_devices[i].subvendor == subvendor)) { 308 device_set_desc(dev, sdhci_devices[i].desc); 309 result = BUS_PROBE_DEFAULT; 310 break; 311 } 312 } 313 if (result == ENXIO && class == PCIC_BASEPERIPH && 314 subclass == PCIS_BASEPERIPH_SDHC) { 315 device_set_desc(dev, "Generic SD HCI"); 316 result = BUS_PROBE_GENERIC; 317 } 318 319 return (result); 320} 321 322static int 323sdhci_pci_attach(device_t dev) 324{ 325 struct sdhci_pci_softc *sc = device_get_softc(dev); 326 struct sdhci_slot *slot; 327 uint32_t model; 328 uint16_t subvendor; 329 int bar, err, rid, slots, i; 330 331 model = (uint32_t)pci_get_device(dev) << 16; 332 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 333 subvendor = pci_get_subvendor(dev); 334 /* Apply chip specific quirks. */ 335 for (i = 0; sdhci_devices[i].model != 0; i++) { 336 if (sdhci_devices[i].model == model && 337 (sdhci_devices[i].subvendor == 0xffff || 338 sdhci_devices[i].subvendor == subvendor)) { 339 sc->quirks = sdhci_devices[i].quirks; 340 break; 341 } 342 } 343 sc->quirks &= ~sdhci_quirk_clear; 344 sc->quirks |= sdhci_quirk_set; 345 346 /* Some controllers need to be bumped into the right mode. */ 347 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 348 sdhci_lower_frequency(dev); 349 /* Read slots info from PCI registers. */ 350 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 351 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 352 slots = PCI_SLOT_INFO_SLOTS(slots); 353 if (slots > 6 || bar > 5) { 354 device_printf(dev, "Incorrect slots information (%d, %d).\n", 355 slots, bar); 356 return (EINVAL); 357 } 358 /* Allocate IRQ. */ 359 i = 1; 360 rid = 0; 361 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 362 rid = 1; 363 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 364 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 365 if (sc->irq_res == NULL) { 366 device_printf(dev, "Can't allocate IRQ\n"); 367 pci_release_msi(dev); 368 return (ENOMEM); 369 } 370 /* Scan all slots. */ 371 for (i = 0; i < slots; i++) { 372 slot = &sc->slots[sc->num_slots]; 373 374 /* Allocate memory. */ 375 rid = PCIR_BAR(bar + i); 376 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 377 &rid, RF_ACTIVE); 378 if (sc->mem_res[i] == NULL) { 379 device_printf(dev, 380 "Can't allocate memory for slot %d\n", i); 381 continue; 382 } 383 384 slot->quirks = sc->quirks; 385 386 if (sdhci_init_slot(dev, slot, i) != 0) 387 continue; 388 389 sc->num_slots++; 390 } 391 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 392 /* Activate the interrupt */ 393 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 394 NULL, sdhci_pci_intr, sc, &sc->intrhand); 395 if (err) 396 device_printf(dev, "Can't setup IRQ\n"); 397 pci_enable_busmaster(dev); 398 /* Process cards detection. */ 399 for (i = 0; i < sc->num_slots; i++) 400 sdhci_start_slot(&sc->slots[i]); 401 402 return (0); 403} 404 405static int 406sdhci_pci_detach(device_t dev) 407{ 408 struct sdhci_pci_softc *sc = device_get_softc(dev); 409 int i; 410 411 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 412 bus_release_resource(dev, SYS_RES_IRQ, 413 rman_get_rid(sc->irq_res), sc->irq_res); 414 pci_release_msi(dev); 415 416 for (i = 0; i < sc->num_slots; i++) { 417 sdhci_cleanup_slot(&sc->slots[i]); 418 bus_release_resource(dev, SYS_RES_MEMORY, 419 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 420 } 421 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 422 sdhci_restore_frequency(dev); 423 return (0); 424} 425 426static int 427sdhci_pci_shutdown(device_t dev) 428{ 429 struct sdhci_pci_softc *sc = device_get_softc(dev); 430 431 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 432 sdhci_restore_frequency(dev); 433 return (0); 434} 435 436static int 437sdhci_pci_suspend(device_t dev) 438{ 439 struct sdhci_pci_softc *sc = device_get_softc(dev); 440 int i, err; 441 442 err = bus_generic_suspend(dev); 443 if (err) 444 return (err); 445 for (i = 0; i < sc->num_slots; i++) 446 sdhci_generic_suspend(&sc->slots[i]); 447 return (0); 448} 449 450static int 451sdhci_pci_resume(device_t dev) 452{ 453 struct sdhci_pci_softc *sc = device_get_softc(dev); 454 int i, err; 455 456 for (i = 0; i < sc->num_slots; i++) 457 sdhci_generic_resume(&sc->slots[i]); 458 err = bus_generic_resume(dev); 459 if (err) 460 return (err); 461 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 462 sdhci_lower_frequency(dev); 463 return (0); 464} 465 466static void 467sdhci_pci_intr(void *arg) 468{ 469 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 470 int i; 471 472 for (i = 0; i < sc->num_slots; i++) 473 sdhci_generic_intr(&sc->slots[i]); 474} 475 476static device_method_t sdhci_methods[] = { 477 /* device_if */ 478 DEVMETHOD(device_probe, sdhci_pci_probe), 479 DEVMETHOD(device_attach, sdhci_pci_attach), 480 DEVMETHOD(device_detach, sdhci_pci_detach), 481 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 482 DEVMETHOD(device_suspend, sdhci_pci_suspend), 483 DEVMETHOD(device_resume, sdhci_pci_resume), 484 485 /* Bus interface */ 486 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 487 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 488 489 /* mmcbr_if */ 490 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 491 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 492 DEVMETHOD(mmcbr_request, sdhci_generic_request), 493 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 494 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 495 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 496 497 /* SDHCI accessors */ 498 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 499 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 500 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 501 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 502 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 503 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 504 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 505 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 506 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 507 508 DEVMETHOD_END 509}; 510 511static driver_t sdhci_pci_driver = { 512 "sdhci_pci", 513 sdhci_methods, 514 sizeof(struct sdhci_pci_softc), 515}; 516static devclass_t sdhci_pci_devclass; 517 518DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 519 NULL); 520MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 521MMC_DECLARE_BRIDGE(sdhci_pci); 522