sdhci_pci.c revision 318197
10SN/A/*- 23365Sksrini * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 30SN/A * All rights reserved. 40SN/A * 50SN/A * Redistribution and use in source and binary forms, with or without 60SN/A * modification, are permitted provided that the following conditions 7553SN/A * are met: 80SN/A * 1. Redistributions of source code must retain the above copyright 9553SN/A * notice, this list of conditions and the following disclaimer. 100SN/A * 2. Redistributions in binary form must reproduce the above copyright 110SN/A * notice, this list of conditions and the following disclaimer in the 120SN/A * documentation and/or other materials provided with the distribution. 130SN/A * 140SN/A * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 150SN/A * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 160SN/A * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 170SN/A * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 180SN/A * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 190SN/A * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 200SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21553SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22553SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23553SN/A * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 240SN/A */ 250SN/A 263233Sksrini#include <sys/cdefs.h> 273233Sksrini__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 318197 2017-05-11 20:55:11Z marius $"); 280SN/A 291410SN/A#include <sys/param.h> 301410SN/A#include <sys/systm.h> 312820SN/A#include <sys/bus.h> 320SN/A#include <sys/kernel.h> 333233Sksrini#include <sys/lock.h> 343233Sksrini#include <sys/module.h> 353233Sksrini#include <sys/mutex.h> 363827Smcimadamore#include <sys/resource.h> 373233Sksrini#include <sys/rman.h> 383233Sksrini#include <sys/sysctl.h> 393233Sksrini#include <sys/taskqueue.h> 403233Sksrini 413233Sksrini#include <dev/pci/pcireg.h> 423233Sksrini#include <dev/pci/pcivar.h> 433233Sksrini 440SN/A#include <machine/bus.h> 451410SN/A#include <machine/resource.h> 461412SN/A 471410SN/A#include <dev/mmc/bridge.h> 481356SN/A 490SN/A#include <dev/sdhci/sdhci.h> 500SN/A 510SN/A#include "mmcbr_if.h" 523691Sksrini#include "sdhci_if.h" 533691Sksrini 540SN/A/* 551358SN/A * PCI registers 561358SN/A */ 571358SN/A#define PCI_SDHCI_IFPIO 0x00 581358SN/A#define PCI_SDHCI_IFDMA 0x01 591358SN/A#define PCI_SDHCI_IFVENDOR 0x02 600SN/A 610SN/A#define PCI_SLOT_INFO 0x40 /* 8 bits */ 620SN/A#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 630SN/A#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 643233Sksrini 653233Sksrini/* 660SN/A * RICOH specific PCI registers 670SN/A */ 680SN/A#define SDHC_PCI_MODE_KEY 0xf9 690SN/A#define SDHC_PCI_MODE 0x150 700SN/A#define SDHC_PCI_MODE_SD20 0x10 710SN/A#define SDHC_PCI_BASE_FREQ_KEY 0xfc 720SN/A#define SDHC_PCI_BASE_FREQ 0xe1 730SN/A 740SN/Astatic const struct sdhci_device { 75892SN/A uint32_t model; 760SN/A uint16_t subvendor; 773827Smcimadamore const char *desc; 783233Sksrini u_int quirks; 793233Sksrini} sdhci_devices[] = { 803233Sksrini { 0x08221180, 0xffff, "RICOH R5C822 SD", 813233Sksrini SDHCI_QUIRK_FORCE_DMA }, 823827Smcimadamore { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 830SN/A SDHCI_QUIRK_FORCE_DMA | 843233Sksrini SDHCI_QUIRK_LOWER_FREQUENCY }, 853233Sksrini { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 863233Sksrini SDHCI_QUIRK_LOWER_FREQUENCY }, 873233Sksrini { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 883233Sksrini SDHCI_QUIRK_FORCE_DMA }, 893233Sksrini { 0x05501524, 0xffff, "ENE CB712 SD", 903233Sksrini SDHCI_QUIRK_BROKEN_TIMINGS }, 913233Sksrini { 0x05511524, 0xffff, "ENE CB712 SD 2", 923233Sksrini SDHCI_QUIRK_BROKEN_TIMINGS }, 933233Sksrini { 0x07501524, 0xffff, "ENE CB714 SD", 943233Sksrini SDHCI_QUIRK_RESET_ON_IOS | 953233Sksrini SDHCI_QUIRK_BROKEN_TIMINGS }, 963233Sksrini { 0x07511524, 0xffff, "ENE CB714 SD 2", 973233Sksrini SDHCI_QUIRK_RESET_ON_IOS | 983233Sksrini SDHCI_QUIRK_BROKEN_TIMINGS }, 993233Sksrini { 0x410111ab, 0xffff, "Marvell CaFe SD", 1003233Sksrini SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 1013233Sksrini { 0x2381197B, 0xffff, "JMicron JMB38X SD", 1023233Sksrini SDHCI_QUIRK_32BIT_DMA_SIZE | 1033233Sksrini SDHCI_QUIRK_RESET_AFTER_REQUEST }, 1043233Sksrini { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 1053233Sksrini SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 1063233Sksrini { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 1073233Sksrini SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 1083233Sksrini SDHCI_QUIRK_INTEL_POWER_UP_RESET | 1093233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1103233Sksrini { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 1113233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1123233Sksrini { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 1133233Sksrini SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 1143233Sksrini SDHCI_QUIRK_INTEL_POWER_UP_RESET | 1153233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1163233Sksrini { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 1173233Sksrini SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 1183233Sksrini SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 1193233Sksrini SDHCI_QUIRK_INTEL_POWER_UP_RESET | 1203233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1213233Sksrini { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 1223233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1233233Sksrini { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 1243233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1253233Sksrini { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 1263233Sksrini SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 1273233Sksrini SDHCI_QUIRK_INTEL_POWER_UP_RESET | 1283233Sksrini SDHCI_QUIRK_WAIT_WHILE_BUSY }, 1293233Sksrini { 0, 0xffff, NULL, 1303233Sksrini 0 } 1310SN/A}; 1320SN/A 133583SN/Astruct sdhci_pci_softc { 1340SN/A u_int quirks; /* Chip specific quirks */ 1351410SN/A struct resource *irq_res; /* IRQ resource */ 1361410SN/A void *intrhand; /* Interrupt handle */ 1371410SN/A 1380SN/A int num_slots; /* Number of slots on this controller */ 1390SN/A struct sdhci_slot slots[6]; 1400SN/A struct resource *mem_res[6]; /* Memory resource */ 1413233Sksrini uint8_t cfg_freq; /* Saved frequency */ 1420SN/A uint8_t cfg_mode; /* Saved mode */ 1430SN/A}; 1440SN/A 1450SN/Astatic int sdhci_enable_msi = 1; 1460SN/ASYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 1470SN/A 0, "Enable MSI interrupts"); 1483233Sksrini 1493233Sksrinistatic uint8_t 1500SN/Asdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 1510SN/A{ 1520SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 1530SN/A 1540SN/A bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 1553688Sjjg BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1563688Sjjg return bus_read_1(sc->mem_res[slot->num], off); 1570SN/A} 158197SN/A 1593233Sksrinistatic void 1603233Sksrinisdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 1611410SN/A bus_size_t off, uint8_t val) 1623233Sksrini{ 1632820SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 1641410SN/A 1650SN/A bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 1663233Sksrini BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1673233Sksrini bus_write_1(sc->mem_res[slot->num], off, val); 1680SN/A} 1690SN/A 1701410SN/Astatic uint16_t 1711410SN/Asdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 1720SN/A{ 1730SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 1740SN/A 1750SN/A bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 1760SN/A BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1770SN/A return bus_read_2(sc->mem_res[slot->num], off); 1781410SN/A} 1790SN/A 1801410SN/Astatic void 1811410SN/Asdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 1820SN/A bus_size_t off, uint16_t val) 1830SN/A{ 1843233Sksrini struct sdhci_pci_softc *sc = device_get_softc(dev); 1853896Sjjg 1863233Sksrini bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 1873233Sksrini BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1883233Sksrini bus_write_2(sc->mem_res[slot->num], off, val); 1893233Sksrini} 1903233Sksrini 1913233Sksrinistatic uint32_t 1923233Sksrinisdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 1933233Sksrini{ 1943233Sksrini struct sdhci_pci_softc *sc = device_get_softc(dev); 1953233Sksrini 1963233Sksrini bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 1973233Sksrini BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1983233Sksrini return bus_read_4(sc->mem_res[slot->num], off); 1993233Sksrini} 2003233Sksrini 2013233Sksrinistatic void 2023233Sksrinisdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 2033233Sksrini bus_size_t off, uint32_t val) 2043233Sksrini{ 2053233Sksrini struct sdhci_pci_softc *sc = device_get_softc(dev); 2063233Sksrini 2073233Sksrini bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 2083233Sksrini BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2093233Sksrini bus_write_4(sc->mem_res[slot->num], off, val); 2103233Sksrini} 2113233Sksrini 2123233Sksrinistatic void 2133233Sksrinisdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 2140SN/A bus_size_t off, uint32_t *data, bus_size_t count) 2150SN/A{ 2160SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 2170SN/A 2180SN/A bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 2190SN/A} 2200SN/A 2213233Sksrinistatic void 2223233Sksrinisdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 2233233Sksrini bus_size_t off, uint32_t *data, bus_size_t count) 2243233Sksrini{ 2253233Sksrini struct sdhci_pci_softc *sc = device_get_softc(dev); 2263233Sksrini 2273233Sksrini bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 2283233Sksrini} 2293233Sksrini 2303691Sksrinistatic void sdhci_pci_intr(void *arg); 2310SN/A 2320SN/Astatic void 2333233Sksrinisdhci_lower_frequency(device_t dev) 2343233Sksrini{ 2351412SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 2363233Sksrini 2371412SN/A /* 2381412SN/A * Enable SD2.0 mode. 2393691Sksrini * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 2403233Sksrini */ 2411412SN/A pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 2423691Sksrini sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 2433691Sksrini pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 2443691Sksrini pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 2453691Sksrini 2463691Sksrini /* 2473691Sksrini * Some SD/MMC cards don't work with the default base 248583SN/A * clock frequency of 200 MHz. Lower it to 50 MHz. 2493560Sjjg */ 2503673Sjjg pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 251583SN/A sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 252583SN/A pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 253583SN/A pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 254583SN/A} 2550SN/A 2560SN/Astatic void 2570SN/Asdhci_restore_frequency(device_t dev) 2580SN/A{ 2590SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 2600SN/A 2610SN/A /* Restore mode. */ 2620SN/A pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 2630SN/A pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 2643233Sksrini pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 2653233Sksrini 2663233Sksrini /* Restore frequency. */ 2673691Sksrini pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 2683691Sksrini pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 2693691Sksrini pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 2703691Sksrini} 2713691Sksrini 2723691Sksrinistatic int 2733691Sksrinisdhci_pci_probe(device_t dev) 2743691Sksrini{ 2753233Sksrini uint32_t model; 2763233Sksrini uint16_t subvendor; 2773233Sksrini uint8_t class, subclass; 2783233Sksrini int i, result; 2793233Sksrini 2803233Sksrini model = (uint32_t)pci_get_device(dev) << 16; 2813691Sksrini model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2820SN/A subvendor = pci_get_subvendor(dev); 2830SN/A class = pci_get_class(dev); 2843233Sksrini subclass = pci_get_subclass(dev); 2853233Sksrini 2861412SN/A result = ENXIO; 2873233Sksrini for (i = 0; sdhci_devices[i].model != 0; i++) { 2881412SN/A if (sdhci_devices[i].model == model && 2891412SN/A (sdhci_devices[i].subvendor == 0xffff || 2903691Sksrini sdhci_devices[i].subvendor == subvendor)) { 2913233Sksrini device_set_desc(dev, sdhci_devices[i].desc); 2921412SN/A result = BUS_PROBE_DEFAULT; 2933691Sksrini break; 2943691Sksrini } 295583SN/A } 2963560Sjjg if (result == ENXIO && class == PCIC_BASEPERIPH && 2973673Sjjg subclass == PCIS_BASEPERIPH_SDHC) { 298583SN/A device_set_desc(dev, "Generic SD HCI"); 299583SN/A result = BUS_PROBE_GENERIC; 300583SN/A } 3010SN/A 3020SN/A return (result); 3030SN/A} 3040SN/A 3050SN/Astatic int 3060SN/Asdhci_pci_attach(device_t dev) 3070SN/A{ 3080SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 3090SN/A struct sdhci_slot *slot; 3103233Sksrini uint32_t model; 3110SN/A uint16_t subvendor; 3120SN/A int bar, err, rid, slots, i; 3133233Sksrini 3143233Sksrini model = (uint32_t)pci_get_device(dev) << 16; 3153233Sksrini model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3163233Sksrini subvendor = pci_get_subvendor(dev); 3173233Sksrini /* Apply chip specific quirks. */ 3183233Sksrini for (i = 0; sdhci_devices[i].model != 0; i++) { 3193233Sksrini if (sdhci_devices[i].model == model && 3203560Sjjg (sdhci_devices[i].subvendor == 0xffff || 3213233Sksrini sdhci_devices[i].subvendor == subvendor)) { 3223673Sjjg sc->quirks = sdhci_devices[i].quirks; 3233233Sksrini break; 3243673Sjjg } 3253233Sksrini } 3263233Sksrini /* Some controllers need to be bumped into the right mode. */ 3273233Sksrini if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 3283233Sksrini sdhci_lower_frequency(dev); 3293233Sksrini /* Read slots info from PCI registers. */ 3303233Sksrini slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 3311412SN/A bar = PCI_SLOT_INFO_FIRST_BAR(slots); 3321412SN/A slots = PCI_SLOT_INFO_SLOTS(slots); 3331412SN/A if (slots > 6 || bar > 5) { 3341412SN/A device_printf(dev, "Incorrect slots information (%d, %d).\n", 3351412SN/A slots, bar); 3363560Sjjg return (EINVAL); 3373233Sksrini } 3383673Sjjg /* Allocate IRQ. */ 3393233Sksrini i = 1; 3403673Sjjg rid = 0; 3413233Sksrini if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 3420SN/A rid = 1; 3430SN/A sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3440SN/A RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3450SN/A if (sc->irq_res == NULL) { 3460SN/A device_printf(dev, "Can't allocate IRQ\n"); 3470SN/A pci_release_msi(dev); 3480SN/A return (ENOMEM); 3490SN/A } 3501410SN/A /* Scan all slots. */ 3511410SN/A for (i = 0; i < slots; i++) { 3520SN/A slot = &sc->slots[sc->num_slots]; 3530SN/A 3540SN/A /* Allocate memory. */ 3553691Sksrini rid = PCIR_BAR(bar + i); 3560SN/A sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3573691Sksrini &rid, RF_ACTIVE); 3583691Sksrini if (sc->mem_res[i] == NULL) { 3593691Sksrini device_printf(dev, 3600SN/A "Can't allocate memory for slot %d\n", i); 3610SN/A continue; 3623691Sksrini } 3630SN/A 3643691Sksrini slot->quirks = sc->quirks; 3653691Sksrini 3663691Sksrini if (sdhci_init_slot(dev, slot, i) != 0) 3670SN/A continue; 3680SN/A 3690SN/A sc->num_slots++; 3700SN/A } 3713691Sksrini device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 3720SN/A /* Activate the interrupt */ 3730SN/A err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3740SN/A NULL, sdhci_pci_intr, sc, &sc->intrhand); 3750SN/A if (err) 3760SN/A device_printf(dev, "Can't setup IRQ\n"); 3770SN/A pci_enable_busmaster(dev); 3780SN/A /* Process cards detection. */ 3790SN/A for (i = 0; i < sc->num_slots; i++) 3800SN/A sdhci_start_slot(&sc->slots[i]); 3810SN/A 3823233Sksrini return (0); 3831412SN/A} 3841412SN/A 3851412SN/Astatic int 3861412SN/Asdhci_pci_detach(device_t dev) 3871412SN/A{ 3881412SN/A struct sdhci_pci_softc *sc = device_get_softc(dev); 3891412SN/A int i; 3901412SN/A 3911412SN/A bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 3921412SN/A bus_release_resource(dev, SYS_RES_IRQ, 3931412SN/A rman_get_rid(sc->irq_res), sc->irq_res); 3941412SN/A pci_release_msi(dev); 3951412SN/A 3961412SN/A for (i = 0; i < sc->num_slots; i++) { 3971412SN/A sdhci_cleanup_slot(&sc->slots[i]); 3981412SN/A bus_release_resource(dev, SYS_RES_MEMORY, 3990SN/A rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 400 } 401 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 402 sdhci_restore_frequency(dev); 403 return (0); 404} 405 406static int 407sdhci_pci_shutdown(device_t dev) 408{ 409 struct sdhci_pci_softc *sc = device_get_softc(dev); 410 411 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 412 sdhci_restore_frequency(dev); 413 return (0); 414} 415 416static int 417sdhci_pci_suspend(device_t dev) 418{ 419 struct sdhci_pci_softc *sc = device_get_softc(dev); 420 int i, err; 421 422 err = bus_generic_suspend(dev); 423 if (err) 424 return (err); 425 for (i = 0; i < sc->num_slots; i++) 426 sdhci_generic_suspend(&sc->slots[i]); 427 return (0); 428} 429 430static int 431sdhci_pci_resume(device_t dev) 432{ 433 struct sdhci_pci_softc *sc = device_get_softc(dev); 434 int i, err; 435 436 for (i = 0; i < sc->num_slots; i++) 437 sdhci_generic_resume(&sc->slots[i]); 438 err = bus_generic_resume(dev); 439 if (err) 440 return (err); 441 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 442 sdhci_lower_frequency(dev); 443 return (0); 444} 445 446static void 447sdhci_pci_intr(void *arg) 448{ 449 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 450 int i; 451 452 for (i = 0; i < sc->num_slots; i++) 453 sdhci_generic_intr(&sc->slots[i]); 454} 455 456static device_method_t sdhci_methods[] = { 457 /* device_if */ 458 DEVMETHOD(device_probe, sdhci_pci_probe), 459 DEVMETHOD(device_attach, sdhci_pci_attach), 460 DEVMETHOD(device_detach, sdhci_pci_detach), 461 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 462 DEVMETHOD(device_suspend, sdhci_pci_suspend), 463 DEVMETHOD(device_resume, sdhci_pci_resume), 464 465 /* Bus interface */ 466 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 467 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 468 469 /* mmcbr_if */ 470 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 471 DEVMETHOD(mmcbr_request, sdhci_generic_request), 472 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 473 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 474 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 475 476 /* SDHCI registers accessors */ 477 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 478 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 479 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 480 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 481 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 482 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 483 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 484 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 485 486 DEVMETHOD_END 487}; 488 489static driver_t sdhci_pci_driver = { 490 "sdhci_pci", 491 sdhci_methods, 492 sizeof(struct sdhci_pci_softc), 493}; 494static devclass_t sdhci_pci_devclass; 495 496DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 497 NULL); 498MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 499MMC_DECLARE_BRIDGE(sdhci_pci); 500