sdhci_pci.c revision 312399
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 312399 2017-01-18 23:25:46Z marius $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44 45#include <machine/bus.h> 46#include <machine/resource.h> 47#include <machine/stdarg.h> 48 49#include <dev/mmc/bridge.h> 50#include <dev/mmc/mmcreg.h> 51#include <dev/mmc/mmcbrvar.h> 52 53#include "sdhci.h" 54#include "mmcbr_if.h" 55#include "sdhci_if.h" 56 57/* 58 * PCI registers 59 */ 60 61#define PCI_SDHCI_IFPIO 0x00 62#define PCI_SDHCI_IFDMA 0x01 63#define PCI_SDHCI_IFVENDOR 0x02 64 65#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69/* 70 * RICOH specific PCI registers 71 */ 72#define SDHC_PCI_MODE_KEY 0xf9 73#define SDHC_PCI_MODE 0x150 74#define SDHC_PCI_MODE_SD20 0x10 75#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76#define SDHC_PCI_BASE_FREQ 0xe1 77 78static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83} sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 109 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 110 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 111 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 112 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 113 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 114 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 115 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 116 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 119 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 120 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 121 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 122 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 123 { 0, 0xffff, NULL, 124 0 } 125}; 126 127struct sdhci_pci_softc { 128 u_int quirks; /* Chip specific quirks */ 129 struct resource *irq_res; /* IRQ resource */ 130 void *intrhand; /* Interrupt handle */ 131 132 int num_slots; /* Number of slots on this controller */ 133 struct sdhci_slot slots[6]; 134 struct resource *mem_res[6]; /* Memory resource */ 135 uint8_t cfg_freq; /* Saved frequency */ 136 uint8_t cfg_mode; /* Saved mode */ 137}; 138 139static int sdhci_enable_msi = 1; 140SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 141 0, "Enable MSI interrupts"); 142 143static uint8_t 144sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 145{ 146 struct sdhci_pci_softc *sc = device_get_softc(dev); 147 148 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 149 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 150 return bus_read_1(sc->mem_res[slot->num], off); 151} 152 153static void 154sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 155{ 156 struct sdhci_pci_softc *sc = device_get_softc(dev); 157 158 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 159 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 160 bus_write_1(sc->mem_res[slot->num], off, val); 161} 162 163static uint16_t 164sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 165{ 166 struct sdhci_pci_softc *sc = device_get_softc(dev); 167 168 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 169 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 170 return bus_read_2(sc->mem_res[slot->num], off); 171} 172 173static void 174sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 175{ 176 struct sdhci_pci_softc *sc = device_get_softc(dev); 177 178 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 180 bus_write_2(sc->mem_res[slot->num], off, val); 181} 182 183static uint32_t 184sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 185{ 186 struct sdhci_pci_softc *sc = device_get_softc(dev); 187 188 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 189 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 190 return bus_read_4(sc->mem_res[slot->num], off); 191} 192 193static void 194sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 195{ 196 struct sdhci_pci_softc *sc = device_get_softc(dev); 197 198 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 199 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 200 bus_write_4(sc->mem_res[slot->num], off, val); 201} 202 203static void 204sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 205 bus_size_t off, uint32_t *data, bus_size_t count) 206{ 207 struct sdhci_pci_softc *sc = device_get_softc(dev); 208 209 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 210} 211 212static void 213sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 214 bus_size_t off, uint32_t *data, bus_size_t count) 215{ 216 struct sdhci_pci_softc *sc = device_get_softc(dev); 217 218 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 219} 220 221static void sdhci_pci_intr(void *arg); 222 223static void 224sdhci_lower_frequency(device_t dev) 225{ 226 struct sdhci_pci_softc *sc = device_get_softc(dev); 227 228 /* 229 * Enable SD2.0 mode. 230 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 231 */ 232 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 233 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 234 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 235 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 236 237 /* 238 * Some SD/MMC cards don't work with the default base 239 * clock frequency of 200 MHz. Lower it to 50 MHz. 240 */ 241 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 242 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 243 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 244 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 245} 246 247static void 248sdhci_restore_frequency(device_t dev) 249{ 250 struct sdhci_pci_softc *sc = device_get_softc(dev); 251 252 /* Restore mode. */ 253 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 254 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 255 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 256 257 /* Restore frequency. */ 258 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 259 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 260 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 261} 262 263static int 264sdhci_pci_probe(device_t dev) 265{ 266 uint32_t model; 267 uint16_t subvendor; 268 uint8_t class, subclass; 269 int i, result; 270 271 model = (uint32_t)pci_get_device(dev) << 16; 272 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 273 subvendor = pci_get_subvendor(dev); 274 class = pci_get_class(dev); 275 subclass = pci_get_subclass(dev); 276 277 result = ENXIO; 278 for (i = 0; sdhci_devices[i].model != 0; i++) { 279 if (sdhci_devices[i].model == model && 280 (sdhci_devices[i].subvendor == 0xffff || 281 sdhci_devices[i].subvendor == subvendor)) { 282 device_set_desc(dev, sdhci_devices[i].desc); 283 result = BUS_PROBE_DEFAULT; 284 break; 285 } 286 } 287 if (result == ENXIO && class == PCIC_BASEPERIPH && 288 subclass == PCIS_BASEPERIPH_SDHC) { 289 device_set_desc(dev, "Generic SD HCI"); 290 result = BUS_PROBE_GENERIC; 291 } 292 293 return (result); 294} 295 296static int 297sdhci_pci_attach(device_t dev) 298{ 299 struct sdhci_pci_softc *sc = device_get_softc(dev); 300 uint32_t model; 301 uint16_t subvendor; 302 int bar, err, rid, slots, i; 303 304 model = (uint32_t)pci_get_device(dev) << 16; 305 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 306 subvendor = pci_get_subvendor(dev); 307 /* Apply chip specific quirks. */ 308 for (i = 0; sdhci_devices[i].model != 0; i++) { 309 if (sdhci_devices[i].model == model && 310 (sdhci_devices[i].subvendor == 0xffff || 311 sdhci_devices[i].subvendor == subvendor)) { 312 sc->quirks = sdhci_devices[i].quirks; 313 break; 314 } 315 } 316 /* Some controllers need to be bumped into the right mode. */ 317 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 318 sdhci_lower_frequency(dev); 319 /* Read slots info from PCI registers. */ 320 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 321 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 322 slots = PCI_SLOT_INFO_SLOTS(slots); 323 if (slots > 6 || bar > 5) { 324 device_printf(dev, "Incorrect slots information (%d, %d).\n", 325 slots, bar); 326 return (EINVAL); 327 } 328 /* Allocate IRQ. */ 329 i = 1; 330 rid = 0; 331 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 332 rid = 1; 333 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 334 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 335 if (sc->irq_res == NULL) { 336 device_printf(dev, "Can't allocate IRQ\n"); 337 pci_release_msi(dev); 338 return (ENOMEM); 339 } 340 /* Scan all slots. */ 341 for (i = 0; i < slots; i++) { 342 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 343 344 /* Allocate memory. */ 345 rid = PCIR_BAR(bar + i); 346 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 347 &rid, RF_ACTIVE); 348 if (sc->mem_res[i] == NULL) { 349 device_printf(dev, "Can't allocate memory for slot %d\n", i); 350 continue; 351 } 352 353 slot->quirks = sc->quirks; 354 355 if (sdhci_init_slot(dev, slot, i) != 0) 356 continue; 357 358 sc->num_slots++; 359 } 360 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 361 /* Activate the interrupt */ 362 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 363 NULL, sdhci_pci_intr, sc, &sc->intrhand); 364 if (err) 365 device_printf(dev, "Can't setup IRQ\n"); 366 pci_enable_busmaster(dev); 367 /* Process cards detection. */ 368 for (i = 0; i < sc->num_slots; i++) { 369 struct sdhci_slot *slot = &sc->slots[i]; 370 371 sdhci_start_slot(slot); 372 } 373 374 return (0); 375} 376 377static int 378sdhci_pci_detach(device_t dev) 379{ 380 struct sdhci_pci_softc *sc = device_get_softc(dev); 381 int i; 382 383 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 384 bus_release_resource(dev, SYS_RES_IRQ, 385 rman_get_rid(sc->irq_res), sc->irq_res); 386 pci_release_msi(dev); 387 388 for (i = 0; i < sc->num_slots; i++) { 389 struct sdhci_slot *slot = &sc->slots[i]; 390 391 sdhci_cleanup_slot(slot); 392 bus_release_resource(dev, SYS_RES_MEMORY, 393 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 394 } 395 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 396 sdhci_restore_frequency(dev); 397 return (0); 398} 399 400static int 401sdhci_pci_shutdown(device_t dev) 402{ 403 struct sdhci_pci_softc *sc = device_get_softc(dev); 404 405 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 406 sdhci_restore_frequency(dev); 407 return (0); 408} 409 410static int 411sdhci_pci_suspend(device_t dev) 412{ 413 struct sdhci_pci_softc *sc = device_get_softc(dev); 414 int i, err; 415 416 err = bus_generic_suspend(dev); 417 if (err) 418 return (err); 419 for (i = 0; i < sc->num_slots; i++) 420 sdhci_generic_suspend(&sc->slots[i]); 421 return (0); 422} 423 424static int 425sdhci_pci_resume(device_t dev) 426{ 427 struct sdhci_pci_softc *sc = device_get_softc(dev); 428 int i, err; 429 430 for (i = 0; i < sc->num_slots; i++) 431 sdhci_generic_resume(&sc->slots[i]); 432 err = bus_generic_resume(dev); 433 if (err) 434 return (err); 435 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 436 sdhci_lower_frequency(dev); 437 return (0); 438} 439 440static void 441sdhci_pci_intr(void *arg) 442{ 443 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 444 int i; 445 446 for (i = 0; i < sc->num_slots; i++) { 447 struct sdhci_slot *slot = &sc->slots[i]; 448 sdhci_generic_intr(slot); 449 } 450} 451 452static device_method_t sdhci_methods[] = { 453 /* device_if */ 454 DEVMETHOD(device_probe, sdhci_pci_probe), 455 DEVMETHOD(device_attach, sdhci_pci_attach), 456 DEVMETHOD(device_detach, sdhci_pci_detach), 457 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 458 DEVMETHOD(device_suspend, sdhci_pci_suspend), 459 DEVMETHOD(device_resume, sdhci_pci_resume), 460 461 /* Bus interface */ 462 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 463 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 464 465 /* mmcbr_if */ 466 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 467 DEVMETHOD(mmcbr_request, sdhci_generic_request), 468 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 469 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 470 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 471 472 /* SDHCI registers accessors */ 473 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 474 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 475 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 476 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 477 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 478 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 479 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 480 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 481 482 DEVMETHOD_END 483}; 484 485static driver_t sdhci_pci_driver = { 486 "sdhci_pci", 487 sdhci_methods, 488 sizeof(struct sdhci_pci_softc), 489}; 490static devclass_t sdhci_pci_devclass; 491 492DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 493 NULL); 494MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 495DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); 496MODULE_DEPEND(sdhci_pci, mmc, 1, 1, 1); 497