sdhci_pci.c revision 289359
1241600Sgonzo/*- 2241600Sgonzo * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3241600Sgonzo * All rights reserved. 4241600Sgonzo * 5241600Sgonzo * Redistribution and use in source and binary forms, with or without 6241600Sgonzo * modification, are permitted provided that the following conditions 7241600Sgonzo * are met: 8241600Sgonzo * 1. Redistributions of source code must retain the above copyright 9241600Sgonzo * notice, this list of conditions and the following disclaimer. 10241600Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11241600Sgonzo * notice, this list of conditions and the following disclaimer in the 12241600Sgonzo * documentation and/or other materials provided with the distribution. 13241600Sgonzo * 14241600Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15241600Sgonzo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16241600Sgonzo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17241600Sgonzo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18241600Sgonzo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19241600Sgonzo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20241600Sgonzo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21241600Sgonzo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22241600Sgonzo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23241600Sgonzo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24241600Sgonzo */ 25241600Sgonzo 26241600Sgonzo#include <sys/cdefs.h> 27241600Sgonzo__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci_pci.c 289359 2015-10-15 04:22:56Z adrian $"); 28241600Sgonzo 29241600Sgonzo#include <sys/param.h> 30241600Sgonzo#include <sys/systm.h> 31241600Sgonzo#include <sys/bus.h> 32241600Sgonzo#include <sys/conf.h> 33241600Sgonzo#include <sys/kernel.h> 34241600Sgonzo#include <sys/lock.h> 35241600Sgonzo#include <sys/module.h> 36241600Sgonzo#include <sys/mutex.h> 37241600Sgonzo#include <sys/resource.h> 38241600Sgonzo#include <sys/rman.h> 39241600Sgonzo#include <sys/sysctl.h> 40241600Sgonzo#include <sys/taskqueue.h> 41241600Sgonzo 42241600Sgonzo#include <dev/pci/pcireg.h> 43241600Sgonzo#include <dev/pci/pcivar.h> 44241600Sgonzo 45241600Sgonzo#include <machine/bus.h> 46241600Sgonzo#include <machine/resource.h> 47241600Sgonzo#include <machine/stdarg.h> 48241600Sgonzo 49241600Sgonzo#include <dev/mmc/bridge.h> 50241600Sgonzo#include <dev/mmc/mmcreg.h> 51241600Sgonzo#include <dev/mmc/mmcbrvar.h> 52241600Sgonzo 53241600Sgonzo#include "sdhci.h" 54241600Sgonzo#include "mmcbr_if.h" 55241600Sgonzo#include "sdhci_if.h" 56241600Sgonzo 57241600Sgonzo/* 58241600Sgonzo * PCI registers 59241600Sgonzo */ 60241600Sgonzo 61241600Sgonzo#define PCI_SDHCI_IFPIO 0x00 62241600Sgonzo#define PCI_SDHCI_IFDMA 0x01 63241600Sgonzo#define PCI_SDHCI_IFVENDOR 0x02 64241600Sgonzo 65241600Sgonzo#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66241600Sgonzo#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67241600Sgonzo#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68241600Sgonzo 69241600Sgonzo/* 70241600Sgonzo * RICOH specific PCI registers 71241600Sgonzo */ 72241600Sgonzo#define SDHC_PCI_MODE_KEY 0xf9 73241600Sgonzo#define SDHC_PCI_MODE 0x150 74276469Smarius#define SDHC_PCI_MODE_SD20 0x10 75241600Sgonzo#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76241600Sgonzo#define SDHC_PCI_BASE_FREQ 0xe1 77241600Sgonzo 78241600Sgonzostatic const struct sdhci_device { 79241600Sgonzo uint32_t model; 80241600Sgonzo uint16_t subvendor; 81270885Smarius const char *desc; 82241600Sgonzo u_int quirks; 83241600Sgonzo} sdhci_devices[] = { 84241600Sgonzo { 0x08221180, 0xffff, "RICOH R5C822 SD", 85241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 86276469Smarius { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87276469Smarius SDHCI_QUIRK_FORCE_DMA | 88276469Smarius SDHCI_QUIRK_LOWER_FREQUENCY }, 89241600Sgonzo { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90241600Sgonzo SDHCI_QUIRK_LOWER_FREQUENCY }, 91241600Sgonzo { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 93241600Sgonzo { 0x05501524, 0xffff, "ENE CB712 SD", 94241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 95241600Sgonzo { 0x05511524, 0xffff, "ENE CB712 SD 2", 96241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 97241600Sgonzo { 0x07501524, 0xffff, "ENE CB714 SD", 98241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 99241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 100241600Sgonzo { 0x07511524, 0xffff, "ENE CB714 SD 2", 101241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 102241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 103241600Sgonzo { 0x410111ab, 0xffff, "Marvell CaFe SD", 104241600Sgonzo SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105241600Sgonzo { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106241600Sgonzo SDHCI_QUIRK_32BIT_DMA_SIZE | 107241600Sgonzo SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108289359Sadrian { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 109289359Sadrian SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 110241600Sgonzo { 0, 0xffff, NULL, 111241600Sgonzo 0 } 112241600Sgonzo}; 113241600Sgonzo 114241600Sgonzostruct sdhci_pci_softc { 115241600Sgonzo u_int quirks; /* Chip specific quirks */ 116241600Sgonzo struct resource *irq_res; /* IRQ resource */ 117241600Sgonzo void *intrhand; /* Interrupt handle */ 118241600Sgonzo 119241600Sgonzo int num_slots; /* Number of slots on this controller */ 120241600Sgonzo struct sdhci_slot slots[6]; 121241600Sgonzo struct resource *mem_res[6]; /* Memory resource */ 122276469Smarius uint8_t cfg_freq; /* Saved mode */ 123276469Smarius uint8_t cfg_mode; /* Saved frequency */ 124241600Sgonzo}; 125241600Sgonzo 126270885Smariusstatic int sdhci_enable_msi = 1; 127270885SmariusSYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 128270885Smarius 0, "Enable MSI interrupts"); 129241600Sgonzo 130241600Sgonzostatic uint8_t 131241600Sgonzosdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 132241600Sgonzo{ 133241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 134241600Sgonzo 135241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 136241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 137241600Sgonzo return bus_read_1(sc->mem_res[slot->num], off); 138241600Sgonzo} 139241600Sgonzo 140241600Sgonzostatic void 141241600Sgonzosdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 142241600Sgonzo{ 143241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 144241600Sgonzo 145241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 146241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 147241600Sgonzo bus_write_1(sc->mem_res[slot->num], off, val); 148241600Sgonzo} 149241600Sgonzo 150241600Sgonzostatic uint16_t 151241600Sgonzosdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 152241600Sgonzo{ 153241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 154241600Sgonzo 155241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 156241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157241600Sgonzo return bus_read_2(sc->mem_res[slot->num], off); 158241600Sgonzo} 159241600Sgonzo 160241600Sgonzostatic void 161241600Sgonzosdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 162241600Sgonzo{ 163241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 164241600Sgonzo 165241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 166241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167241600Sgonzo bus_write_2(sc->mem_res[slot->num], off, val); 168241600Sgonzo} 169241600Sgonzo 170241600Sgonzostatic uint32_t 171241600Sgonzosdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 172241600Sgonzo{ 173241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 174241600Sgonzo 175241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 176241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177241600Sgonzo return bus_read_4(sc->mem_res[slot->num], off); 178241600Sgonzo} 179241600Sgonzo 180241600Sgonzostatic void 181241600Sgonzosdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 182241600Sgonzo{ 183241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 184241600Sgonzo 185241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 186241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 187241600Sgonzo bus_write_4(sc->mem_res[slot->num], off, val); 188241600Sgonzo} 189241600Sgonzo 190241600Sgonzostatic void 191241600Sgonzosdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 192241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 193241600Sgonzo{ 194241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 195241600Sgonzo 196241600Sgonzo bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 197241600Sgonzo} 198241600Sgonzo 199241600Sgonzostatic void 200241600Sgonzosdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 201241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 202241600Sgonzo{ 203241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 204241600Sgonzo 205241600Sgonzo bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 206241600Sgonzo} 207241600Sgonzo 208241600Sgonzostatic void sdhci_pci_intr(void *arg); 209241600Sgonzo 210241600Sgonzostatic void 211241600Sgonzosdhci_lower_frequency(device_t dev) 212241600Sgonzo{ 213276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 214241600Sgonzo 215276469Smarius /* 216276469Smarius * Enable SD2.0 mode. 217276469Smarius * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 218276469Smarius */ 219241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 220276469Smarius sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 221241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 222241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 223241600Sgonzo 224241600Sgonzo /* 225241600Sgonzo * Some SD/MMC cards don't work with the default base 226276469Smarius * clock frequency of 200 MHz. Lower it to 50 MHz. 227241600Sgonzo */ 228241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 229276469Smarius sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 230241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 231241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 232241600Sgonzo} 233241600Sgonzo 234276469Smariusstatic void 235276469Smariussdhci_restore_frequency(device_t dev) 236276469Smarius{ 237276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 238276469Smarius 239276469Smarius /* Restore mode. */ 240276469Smarius pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 241276469Smarius pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 242276469Smarius pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 243276469Smarius 244276469Smarius /* Restore frequency. */ 245276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 246276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 247276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 248276469Smarius} 249276469Smarius 250241600Sgonzostatic int 251241600Sgonzosdhci_pci_probe(device_t dev) 252241600Sgonzo{ 253241600Sgonzo uint32_t model; 254241600Sgonzo uint16_t subvendor; 255241600Sgonzo uint8_t class, subclass; 256241600Sgonzo int i, result; 257270885Smarius 258241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 259241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 260241600Sgonzo subvendor = pci_get_subvendor(dev); 261241600Sgonzo class = pci_get_class(dev); 262241600Sgonzo subclass = pci_get_subclass(dev); 263270885Smarius 264241600Sgonzo result = ENXIO; 265241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 266241600Sgonzo if (sdhci_devices[i].model == model && 267241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 268241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 269241600Sgonzo device_set_desc(dev, sdhci_devices[i].desc); 270241600Sgonzo result = BUS_PROBE_DEFAULT; 271241600Sgonzo break; 272241600Sgonzo } 273241600Sgonzo } 274241600Sgonzo if (result == ENXIO && class == PCIC_BASEPERIPH && 275241600Sgonzo subclass == PCIS_BASEPERIPH_SDHC) { 276241600Sgonzo device_set_desc(dev, "Generic SD HCI"); 277241600Sgonzo result = BUS_PROBE_GENERIC; 278241600Sgonzo } 279270885Smarius 280241600Sgonzo return (result); 281241600Sgonzo} 282241600Sgonzo 283241600Sgonzostatic int 284241600Sgonzosdhci_pci_attach(device_t dev) 285241600Sgonzo{ 286241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 287241600Sgonzo uint32_t model; 288241600Sgonzo uint16_t subvendor; 289270885Smarius int bar, err, rid, slots, i; 290241600Sgonzo 291241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 292241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 293241600Sgonzo subvendor = pci_get_subvendor(dev); 294241600Sgonzo /* Apply chip specific quirks. */ 295241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 296241600Sgonzo if (sdhci_devices[i].model == model && 297241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 298241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 299241600Sgonzo sc->quirks = sdhci_devices[i].quirks; 300241600Sgonzo break; 301241600Sgonzo } 302241600Sgonzo } 303241600Sgonzo /* Some controllers need to be bumped into the right mode. */ 304241600Sgonzo if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 305241600Sgonzo sdhci_lower_frequency(dev); 306241600Sgonzo /* Read slots info from PCI registers. */ 307241600Sgonzo slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 308241600Sgonzo bar = PCI_SLOT_INFO_FIRST_BAR(slots); 309241600Sgonzo slots = PCI_SLOT_INFO_SLOTS(slots); 310241600Sgonzo if (slots > 6 || bar > 5) { 311241600Sgonzo device_printf(dev, "Incorrect slots information (%d, %d).\n", 312241600Sgonzo slots, bar); 313241600Sgonzo return (EINVAL); 314241600Sgonzo } 315241600Sgonzo /* Allocate IRQ. */ 316270885Smarius i = 1; 317270885Smarius rid = 0; 318270885Smarius if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 319270885Smarius rid = 1; 320270885Smarius sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 321270885Smarius RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 322241600Sgonzo if (sc->irq_res == NULL) { 323241600Sgonzo device_printf(dev, "Can't allocate IRQ\n"); 324270885Smarius pci_release_msi(dev); 325241600Sgonzo return (ENOMEM); 326241600Sgonzo } 327241600Sgonzo /* Scan all slots. */ 328241600Sgonzo for (i = 0; i < slots; i++) { 329241600Sgonzo struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 330241600Sgonzo 331241600Sgonzo /* Allocate memory. */ 332270885Smarius rid = PCIR_BAR(bar + i); 333270885Smarius sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 334270885Smarius &rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 335241600Sgonzo if (sc->mem_res[i] == NULL) { 336241600Sgonzo device_printf(dev, "Can't allocate memory for slot %d\n", i); 337241600Sgonzo continue; 338241600Sgonzo } 339289359Sadrian 340289359Sadrian slot->quirks = sc->quirks; 341241600Sgonzo 342241600Sgonzo if (sdhci_init_slot(dev, slot, i) != 0) 343241600Sgonzo continue; 344241600Sgonzo 345241600Sgonzo sc->num_slots++; 346241600Sgonzo } 347241600Sgonzo device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 348241600Sgonzo /* Activate the interrupt */ 349241600Sgonzo err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 350241600Sgonzo NULL, sdhci_pci_intr, sc, &sc->intrhand); 351241600Sgonzo if (err) 352241600Sgonzo device_printf(dev, "Can't setup IRQ\n"); 353241600Sgonzo pci_enable_busmaster(dev); 354241600Sgonzo /* Process cards detection. */ 355241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 356241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 357241600Sgonzo 358241600Sgonzo sdhci_start_slot(slot); 359241600Sgonzo } 360270885Smarius 361241600Sgonzo return (0); 362241600Sgonzo} 363241600Sgonzo 364241600Sgonzostatic int 365241600Sgonzosdhci_pci_detach(device_t dev) 366241600Sgonzo{ 367241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 368241600Sgonzo int i; 369241600Sgonzo 370241600Sgonzo bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 371241600Sgonzo bus_release_resource(dev, SYS_RES_IRQ, 372270885Smarius rman_get_rid(sc->irq_res), sc->irq_res); 373270885Smarius pci_release_msi(dev); 374241600Sgonzo 375241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 376241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 377241600Sgonzo 378241600Sgonzo sdhci_cleanup_slot(slot); 379241600Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 380270885Smarius rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 381241600Sgonzo } 382276469Smarius if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 383276469Smarius sdhci_restore_frequency(dev); 384241600Sgonzo return (0); 385241600Sgonzo} 386241600Sgonzo 387241600Sgonzostatic int 388276469Smariussdhci_pci_shutdown(device_t dev) 389276469Smarius{ 390276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 391276469Smarius 392276469Smarius if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 393276469Smarius sdhci_restore_frequency(dev); 394276469Smarius return (0); 395276469Smarius} 396276469Smarius 397276469Smariusstatic int 398241600Sgonzosdhci_pci_suspend(device_t dev) 399241600Sgonzo{ 400241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 401241600Sgonzo int i, err; 402241600Sgonzo 403241600Sgonzo err = bus_generic_suspend(dev); 404241600Sgonzo if (err) 405241600Sgonzo return (err); 406241600Sgonzo for (i = 0; i < sc->num_slots; i++) 407270885Smarius sdhci_generic_suspend(&sc->slots[i]); 408241600Sgonzo return (0); 409241600Sgonzo} 410241600Sgonzo 411241600Sgonzostatic int 412241600Sgonzosdhci_pci_resume(device_t dev) 413241600Sgonzo{ 414241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 415241600Sgonzo int i; 416241600Sgonzo 417241600Sgonzo for (i = 0; i < sc->num_slots; i++) 418241600Sgonzo sdhci_generic_resume(&sc->slots[i]); 419241600Sgonzo return (bus_generic_resume(dev)); 420241600Sgonzo} 421241600Sgonzo 422241600Sgonzostatic void 423241600Sgonzosdhci_pci_intr(void *arg) 424241600Sgonzo{ 425241600Sgonzo struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 426241600Sgonzo int i; 427241600Sgonzo 428241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 429241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 430241600Sgonzo sdhci_generic_intr(slot); 431241600Sgonzo } 432241600Sgonzo} 433241600Sgonzo 434241600Sgonzostatic device_method_t sdhci_methods[] = { 435241600Sgonzo /* device_if */ 436241600Sgonzo DEVMETHOD(device_probe, sdhci_pci_probe), 437241600Sgonzo DEVMETHOD(device_attach, sdhci_pci_attach), 438241600Sgonzo DEVMETHOD(device_detach, sdhci_pci_detach), 439276469Smarius DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 440241600Sgonzo DEVMETHOD(device_suspend, sdhci_pci_suspend), 441241600Sgonzo DEVMETHOD(device_resume, sdhci_pci_resume), 442241600Sgonzo 443241600Sgonzo /* Bus interface */ 444241600Sgonzo DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 445241600Sgonzo DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 446241600Sgonzo 447241600Sgonzo /* mmcbr_if */ 448241600Sgonzo DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 449241600Sgonzo DEVMETHOD(mmcbr_request, sdhci_generic_request), 450241600Sgonzo DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 451241600Sgonzo DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 452241600Sgonzo DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 453241600Sgonzo 454241600Sgonzo /* SDHCI registers accessors */ 455241600Sgonzo DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 456241600Sgonzo DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 457241600Sgonzo DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 458241600Sgonzo DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 459241600Sgonzo DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 460241600Sgonzo DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 461241600Sgonzo DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 462241600Sgonzo DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 463241600Sgonzo 464246128Ssbz DEVMETHOD_END 465241600Sgonzo}; 466241600Sgonzo 467241600Sgonzostatic driver_t sdhci_pci_driver = { 468241600Sgonzo "sdhci_pci", 469241600Sgonzo sdhci_methods, 470241600Sgonzo sizeof(struct sdhci_pci_softc), 471241600Sgonzo}; 472241600Sgonzostatic devclass_t sdhci_pci_devclass; 473241600Sgonzo 474270885SmariusDRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 475270885Smarius NULL); 476241600SgonzoMODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 477