sdhci_pci.c revision 246128
1241600Sgonzo/*- 2241600Sgonzo * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3241600Sgonzo * All rights reserved. 4241600Sgonzo * 5241600Sgonzo * Redistribution and use in source and binary forms, with or without 6241600Sgonzo * modification, are permitted provided that the following conditions 7241600Sgonzo * are met: 8241600Sgonzo * 1. Redistributions of source code must retain the above copyright 9241600Sgonzo * notice, this list of conditions and the following disclaimer. 10241600Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11241600Sgonzo * notice, this list of conditions and the following disclaimer in the 12241600Sgonzo * documentation and/or other materials provided with the distribution. 13241600Sgonzo * 14241600Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15241600Sgonzo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16241600Sgonzo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17241600Sgonzo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18241600Sgonzo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19241600Sgonzo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20241600Sgonzo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21241600Sgonzo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22241600Sgonzo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23241600Sgonzo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24241600Sgonzo */ 25241600Sgonzo 26241600Sgonzo#include <sys/cdefs.h> 27241600Sgonzo__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci_pci.c 246128 2013-01-30 18:01:20Z sbz $"); 28241600Sgonzo 29241600Sgonzo#include <sys/param.h> 30241600Sgonzo#include <sys/systm.h> 31241600Sgonzo#include <sys/bus.h> 32241600Sgonzo#include <sys/conf.h> 33241600Sgonzo#include <sys/kernel.h> 34241600Sgonzo#include <sys/lock.h> 35241600Sgonzo#include <sys/module.h> 36241600Sgonzo#include <sys/mutex.h> 37241600Sgonzo#include <sys/resource.h> 38241600Sgonzo#include <sys/rman.h> 39241600Sgonzo#include <sys/sysctl.h> 40241600Sgonzo#include <sys/taskqueue.h> 41241600Sgonzo 42241600Sgonzo#include <dev/pci/pcireg.h> 43241600Sgonzo#include <dev/pci/pcivar.h> 44241600Sgonzo 45241600Sgonzo#include <machine/bus.h> 46241600Sgonzo#include <machine/resource.h> 47241600Sgonzo#include <machine/stdarg.h> 48241600Sgonzo 49241600Sgonzo#include <dev/mmc/bridge.h> 50241600Sgonzo#include <dev/mmc/mmcreg.h> 51241600Sgonzo#include <dev/mmc/mmcbrvar.h> 52241600Sgonzo 53241600Sgonzo#include "sdhci.h" 54241600Sgonzo#include "mmcbr_if.h" 55241600Sgonzo#include "sdhci_if.h" 56241600Sgonzo 57241600Sgonzo/* 58241600Sgonzo * PCI registers 59241600Sgonzo */ 60241600Sgonzo 61241600Sgonzo#define PCI_SDHCI_IFPIO 0x00 62241600Sgonzo#define PCI_SDHCI_IFDMA 0x01 63241600Sgonzo#define PCI_SDHCI_IFVENDOR 0x02 64241600Sgonzo 65241600Sgonzo#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66241600Sgonzo#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67241600Sgonzo#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68241600Sgonzo 69241600Sgonzo/* 70241600Sgonzo * RICOH specific PCI registers 71241600Sgonzo */ 72241600Sgonzo#define SDHC_PCI_MODE_KEY 0xf9 73241600Sgonzo#define SDHC_PCI_MODE 0x150 74241600Sgonzo#define SDHC_PCI_MODE_SD20 0x10 75241600Sgonzo#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76241600Sgonzo#define SDHC_PCI_BASE_FREQ 0xe1 77241600Sgonzo 78241600Sgonzostatic const struct sdhci_device { 79241600Sgonzo uint32_t model; 80241600Sgonzo uint16_t subvendor; 81241600Sgonzo char *desc; 82241600Sgonzo u_int quirks; 83241600Sgonzo} sdhci_devices[] = { 84241600Sgonzo { 0x08221180, 0xffff, "RICOH R5C822 SD", 85241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 86241600Sgonzo { 0xe8221180, 0xffff, "RICOH SD", 87241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 88241600Sgonzo { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 89241600Sgonzo SDHCI_QUIRK_LOWER_FREQUENCY }, 90241600Sgonzo { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 91241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 92241600Sgonzo { 0x05501524, 0xffff, "ENE CB712 SD", 93241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 94241600Sgonzo { 0x05511524, 0xffff, "ENE CB712 SD 2", 95241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 96241600Sgonzo { 0x07501524, 0xffff, "ENE CB714 SD", 97241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 98241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 99241600Sgonzo { 0x07511524, 0xffff, "ENE CB714 SD 2", 100241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 101241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 102241600Sgonzo { 0x410111ab, 0xffff, "Marvell CaFe SD", 103241600Sgonzo SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 104241600Sgonzo { 0x2381197B, 0xffff, "JMicron JMB38X SD", 105241600Sgonzo SDHCI_QUIRK_32BIT_DMA_SIZE | 106241600Sgonzo SDHCI_QUIRK_RESET_AFTER_REQUEST }, 107241600Sgonzo { 0, 0xffff, NULL, 108241600Sgonzo 0 } 109241600Sgonzo}; 110241600Sgonzo 111241600Sgonzostruct sdhci_pci_softc { 112241600Sgonzo device_t dev; /* Controller device */ 113241600Sgonzo u_int quirks; /* Chip specific quirks */ 114241600Sgonzo struct resource *irq_res; /* IRQ resource */ 115241600Sgonzo int irq_rid; 116241600Sgonzo void *intrhand; /* Interrupt handle */ 117241600Sgonzo 118241600Sgonzo int num_slots; /* Number of slots on this controller */ 119241600Sgonzo struct sdhci_slot slots[6]; 120241600Sgonzo struct resource *mem_res[6]; /* Memory resource */ 121241600Sgonzo int mem_rid[6]; 122241600Sgonzo}; 123241600Sgonzo 124241600Sgonzostatic SYSCTL_NODE(_hw, OID_AUTO, sdhci_pci, CTLFLAG_RD, 0, "sdhci PCI driver"); 125241600Sgonzo 126241600Sgonzoint sdhci_pci_debug; 127241600SgonzoTUNABLE_INT("hw.sdhci_pci.debug", &sdhci_pci_debug); 128241600SgonzoSYSCTL_INT(_hw_sdhci_pci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_pci_debug, 0, "Debug level"); 129241600Sgonzo 130241600Sgonzostatic uint8_t 131241600Sgonzosdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 132241600Sgonzo{ 133241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 134241600Sgonzo 135241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 136241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 137241600Sgonzo return bus_read_1(sc->mem_res[slot->num], off); 138241600Sgonzo} 139241600Sgonzo 140241600Sgonzostatic void 141241600Sgonzosdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 142241600Sgonzo{ 143241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 144241600Sgonzo 145241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 146241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 147241600Sgonzo bus_write_1(sc->mem_res[slot->num], off, val); 148241600Sgonzo} 149241600Sgonzo 150241600Sgonzostatic uint16_t 151241600Sgonzosdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 152241600Sgonzo{ 153241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 154241600Sgonzo 155241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 156241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157241600Sgonzo return bus_read_2(sc->mem_res[slot->num], off); 158241600Sgonzo} 159241600Sgonzo 160241600Sgonzostatic void 161241600Sgonzosdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 162241600Sgonzo{ 163241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 164241600Sgonzo 165241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 166241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167241600Sgonzo bus_write_2(sc->mem_res[slot->num], off, val); 168241600Sgonzo} 169241600Sgonzo 170241600Sgonzostatic uint32_t 171241600Sgonzosdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 172241600Sgonzo{ 173241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 174241600Sgonzo 175241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 176241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177241600Sgonzo return bus_read_4(sc->mem_res[slot->num], off); 178241600Sgonzo} 179241600Sgonzo 180241600Sgonzostatic void 181241600Sgonzosdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 182241600Sgonzo{ 183241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 184241600Sgonzo 185241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 186241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 187241600Sgonzo bus_write_4(sc->mem_res[slot->num], off, val); 188241600Sgonzo} 189241600Sgonzo 190241600Sgonzostatic void 191241600Sgonzosdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 192241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 193241600Sgonzo{ 194241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 195241600Sgonzo 196241600Sgonzo bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 197241600Sgonzo} 198241600Sgonzo 199241600Sgonzostatic void 200241600Sgonzosdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 201241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 202241600Sgonzo{ 203241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 204241600Sgonzo 205241600Sgonzo bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 206241600Sgonzo} 207241600Sgonzo 208241600Sgonzostatic void sdhci_pci_intr(void *arg); 209241600Sgonzo 210241600Sgonzostatic void 211241600Sgonzosdhci_lower_frequency(device_t dev) 212241600Sgonzo{ 213241600Sgonzo 214241600Sgonzo /* Enable SD2.0 mode. */ 215241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 216241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 217241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 218241600Sgonzo 219241600Sgonzo /* 220241600Sgonzo * Some SD/MMC cards don't work with the default base 221241600Sgonzo * clock frequency of 200MHz. Lower it to 50Hz. 222241600Sgonzo */ 223241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 224241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 225241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 226241600Sgonzo} 227241600Sgonzo 228241600Sgonzostatic int 229241600Sgonzosdhci_pci_probe(device_t dev) 230241600Sgonzo{ 231241600Sgonzo uint32_t model; 232241600Sgonzo uint16_t subvendor; 233241600Sgonzo uint8_t class, subclass; 234241600Sgonzo int i, result; 235241600Sgonzo 236241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 237241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 238241600Sgonzo subvendor = pci_get_subvendor(dev); 239241600Sgonzo class = pci_get_class(dev); 240241600Sgonzo subclass = pci_get_subclass(dev); 241241600Sgonzo 242241600Sgonzo result = ENXIO; 243241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 244241600Sgonzo if (sdhci_devices[i].model == model && 245241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 246241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 247241600Sgonzo device_set_desc(dev, sdhci_devices[i].desc); 248241600Sgonzo result = BUS_PROBE_DEFAULT; 249241600Sgonzo break; 250241600Sgonzo } 251241600Sgonzo } 252241600Sgonzo if (result == ENXIO && class == PCIC_BASEPERIPH && 253241600Sgonzo subclass == PCIS_BASEPERIPH_SDHC) { 254241600Sgonzo device_set_desc(dev, "Generic SD HCI"); 255241600Sgonzo result = BUS_PROBE_GENERIC; 256241600Sgonzo } 257241600Sgonzo 258241600Sgonzo return (result); 259241600Sgonzo} 260241600Sgonzo 261241600Sgonzostatic int 262241600Sgonzosdhci_pci_attach(device_t dev) 263241600Sgonzo{ 264241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 265241600Sgonzo uint32_t model; 266241600Sgonzo uint16_t subvendor; 267241600Sgonzo uint8_t class, subclass, progif; 268241600Sgonzo int err, slots, bar, i; 269241600Sgonzo 270241600Sgonzo sc->dev = dev; 271241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 272241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 273241600Sgonzo subvendor = pci_get_subvendor(dev); 274241600Sgonzo class = pci_get_class(dev); 275241600Sgonzo subclass = pci_get_subclass(dev); 276241600Sgonzo progif = pci_get_progif(dev); 277241600Sgonzo /* Apply chip specific quirks. */ 278241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 279241600Sgonzo if (sdhci_devices[i].model == model && 280241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 281241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 282241600Sgonzo sc->quirks = sdhci_devices[i].quirks; 283241600Sgonzo break; 284241600Sgonzo } 285241600Sgonzo } 286241600Sgonzo /* Some controllers need to be bumped into the right mode. */ 287241600Sgonzo if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 288241600Sgonzo sdhci_lower_frequency(dev); 289241600Sgonzo /* Read slots info from PCI registers. */ 290241600Sgonzo slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 291241600Sgonzo bar = PCI_SLOT_INFO_FIRST_BAR(slots); 292241600Sgonzo slots = PCI_SLOT_INFO_SLOTS(slots); 293241600Sgonzo if (slots > 6 || bar > 5) { 294241600Sgonzo device_printf(dev, "Incorrect slots information (%d, %d).\n", 295241600Sgonzo slots, bar); 296241600Sgonzo return (EINVAL); 297241600Sgonzo } 298241600Sgonzo /* Allocate IRQ. */ 299241600Sgonzo sc->irq_rid = 0; 300241600Sgonzo sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 301241600Sgonzo RF_SHAREABLE | RF_ACTIVE); 302241600Sgonzo if (sc->irq_res == NULL) { 303241600Sgonzo device_printf(dev, "Can't allocate IRQ\n"); 304241600Sgonzo return (ENOMEM); 305241600Sgonzo } 306241600Sgonzo /* Scan all slots. */ 307241600Sgonzo for (i = 0; i < slots; i++) { 308241600Sgonzo struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 309241600Sgonzo 310241600Sgonzo /* Allocate memory. */ 311241600Sgonzo sc->mem_rid[i] = PCIR_BAR(bar + i); 312241600Sgonzo sc->mem_res[i] = bus_alloc_resource(dev, 313241600Sgonzo SYS_RES_MEMORY, &(sc->mem_rid[i]), 0ul, ~0ul, 0x100, RF_ACTIVE); 314241600Sgonzo if (sc->mem_res[i] == NULL) { 315241600Sgonzo device_printf(dev, "Can't allocate memory for slot %d\n", i); 316241600Sgonzo continue; 317241600Sgonzo } 318241600Sgonzo 319241600Sgonzo if (sdhci_init_slot(dev, slot, i) != 0) 320241600Sgonzo continue; 321241600Sgonzo 322241600Sgonzo 323241600Sgonzo sc->num_slots++; 324241600Sgonzo } 325241600Sgonzo device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 326241600Sgonzo /* Activate the interrupt */ 327241600Sgonzo err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 328241600Sgonzo NULL, sdhci_pci_intr, sc, &sc->intrhand); 329241600Sgonzo if (err) 330241600Sgonzo device_printf(dev, "Can't setup IRQ\n"); 331241600Sgonzo pci_enable_busmaster(dev); 332241600Sgonzo /* Process cards detection. */ 333241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 334241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 335241600Sgonzo 336241600Sgonzo sdhci_start_slot(slot); 337241600Sgonzo } 338241600Sgonzo 339241600Sgonzo return (0); 340241600Sgonzo} 341241600Sgonzo 342241600Sgonzostatic int 343241600Sgonzosdhci_pci_detach(device_t dev) 344241600Sgonzo{ 345241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 346241600Sgonzo int i; 347241600Sgonzo 348241600Sgonzo bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 349241600Sgonzo bus_release_resource(dev, SYS_RES_IRQ, 350241600Sgonzo sc->irq_rid, sc->irq_res); 351241600Sgonzo 352241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 353241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 354241600Sgonzo 355241600Sgonzo sdhci_cleanup_slot(slot); 356241600Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 357241600Sgonzo sc->mem_rid[i], sc->mem_res[i]); 358241600Sgonzo } 359241600Sgonzo return (0); 360241600Sgonzo} 361241600Sgonzo 362241600Sgonzostatic int 363241600Sgonzosdhci_pci_suspend(device_t dev) 364241600Sgonzo{ 365241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 366241600Sgonzo int i, err; 367241600Sgonzo 368241600Sgonzo err = bus_generic_suspend(dev); 369241600Sgonzo if (err) 370241600Sgonzo return (err); 371241600Sgonzo for (i = 0; i < sc->num_slots; i++) 372241600Sgonzo sdhci_generic_suspend(&sc->slots[i]); 373241600Sgonzo return (0); 374241600Sgonzo} 375241600Sgonzo 376241600Sgonzostatic int 377241600Sgonzosdhci_pci_resume(device_t dev) 378241600Sgonzo{ 379241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 380241600Sgonzo int i; 381241600Sgonzo 382241600Sgonzo for (i = 0; i < sc->num_slots; i++) 383241600Sgonzo sdhci_generic_resume(&sc->slots[i]); 384241600Sgonzo return (bus_generic_resume(dev)); 385241600Sgonzo} 386241600Sgonzo 387241600Sgonzo 388241600Sgonzostatic void 389241600Sgonzosdhci_pci_intr(void *arg) 390241600Sgonzo{ 391241600Sgonzo struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 392241600Sgonzo int i; 393241600Sgonzo 394241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 395241600Sgonzo struct sdhci_slot *slot = &sc->slots[i]; 396241600Sgonzo sdhci_generic_intr(slot); 397241600Sgonzo } 398241600Sgonzo} 399241600Sgonzo 400241600Sgonzostatic device_method_t sdhci_methods[] = { 401241600Sgonzo /* device_if */ 402241600Sgonzo DEVMETHOD(device_probe, sdhci_pci_probe), 403241600Sgonzo DEVMETHOD(device_attach, sdhci_pci_attach), 404241600Sgonzo DEVMETHOD(device_detach, sdhci_pci_detach), 405241600Sgonzo DEVMETHOD(device_suspend, sdhci_pci_suspend), 406241600Sgonzo DEVMETHOD(device_resume, sdhci_pci_resume), 407241600Sgonzo 408241600Sgonzo /* Bus interface */ 409241600Sgonzo DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 410241600Sgonzo DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 411241600Sgonzo 412241600Sgonzo /* mmcbr_if */ 413241600Sgonzo DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 414241600Sgonzo DEVMETHOD(mmcbr_request, sdhci_generic_request), 415241600Sgonzo DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 416241600Sgonzo DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 417241600Sgonzo DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 418241600Sgonzo 419241600Sgonzo /* SDHCI registers accessors */ 420241600Sgonzo DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 421241600Sgonzo DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 422241600Sgonzo DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 423241600Sgonzo DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 424241600Sgonzo DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 425241600Sgonzo DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 426241600Sgonzo DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 427241600Sgonzo DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 428241600Sgonzo 429246128Ssbz DEVMETHOD_END 430241600Sgonzo}; 431241600Sgonzo 432241600Sgonzostatic driver_t sdhci_pci_driver = { 433241600Sgonzo "sdhci_pci", 434241600Sgonzo sdhci_methods, 435241600Sgonzo sizeof(struct sdhci_pci_softc), 436241600Sgonzo}; 437241600Sgonzostatic devclass_t sdhci_pci_devclass; 438241600Sgonzo 439241600SgonzoDRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, 0, 0); 440241600SgonzoMODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 441