sdhci_pci.c revision 241600 
1/*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci_pci.c 241600 2012-10-16 01:10:43Z gonzo $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/lock.h>
35#include <sys/module.h>
36#include <sys/mutex.h>
37#include <sys/resource.h>
38#include <sys/rman.h>
39#include <sys/sysctl.h>
40#include <sys/taskqueue.h>
41
42#include <dev/pci/pcireg.h>
43#include <dev/pci/pcivar.h>
44
45#include <machine/bus.h>
46#include <machine/resource.h>
47#include <machine/stdarg.h>
48
49#include <dev/mmc/bridge.h>
50#include <dev/mmc/mmcreg.h>
51#include <dev/mmc/mmcbrvar.h>
52
53#include "sdhci.h"
54#include "mmcbr_if.h"
55#include "sdhci_if.h"
56
57/*
58 * PCI registers
59 */
60
61#define PCI_SDHCI_IFPIO			0x00
62#define PCI_SDHCI_IFDMA			0x01
63#define PCI_SDHCI_IFVENDOR		0x02
64
65#define PCI_SLOT_INFO			0x40	/* 8 bits */
66#define  PCI_SLOT_INFO_SLOTS(x)		(((x >> 4) & 7) + 1)
67#define  PCI_SLOT_INFO_FIRST_BAR(x)	((x) & 7)
68
69/*
70 * RICOH specific PCI registers
71 */
72#define	SDHC_PCI_MODE_KEY		0xf9
73#define	SDHC_PCI_MODE			0x150
74#define	SDHC_PCI_MODE_SD20		0x10
75#define	SDHC_PCI_BASE_FREQ_KEY		0xfc
76#define	SDHC_PCI_BASE_FREQ		0xe1
77
78static const struct sdhci_device {
79	uint32_t	model;
80	uint16_t	subvendor;
81	char		*desc;
82	u_int		quirks;
83} sdhci_devices[] = {
84	{ 0x08221180, 	0xffff,	"RICOH R5C822 SD",
85	    SDHCI_QUIRK_FORCE_DMA },
86	{ 0xe8221180, 	0xffff,	"RICOH SD",
87	    SDHCI_QUIRK_FORCE_DMA },
88	{ 0xe8231180, 	0xffff,	"RICOH R5CE823 SD",
89	    SDHCI_QUIRK_LOWER_FREQUENCY },
90	{ 0x8034104c, 	0xffff, "TI XX21/XX11 SD",
91	    SDHCI_QUIRK_FORCE_DMA },
92	{ 0x05501524, 	0xffff, "ENE CB712 SD",
93	    SDHCI_QUIRK_BROKEN_TIMINGS },
94	{ 0x05511524, 	0xffff, "ENE CB712 SD 2",
95	    SDHCI_QUIRK_BROKEN_TIMINGS },
96	{ 0x07501524, 	0xffff, "ENE CB714 SD",
97	    SDHCI_QUIRK_RESET_ON_IOS |
98	    SDHCI_QUIRK_BROKEN_TIMINGS },
99	{ 0x07511524, 	0xffff, "ENE CB714 SD 2",
100	    SDHCI_QUIRK_RESET_ON_IOS |
101	    SDHCI_QUIRK_BROKEN_TIMINGS },
102	{ 0x410111ab, 	0xffff, "Marvell CaFe SD",
103	    SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
104	{ 0x2381197B, 	0xffff,	"JMicron JMB38X SD",
105	    SDHCI_QUIRK_32BIT_DMA_SIZE |
106	    SDHCI_QUIRK_RESET_AFTER_REQUEST },
107	{ 0,		0xffff,	NULL,
108	    0 }
109};
110
111struct sdhci_pci_softc {
112	device_t	dev;		/* Controller device */
113	u_int		quirks;		/* Chip specific quirks */
114	struct resource *irq_res;	/* IRQ resource */
115	int 		irq_rid;
116	void 		*intrhand;	/* Interrupt handle */
117
118	int		num_slots;	/* Number of slots on this controller */
119	struct sdhci_slot slots[6];
120	struct resource	*mem_res[6];	/* Memory resource */
121	int		mem_rid[6];
122};
123
124static SYSCTL_NODE(_hw, OID_AUTO, sdhci_pci, CTLFLAG_RD, 0, "sdhci PCI driver");
125
126int	sdhci_pci_debug;
127TUNABLE_INT("hw.sdhci_pci.debug", &sdhci_pci_debug);
128SYSCTL_INT(_hw_sdhci_pci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_pci_debug, 0, "Debug level");
129
130static uint8_t
131sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
132{
133	struct sdhci_pci_softc *sc = device_get_softc(dev);
134
135	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
136	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
137	return bus_read_1(sc->mem_res[slot->num], off);
138}
139
140static void
141sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
142{
143	struct sdhci_pci_softc *sc = device_get_softc(dev);
144
145	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
146	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
147	bus_write_1(sc->mem_res[slot->num], off, val);
148}
149
150static uint16_t
151sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
152{
153	struct sdhci_pci_softc *sc = device_get_softc(dev);
154
155	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
156	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
157	return bus_read_2(sc->mem_res[slot->num], off);
158}
159
160static void
161sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
162{
163	struct sdhci_pci_softc *sc = device_get_softc(dev);
164
165	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
166	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
167	bus_write_2(sc->mem_res[slot->num], off, val);
168}
169
170static uint32_t
171sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
172{
173	struct sdhci_pci_softc *sc = device_get_softc(dev);
174
175	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
176	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
177	return bus_read_4(sc->mem_res[slot->num], off);
178}
179
180static void
181sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
182{
183	struct sdhci_pci_softc *sc = device_get_softc(dev);
184
185	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
186	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
187	bus_write_4(sc->mem_res[slot->num], off, val);
188}
189
190static void
191sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot,
192    bus_size_t off, uint32_t *data, bus_size_t count)
193{
194	struct sdhci_pci_softc *sc = device_get_softc(dev);
195
196	bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
197}
198
199static void
200sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot,
201    bus_size_t off, uint32_t *data, bus_size_t count)
202{
203	struct sdhci_pci_softc *sc = device_get_softc(dev);
204
205	bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
206}
207
208static void sdhci_pci_intr(void *arg);
209
210static void
211sdhci_lower_frequency(device_t dev)
212{
213
214	/* Enable SD2.0 mode. */
215	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
216	pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
217	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
218
219	/*
220	 * Some SD/MMC cards don't work with the default base
221	 * clock frequency of 200MHz.  Lower it to 50Hz.
222	 */
223	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
224	pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
225	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
226}
227
228static int
229sdhci_pci_probe(device_t dev)
230{
231	uint32_t model;
232	uint16_t subvendor;
233	uint8_t class, subclass;
234	int i, result;
235
236	model = (uint32_t)pci_get_device(dev) << 16;
237	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
238	subvendor = pci_get_subvendor(dev);
239	class = pci_get_class(dev);
240	subclass = pci_get_subclass(dev);
241
242	result = ENXIO;
243	for (i = 0; sdhci_devices[i].model != 0; i++) {
244		if (sdhci_devices[i].model == model &&
245		    (sdhci_devices[i].subvendor == 0xffff ||
246		    sdhci_devices[i].subvendor == subvendor)) {
247			device_set_desc(dev, sdhci_devices[i].desc);
248			result = BUS_PROBE_DEFAULT;
249			break;
250		}
251	}
252	if (result == ENXIO && class == PCIC_BASEPERIPH &&
253	    subclass == PCIS_BASEPERIPH_SDHC) {
254		device_set_desc(dev, "Generic SD HCI");
255		result = BUS_PROBE_GENERIC;
256	}
257
258	return (result);
259}
260
261static int
262sdhci_pci_attach(device_t dev)
263{
264	struct sdhci_pci_softc *sc = device_get_softc(dev);
265	uint32_t model;
266	uint16_t subvendor;
267	uint8_t class, subclass, progif;
268	int err, slots, bar, i;
269
270	sc->dev = dev;
271	model = (uint32_t)pci_get_device(dev) << 16;
272	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
273	subvendor = pci_get_subvendor(dev);
274	class = pci_get_class(dev);
275	subclass = pci_get_subclass(dev);
276	progif = pci_get_progif(dev);
277	/* Apply chip specific quirks. */
278	for (i = 0; sdhci_devices[i].model != 0; i++) {
279		if (sdhci_devices[i].model == model &&
280		    (sdhci_devices[i].subvendor == 0xffff ||
281		    sdhci_devices[i].subvendor == subvendor)) {
282			sc->quirks = sdhci_devices[i].quirks;
283			break;
284		}
285	}
286	/* Some controllers need to be bumped into the right mode. */
287	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
288		sdhci_lower_frequency(dev);
289	/* Read slots info from PCI registers. */
290	slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
291	bar = PCI_SLOT_INFO_FIRST_BAR(slots);
292	slots = PCI_SLOT_INFO_SLOTS(slots);
293	if (slots > 6 || bar > 5) {
294		device_printf(dev, "Incorrect slots information (%d, %d).\n",
295		    slots, bar);
296		return (EINVAL);
297	}
298	/* Allocate IRQ. */
299	sc->irq_rid = 0;
300	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
301	    RF_SHAREABLE | RF_ACTIVE);
302	if (sc->irq_res == NULL) {
303		device_printf(dev, "Can't allocate IRQ\n");
304		return (ENOMEM);
305	}
306	/* Scan all slots. */
307	for (i = 0; i < slots; i++) {
308		struct sdhci_slot *slot = &sc->slots[sc->num_slots];
309
310		/* Allocate memory. */
311		sc->mem_rid[i] = PCIR_BAR(bar + i);
312		sc->mem_res[i] = bus_alloc_resource(dev,
313		    SYS_RES_MEMORY, &(sc->mem_rid[i]), 0ul, ~0ul, 0x100, RF_ACTIVE);
314		if (sc->mem_res[i] == NULL) {
315			device_printf(dev, "Can't allocate memory for slot %d\n", i);
316			continue;
317		}
318
319		if (sdhci_init_slot(dev, slot, i) != 0)
320			continue;
321
322
323		sc->num_slots++;
324	}
325	device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
326	/* Activate the interrupt */
327	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
328	    NULL, sdhci_pci_intr, sc, &sc->intrhand);
329	if (err)
330		device_printf(dev, "Can't setup IRQ\n");
331	pci_enable_busmaster(dev);
332	/* Process cards detection. */
333	for (i = 0; i < sc->num_slots; i++) {
334		struct sdhci_slot *slot = &sc->slots[i];
335
336		sdhci_start_slot(slot);
337	}
338
339	return (0);
340}
341
342static int
343sdhci_pci_detach(device_t dev)
344{
345	struct sdhci_pci_softc *sc = device_get_softc(dev);
346	int i;
347
348	bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
349	bus_release_resource(dev, SYS_RES_IRQ,
350	    sc->irq_rid, sc->irq_res);
351
352	for (i = 0; i < sc->num_slots; i++) {
353		struct sdhci_slot *slot = &sc->slots[i];
354
355		sdhci_cleanup_slot(slot);
356		bus_release_resource(dev, SYS_RES_MEMORY,
357		    sc->mem_rid[i], sc->mem_res[i]);
358	}
359	return (0);
360}
361
362static int
363sdhci_pci_suspend(device_t dev)
364{
365	struct sdhci_pci_softc *sc = device_get_softc(dev);
366	int i, err;
367
368	err = bus_generic_suspend(dev);
369	if (err)
370		return (err);
371	for (i = 0; i < sc->num_slots; i++)
372		 sdhci_generic_suspend(&sc->slots[i]);
373	return (0);
374}
375
376static int
377sdhci_pci_resume(device_t dev)
378{
379	struct sdhci_pci_softc *sc = device_get_softc(dev);
380	int i;
381
382	for (i = 0; i < sc->num_slots; i++)
383		sdhci_generic_resume(&sc->slots[i]);
384	return (bus_generic_resume(dev));
385}
386
387
388static void
389sdhci_pci_intr(void *arg)
390{
391	struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
392	int i;
393
394	for (i = 0; i < sc->num_slots; i++) {
395		struct sdhci_slot *slot = &sc->slots[i];
396		sdhci_generic_intr(slot);
397	}
398}
399
400static device_method_t sdhci_methods[] = {
401	/* device_if */
402	DEVMETHOD(device_probe, sdhci_pci_probe),
403	DEVMETHOD(device_attach, sdhci_pci_attach),
404	DEVMETHOD(device_detach, sdhci_pci_detach),
405	DEVMETHOD(device_suspend, sdhci_pci_suspend),
406	DEVMETHOD(device_resume, sdhci_pci_resume),
407
408	/* Bus interface */
409	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
410	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
411
412	/* mmcbr_if */
413	DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
414	DEVMETHOD(mmcbr_request, sdhci_generic_request),
415	DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
416	DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
417	DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
418
419	/* SDHCI registers accessors */
420	DEVMETHOD(sdhci_read_1,		sdhci_pci_read_1),
421	DEVMETHOD(sdhci_read_2,		sdhci_pci_read_2),
422	DEVMETHOD(sdhci_read_4,		sdhci_pci_read_4),
423	DEVMETHOD(sdhci_read_multi_4,	sdhci_pci_read_multi_4),
424	DEVMETHOD(sdhci_write_1,	sdhci_pci_write_1),
425	DEVMETHOD(sdhci_write_2,	sdhci_pci_write_2),
426	DEVMETHOD(sdhci_write_4,	sdhci_pci_write_4),
427	DEVMETHOD(sdhci_write_multi_4,	sdhci_pci_write_multi_4),
428
429	{0, 0},
430};
431
432static driver_t sdhci_pci_driver = {
433	"sdhci_pci",
434	sdhci_methods,
435	sizeof(struct sdhci_pci_softc),
436};
437static devclass_t sdhci_pci_devclass;
438
439DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, 0, 0);
440MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
441