sdhci.c revision 254423
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci.c 254423 2013-08-16 19:40:00Z ian $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/stdarg.h> 45 46#include <dev/mmc/bridge.h> 47#include <dev/mmc/mmcreg.h> 48#include <dev/mmc/mmcbrvar.h> 49 50#include "mmcbr_if.h" 51#include "sdhci.h" 52#include "sdhci_if.h" 53 54struct sdhci_softc; 55 56struct sdhci_softc { 57 device_t dev; /* Controller device */ 58 struct resource *irq_res; /* IRQ resource */ 59 int irq_rid; 60 void *intrhand; /* Interrupt handle */ 61 62 int num_slots; /* Number of slots on this controller */ 63 struct sdhci_slot slots[6]; 64}; 65 66static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 67 68int sdhci_debug = 0; 69TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 70SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 71 72#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 73#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 74#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 75#define RD_MULTI_4(slot, off, ptr, count) \ 76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 77 78#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 79#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 80#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 81#define WR_MULTI_4(slot, off, ptr, count) \ 82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 83 84static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 85static void sdhci_start(struct sdhci_slot *slot); 86static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 87 88static void sdhci_card_task(void *, int); 89 90/* helper routines */ 91#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93#define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99#define SDHCI_DEFAULT_MAX_FREQ 50 100 101#define SDHCI_200_MAX_DIVIDER 256 102#define SDHCI_300_MAX_DIVIDER 2046 103 104static void 105sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 106{ 107 if (error != 0) { 108 printf("getaddr: error %d\n", error); 109 return; 110 } 111 *(bus_addr_t *)arg = segs[0].ds_addr; 112} 113 114static int 115slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 116{ 117 va_list ap; 118 int retval; 119 120 retval = printf("%s-slot%d: ", 121 device_get_nameunit(slot->bus), slot->num); 122 123 va_start(ap, fmt); 124 retval += vprintf(fmt, ap); 125 va_end(ap); 126 return (retval); 127} 128 129static void 130sdhci_dumpregs(struct sdhci_slot *slot) 131{ 132 slot_printf(slot, 133 "============== REGISTER DUMP ==============\n"); 134 135 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 136 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 137 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 138 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 139 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 140 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 141 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 142 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 143 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 144 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 145 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 146 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 147 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 148 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 149 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 150 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 151 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 152 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 153 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 154 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 155 156 slot_printf(slot, 157 "===========================================\n"); 158} 159 160static void 161sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 162{ 163 int timeout; 164 uint8_t res; 165 166 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 167 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 168 SDHCI_CARD_PRESENT)) 169 return; 170 } 171 172 /* Some controllers need this kick or reset won't work. */ 173 if ((mask & SDHCI_RESET_ALL) == 0 && 174 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 175 uint32_t clock; 176 177 /* This is to force an update */ 178 clock = slot->clock; 179 slot->clock = 0; 180 sdhci_set_clock(slot, clock); 181 } 182 183 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 184 185 if (mask & SDHCI_RESET_ALL) { 186 slot->clock = 0; 187 slot->power = 0; 188 } 189 190 /* Wait max 100 ms */ 191 timeout = 100; 192 /* Controller clears the bits when it's done */ 193 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 194 if (timeout == 0) { 195 slot_printf(slot, 196 "Reset 0x%x never completed - 0x%x.\n", 197 (int)mask, (int)res); 198 sdhci_dumpregs(slot); 199 return; 200 } 201 timeout--; 202 DELAY(1000); 203 } 204} 205 206static void 207sdhci_init(struct sdhci_slot *slot) 208{ 209 210 sdhci_reset(slot, SDHCI_RESET_ALL); 211 212 /* Enable interrupts. */ 213 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 214 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 215 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 216 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 217 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 218 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 219 SDHCI_INT_ACMD12ERR; 220 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 221 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 222} 223 224static void 225sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 226{ 227 uint32_t res; 228 uint16_t clk; 229 uint16_t div; 230 int timeout; 231 232 if (clock == slot->clock) 233 return; 234 slot->clock = clock; 235 236 /* Turn off the clock. */ 237 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 238 /* If no clock requested - left it so. */ 239 if (clock == 0) 240 return; 241 242 /* Recalculate timeout clock frequency based on the new sd clock. */ 243 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 244 slot->timeout_clk = slot->clock / 1000; 245 246 if (slot->version < SDHCI_SPEC_300) { 247 /* Looking for highest freq <= clock. */ 248 res = slot->max_clk; 249 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 250 if (res <= clock) 251 break; 252 res >>= 1; 253 } 254 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 255 div >>= 1; 256 } 257 else { 258 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 259 if (clock >= slot->max_clk) 260 div = 0; 261 else { 262 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 263 if ((slot->max_clk / div) <= clock) 264 break; 265 } 266 } 267 div >>= 1; 268 } 269 270 if (bootverbose || sdhci_debug) 271 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 272 div, clock, slot->max_clk); 273 274 /* Now we have got divider, set it. */ 275 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 276 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 277 << SDHCI_DIVIDER_HI_SHIFT; 278 279 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 280 /* Enable clock. */ 281 clk |= SDHCI_CLOCK_INT_EN; 282 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 283 /* Wait up to 10 ms until it stabilize. */ 284 timeout = 10; 285 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 286 & SDHCI_CLOCK_INT_STABLE)) { 287 if (timeout == 0) { 288 slot_printf(slot, 289 "Internal clock never stabilised.\n"); 290 sdhci_dumpregs(slot); 291 return; 292 } 293 timeout--; 294 DELAY(1000); 295 } 296 /* Pass clock signal to the bus. */ 297 clk |= SDHCI_CLOCK_CARD_EN; 298 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 299} 300 301static void 302sdhci_set_power(struct sdhci_slot *slot, u_char power) 303{ 304 uint8_t pwr; 305 306 if (slot->power == power) 307 return; 308 309 slot->power = power; 310 311 /* Turn off the power. */ 312 pwr = 0; 313 WR1(slot, SDHCI_POWER_CONTROL, pwr); 314 /* If power down requested - left it so. */ 315 if (power == 0) 316 return; 317 /* Set voltage. */ 318 switch (1 << power) { 319 case MMC_OCR_LOW_VOLTAGE: 320 pwr |= SDHCI_POWER_180; 321 break; 322 case MMC_OCR_290_300: 323 case MMC_OCR_300_310: 324 pwr |= SDHCI_POWER_300; 325 break; 326 case MMC_OCR_320_330: 327 case MMC_OCR_330_340: 328 pwr |= SDHCI_POWER_330; 329 break; 330 } 331 WR1(slot, SDHCI_POWER_CONTROL, pwr); 332 /* Turn on the power. */ 333 pwr |= SDHCI_POWER_ON; 334 WR1(slot, SDHCI_POWER_CONTROL, pwr); 335} 336 337static void 338sdhci_read_block_pio(struct sdhci_slot *slot) 339{ 340 uint32_t data; 341 char *buffer; 342 size_t left; 343 344 buffer = slot->curcmd->data->data; 345 buffer += slot->offset; 346 /* Transfer one block at a time. */ 347 left = min(512, slot->curcmd->data->len - slot->offset); 348 slot->offset += left; 349 350 /* If we are too fast, broken controllers return zeroes. */ 351 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 352 DELAY(10); 353 /* Handle unalligned and alligned buffer cases. */ 354 if ((intptr_t)buffer & 3) { 355 while (left > 3) { 356 data = RD4(slot, SDHCI_BUFFER); 357 buffer[0] = data; 358 buffer[1] = (data >> 8); 359 buffer[2] = (data >> 16); 360 buffer[3] = (data >> 24); 361 buffer += 4; 362 left -= 4; 363 } 364 } else { 365 RD_MULTI_4(slot, SDHCI_BUFFER, 366 (uint32_t *)buffer, left >> 2); 367 left &= 3; 368 } 369 /* Handle uneven size case. */ 370 if (left > 0) { 371 data = RD4(slot, SDHCI_BUFFER); 372 while (left > 0) { 373 *(buffer++) = data; 374 data >>= 8; 375 left--; 376 } 377 } 378} 379 380static void 381sdhci_write_block_pio(struct sdhci_slot *slot) 382{ 383 uint32_t data = 0; 384 char *buffer; 385 size_t left; 386 387 buffer = slot->curcmd->data->data; 388 buffer += slot->offset; 389 /* Transfer one block at a time. */ 390 left = min(512, slot->curcmd->data->len - slot->offset); 391 slot->offset += left; 392 393 /* Handle unalligned and alligned buffer cases. */ 394 if ((intptr_t)buffer & 3) { 395 while (left > 3) { 396 data = buffer[0] + 397 (buffer[1] << 8) + 398 (buffer[2] << 16) + 399 (buffer[3] << 24); 400 left -= 4; 401 buffer += 4; 402 WR4(slot, SDHCI_BUFFER, data); 403 } 404 } else { 405 WR_MULTI_4(slot, SDHCI_BUFFER, 406 (uint32_t *)buffer, left >> 2); 407 left &= 3; 408 } 409 /* Handle uneven size case. */ 410 if (left > 0) { 411 while (left > 0) { 412 data <<= 8; 413 data += *(buffer++); 414 left--; 415 } 416 WR4(slot, SDHCI_BUFFER, data); 417 } 418} 419 420static void 421sdhci_transfer_pio(struct sdhci_slot *slot) 422{ 423 424 /* Read as many blocks as possible. */ 425 if (slot->curcmd->data->flags & MMC_DATA_READ) { 426 while (RD4(slot, SDHCI_PRESENT_STATE) & 427 SDHCI_DATA_AVAILABLE) { 428 sdhci_read_block_pio(slot); 429 if (slot->offset >= slot->curcmd->data->len) 430 break; 431 } 432 } else { 433 while (RD4(slot, SDHCI_PRESENT_STATE) & 434 SDHCI_SPACE_AVAILABLE) { 435 sdhci_write_block_pio(slot); 436 if (slot->offset >= slot->curcmd->data->len) 437 break; 438 } 439 } 440} 441 442static void 443sdhci_card_delay(void *arg) 444{ 445 struct sdhci_slot *slot = arg; 446 447 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 448} 449 450static void 451sdhci_card_task(void *arg, int pending) 452{ 453 struct sdhci_slot *slot = arg; 454 455 SDHCI_LOCK(slot); 456 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 457 if (slot->dev == NULL) { 458 /* If card is present - attach mmc bus. */ 459 slot->dev = device_add_child(slot->bus, "mmc", -1); 460 device_set_ivars(slot->dev, slot); 461 SDHCI_UNLOCK(slot); 462 device_probe_and_attach(slot->dev); 463 } else 464 SDHCI_UNLOCK(slot); 465 } else { 466 if (slot->dev != NULL) { 467 /* If no card present - detach mmc bus. */ 468 device_t d = slot->dev; 469 slot->dev = NULL; 470 SDHCI_UNLOCK(slot); 471 device_delete_child(slot->bus, d); 472 } else 473 SDHCI_UNLOCK(slot); 474 } 475} 476 477int 478sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 479{ 480 uint32_t caps; 481 int err; 482 483 SDHCI_LOCK_INIT(slot); 484 slot->num = num; 485 slot->bus = dev; 486 487 /* Allocate DMA tag. */ 488 err = bus_dma_tag_create(bus_get_dma_tag(dev), 489 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 490 BUS_SPACE_MAXADDR, NULL, NULL, 491 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 492 BUS_DMA_ALLOCNOW, NULL, NULL, 493 &slot->dmatag); 494 if (err != 0) { 495 device_printf(dev, "Can't create DMA tag\n"); 496 SDHCI_LOCK_DESTROY(slot); 497 return (err); 498 } 499 /* Allocate DMA memory. */ 500 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 501 BUS_DMA_NOWAIT, &slot->dmamap); 502 if (err != 0) { 503 device_printf(dev, "Can't alloc DMA memory\n"); 504 SDHCI_LOCK_DESTROY(slot); 505 return (err); 506 } 507 /* Map the memory. */ 508 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 509 (void *)slot->dmamem, DMA_BLOCK_SIZE, 510 sdhci_getaddr, &slot->paddr, 0); 511 if (err != 0 || slot->paddr == 0) { 512 device_printf(dev, "Can't load DMA memory\n"); 513 SDHCI_LOCK_DESTROY(slot); 514 if(err) 515 return (err); 516 else 517 return (EFAULT); 518 } 519 520 /* Initialize slot. */ 521 sdhci_init(slot); 522 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 523 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 524 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 525 caps = slot->caps; 526 else 527 caps = RD4(slot, SDHCI_CAPABILITIES); 528 /* Calculate base clock frequency. */ 529 if (slot->version >= SDHCI_SPEC_300) 530 slot->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) 531 >> SDHCI_CLOCK_BASE_SHIFT; 532 else 533 slot->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) 534 >> SDHCI_CLOCK_BASE_SHIFT; 535 if (slot->max_clk == 0) { 536 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ; 537 device_printf(dev, "Hardware doesn't specify base clock " 538 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 539 } 540 slot->max_clk *= 1000000; 541 /* Calculate timeout clock frequency. */ 542 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 543 slot->timeout_clk = slot->max_clk / 1000; 544 } else { 545 slot->timeout_clk = 546 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 547 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 548 slot->timeout_clk *= 1000; 549 } 550 551 if (slot->timeout_clk == 0) { 552 device_printf(dev, "Hardware doesn't specify timeout clock " 553 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 554 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 555 } 556 557 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 558 slot->host.f_max = slot->max_clk; 559 slot->host.host_ocr = 0; 560 if (caps & SDHCI_CAN_VDD_330) 561 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 562 if (caps & SDHCI_CAN_VDD_300) 563 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 564 if (caps & SDHCI_CAN_VDD_180) 565 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 566 if (slot->host.host_ocr == 0) { 567 device_printf(dev, "Hardware doesn't report any " 568 "support voltages.\n"); 569 } 570 slot->host.caps = MMC_CAP_4_BIT_DATA; 571 if (caps & SDHCI_CAN_DO_HISPD) 572 slot->host.caps |= MMC_CAP_HSPEED; 573 /* Decide if we have usable DMA. */ 574 if (caps & SDHCI_CAN_DO_DMA) 575 slot->opt |= SDHCI_HAVE_DMA; 576 577 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 578 slot->opt &= ~SDHCI_HAVE_DMA; 579 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 580 slot->opt |= SDHCI_HAVE_DMA; 581 582 /* 583 * Use platform-provided transfer backend 584 * with PIO as a fallback mechanism 585 */ 586 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 587 slot->opt &= ~SDHCI_HAVE_DMA; 588 589 if (bootverbose || sdhci_debug) { 590 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 591 slot->max_clk / 1000000, 592 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 593 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 594 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 595 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 596 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 597 sdhci_dumpregs(slot); 598 } 599 600 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 601 callout_init(&slot->card_callout, 1); 602 return (0); 603} 604 605void 606sdhci_start_slot(struct sdhci_slot *slot) 607{ 608 sdhci_card_task(slot, 0); 609} 610 611int 612sdhci_cleanup_slot(struct sdhci_slot *slot) 613{ 614 device_t d; 615 616 callout_drain(&slot->card_callout); 617 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 618 619 SDHCI_LOCK(slot); 620 d = slot->dev; 621 slot->dev = NULL; 622 SDHCI_UNLOCK(slot); 623 if (d != NULL) 624 device_delete_child(slot->bus, d); 625 626 SDHCI_LOCK(slot); 627 sdhci_reset(slot, SDHCI_RESET_ALL); 628 SDHCI_UNLOCK(slot); 629 bus_dmamap_unload(slot->dmatag, slot->dmamap); 630 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 631 bus_dma_tag_destroy(slot->dmatag); 632 633 SDHCI_LOCK_DESTROY(slot); 634 635 return (0); 636} 637 638int 639sdhci_generic_suspend(struct sdhci_slot *slot) 640{ 641 sdhci_reset(slot, SDHCI_RESET_ALL); 642 643 return (0); 644} 645 646int 647sdhci_generic_resume(struct sdhci_slot *slot) 648{ 649 sdhci_init(slot); 650 651 return (0); 652} 653 654uint32_t 655sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 656{ 657 if (slot->version >= SDHCI_SPEC_300) 658 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 659 else 660 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 661} 662 663int 664sdhci_generic_update_ios(device_t brdev, device_t reqdev) 665{ 666 struct sdhci_slot *slot = device_get_ivars(reqdev); 667 struct mmc_ios *ios = &slot->host.ios; 668 669 SDHCI_LOCK(slot); 670 /* Do full reset on bus power down to clear from any state. */ 671 if (ios->power_mode == power_off) { 672 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 673 sdhci_init(slot); 674 } 675 /* Configure the bus. */ 676 sdhci_set_clock(slot, ios->clock); 677 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 678 if (ios->bus_width == bus_width_4) 679 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 680 else 681 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 682 if (ios->timing == bus_timing_hs) 683 slot->hostctrl |= SDHCI_CTRL_HISPD; 684 else 685 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 686 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 687 /* Some controllers like reset after bus changes. */ 688 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 689 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 690 691 SDHCI_UNLOCK(slot); 692 return (0); 693} 694 695static void 696sdhci_set_transfer_mode(struct sdhci_slot *slot, 697 struct mmc_data *data) 698{ 699 uint16_t mode; 700 701 if (data == NULL) 702 return; 703 704 mode = SDHCI_TRNS_BLK_CNT_EN; 705 if (data->len > 512) 706 mode |= SDHCI_TRNS_MULTI; 707 if (data->flags & MMC_DATA_READ) 708 mode |= SDHCI_TRNS_READ; 709 if (slot->req->stop) 710 mode |= SDHCI_TRNS_ACMD12; 711 if (slot->flags & SDHCI_USE_DMA) 712 mode |= SDHCI_TRNS_DMA; 713 714 WR2(slot, SDHCI_TRANSFER_MODE, mode); 715} 716 717static void 718sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 719{ 720 struct mmc_request *req = slot->req; 721 int flags, timeout; 722 uint32_t mask, state; 723 724 slot->curcmd = cmd; 725 slot->cmd_done = 0; 726 727 cmd->error = MMC_ERR_NONE; 728 729 /* This flags combination is not supported by controller. */ 730 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 731 slot_printf(slot, "Unsupported response type!\n"); 732 cmd->error = MMC_ERR_FAILED; 733 slot->req = NULL; 734 slot->curcmd = NULL; 735 req->done(req); 736 return; 737 } 738 739 /* Read controller present state. */ 740 state = RD4(slot, SDHCI_PRESENT_STATE); 741 /* Do not issue command if there is no card, clock or power. 742 * Controller will not detect timeout without clock active. */ 743 if ((state & SDHCI_CARD_PRESENT) == 0 || 744 slot->power == 0 || 745 slot->clock == 0) { 746 cmd->error = MMC_ERR_FAILED; 747 slot->req = NULL; 748 slot->curcmd = NULL; 749 req->done(req); 750 return; 751 } 752 /* Always wait for free CMD bus. */ 753 mask = SDHCI_CMD_INHIBIT; 754 /* Wait for free DAT if we have data or busy signal. */ 755 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 756 mask |= SDHCI_DAT_INHIBIT; 757 /* We shouldn't wait for DAT for stop commands. */ 758 if (cmd == slot->req->stop) 759 mask &= ~SDHCI_DAT_INHIBIT; 760 /* Wait for bus no more then 10 ms. */ 761 timeout = 10; 762 while (state & mask) { 763 if (timeout == 0) { 764 slot_printf(slot, "Controller never released " 765 "inhibit bit(s).\n"); 766 sdhci_dumpregs(slot); 767 cmd->error = MMC_ERR_FAILED; 768 slot->req = NULL; 769 slot->curcmd = NULL; 770 req->done(req); 771 return; 772 } 773 timeout--; 774 DELAY(1000); 775 state = RD4(slot, SDHCI_PRESENT_STATE); 776 } 777 778 /* Prepare command flags. */ 779 if (!(cmd->flags & MMC_RSP_PRESENT)) 780 flags = SDHCI_CMD_RESP_NONE; 781 else if (cmd->flags & MMC_RSP_136) 782 flags = SDHCI_CMD_RESP_LONG; 783 else if (cmd->flags & MMC_RSP_BUSY) 784 flags = SDHCI_CMD_RESP_SHORT_BUSY; 785 else 786 flags = SDHCI_CMD_RESP_SHORT; 787 if (cmd->flags & MMC_RSP_CRC) 788 flags |= SDHCI_CMD_CRC; 789 if (cmd->flags & MMC_RSP_OPCODE) 790 flags |= SDHCI_CMD_INDEX; 791 if (cmd->data) 792 flags |= SDHCI_CMD_DATA; 793 if (cmd->opcode == MMC_STOP_TRANSMISSION) 794 flags |= SDHCI_CMD_TYPE_ABORT; 795 /* Prepare data. */ 796 sdhci_start_data(slot, cmd->data); 797 /* 798 * Interrupt aggregation: To reduce total number of interrupts 799 * group response interrupt with data interrupt when possible. 800 * If there going to be data interrupt, mask response one. 801 */ 802 if (slot->data_done == 0) { 803 WR4(slot, SDHCI_SIGNAL_ENABLE, 804 slot->intmask &= ~SDHCI_INT_RESPONSE); 805 } 806 /* Set command argument. */ 807 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 808 /* Set data transfer mode. */ 809 sdhci_set_transfer_mode(slot, cmd->data); 810 /* Start command. */ 811 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 812} 813 814static void 815sdhci_finish_command(struct sdhci_slot *slot) 816{ 817 int i; 818 819 slot->cmd_done = 1; 820 /* Interrupt aggregation: Restore command interrupt. 821 * Main restore point for the case when command interrupt 822 * happened first. */ 823 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 824 /* In case of error - reset host and return. */ 825 if (slot->curcmd->error) { 826 sdhci_reset(slot, SDHCI_RESET_CMD); 827 sdhci_reset(slot, SDHCI_RESET_DATA); 828 sdhci_start(slot); 829 return; 830 } 831 /* If command has response - fetch it. */ 832 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 833 if (slot->curcmd->flags & MMC_RSP_136) { 834 /* CRC is stripped so we need one byte shift. */ 835 uint8_t extra = 0; 836 for (i = 0; i < 4; i++) { 837 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 838 slot->curcmd->resp[3 - i] = (val << 8) + extra; 839 extra = val >> 24; 840 } 841 } else 842 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 843 } 844 /* If data ready - finish. */ 845 if (slot->data_done) 846 sdhci_start(slot); 847} 848 849static void 850sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 851{ 852 uint32_t target_timeout, current_timeout; 853 uint8_t div; 854 855 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 856 slot->data_done = 1; 857 return; 858 } 859 860 slot->data_done = 0; 861 862 /* Calculate and set data timeout.*/ 863 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 864 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 865 div = 0xE; 866 } else { 867 target_timeout = 1000000; 868 div = 0; 869 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 870 while (current_timeout < target_timeout && div < 0xE) { 871 ++div; 872 current_timeout <<= 1; 873 } 874 /* Compensate for an off-by-one error in the CaFe chip.*/ 875 if (div < 0xE && 876 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 877 ++div; 878 } 879 } 880 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 881 882 if (data == NULL) 883 return; 884 885 /* Use DMA if possible. */ 886 if ((slot->opt & SDHCI_HAVE_DMA)) 887 slot->flags |= SDHCI_USE_DMA; 888 /* If data is small, broken DMA may return zeroes instead of data, */ 889 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 890 (data->len <= 512)) 891 slot->flags &= ~SDHCI_USE_DMA; 892 /* Some controllers require even block sizes. */ 893 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 894 ((data->len) & 0x3)) 895 slot->flags &= ~SDHCI_USE_DMA; 896 /* Load DMA buffer. */ 897 if (slot->flags & SDHCI_USE_DMA) { 898 if (data->flags & MMC_DATA_READ) 899 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 900 else { 901 memcpy(slot->dmamem, data->data, 902 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 903 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 904 } 905 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 906 /* Interrupt aggregation: Mask border interrupt 907 * for the last page and unmask else. */ 908 if (data->len == DMA_BLOCK_SIZE) 909 slot->intmask &= ~SDHCI_INT_DMA_END; 910 else 911 slot->intmask |= SDHCI_INT_DMA_END; 912 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 913 } 914 /* Current data offset for both PIO and DMA. */ 915 slot->offset = 0; 916 /* Set block size and request IRQ on 4K border. */ 917 WR2(slot, SDHCI_BLOCK_SIZE, 918 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 919 /* Set block count. */ 920 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 921} 922 923void 924sdhci_finish_data(struct sdhci_slot *slot) 925{ 926 struct mmc_data *data = slot->curcmd->data; 927 928 slot->data_done = 1; 929 /* Interrupt aggregation: Restore command interrupt. 930 * Auxillary restore point for the case when data interrupt 931 * happened first. */ 932 if (!slot->cmd_done) { 933 WR4(slot, SDHCI_SIGNAL_ENABLE, 934 slot->intmask |= SDHCI_INT_RESPONSE); 935 } 936 /* Unload rest of data from DMA buffer. */ 937 if (slot->flags & SDHCI_USE_DMA) { 938 if (data->flags & MMC_DATA_READ) { 939 size_t left = data->len - slot->offset; 940 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 941 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 942 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 943 } else 944 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 945 } 946 /* If there was error - reset the host. */ 947 if (slot->curcmd->error) { 948 sdhci_reset(slot, SDHCI_RESET_CMD); 949 sdhci_reset(slot, SDHCI_RESET_DATA); 950 sdhci_start(slot); 951 return; 952 } 953 /* If we already have command response - finish. */ 954 if (slot->cmd_done) 955 sdhci_start(slot); 956} 957 958static void 959sdhci_start(struct sdhci_slot *slot) 960{ 961 struct mmc_request *req; 962 963 req = slot->req; 964 if (req == NULL) 965 return; 966 967 if (!(slot->flags & CMD_STARTED)) { 968 slot->flags |= CMD_STARTED; 969 sdhci_start_command(slot, req->cmd); 970 return; 971 } 972/* We don't need this until using Auto-CMD12 feature 973 if (!(slot->flags & STOP_STARTED) && req->stop) { 974 slot->flags |= STOP_STARTED; 975 sdhci_start_command(slot, req->stop); 976 return; 977 } 978*/ 979 if (sdhci_debug > 1) 980 slot_printf(slot, "result: %d\n", req->cmd->error); 981 if (!req->cmd->error && 982 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 983 sdhci_reset(slot, SDHCI_RESET_CMD); 984 sdhci_reset(slot, SDHCI_RESET_DATA); 985 } 986 987 /* We must be done -- bad idea to do this while locked? */ 988 slot->req = NULL; 989 slot->curcmd = NULL; 990 req->done(req); 991} 992 993int 994sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 995{ 996 struct sdhci_slot *slot = device_get_ivars(reqdev); 997 998 SDHCI_LOCK(slot); 999 if (slot->req != NULL) { 1000 SDHCI_UNLOCK(slot); 1001 return (EBUSY); 1002 } 1003 if (sdhci_debug > 1) { 1004 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1005 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1006 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1007 (req->cmd->data)?req->cmd->data->flags:0); 1008 } 1009 slot->req = req; 1010 slot->flags = 0; 1011 sdhci_start(slot); 1012 SDHCI_UNLOCK(slot); 1013 if (dumping) { 1014 while (slot->req != NULL) { 1015 sdhci_generic_intr(slot); 1016 DELAY(10); 1017 } 1018 } 1019 return (0); 1020} 1021 1022int 1023sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1024{ 1025 struct sdhci_slot *slot = device_get_ivars(reqdev); 1026 uint32_t val; 1027 1028 SDHCI_LOCK(slot); 1029 val = RD4(slot, SDHCI_PRESENT_STATE); 1030 SDHCI_UNLOCK(slot); 1031 return (!(val & SDHCI_WRITE_PROTECT)); 1032} 1033 1034int 1035sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1036{ 1037 struct sdhci_slot *slot = device_get_ivars(reqdev); 1038 int err = 0; 1039 1040 SDHCI_LOCK(slot); 1041 while (slot->bus_busy) 1042 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1043 slot->bus_busy++; 1044 /* Activate led. */ 1045 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1046 SDHCI_UNLOCK(slot); 1047 return (err); 1048} 1049 1050int 1051sdhci_generic_release_host(device_t brdev, device_t reqdev) 1052{ 1053 struct sdhci_slot *slot = device_get_ivars(reqdev); 1054 1055 SDHCI_LOCK(slot); 1056 /* Deactivate led. */ 1057 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1058 slot->bus_busy--; 1059 SDHCI_UNLOCK(slot); 1060 wakeup(slot); 1061 return (0); 1062} 1063 1064static void 1065sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1066{ 1067 1068 if (!slot->curcmd) { 1069 slot_printf(slot, "Got command interrupt 0x%08x, but " 1070 "there is no active command.\n", intmask); 1071 sdhci_dumpregs(slot); 1072 return; 1073 } 1074 if (intmask & SDHCI_INT_TIMEOUT) 1075 slot->curcmd->error = MMC_ERR_TIMEOUT; 1076 else if (intmask & SDHCI_INT_CRC) 1077 slot->curcmd->error = MMC_ERR_BADCRC; 1078 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1079 slot->curcmd->error = MMC_ERR_FIFO; 1080 1081 sdhci_finish_command(slot); 1082} 1083 1084static void 1085sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1086{ 1087 1088 if (!slot->curcmd) { 1089 slot_printf(slot, "Got data interrupt 0x%08x, but " 1090 "there is no active command.\n", intmask); 1091 sdhci_dumpregs(slot); 1092 return; 1093 } 1094 if (slot->curcmd->data == NULL && 1095 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1096 slot_printf(slot, "Got data interrupt 0x%08x, but " 1097 "there is no active data operation.\n", 1098 intmask); 1099 sdhci_dumpregs(slot); 1100 return; 1101 } 1102 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1103 slot->curcmd->error = MMC_ERR_TIMEOUT; 1104 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1105 slot->curcmd->error = MMC_ERR_BADCRC; 1106 if (slot->curcmd->data == NULL && 1107 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1108 SDHCI_INT_DMA_END))) { 1109 slot_printf(slot, "Got data interrupt 0x%08x, but " 1110 "there is busy-only command.\n", intmask); 1111 sdhci_dumpregs(slot); 1112 slot->curcmd->error = MMC_ERR_INVALID; 1113 } 1114 if (slot->curcmd->error) { 1115 /* No need to continue after any error. */ 1116 if (slot->flags & PLATFORM_DATA_STARTED) { 1117 slot->flags &= ~PLATFORM_DATA_STARTED; 1118 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1119 } else 1120 sdhci_finish_data(slot); 1121 return; 1122 } 1123 1124 /* Handle PIO interrupt. */ 1125 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1126 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1127 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1128 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1129 slot->flags |= PLATFORM_DATA_STARTED; 1130 } else 1131 sdhci_transfer_pio(slot); 1132 } 1133 /* Handle DMA border. */ 1134 if (intmask & SDHCI_INT_DMA_END) { 1135 struct mmc_data *data = slot->curcmd->data; 1136 size_t left; 1137 1138 /* Unload DMA buffer... */ 1139 left = data->len - slot->offset; 1140 if (data->flags & MMC_DATA_READ) { 1141 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1142 BUS_DMASYNC_POSTREAD); 1143 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1144 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1145 } else { 1146 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1147 BUS_DMASYNC_POSTWRITE); 1148 } 1149 /* ... and reload it again. */ 1150 slot->offset += DMA_BLOCK_SIZE; 1151 left = data->len - slot->offset; 1152 if (data->flags & MMC_DATA_READ) { 1153 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1154 BUS_DMASYNC_PREREAD); 1155 } else { 1156 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1157 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1158 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1159 BUS_DMASYNC_PREWRITE); 1160 } 1161 /* Interrupt aggregation: Mask border interrupt 1162 * for the last page. */ 1163 if (left == DMA_BLOCK_SIZE) { 1164 slot->intmask &= ~SDHCI_INT_DMA_END; 1165 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1166 } 1167 /* Restart DMA. */ 1168 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1169 } 1170 /* We have got all data. */ 1171 if (intmask & SDHCI_INT_DATA_END) { 1172 if (slot->flags & PLATFORM_DATA_STARTED) { 1173 slot->flags &= ~PLATFORM_DATA_STARTED; 1174 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1175 } else 1176 sdhci_finish_data(slot); 1177 } 1178} 1179 1180static void 1181sdhci_acmd_irq(struct sdhci_slot *slot) 1182{ 1183 uint16_t err; 1184 1185 err = RD4(slot, SDHCI_ACMD12_ERR); 1186 if (!slot->curcmd) { 1187 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1188 "there is no active command.\n", err); 1189 sdhci_dumpregs(slot); 1190 return; 1191 } 1192 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1193 sdhci_reset(slot, SDHCI_RESET_CMD); 1194} 1195 1196void 1197sdhci_generic_intr(struct sdhci_slot *slot) 1198{ 1199 uint32_t intmask; 1200 1201 SDHCI_LOCK(slot); 1202 /* Read slot interrupt status. */ 1203 intmask = RD4(slot, SDHCI_INT_STATUS); 1204 if (intmask == 0 || intmask == 0xffffffff) { 1205 SDHCI_UNLOCK(slot); 1206 return; 1207 } 1208 if (sdhci_debug > 2) 1209 slot_printf(slot, "Interrupt %#x\n", intmask); 1210 1211 /* Handle card presence interrupts. */ 1212 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1213 WR4(slot, SDHCI_INT_STATUS, intmask & 1214 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1215 1216 if (intmask & SDHCI_INT_CARD_REMOVE) { 1217 if (bootverbose || sdhci_debug) 1218 slot_printf(slot, "Card removed\n"); 1219 callout_stop(&slot->card_callout); 1220 taskqueue_enqueue(taskqueue_swi_giant, 1221 &slot->card_task); 1222 } 1223 if (intmask & SDHCI_INT_CARD_INSERT) { 1224 if (bootverbose || sdhci_debug) 1225 slot_printf(slot, "Card inserted\n"); 1226 callout_reset(&slot->card_callout, hz / 2, 1227 sdhci_card_delay, slot); 1228 } 1229 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1230 } 1231 /* Handle command interrupts. */ 1232 if (intmask & SDHCI_INT_CMD_MASK) { 1233 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1234 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1235 } 1236 /* Handle data interrupts. */ 1237 if (intmask & SDHCI_INT_DATA_MASK) { 1238 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1239 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1240 } 1241 /* Handle AutoCMD12 error interrupt. */ 1242 if (intmask & SDHCI_INT_ACMD12ERR) { 1243 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1244 sdhci_acmd_irq(slot); 1245 } 1246 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1247 intmask &= ~SDHCI_INT_ACMD12ERR; 1248 intmask &= ~SDHCI_INT_ERROR; 1249 /* Handle bus power interrupt. */ 1250 if (intmask & SDHCI_INT_BUS_POWER) { 1251 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1252 slot_printf(slot, 1253 "Card is consuming too much power!\n"); 1254 intmask &= ~SDHCI_INT_BUS_POWER; 1255 } 1256 /* The rest is unknown. */ 1257 if (intmask) { 1258 WR4(slot, SDHCI_INT_STATUS, intmask); 1259 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1260 intmask); 1261 sdhci_dumpregs(slot); 1262 } 1263 1264 SDHCI_UNLOCK(slot); 1265} 1266 1267int 1268sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1269{ 1270 struct sdhci_slot *slot = device_get_ivars(child); 1271 1272 switch (which) { 1273 default: 1274 return (EINVAL); 1275 case MMCBR_IVAR_BUS_MODE: 1276 *result = slot->host.ios.bus_mode; 1277 break; 1278 case MMCBR_IVAR_BUS_WIDTH: 1279 *result = slot->host.ios.bus_width; 1280 break; 1281 case MMCBR_IVAR_CHIP_SELECT: 1282 *result = slot->host.ios.chip_select; 1283 break; 1284 case MMCBR_IVAR_CLOCK: 1285 *result = slot->host.ios.clock; 1286 break; 1287 case MMCBR_IVAR_F_MIN: 1288 *result = slot->host.f_min; 1289 break; 1290 case MMCBR_IVAR_F_MAX: 1291 *result = slot->host.f_max; 1292 break; 1293 case MMCBR_IVAR_HOST_OCR: 1294 *result = slot->host.host_ocr; 1295 break; 1296 case MMCBR_IVAR_MODE: 1297 *result = slot->host.mode; 1298 break; 1299 case MMCBR_IVAR_OCR: 1300 *result = slot->host.ocr; 1301 break; 1302 case MMCBR_IVAR_POWER_MODE: 1303 *result = slot->host.ios.power_mode; 1304 break; 1305 case MMCBR_IVAR_VDD: 1306 *result = slot->host.ios.vdd; 1307 break; 1308 case MMCBR_IVAR_CAPS: 1309 *result = slot->host.caps; 1310 break; 1311 case MMCBR_IVAR_TIMING: 1312 *result = slot->host.ios.timing; 1313 break; 1314 case MMCBR_IVAR_MAX_DATA: 1315 *result = 65535; 1316 break; 1317 } 1318 return (0); 1319} 1320 1321int 1322sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1323{ 1324 struct sdhci_slot *slot = device_get_ivars(child); 1325 1326 switch (which) { 1327 default: 1328 return (EINVAL); 1329 case MMCBR_IVAR_BUS_MODE: 1330 slot->host.ios.bus_mode = value; 1331 break; 1332 case MMCBR_IVAR_BUS_WIDTH: 1333 slot->host.ios.bus_width = value; 1334 break; 1335 case MMCBR_IVAR_CHIP_SELECT: 1336 slot->host.ios.chip_select = value; 1337 break; 1338 case MMCBR_IVAR_CLOCK: 1339 if (value > 0) { 1340 uint32_t max_clock; 1341 uint32_t clock; 1342 int i; 1343 1344 max_clock = slot->max_clk; 1345 clock = max_clock; 1346 1347 if (slot->version < SDHCI_SPEC_300) { 1348 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1349 i <<= 1) { 1350 if (clock <= value) 1351 break; 1352 clock >>= 1; 1353 } 1354 } 1355 else { 1356 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1357 i += 2) { 1358 if (clock <= value) 1359 break; 1360 clock = max_clock / (i + 2); 1361 } 1362 } 1363 1364 slot->host.ios.clock = clock; 1365 } else 1366 slot->host.ios.clock = 0; 1367 break; 1368 case MMCBR_IVAR_MODE: 1369 slot->host.mode = value; 1370 break; 1371 case MMCBR_IVAR_OCR: 1372 slot->host.ocr = value; 1373 break; 1374 case MMCBR_IVAR_POWER_MODE: 1375 slot->host.ios.power_mode = value; 1376 break; 1377 case MMCBR_IVAR_VDD: 1378 slot->host.ios.vdd = value; 1379 break; 1380 case MMCBR_IVAR_TIMING: 1381 slot->host.ios.timing = value; 1382 break; 1383 case MMCBR_IVAR_CAPS: 1384 case MMCBR_IVAR_HOST_OCR: 1385 case MMCBR_IVAR_F_MIN: 1386 case MMCBR_IVAR_F_MAX: 1387 case MMCBR_IVAR_MAX_DATA: 1388 return (EINVAL); 1389 } 1390 return (0); 1391} 1392 1393MODULE_VERSION(sdhci, 1); 1394