rpreg.h revision 59874
1/* 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted prodived that the follwoing conditions 7 * are met. 8 * 1. Redistributions of source code must retain the above copyright 9 * notive, this list of conditions and the following disclainer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials prodided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Comtrol Corporation. 16 * 4. The name of Comtrol Corporation may not be used to endorse or 17 * promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/rp/rpreg.h 59874 2000-05-01 20:32:07Z peter $ 33 */ 34 35/* 36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 37 */ 38 39typedef unsigned char Byte_t; 40typedef unsigned int ByteIO_t; 41 42typedef unsigned int Word_t; 43typedef unsigned int WordIO_t; 44 45typedef unsigned long DWord_t; 46typedef unsigned int DWordIO_t; 47 48#define sOutB(a, b) outb(a, b) 49#define sOutW(a, b) outw(a, b) 50#define sOutDW(a, b) outl(a, b) 51#define sInB(a) (inb(a)) 52#define sInW(a) (inw(a)) 53#define sOutStrW(port, addr, count) outsw(port, addr, count) 54#define sInStrW(port, addr, count) insw(port, addr, count) 55 56/* 57 * End of OS-specific defines 58 */ 59 60#define ROCKET_H 61 62#define CTL_SIZE 4 63#define AIOP_CTL_SIZE 4 64#define CHAN_AIOP_SIZE 8 65#define MAX_PORTS_PER_AIOP 8 66#define MAX_AIOPS_PER_BOARD 4 67#define MAX_PORTS_PER_BOARD 32 68 69/* Bus Type ID */ 70#define isISA 0 71#define isPCI 1 72#define isMC 2 73 74/* Controller ID numbers */ 75#define CTLID_NULL -1 /* no controller exists */ 76#define CTLID_0001 0x0001 /* controller release 1 */ 77 78/* PCI IDs */ 79#define RP_VENDOR_ID 0x11FE 80#define RP_DEVICE_ID_8OCTA 0x0001 81#define RP_DEVICE_ID_8INTF 0x0002 82#define RP_DEVICE_ID_16INTF 0x0003 83#define RP_DEVICE_ID_32INTF 0x0004 84 85/* AIOP ID numbers, identifies AIOP type implementing channel */ 86#define AIOPID_NULL -1 /* no AIOP or channel exists */ 87#define AIOPID_0001 0x0001 /* AIOP release 1 */ 88 89#define NULLDEV -1 /* identifies non-existant device */ 90#define NULLCTL -1 /* identifies non-existant controller */ 91#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 92#define NULLAIOP -1 /* identifies non-existant AIOP */ 93#define NULLCHAN -1 /* identifies non-existant channel */ 94 95/************************************************************************ 96 Global Register Offsets - Direct Access - Fixed values 97************************************************************************/ 98 99#define _CMD_REG 0x38 /* Command Register 8 Write */ 100#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 101#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 102#define _UNUSED 0x3B /* Unused 8 */ 103#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 104#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 105 106/************************************************************************ 107 Channel Register Offsets for 1st channel in AIOP - Direct Access 108************************************************************************/ 109#define _TD0 0x00 /* Transmit Data 16 Write */ 110#define _RD0 0x00 /* Receive Data 16 Read */ 111#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 112#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 113#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 114 115/************************************************************************ 116 Tx Control Register Offsets - Indexed - External - Fixed 117************************************************************************/ 118#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 119#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 120#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 121#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 122#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 123#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 124 125/************************************************************************ 126 Receive FIFO 127************************************************************************/ 128#define RXFIFO_DATA 0x5f 129#define RXFIFO_OUT 0x5c 130#define RXFIFO_EN 0x08 131#define RXFIFO_DIS 0xa7 132 133/************************************************************************ 134Memory Controller Register Offsets - Indexed - External - Fixed 135************************************************************************/ 136#define _RX_FIFO 0x000 /* Rx FIFO */ 137#define _TX_FIFO 0x800 /* Tx FIFO */ 138#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 139#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 140#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 141#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 142#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 143#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 144 145#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 146#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 147#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 148 149/************************************************************************ 150Tx Priority Buffer - Indexed - External - Fixed 151************************************************************************/ 152#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 153#define TXP_SIZE 0x20 /* 32 bytes */ 154 155/************************************************************************ 156Channel Register Offsets - Indexed - Internal - Fixed 157************************************************************************/ 158 159#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 160#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 161#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 162#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 163 164#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 165 166#define BRD50 4607 167#define BRD75 3071 168#define BRD110 2094 169#define BRD134 1712 170#define BRD150 1535 171#define BRD200 1151 172#define BRD300 767 173#define BRD600 383 174#define BRD1200 191 175#define BRD1800 127 176#define BRD2000 114 177#define BRD2400 95 178#define BRD3600 64 179#define BRD4800 47 180#define BRD7200 31 181#define BRD9600 23 182#define BRD14400 15 183#define BRD19200 11 184#define BRD38400 5 185#define BRD57600 3 186#define BRD76800 2 187#define BRD115200 1 188#define BRD230400 0 189 190#define STMBREAK 0x08 /* BREAK */ 191#define STMFRAME 0x04 /* framing error */ 192#define STMRCVROVR 0x02 /* receiver over run error */ 193#define STMPARITY 0x01 /* parity error */ 194#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 195#define STMBREAKH 0x800 /* BREAK */ 196#define STMFRAMEH 0x400 /* framing error */ 197#define STMRCVROVRH 0x200 /* receiver over run error */ 198#define STMPARITYH 0x100 /* parity error */ 199#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 200 201#define CTS_ACT 0x20 /* CTS input asserted */ 202#define DSR_ACT 0x10 /* DSR input asserted */ 203#define CD_ACT 0x08 /* CD input asserted */ 204#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 205#define TXSHRMT 0x02 /* Tx shift register is empty */ 206#define RDA 0x01 /* Rx data available */ 207#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 208 209#define STATMODE 0x8000 /* status mode enable bit */ 210#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 211#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 212#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 213#define RXBREAK 0x0400 /* received BREAK */ 214#define RXFRAME 0x0200 /* received framing error */ 215#define RXPARITY 0x0100 /* received parity error */ 216#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 217 218#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 219#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 220#define TXINT_EN 0x10 /* transmit interrupt enable */ 221#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 222#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 223#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 224#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 225 226#define SETBREAK 0x10 /* send break condition (must clear) */ 227#define LOCALLOOP 0x08 /* local loopback set for test */ 228#define SET_DTR 0x04 /* assert DTR */ 229#define SET_RTS 0x02 /* assert RTS */ 230#define TX_ENABLE 0x01 /* enable transmitter */ 231 232#define RTSFC_EN 0x40 /* RTS flow control enable */ 233#define RXPROC_EN 0x20 /* receive processor enable */ 234#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 235#define TRIG_1 0x08 /* trigger level 1 char */ 236#define TRIG_1_2 0x10 /* trigger level 1/2 */ 237#define TRIG_7_8 0x18 /* trigger level 7/8 */ 238#define TRIG_MASK 0x18 /* trigger level mask */ 239#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 240#define RXINT_EN 0x02 /* Rx interrupt enable */ 241#define MCINT_EN 0x01 /* modem change interrupt enable */ 242 243#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 244#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 245#define SRC_INT 0x08 /* special receive condition interrupt */ 246#define DELTA_CD 0x04 /* CD change interrupt */ 247#define DELTA_CTS 0x02 /* CTS change interrupt */ 248#define DELTA_DSR 0x01 /* DSR change interrupt */ 249 250#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 251#define IGN2_EN 0x08 /* ignore byte 2 enable */ 252#define IGN1_EN 0x04 /* ignore byte 1 enable */ 253#define COMP2_EN 0x02 /* compare byte 2 enable */ 254#define COMP1_EN 0x01 /* compare byte 1 enable */ 255 256#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 257#define TXOVERIDE 0x40 /* Transmit software off override */ 258#define RESETUART 0x20 /* reset channel's UART */ 259#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 260#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 261 262#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 263#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 264#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 265#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 266 267#define INTR_EN 0x08 /* allow interrupts to host */ 268#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 269 270/************************************************************************** 271 MUDBAC remapped for PCI 272**************************************************************************/ 273 274#define _CFG_INT_PCI 0x40 275#define _PCI_INT_FUNC 0x3A 276 277#define PCI_STROB 0x2000 278#define INTR_EN_PCI 0x0010 279 280#define CHAN3_EN 0x08 /* enable AIOP 3 */ 281#define CHAN2_EN 0x04 /* enable AIOP 2 */ 282#define CHAN1_EN 0x02 /* enable AIOP 1 */ 283#define CHAN0_EN 0x01 /* enable AIOP 0 */ 284#define FREQ_DIS 0x00 285#define FREQ_274HZ 0x60 286#define FREQ_137HZ 0x50 287#define FREQ_69HZ 0x40 288#define FREQ_34HZ 0x30 289#define FREQ_17HZ 0x20 290#define FREQ_9HZ 0x10 291#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 292 293#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 294 295#define RDATASIZE 72 296#define RREGDATASIZE 52 297 298/* Controller level information structure */ 299typedef struct 300{ 301 int CtlID; 302 int CtlNum; 303 int BusType; 304 WordIO_t PCIIO; 305 ByteIO_t MBaseIO; 306 ByteIO_t MReg1IO; 307 ByteIO_t MReg2IO; 308 ByteIO_t MReg3IO; 309 Byte_t MReg2; 310 Byte_t MReg3; 311 int NumAiop; 312 WordIO_t AiopIO[AIOP_CTL_SIZE]; 313 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; 314 int AiopID[AIOP_CTL_SIZE]; 315 int AiopNumChan[AIOP_CTL_SIZE]; 316} CONTROLLER_T; 317 318typedef CONTROLLER_T CONTROLLER_t; 319 320/* Channel level information structure */ 321typedef struct 322{ 323 CONTROLLER_T *CtlP; 324 int AiopNum; 325 int ChanID; 326 int ChanNum; 327 328 ByteIO_t Cmd; 329 ByteIO_t IntChan; 330 ByteIO_t IntMask; 331 DWordIO_t IndexAddr; 332 WordIO_t IndexData; 333 334 WordIO_t TxRxData; 335 WordIO_t ChanStat; 336 WordIO_t TxRxCount; 337 ByteIO_t IntID; 338 339 Word_t TxFIFO; 340 Word_t TxFIFOPtrs; 341 Word_t RxFIFO; 342 Word_t RxFIFOPtrs; 343 Word_t TxPrioCnt; 344 Word_t TxPrioPtr; 345 Word_t TxPrioBuf; 346 347 Byte_t R[RREGDATASIZE]; 348 349 Byte_t BaudDiv[4]; 350 Byte_t TxControl[4]; 351 Byte_t RxControl[4]; 352 Byte_t TxEnables[4]; 353 Byte_t TxCompare[4]; 354 Byte_t TxReplace1[4]; 355 Byte_t TxReplace2[4]; 356} CHANNEL_T; 357 358typedef CHANNEL_T CHANNEL_t; 359typedef CHANNEL_T * CHANPTR_T; 360 361/*************************************************************************** 362Function: sClrBreak 363Purpose: Stop sending a transmit BREAK signal 364Call: sClrBreak(ChP) 365 CHANNEL_T *ChP; Ptr to channel structure 366*/ 367#define sClrBreak(ChP) \ 368{ \ 369 (ChP)->TxControl[3] &= ~SETBREAK; \ 370 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 371} 372 373/*************************************************************************** 374Function: sClrDTR 375Purpose: Clr the DTR output 376Call: sClrDTR(ChP) 377 CHANNEL_T *ChP; Ptr to channel structure 378*/ 379#define sClrDTR(ChP) \ 380{ \ 381 (ChP)->TxControl[3] &= ~SET_DTR; \ 382 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 383} 384 385/*************************************************************************** 386Function: sClrRTS 387Purpose: Clr the RTS output 388Call: sClrRTS(ChP) 389 CHANNEL_T *ChP; Ptr to channel structure 390*/ 391#define sClrRTS(ChP) \ 392{ \ 393 (ChP)->TxControl[3] &= ~SET_RTS; \ 394 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 395} 396 397/*************************************************************************** 398Function: sClrTxXOFF 399Purpose: Clear any existing transmit software flow control off condition 400Call: sClrTxXOFF(ChP) 401 CHANNEL_T *ChP; Ptr to channel structure 402*/ 403#define sClrTxXOFF(ChP) \ 404{ \ 405 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 406 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ 407} 408 409/*************************************************************************** 410Function: sCtlNumToCtlPtr 411Purpose: Convert a controller number to controller structure pointer 412Call: sCtlNumToCtlPtr(CtlNum) 413 int CtlNum; Controller number 414Return: CONTROLLER_T *: Ptr to controller structure 415*/ 416#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] 417 418/*************************************************************************** 419Function: sControllerEOI 420Purpose: Strobe the MUDBAC's End Of Interrupt bit. 421Call: sControllerEOI(CtlP) 422 CONTROLLER_T *CtlP; Ptr to controller structure 423*/ 424#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) 425 426 427/*************************************************************************** 428Function: sPCIControllerEOI 429Purpose: Strobe the MUDBAC's End Of Interrupt bit. 430Call: sPCIControllerEOI(CtlP) 431 CONTROLLER_T *CtlP; Ptr to controller structure 432*/ 433#define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB) 434 435/*************************************************************************** 436Function: sDisAiop 437Purpose: Disable I/O access to an AIOP 438Call: sDisAiop(CltP) 439 CONTROLLER_T *CtlP; Ptr to controller structure 440 int AiopNum; Number of AIOP on controller 441*/ 442#define sDisAiop(CTLP,AIOPNUM) \ 443{ \ 444 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ 445 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 446} 447 448/*************************************************************************** 449Function: sDisCTSFlowCtl 450Purpose: Disable output flow control using CTS 451Call: sDisCTSFlowCtl(ChP) 452 CHANNEL_T *ChP; Ptr to channel structure 453*/ 454#define sDisCTSFlowCtl(ChP) \ 455{ \ 456 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 457 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 458} 459 460/*************************************************************************** 461Function: DisParity 462Purpose: Disable parity 463Call: sDisParity(ChP) 464 CHANNEL_T *ChP; Ptr to channel structure 465Comments: Function sSetParity() can be used in place of functions sEnParity(), 466 sDisParity(), sSetOddParity(), and sSetEvenParity(). 467*/ 468#define sDisParity(ChP) \ 469{ \ 470 (ChP)->TxControl[2] &= ~PARITY_EN; \ 471 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 472} 473 474/*************************************************************************** 475Function: sDisRxFIFO 476Purpose: Disable Rx FIFO 477Call: sDisRxFIFO(ChP) 478 CHANNEL_T *ChP; Ptr to channel structure 479*/ 480#define sDisRxFIFO(ChP) \ 481{ \ 482 (ChP)->R[0x32] = 0x0a; \ 483 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 484} 485 486/*************************************************************************** 487Function: sDisRxStatusMode 488Purpose: Disable the Rx status mode 489Call: sDisRxStatusMode(ChP) 490 CHANNEL_T *ChP; Ptr to channel structure 491Comments: This takes the channel out of the receive status mode. All 492 subsequent reads of receive data using sReadRxWord() will return 493 two data bytes. 494*/ 495#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) 496 497/*************************************************************************** 498Function: sDisTransmit 499Purpose: Disable transmit 500Call: sDisTransmit(ChP) 501 CHANNEL_T *ChP; Ptr to channel structure 502 This disables movement of Tx data from the Tx FIFO into the 1 byte 503 Tx buffer. Therefore there could be up to a 2 byte latency 504 between the time sDisTransmit() is called and the transmit buffer 505 and transmit shift register going completely empty. 506*/ 507#define sDisTransmit(ChP) \ 508{ \ 509 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 510 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 511} 512 513/*************************************************************************** 514Function: sDisTxSoftFlowCtl 515Purpose: Disable Tx Software Flow Control 516Call: sDisTxSoftFlowCtl(ChP) 517 CHANNEL_T *ChP; Ptr to channel structure 518*/ 519#define sDisTxSoftFlowCtl(ChP) \ 520{ \ 521 (ChP)->R[0x06] = 0x8a; \ 522 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 523} 524 525/*************************************************************************** 526Function: sEnAiop 527Purpose: Enable I/O access to an AIOP 528Call: sEnAiop(CltP) 529 CONTROLLER_T *CtlP; Ptr to controller structure 530 int AiopNum; Number of AIOP on controller 531*/ 532#define sEnAiop(CTLP,AIOPNUM) \ 533{ \ 534 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ 535 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 536} 537 538/*************************************************************************** 539Function: sEnCTSFlowCtl 540Purpose: Enable output flow control using CTS 541Call: sEnCTSFlowCtl(ChP) 542 CHANNEL_T *ChP; Ptr to channel structure 543*/ 544#define sEnCTSFlowCtl(ChP) \ 545{ \ 546 (ChP)->TxControl[2] |= CTSFC_EN; \ 547 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 548} 549 550/*************************************************************************** 551Function: EnParity 552Purpose: Enable parity 553Call: sEnParity(ChP) 554 CHANNEL_T *ChP; Ptr to channel structure 555Comments: Function sSetParity() can be used in place of functions sEnParity(), 556 sDisParity(), sSetOddParity(), and sSetEvenParity(). 557 558Warnings: Before enabling parity odd or even parity should be chosen using 559 functions sSetOddParity() or sSetEvenParity(). 560*/ 561#define sEnParity(ChP) \ 562{ \ 563 (ChP)->TxControl[2] |= PARITY_EN; \ 564 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 565} 566 567/*************************************************************************** 568Function: sEnRTSFlowCtl 569Return: void 570*/ 571#define sEnRTSFlowCtl(ChP) \ 572{ \ 573 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 574 (ChP)->TxControl[3] &= ~SET_RTS; \ 575 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 576 (ChP)->RxControl[2] |= RTSFC_EN; \ 577 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 578} 579 580/*************************************************************************** 581Function: sDisRTSFlowCtl 582Return: void 583*/ 584#define sDisRTSFlowCtl(ChP) \ 585{ \ 586 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 587 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 588} 589 590/*************************************************************************** 591Function: sEnRxFIFO 592Purpose: Enable Rx FIFO 593Call: sEnRxFIFO(ChP) 594 CHANNEL_T *ChP; Ptr to channel structure 595*/ 596#define sEnRxFIFO(ChP) \ 597{ \ 598 (ChP)->R[0x32] = 0x08; \ 599 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 600} 601 602/*************************************************************************** 603Function: sEnRxProcessor 604Purpose: Enable the receive processor 605Call: sEnRxProcessor(ChP) 606 CHANNEL_T *ChP; Ptr to channel structure 607Comments: This function is used to start the receive processor. When 608 the channel is in the reset state the receive processor is not 609 running. This is done to prevent the receive processor from 610 executing invalid microcode instructions prior to the 611 downloading of the microcode. 612 613Warnings: This function must be called after valid microcode has been 614 downloaded to the AIOP, and it must not be called before the 615 microcode has been downloaded. 616*/ 617#define sEnRxProcessor(ChP) \ 618{ \ 619 (ChP)->RxControl[2] |= RXPROC_EN; \ 620 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 621} 622 623/*************************************************************************** 624Function: sEnRxStatusMode 625Purpose: Enable the Rx status mode 626Call: sEnRxStatusMode(ChP) 627 CHANNEL_T *ChP; Ptr to channel structure 628Comments: This places the channel in the receive status mode. All subsequent 629 reads of receive data using sReadRxWord() will return a data byte 630 in the low word and a status byte in the high word. 631 632*/ 633#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) 634 635/*************************************************************************** 636Function: sEnTransmit 637Purpose: Enable transmit 638Call: sEnTransmit(ChP) 639 CHANNEL_T *ChP; Ptr to channel structure 640*/ 641#define sEnTransmit(ChP) \ 642{ \ 643 (ChP)->TxControl[3] |= TX_ENABLE; \ 644 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 645} 646 647/*************************************************************************** 648Function: sGetAiopIntStatus 649Purpose: Get the AIOP interrupt status 650Call: sGetAiopIntStatus(CtlP,AiopNum) 651 CONTROLLER_T *CtlP; Ptr to controller structure 652 int AiopNum; AIOP number 653Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 654 represent channels 0 through 7 respectively. If a 655 bit is set that channel is interrupting. 656*/ 657#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) 658 659/*************************************************************************** 660Function: sGetAiopNumChan 661Purpose: Get the number of channels supported by an AIOP 662Call: sGetAiopNumChan(CtlP,AiopNum) 663 CONTROLLER_T *CtlP; Ptr to controller structure 664 int AiopNum; AIOP number 665Return: int: The number of channels supported by the AIOP 666*/ 667#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] 668 669/*************************************************************************** 670Function: sGetChanIntID 671Purpose: Get a channel's interrupt identification byte 672Call: sGetChanIntID(ChP) 673 CHANNEL_T *ChP; Ptr to channel structure 674Return: Byte_t: The channel interrupt ID. Can be any 675 combination of the following flags: 676 RXF_TRIG: Rx FIFO trigger level interrupt 677 TXFIFO_MT: Tx FIFO empty interrupt 678 SRC_INT: Special receive condition interrupt 679 DELTA_CD: CD change interrupt 680 DELTA_CTS: CTS change interrupt 681 DELTA_DSR: DSR change interrupt 682*/ 683#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 684 685/*************************************************************************** 686Function: sGetChanNum 687Purpose: Get the number of a channel within an AIOP 688Call: sGetChanNum(ChP) 689 CHANNEL_T *ChP; Ptr to channel structure 690Return: int: Channel number within AIOP, or NULLCHAN if channel does 691 not exist. 692*/ 693#define sGetChanNum(ChP) (ChP)->ChanNum 694 695/*************************************************************************** 696Function: sGetChanStatus 697Purpose: Get the channel status 698Call: sGetChanStatus(ChP) 699 CHANNEL_T *ChP; Ptr to channel structure 700Return: Word_t: The channel status. Can be any combination of 701 the following flags: 702 LOW BYTE FLAGS 703 CTS_ACT: CTS input asserted 704 DSR_ACT: DSR input asserted 705 CD_ACT: CD input asserted 706 TXFIFOMT: Tx FIFO is empty 707 TXSHRMT: Tx shift register is empty 708 RDA: Rx data available 709 710 HIGH BYTE FLAGS 711 STATMODE: status mode enable bit 712 RXFOVERFL: receive FIFO overflow 713 RX2MATCH: receive compare byte 2 match 714 RX1MATCH: receive compare byte 1 match 715 RXBREAK: received BREAK 716 RXFRAME: received framing error 717 RXPARITY: received parity error 718Warnings: This function will clear the high byte flags in the Channel 719 Status Register. 720*/ 721#define sGetChanStatus(ChP) sInW((ChP)->ChanStat) 722 723/*************************************************************************** 724Function: sGetChanStatusLo 725Purpose: Get the low byte only of the channel status 726Call: sGetChanStatusLo(ChP) 727 CHANNEL_T *ChP; Ptr to channel structure 728Return: Byte_t: The channel status low byte. Can be any combination 729 of the following flags: 730 CTS_ACT: CTS input asserted 731 DSR_ACT: DSR input asserted 732 CD_ACT: CD input asserted 733 TXFIFOMT: Tx FIFO is empty 734 TXSHRMT: Tx shift register is empty 735 RDA: Rx data available 736*/ 737#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) 738 739/*************************************************************************** 740Function: sGetControllerIntStatus 741Purpose: Get the controller interrupt status 742Call: sGetControllerIntStatus(CtlP) 743 CONTROLLER_T *CtlP; Ptr to controller structure 744Return: Byte_t: The controller interrupt status in the lower 4 745 bits. Bits 0 through 3 represent AIOP's 0 746 through 3 respectively. If a bit is set that 747 AIOP is interrupting. Bits 4 through 7 will 748 always be cleared. 749*/ 750#define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) 751 752/*************************************************************************** 753Function: sPCIGetControllerIntStatus 754Purpose: Get the controller interrupt status 755Call: sPCIGetControllerIntStatus(CtlP) 756 CONTROLLER_T *CtlP; Ptr to controller structure 757Return: Byte_t: The controller interrupt status in the lower 4 758 bits. Bits 0 through 3 represent AIOP's 0 759 through 3 respectively. If a bit is set that 760 AIOP is interrupting. Bits 4 through 7 will 761 always be cleared. 762*/ 763#define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f) 764 765/*************************************************************************** 766Function: sGetRxCnt 767Purpose: Get the number of data bytes in the Rx FIFO 768Call: sGetRxCnt(ChP) 769 CHANNEL_T *ChP; Ptr to channel structure 770Return: int: The number of data bytes in the Rx FIFO. 771Comments: Byte read of count register is required to obtain Rx count. 772 773*/ 774#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) 775 776/*************************************************************************** 777Function: sGetTxCnt 778Purpose: Get the number of data bytes in the Tx FIFO 779Call: sGetTxCnt(ChP) 780 CHANNEL_T *ChP; Ptr to channel structure 781Return: Byte_t: The number of data bytes in the Tx FIFO. 782Comments: Byte read of count register is required to obtain Tx count. 783 784*/ 785#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) 786 787/***************************************************************************** 788Function: sGetTxRxDataIO 789Purpose: Get the I/O address of a channel's TxRx Data register 790Call: sGetTxRxDataIO(ChP) 791 CHANNEL_T *ChP; Ptr to channel structure 792Return: WordIO_t: I/O address of a channel's TxRx Data register 793*/ 794#define sGetTxRxDataIO(ChP) (ChP)->TxRxData 795 796/*************************************************************************** 797Function: sInitChanDefaults 798Purpose: Initialize a channel structure to its default state. 799Call: sInitChanDefaults(ChP) 800 CHANNEL_T *ChP; Ptr to the channel structure 801Comments: This function must be called once for every channel structure 802 that exists before any other SSCI calls can be made. 803 804*/ 805#define sInitChanDefaults(ChP) \ 806{ \ 807 (ChP)->CtlP = NULLCTLPTR; \ 808 (ChP)->AiopNum = NULLAIOP; \ 809 (ChP)->ChanID = AIOPID_NULL; \ 810 (ChP)->ChanNum = NULLCHAN; \ 811} 812 813/*************************************************************************** 814Function: sResetAiopByNum 815Purpose: Reset the AIOP by number 816Call: sResetAiopByNum(CTLP,AIOPNUM) 817 CONTROLLER_T CTLP; Ptr to controller structure 818 AIOPNUM; AIOP index 819*/ 820#define sResetAiopByNum(CTLP,AIOPNUM) \ 821{ \ 822 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ 823 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ 824} 825 826/*************************************************************************** 827Function: sSendBreak 828Purpose: Send a transmit BREAK signal 829Call: sSendBreak(ChP) 830 CHANNEL_T *ChP; Ptr to channel structure 831*/ 832#define sSendBreak(ChP) \ 833{ \ 834 (ChP)->TxControl[3] |= SETBREAK; \ 835 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 836} 837 838/*************************************************************************** 839Function: sSetBaud 840Purpose: Set baud rate 841Call: sSetBaud(ChP,Divisor) 842 CHANNEL_T *ChP; Ptr to channel structure 843 Word_t Divisor; 16 bit baud rate divisor for channel 844*/ 845#define sSetBaud(ChP,DIVISOR) \ 846{ \ 847 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 848 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 849 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 850} 851 852/*************************************************************************** 853Function: sSetData7 854Purpose: Set data bits to 7 855Call: sSetData7(ChP) 856 CHANNEL_T *ChP; Ptr to channel structure 857*/ 858#define sSetData7(ChP) \ 859{ \ 860 (ChP)->TxControl[2] &= ~DATA8BIT; \ 861 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 862} 863 864/*************************************************************************** 865Function: sSetData8 866Purpose: Set data bits to 8 867Call: sSetData8(ChP) 868 CHANNEL_T *ChP; Ptr to channel structure 869*/ 870#define sSetData8(ChP) \ 871{ \ 872 (ChP)->TxControl[2] |= DATA8BIT; \ 873 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 874} 875 876/*************************************************************************** 877Function: sSetDTR 878Purpose: Set the DTR output 879Call: sSetDTR(ChP) 880 CHANNEL_T *ChP; Ptr to channel structure 881*/ 882#define sSetDTR(ChP) \ 883{ \ 884 (ChP)->TxControl[3] |= SET_DTR; \ 885 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 886} 887 888/*************************************************************************** 889Function: sSetEvenParity 890Purpose: Set even parity 891Call: sSetEvenParity(ChP) 892 CHANNEL_T *ChP; Ptr to channel structure 893Comments: Function sSetParity() can be used in place of functions sEnParity(), 894 sDisParity(), sSetOddParity(), and sSetEvenParity(). 895 896Warnings: This function has no effect unless parity is enabled with function 897 sEnParity(). 898*/ 899#define sSetEvenParity(ChP) \ 900{ \ 901 (ChP)->TxControl[2] |= EVEN_PAR; \ 902 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 903} 904 905/*************************************************************************** 906Function: sSetOddParity 907Purpose: Set odd parity 908Call: sSetOddParity(ChP) 909 CHANNEL_T *ChP; Ptr to channel structure 910Comments: Function sSetParity() can be used in place of functions sEnParity(), 911 sDisParity(), sSetOddParity(), and sSetEvenParity(). 912 913Warnings: This function has no effect unless parity is enabled with function 914 sEnParity(). 915*/ 916#define sSetOddParity(ChP) \ 917{ \ 918 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 919 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 920} 921 922/*************************************************************************** 923Function: sSetRTS 924Purpose: Set the RTS output 925Call: sSetRTS(ChP) 926 CHANNEL_T *ChP; Ptr to channel structure 927*/ 928#define sSetRTS(ChP) \ 929{ \ 930 (ChP)->TxControl[3] |= SET_RTS; \ 931 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 932} 933 934/*************************************************************************** 935Function: sSetRxTrigger 936Purpose: Set the Rx FIFO trigger level 937Call: sSetRxProcessor(ChP,Level) 938 CHANNEL_T *ChP; Ptr to channel structure 939 Byte_t Level; Number of characters in Rx FIFO at which the 940 interrupt will be generated. Can be any of the following flags: 941 942 TRIG_NO: no trigger 943 TRIG_1: 1 character in FIFO 944 TRIG_1_2: FIFO 1/2 full 945 TRIG_7_8: FIFO 7/8 full 946Comments: An interrupt will be generated when the trigger level is reached 947 only if function sEnInterrupt() has been called with flag 948 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 949 register will be set whenever the trigger level is reached 950 regardless of the setting of RXINT_EN. 951 952*/ 953#define sSetRxTrigger(ChP,LEVEL) \ 954{ \ 955 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 956 (ChP)->RxControl[2] |= LEVEL; \ 957 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 958} 959 960/*************************************************************************** 961Function: sSetStop1 962Purpose: Set stop bits to 1 963Call: sSetStop1(ChP) 964 CHANNEL_T *ChP; Ptr to channel structure 965*/ 966#define sSetStop1(ChP) \ 967{ \ 968 (ChP)->TxControl[2] &= ~STOP2; \ 969 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 970} 971 972/*************************************************************************** 973Function: sSetStop2 974Purpose: Set stop bits to 2 975Call: sSetStop2(ChP) 976 CHANNEL_T *ChP; Ptr to channel structure 977*/ 978#define sSetStop2(ChP) \ 979{ \ 980 (ChP)->TxControl[2] |= STOP2; \ 981 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 982} 983 984/*************************************************************************** 985Function: sStartRxProcessor 986Purpose: Start a channel's receive processor 987Call: sStartRxProcessor(ChP) 988 CHANNEL_T *ChP; Ptr to channel structure 989Comments: This function is used to start a Rx processor after it was 990 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 991 will restart both the Rx processor and software input flow control. 992 993*/ 994#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) 995 996/*************************************************************************** 997Function: sWriteTxByte 998Purpose: Write a transmit data byte to a channel. 999 ByteIO_t io: Channel transmit register I/O address. This can 1000 be obtained with sGetTxRxDataIO(). 1001 Byte_t Data; The transmit data byte. 1002Warnings: This function writes the data byte without checking to see if 1003 sMaxTxSize is exceeded in the Tx FIFO. 1004*/ 1005#define sWriteTxByte(IO,DATA) sOutB(IO,DATA) 1006 1007int sInitController( CONTROLLER_T *CtlP, 1008 int CtlNum, 1009 ByteIO_t MudbacIO, 1010 ByteIO_t *AiopIOList, 1011 int AiopIOListSize, 1012 int IRQNum, 1013 Byte_t Frequency, 1014 int PeriodicOnly); 1015 1016int sPCIInitController( CONTROLLER_T *CtlP, 1017 int CtlNum, 1018 ByteIO_t *AiopIOList, 1019 int AiopIOListSize, 1020 int IRQNum, 1021 Byte_t Frequency, 1022 int PeriodicOnly); 1023 1024int sReadAiopID(ByteIO_t io); 1025int sReadAiopNumChan(WordIO_t io); 1026int sInitChan( CONTROLLER_T *CtlP, 1027 CHANNEL_T *ChP, 1028 int AiopNum, 1029 int ChanNum); 1030Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 1031void sStopRxProcessor(CHANNEL_T *ChP); 1032void sStopSWInFlowCtl(CHANNEL_T *ChP); 1033void sFlushRxFIFO(CHANNEL_T *ChP); 1034void sFlushTxFIFO(CHANNEL_T *ChP); 1035int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1036void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1037void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1038 1039#ifndef ROCKET_C 1040extern Byte_t R[RDATASIZE]; 1041extern CONTROLLER_T sController[CTL_SIZE]; 1042extern Byte_t sIRQMap[16]; 1043extern Byte_t sBitMapClrTbl[8]; 1044extern Byte_t sBitMapSetTbl[8]; 1045#endif 1046