rpreg.h revision 28868
1/* 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted prodived that the follwoing conditions 7 * are met. 8 * 1. Redistributions of source code must retain the above copyright 9 * notive, this list of conditions and the following disclainer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials prodided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Comtrol Corporation. 16 * 4. The name of Comtrol Corporation may not be used to endorse or 17 * promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33/* 34 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 35 */ 36 37typedef unsigned char Byte_t; 38typedef unsigned int ByteIO_t; 39 40typedef unsigned int Word_t; 41typedef unsigned int WordIO_t; 42 43typedef unsigned long DWord_t; 44typedef unsigned int DWordIO_t; 45 46#define sOutB(a, b) outb(a, b) 47#define sOutW(a, b) outw(a, b) 48#define sOutDW(a, b) outl(a, b) 49#define sInB(a) (inb(a)) 50#define sInW(a) (inw(a)) 51#define sOutStrW(port, addr, count) outsw(port, addr, count) 52#define sInStrW(port, addr, count) insw(port, addr, count) 53 54/* 55 * End of OS-specific defines 56 */ 57 58#define ROCKET_H 59 60#define CTL_SIZE 4 61#define AIOP_CTL_SIZE 4 62#define CHAN_AIOP_SIZE 8 63#define MAX_PORTS_PER_AIOP 8 64#define MAX_AIOPS_PER_BOARD 4 65#define MAX_PORTS_PER_BOARD 32 66 67/* Bus Type ID */ 68#define isISA 0 69#define isPCI 1 70#define isMC 2 71 72/* Controller ID numbers */ 73#define CTLID_NULL -1 /* no controller exists */ 74#define CTLID_0001 0x0001 /* controller release 1 */ 75 76/* PCI IDs */ 77#define RP_VENDOR_ID 0x11FE 78#define RP_DEVICE_ID_8OCTA 0x0001 79#define RP_DEVICE_ID_8INTF 0x0002 80#define RP_DEVICE_ID_16INTF 0x0003 81#define RP_DEVICE_ID_32INTF 0x0004 82 83/* AIOP ID numbers, identifies AIOP type implementing channel */ 84#define AIOPID_NULL -1 /* no AIOP or channel exists */ 85#define AIOPID_0001 0x0001 /* AIOP release 1 */ 86 87#define NULLDEV -1 /* identifies non-existant device */ 88#define NULLCTL -1 /* identifies non-existant controller */ 89#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 90#define NULLAIOP -1 /* identifies non-existant AIOP */ 91#define NULLCHAN -1 /* identifies non-existant channel */ 92 93/************************************************************************ 94 Global Register Offsets - Direct Access - Fixed values 95************************************************************************/ 96 97#define _CMD_REG 0x38 /* Command Register 8 Write */ 98#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 99#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 100#define _UNUSED 0x3B /* Unused 8 */ 101#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 102#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 103 104/************************************************************************ 105 Channel Register Offsets for 1st channel in AIOP - Direct Access 106************************************************************************/ 107#define _TD0 0x00 /* Transmit Data 16 Write */ 108#define _RD0 0x00 /* Receive Data 16 Read */ 109#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 110#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 111#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 112 113/************************************************************************ 114 Tx Control Register Offsets - Indexed - External - Fixed 115************************************************************************/ 116#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 117#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 118#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 119#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 120#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 121#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 122 123/************************************************************************ 124 Receive FIFO 125************************************************************************/ 126#define RXFIFO_DATA 0x5f 127#define RXFIFO_OUT 0x5c 128#define RXFIFO_EN 0x08 129#define RXFIFO_DIS 0xa7 130 131/************************************************************************ 132Memory Controller Register Offsets - Indexed - External - Fixed 133************************************************************************/ 134#define _RX_FIFO 0x000 /* Rx FIFO */ 135#define _TX_FIFO 0x800 /* Tx FIFO */ 136#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 137#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 138#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 139#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 140#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 141#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 142 143#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 144#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 145#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 146 147/************************************************************************ 148Tx Priority Buffer - Indexed - External - Fixed 149************************************************************************/ 150#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 151#define TXP_SIZE 0x20 /* 32 bytes */ 152 153/************************************************************************ 154Channel Register Offsets - Indexed - Internal - Fixed 155************************************************************************/ 156 157#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 158#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 159#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 160#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 161 162#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 163 164#define BRD50 4607 165#define BRD75 3071 166#define BRD110 2094 167#define BRD134 1712 168#define BRD150 1535 169#define BRD200 1151 170#define BRD300 767 171#define BRD600 383 172#define BRD1200 191 173#define BRD1800 127 174#define BRD2000 114 175#define BRD2400 95 176#define BRD3600 64 177#define BRD4800 47 178#define BRD7200 31 179#define BRD9600 23 180#define BRD14400 15 181#define BRD19200 11 182#define BRD38400 5 183#define BRD57600 3 184#define BRD76800 2 185#define BRD115200 1 186#define BRD230400 0 187 188#define STMBREAK 0x08 /* BREAK */ 189#define STMFRAME 0x04 /* framing error */ 190#define STMRCVROVR 0x02 /* receiver over run error */ 191#define STMPARITY 0x01 /* parity error */ 192#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 193#define STMBREAKH 0x800 /* BREAK */ 194#define STMFRAMEH 0x400 /* framing error */ 195#define STMRCVROVRH 0x200 /* receiver over run error */ 196#define STMPARITYH 0x100 /* parity error */ 197#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 198 199#define CTS_ACT 0x20 /* CTS input asserted */ 200#define DSR_ACT 0x10 /* DSR input asserted */ 201#define CD_ACT 0x08 /* CD input asserted */ 202#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 203#define TXSHRMT 0x02 /* Tx shift register is empty */ 204#define RDA 0x01 /* Rx data available */ 205#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 206 207#define STATMODE 0x8000 /* status mode enable bit */ 208#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 209#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 210#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 211#define RXBREAK 0x0400 /* received BREAK */ 212#define RXFRAME 0x0200 /* received framing error */ 213#define RXPARITY 0x0100 /* received parity error */ 214#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 215 216#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 217#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 218#define TXINT_EN 0x10 /* transmit interrupt enable */ 219#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 220#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 221#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 222#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 223 224#define SETBREAK 0x10 /* send break condition (must clear) */ 225#define LOCALLOOP 0x08 /* local loopback set for test */ 226#define SET_DTR 0x04 /* assert DTR */ 227#define SET_RTS 0x02 /* assert RTS */ 228#define TX_ENABLE 0x01 /* enable transmitter */ 229 230#define RTSFC_EN 0x40 /* RTS flow control enable */ 231#define RXPROC_EN 0x20 /* receive processor enable */ 232#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 233#define TRIG_1 0x08 /* trigger level 1 char */ 234#define TRIG_1_2 0x10 /* trigger level 1/2 */ 235#define TRIG_7_8 0x18 /* trigger level 7/8 */ 236#define TRIG_MASK 0x18 /* trigger level mask */ 237#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 238#define RXINT_EN 0x02 /* Rx interrupt enable */ 239#define MCINT_EN 0x01 /* modem change interrupt enable */ 240 241#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 242#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 243#define SRC_INT 0x08 /* special receive condition interrupt */ 244#define DELTA_CD 0x04 /* CD change interrupt */ 245#define DELTA_CTS 0x02 /* CTS change interrupt */ 246#define DELTA_DSR 0x01 /* DSR change interrupt */ 247 248#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 249#define IGN2_EN 0x08 /* ignore byte 2 enable */ 250#define IGN1_EN 0x04 /* ignore byte 1 enable */ 251#define COMP2_EN 0x02 /* compare byte 2 enable */ 252#define COMP1_EN 0x01 /* compare byte 1 enable */ 253 254#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 255#define TXOVERIDE 0x40 /* Transmit software off override */ 256#define RESETUART 0x20 /* reset channel's UART */ 257#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 258#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 259 260#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 261#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 262#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 263#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 264 265#define INTR_EN 0x08 /* allow interrupts to host */ 266#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 267 268/************************************************************************** 269 MUDBAC remapped for PCI 270**************************************************************************/ 271 272#define _CFG_INT_PCI 0x40 273#define _PCI_INT_FUNC 0x3A 274 275#define PCI_STROB 0x2000 276#define INTR_EN_PCI 0x0010 277 278#define CHAN3_EN 0x08 /* enable AIOP 3 */ 279#define CHAN2_EN 0x04 /* enable AIOP 2 */ 280#define CHAN1_EN 0x02 /* enable AIOP 1 */ 281#define CHAN0_EN 0x01 /* enable AIOP 0 */ 282#define FREQ_DIS 0x00 283#define FREQ_274HZ 0x60 284#define FREQ_137HZ 0x50 285#define FREQ_69HZ 0x40 286#define FREQ_34HZ 0x30 287#define FREQ_17HZ 0x20 288#define FREQ_9HZ 0x10 289#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 290 291#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 292 293#define RDATASIZE 72 294#define RREGDATASIZE 52 295 296/* Controller level information structure */ 297typedef struct 298{ 299 int CtlID; 300 int CtlNum; 301 int BusType; 302 WordIO_t PCIIO; 303 ByteIO_t MBaseIO; 304 ByteIO_t MReg1IO; 305 ByteIO_t MReg2IO; 306 ByteIO_t MReg3IO; 307 Byte_t MReg2; 308 Byte_t MReg3; 309 int NumAiop; 310 WordIO_t AiopIO[AIOP_CTL_SIZE]; 311 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; 312 int AiopID[AIOP_CTL_SIZE]; 313 int AiopNumChan[AIOP_CTL_SIZE]; 314} CONTROLLER_T; 315 316typedef CONTROLLER_T CONTROLLER_t; 317 318/* Channel level information structure */ 319typedef struct 320{ 321 CONTROLLER_T *CtlP; 322 int AiopNum; 323 int ChanID; 324 int ChanNum; 325 326 ByteIO_t Cmd; 327 ByteIO_t IntChan; 328 ByteIO_t IntMask; 329 DWordIO_t IndexAddr; 330 WordIO_t IndexData; 331 332 WordIO_t TxRxData; 333 WordIO_t ChanStat; 334 WordIO_t TxRxCount; 335 ByteIO_t IntID; 336 337 Word_t TxFIFO; 338 Word_t TxFIFOPtrs; 339 Word_t RxFIFO; 340 Word_t RxFIFOPtrs; 341 Word_t TxPrioCnt; 342 Word_t TxPrioPtr; 343 Word_t TxPrioBuf; 344 345 Byte_t R[RREGDATASIZE]; 346 347 Byte_t BaudDiv[4]; 348 Byte_t TxControl[4]; 349 Byte_t RxControl[4]; 350 Byte_t TxEnables[4]; 351 Byte_t TxCompare[4]; 352 Byte_t TxReplace1[4]; 353 Byte_t TxReplace2[4]; 354} CHANNEL_T; 355 356typedef CHANNEL_T CHANNEL_t; 357typedef CHANNEL_T * CHANPTR_T; 358 359/*************************************************************************** 360Function: sClrBreak 361Purpose: Stop sending a transmit BREAK signal 362Call: sClrBreak(ChP) 363 CHANNEL_T *ChP; Ptr to channel structure 364*/ 365#define sClrBreak(ChP) \ 366{ \ 367 (ChP)->TxControl[3] &= ~SETBREAK; \ 368 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 369} 370 371/*************************************************************************** 372Function: sClrDTR 373Purpose: Clr the DTR output 374Call: sClrDTR(ChP) 375 CHANNEL_T *ChP; Ptr to channel structure 376*/ 377#define sClrDTR(ChP) \ 378{ \ 379 (ChP)->TxControl[3] &= ~SET_DTR; \ 380 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 381} 382 383/*************************************************************************** 384Function: sClrRTS 385Purpose: Clr the RTS output 386Call: sClrRTS(ChP) 387 CHANNEL_T *ChP; Ptr to channel structure 388*/ 389#define sClrRTS(ChP) \ 390{ \ 391 (ChP)->TxControl[3] &= ~SET_RTS; \ 392 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 393} 394 395/*************************************************************************** 396Function: sClrTxXOFF 397Purpose: Clear any existing transmit software flow control off condition 398Call: sClrTxXOFF(ChP) 399 CHANNEL_T *ChP; Ptr to channel structure 400*/ 401#define sClrTxXOFF(ChP) \ 402{ \ 403 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 404 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ 405} 406 407/*************************************************************************** 408Function: sCtlNumToCtlPtr 409Purpose: Convert a controller number to controller structure pointer 410Call: sCtlNumToCtlPtr(CtlNum) 411 int CtlNum; Controller number 412Return: CONTROLLER_T *: Ptr to controller structure 413*/ 414#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] 415 416/*************************************************************************** 417Function: sControllerEOI 418Purpose: Strobe the MUDBAC's End Of Interrupt bit. 419Call: sControllerEOI(CtlP) 420 CONTROLLER_T *CtlP; Ptr to controller structure 421*/ 422#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) 423 424 425/*************************************************************************** 426Function: sPCIControllerEOI 427Purpose: Strobe the MUDBAC's End Of Interrupt bit. 428Call: sPCIControllerEOI(CtlP) 429 CONTROLLER_T *CtlP; Ptr to controller structure 430*/ 431#define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB) 432 433/*************************************************************************** 434Function: sDisAiop 435Purpose: Disable I/O access to an AIOP 436Call: sDisAiop(CltP) 437 CONTROLLER_T *CtlP; Ptr to controller structure 438 int AiopNum; Number of AIOP on controller 439*/ 440#define sDisAiop(CTLP,AIOPNUM) \ 441{ \ 442 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ 443 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 444} 445 446/*************************************************************************** 447Function: sDisCTSFlowCtl 448Purpose: Disable output flow control using CTS 449Call: sDisCTSFlowCtl(ChP) 450 CHANNEL_T *ChP; Ptr to channel structure 451*/ 452#define sDisCTSFlowCtl(ChP) \ 453{ \ 454 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 455 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 456} 457 458/*************************************************************************** 459Function: DisParity 460Purpose: Disable parity 461Call: sDisParity(ChP) 462 CHANNEL_T *ChP; Ptr to channel structure 463Comments: Function sSetParity() can be used in place of functions sEnParity(), 464 sDisParity(), sSetOddParity(), and sSetEvenParity(). 465*/ 466#define sDisParity(ChP) \ 467{ \ 468 (ChP)->TxControl[2] &= ~PARITY_EN; \ 469 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 470} 471 472/*************************************************************************** 473Function: sDisRxFIFO 474Purpose: Disable Rx FIFO 475Call: sDisRxFIFO(ChP) 476 CHANNEL_T *ChP; Ptr to channel structure 477*/ 478#define sDisRxFIFO(ChP) \ 479{ \ 480 (ChP)->R[0x32] = 0x0a; \ 481 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 482} 483 484/*************************************************************************** 485Function: sDisRxStatusMode 486Purpose: Disable the Rx status mode 487Call: sDisRxStatusMode(ChP) 488 CHANNEL_T *ChP; Ptr to channel structure 489Comments: This takes the channel out of the receive status mode. All 490 subsequent reads of receive data using sReadRxWord() will return 491 two data bytes. 492*/ 493#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) 494 495/*************************************************************************** 496Function: sDisTransmit 497Purpose: Disable transmit 498Call: sDisTransmit(ChP) 499 CHANNEL_T *ChP; Ptr to channel structure 500 This disables movement of Tx data from the Tx FIFO into the 1 byte 501 Tx buffer. Therefore there could be up to a 2 byte latency 502 between the time sDisTransmit() is called and the transmit buffer 503 and transmit shift register going completely empty. 504*/ 505#define sDisTransmit(ChP) \ 506{ \ 507 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 508 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 509} 510 511/*************************************************************************** 512Function: sDisTxSoftFlowCtl 513Purpose: Disable Tx Software Flow Control 514Call: sDisTxSoftFlowCtl(ChP) 515 CHANNEL_T *ChP; Ptr to channel structure 516*/ 517#define sDisTxSoftFlowCtl(ChP) \ 518{ \ 519 (ChP)->R[0x06] = 0x8a; \ 520 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 521} 522 523/*************************************************************************** 524Function: sEnAiop 525Purpose: Enable I/O access to an AIOP 526Call: sEnAiop(CltP) 527 CONTROLLER_T *CtlP; Ptr to controller structure 528 int AiopNum; Number of AIOP on controller 529*/ 530#define sEnAiop(CTLP,AIOPNUM) \ 531{ \ 532 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ 533 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 534} 535 536/*************************************************************************** 537Function: sEnCTSFlowCtl 538Purpose: Enable output flow control using CTS 539Call: sEnCTSFlowCtl(ChP) 540 CHANNEL_T *ChP; Ptr to channel structure 541*/ 542#define sEnCTSFlowCtl(ChP) \ 543{ \ 544 (ChP)->TxControl[2] |= CTSFC_EN; \ 545 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 546} 547 548/*************************************************************************** 549Function: EnParity 550Purpose: Enable parity 551Call: sEnParity(ChP) 552 CHANNEL_T *ChP; Ptr to channel structure 553Comments: Function sSetParity() can be used in place of functions sEnParity(), 554 sDisParity(), sSetOddParity(), and sSetEvenParity(). 555 556Warnings: Before enabling parity odd or even parity should be chosen using 557 functions sSetOddParity() or sSetEvenParity(). 558*/ 559#define sEnParity(ChP) \ 560{ \ 561 (ChP)->TxControl[2] |= PARITY_EN; \ 562 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 563} 564 565/*************************************************************************** 566Function: sEnRTSFlowCtl 567Return: void 568*/ 569#define sEnRTSFlowCtl(ChP) \ 570{ \ 571 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 572 (ChP)->TxControl[3] &= ~SET_RTS; \ 573 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 574 (ChP)->RxControl[2] |= RTSFC_EN; \ 575 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 576} 577 578/*************************************************************************** 579Function: sDisRTSFlowCtl 580Return: void 581*/ 582#define sDisRTSFlowCtl(ChP) \ 583{ \ 584 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 585 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 586} 587 588/*************************************************************************** 589Function: sEnRxFIFO 590Purpose: Enable Rx FIFO 591Call: sEnRxFIFO(ChP) 592 CHANNEL_T *ChP; Ptr to channel structure 593*/ 594#define sEnRxFIFO(ChP) \ 595{ \ 596 (ChP)->R[0x32] = 0x08; \ 597 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 598} 599 600/*************************************************************************** 601Function: sEnRxProcessor 602Purpose: Enable the receive processor 603Call: sEnRxProcessor(ChP) 604 CHANNEL_T *ChP; Ptr to channel structure 605Comments: This function is used to start the receive processor. When 606 the channel is in the reset state the receive processor is not 607 running. This is done to prevent the receive processor from 608 executing invalid microcode instructions prior to the 609 downloading of the microcode. 610 611Warnings: This function must be called after valid microcode has been 612 downloaded to the AIOP, and it must not be called before the 613 microcode has been downloaded. 614*/ 615#define sEnRxProcessor(ChP) \ 616{ \ 617 (ChP)->RxControl[2] |= RXPROC_EN; \ 618 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 619} 620 621/*************************************************************************** 622Function: sEnRxStatusMode 623Purpose: Enable the Rx status mode 624Call: sEnRxStatusMode(ChP) 625 CHANNEL_T *ChP; Ptr to channel structure 626Comments: This places the channel in the receive status mode. All subsequent 627 reads of receive data using sReadRxWord() will return a data byte 628 in the low word and a status byte in the high word. 629 630*/ 631#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) 632 633/*************************************************************************** 634Function: sEnTransmit 635Purpose: Enable transmit 636Call: sEnTransmit(ChP) 637 CHANNEL_T *ChP; Ptr to channel structure 638*/ 639#define sEnTransmit(ChP) \ 640{ \ 641 (ChP)->TxControl[3] |= TX_ENABLE; \ 642 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 643} 644 645/*************************************************************************** 646Function: sGetAiopIntStatus 647Purpose: Get the AIOP interrupt status 648Call: sGetAiopIntStatus(CtlP,AiopNum) 649 CONTROLLER_T *CtlP; Ptr to controller structure 650 int AiopNum; AIOP number 651Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 652 represent channels 0 through 7 respectively. If a 653 bit is set that channel is interrupting. 654*/ 655#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) 656 657/*************************************************************************** 658Function: sGetAiopNumChan 659Purpose: Get the number of channels supported by an AIOP 660Call: sGetAiopNumChan(CtlP,AiopNum) 661 CONTROLLER_T *CtlP; Ptr to controller structure 662 int AiopNum; AIOP number 663Return: int: The number of channels supported by the AIOP 664*/ 665#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] 666 667/*************************************************************************** 668Function: sGetChanIntID 669Purpose: Get a channel's interrupt identification byte 670Call: sGetChanIntID(ChP) 671 CHANNEL_T *ChP; Ptr to channel structure 672Return: Byte_t: The channel interrupt ID. Can be any 673 combination of the following flags: 674 RXF_TRIG: Rx FIFO trigger level interrupt 675 TXFIFO_MT: Tx FIFO empty interrupt 676 SRC_INT: Special receive condition interrupt 677 DELTA_CD: CD change interrupt 678 DELTA_CTS: CTS change interrupt 679 DELTA_DSR: DSR change interrupt 680*/ 681#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 682 683/*************************************************************************** 684Function: sGetChanNum 685Purpose: Get the number of a channel within an AIOP 686Call: sGetChanNum(ChP) 687 CHANNEL_T *ChP; Ptr to channel structure 688Return: int: Channel number within AIOP, or NULLCHAN if channel does 689 not exist. 690*/ 691#define sGetChanNum(ChP) (ChP)->ChanNum 692 693/*************************************************************************** 694Function: sGetChanStatus 695Purpose: Get the channel status 696Call: sGetChanStatus(ChP) 697 CHANNEL_T *ChP; Ptr to channel structure 698Return: Word_t: The channel status. Can be any combination of 699 the following flags: 700 LOW BYTE FLAGS 701 CTS_ACT: CTS input asserted 702 DSR_ACT: DSR input asserted 703 CD_ACT: CD input asserted 704 TXFIFOMT: Tx FIFO is empty 705 TXSHRMT: Tx shift register is empty 706 RDA: Rx data available 707 708 HIGH BYTE FLAGS 709 STATMODE: status mode enable bit 710 RXFOVERFL: receive FIFO overflow 711 RX2MATCH: receive compare byte 2 match 712 RX1MATCH: receive compare byte 1 match 713 RXBREAK: received BREAK 714 RXFRAME: received framing error 715 RXPARITY: received parity error 716Warnings: This function will clear the high byte flags in the Channel 717 Status Register. 718*/ 719#define sGetChanStatus(ChP) sInW((ChP)->ChanStat) 720 721/*************************************************************************** 722Function: sGetChanStatusLo 723Purpose: Get the low byte only of the channel status 724Call: sGetChanStatusLo(ChP) 725 CHANNEL_T *ChP; Ptr to channel structure 726Return: Byte_t: The channel status low byte. Can be any combination 727 of the following flags: 728 CTS_ACT: CTS input asserted 729 DSR_ACT: DSR input asserted 730 CD_ACT: CD input asserted 731 TXFIFOMT: Tx FIFO is empty 732 TXSHRMT: Tx shift register is empty 733 RDA: Rx data available 734*/ 735#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) 736 737/*************************************************************************** 738Function: sGetControllerIntStatus 739Purpose: Get the controller interrupt status 740Call: sGetControllerIntStatus(CtlP) 741 CONTROLLER_T *CtlP; Ptr to controller structure 742Return: Byte_t: The controller interrupt status in the lower 4 743 bits. Bits 0 through 3 represent AIOP's 0 744 through 3 respectively. If a bit is set that 745 AIOP is interrupting. Bits 4 through 7 will 746 always be cleared. 747*/ 748#define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) 749 750/*************************************************************************** 751Function: sPCIGetControllerIntStatus 752Purpose: Get the controller interrupt status 753Call: sPCIGetControllerIntStatus(CtlP) 754 CONTROLLER_T *CtlP; Ptr to controller structure 755Return: Byte_t: The controller interrupt status in the lower 4 756 bits. Bits 0 through 3 represent AIOP's 0 757 through 3 respectively. If a bit is set that 758 AIOP is interrupting. Bits 4 through 7 will 759 always be cleared. 760*/ 761#define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f) 762 763/*************************************************************************** 764Function: sGetRxCnt 765Purpose: Get the number of data bytes in the Rx FIFO 766Call: sGetRxCnt(ChP) 767 CHANNEL_T *ChP; Ptr to channel structure 768Return: int: The number of data bytes in the Rx FIFO. 769Comments: Byte read of count register is required to obtain Rx count. 770 771*/ 772#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) 773 774/*************************************************************************** 775Function: sGetTxCnt 776Purpose: Get the number of data bytes in the Tx FIFO 777Call: sGetTxCnt(ChP) 778 CHANNEL_T *ChP; Ptr to channel structure 779Return: Byte_t: The number of data bytes in the Tx FIFO. 780Comments: Byte read of count register is required to obtain Tx count. 781 782*/ 783#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) 784 785/***************************************************************************** 786Function: sGetTxRxDataIO 787Purpose: Get the I/O address of a channel's TxRx Data register 788Call: sGetTxRxDataIO(ChP) 789 CHANNEL_T *ChP; Ptr to channel structure 790Return: WordIO_t: I/O address of a channel's TxRx Data register 791*/ 792#define sGetTxRxDataIO(ChP) (ChP)->TxRxData 793 794/*************************************************************************** 795Function: sInitChanDefaults 796Purpose: Initialize a channel structure to it's default state. 797Call: sInitChanDefaults(ChP) 798 CHANNEL_T *ChP; Ptr to the channel structure 799Comments: This function must be called once for every channel structure 800 that exists before any other SSCI calls can be made. 801 802*/ 803#define sInitChanDefaults(ChP) \ 804{ \ 805 (ChP)->CtlP = NULLCTLPTR; \ 806 (ChP)->AiopNum = NULLAIOP; \ 807 (ChP)->ChanID = AIOPID_NULL; \ 808 (ChP)->ChanNum = NULLCHAN; \ 809} 810 811/*************************************************************************** 812Function: sResetAiopByNum 813Purpose: Reset the AIOP by number 814Call: sResetAiopByNum(CTLP,AIOPNUM) 815 CONTROLLER_T CTLP; Ptr to controller structure 816 AIOPNUM; AIOP index 817*/ 818#define sResetAiopByNum(CTLP,AIOPNUM) \ 819{ \ 820 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ 821 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ 822} 823 824/*************************************************************************** 825Function: sSendBreak 826Purpose: Send a transmit BREAK signal 827Call: sSendBreak(ChP) 828 CHANNEL_T *ChP; Ptr to channel structure 829*/ 830#define sSendBreak(ChP) \ 831{ \ 832 (ChP)->TxControl[3] |= SETBREAK; \ 833 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 834} 835 836/*************************************************************************** 837Function: sSetBaud 838Purpose: Set baud rate 839Call: sSetBaud(ChP,Divisor) 840 CHANNEL_T *ChP; Ptr to channel structure 841 Word_t Divisor; 16 bit baud rate divisor for channel 842*/ 843#define sSetBaud(ChP,DIVISOR) \ 844{ \ 845 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 846 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 847 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 848} 849 850/*************************************************************************** 851Function: sSetData7 852Purpose: Set data bits to 7 853Call: sSetData7(ChP) 854 CHANNEL_T *ChP; Ptr to channel structure 855*/ 856#define sSetData7(ChP) \ 857{ \ 858 (ChP)->TxControl[2] &= ~DATA8BIT; \ 859 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 860} 861 862/*************************************************************************** 863Function: sSetData8 864Purpose: Set data bits to 8 865Call: sSetData8(ChP) 866 CHANNEL_T *ChP; Ptr to channel structure 867*/ 868#define sSetData8(ChP) \ 869{ \ 870 (ChP)->TxControl[2] |= DATA8BIT; \ 871 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 872} 873 874/*************************************************************************** 875Function: sSetDTR 876Purpose: Set the DTR output 877Call: sSetDTR(ChP) 878 CHANNEL_T *ChP; Ptr to channel structure 879*/ 880#define sSetDTR(ChP) \ 881{ \ 882 (ChP)->TxControl[3] |= SET_DTR; \ 883 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 884} 885 886/*************************************************************************** 887Function: sSetEvenParity 888Purpose: Set even parity 889Call: sSetEvenParity(ChP) 890 CHANNEL_T *ChP; Ptr to channel structure 891Comments: Function sSetParity() can be used in place of functions sEnParity(), 892 sDisParity(), sSetOddParity(), and sSetEvenParity(). 893 894Warnings: This function has no effect unless parity is enabled with function 895 sEnParity(). 896*/ 897#define sSetEvenParity(ChP) \ 898{ \ 899 (ChP)->TxControl[2] |= EVEN_PAR; \ 900 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 901} 902 903/*************************************************************************** 904Function: sSetOddParity 905Purpose: Set odd parity 906Call: sSetOddParity(ChP) 907 CHANNEL_T *ChP; Ptr to channel structure 908Comments: Function sSetParity() can be used in place of functions sEnParity(), 909 sDisParity(), sSetOddParity(), and sSetEvenParity(). 910 911Warnings: This function has no effect unless parity is enabled with function 912 sEnParity(). 913*/ 914#define sSetOddParity(ChP) \ 915{ \ 916 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 917 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 918} 919 920/*************************************************************************** 921Function: sSetRTS 922Purpose: Set the RTS output 923Call: sSetRTS(ChP) 924 CHANNEL_T *ChP; Ptr to channel structure 925*/ 926#define sSetRTS(ChP) \ 927{ \ 928 (ChP)->TxControl[3] |= SET_RTS; \ 929 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 930} 931 932/*************************************************************************** 933Function: sSetRxTrigger 934Purpose: Set the Rx FIFO trigger level 935Call: sSetRxProcessor(ChP,Level) 936 CHANNEL_T *ChP; Ptr to channel structure 937 Byte_t Level; Number of characters in Rx FIFO at which the 938 interrupt will be generated. Can be any of the following flags: 939 940 TRIG_NO: no trigger 941 TRIG_1: 1 character in FIFO 942 TRIG_1_2: FIFO 1/2 full 943 TRIG_7_8: FIFO 7/8 full 944Comments: An interrupt will be generated when the trigger level is reached 945 only if function sEnInterrupt() has been called with flag 946 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 947 register will be set whenever the trigger level is reached 948 regardless of the setting of RXINT_EN. 949 950*/ 951#define sSetRxTrigger(ChP,LEVEL) \ 952{ \ 953 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 954 (ChP)->RxControl[2] |= LEVEL; \ 955 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 956} 957 958/*************************************************************************** 959Function: sSetStop1 960Purpose: Set stop bits to 1 961Call: sSetStop1(ChP) 962 CHANNEL_T *ChP; Ptr to channel structure 963*/ 964#define sSetStop1(ChP) \ 965{ \ 966 (ChP)->TxControl[2] &= ~STOP2; \ 967 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 968} 969 970/*************************************************************************** 971Function: sSetStop2 972Purpose: Set stop bits to 2 973Call: sSetStop2(ChP) 974 CHANNEL_T *ChP; Ptr to channel structure 975*/ 976#define sSetStop2(ChP) \ 977{ \ 978 (ChP)->TxControl[2] |= STOP2; \ 979 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 980} 981 982/*************************************************************************** 983Function: sStartRxProcessor 984Purpose: Start a channel's receive processor 985Call: sStartRxProcessor(ChP) 986 CHANNEL_T *ChP; Ptr to channel structure 987Comments: This function is used to start a Rx processor after it was 988 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 989 will restart both the Rx processor and software input flow control. 990 991*/ 992#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) 993 994/*************************************************************************** 995Function: sWriteTxByte 996Purpose: Write a transmit data byte to a channel. 997 ByteIO_t io: Channel transmit register I/O address. This can 998 be obtained with sGetTxRxDataIO(). 999 Byte_t Data; The transmit data byte. 1000Warnings: This function writes the data byte without checking to see if 1001 sMaxTxSize is exceeded in the Tx FIFO. 1002*/ 1003#define sWriteTxByte(IO,DATA) sOutB(IO,DATA) 1004 1005int sInitController( CONTROLLER_T *CtlP, 1006 int CtlNum, 1007 ByteIO_t MudbacIO, 1008 ByteIO_t *AiopIOList, 1009 int AiopIOListSize, 1010 int IRQNum, 1011 Byte_t Frequency, 1012 int PeriodicOnly); 1013 1014int sPCIInitController( CONTROLLER_T *CtlP, 1015 int CtlNum, 1016 ByteIO_t *AiopIOList, 1017 int AiopIOListSize, 1018 int IRQNum, 1019 Byte_t Frequency, 1020 int PeriodicOnly); 1021 1022int sReadAiopID(ByteIO_t io); 1023int sReadAiopNumChan(WordIO_t io); 1024int sInitChan( CONTROLLER_T *CtlP, 1025 CHANNEL_T *ChP, 1026 int AiopNum, 1027 int ChanNum); 1028Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 1029void sStopRxProcessor(CHANNEL_T *ChP); 1030void sStopSWInFlowCtl(CHANNEL_T *ChP); 1031void sFlushRxFIFO(CHANNEL_T *ChP); 1032void sFlushTxFIFO(CHANNEL_T *ChP); 1033int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1034void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1035void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1036 1037#ifndef ROCKET_C 1038extern Byte_t R[RDATASIZE]; 1039extern CONTROLLER_T sController[CTL_SIZE]; 1040extern Byte_t sIRQMap[16]; 1041extern Byte_t sBitMapClrTbl[8]; 1042extern Byte_t sBitMapSetTbl[8]; 1043#endif 1044