rpreg.h revision 191563
1/*- 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted prodived that the follwoing conditions 7 * are met. 8 * 1. Redistributions of source code must retain the above copyright 9 * notive, this list of conditions and the following disclainer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials prodided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Comtrol Corporation. 16 * 4. The name of Comtrol Corporation may not be used to endorse or 17 * promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/rp/rpreg.h 191563 2009-04-27 15:58:38Z ambrisko $ 33 */ 34 35/* 36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 37 */ 38 39typedef uint8_t Byte_t; 40typedef uint8_t ByteIO_t; 41 42typedef uint16_t Word_t; 43typedef uint16_t WordIO_t; 44 45typedef uint32_t DWord_t; 46typedef uint32_t DWordIO_t; 47 48#define rp_readio(size, ctlp, rid, offset) \ 49 (bus_read_##size(ctlp->io[rid], offset)) 50#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \ 51 (bus_read_multi_##size(ctlp->io[rid], offset, addr, count)) 52#define rp_writeio(size, ctlp, rid, offset, data) \ 53 (bus_write_##size(ctlp->io[rid], offset, data)) 54#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \ 55 (bus_write_multi_##size(ctlp->io[rid], offset, addr, count)) 56 57#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset) 58#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset) 59#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset) 60#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data) 61#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data) 62#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data) 63#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count) 64#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count) 65#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count) 66#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count) 67#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count) 68#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count) 69 70#define rp_readaiop1(ctlp, aiop, offset) \ 71 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 72#define rp_readaiop2(ctlp, aiop, offset) \ 73 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 74#define rp_readaiop4(ctlp, aiop, offset) \ 75 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 76#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \ 77 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 78#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \ 79 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 80#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \ 81 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 82#define rp_writeaiop1(ctlp, aiop, offset, data) \ 83 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 84#define rp_writeaiop2(ctlp, aiop, offset, data) \ 85 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 86#define rp_writeaiop4(ctlp, aiop, offset, data) \ 87 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 88#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \ 89 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 90#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \ 91 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 92#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \ 93 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 94 95#define rp_readch1(chp, offset) \ 96 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset)) 97#define rp_readch2(chp, offset) \ 98 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset)) 99#define rp_readch4(chp, offset) \ 100 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset)) 101#define rp_readmultich1(chp, offset, addr, count) \ 102 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 103#define rp_readmultich2(chp, offset, addr, count) \ 104 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 105#define rp_readmultich4(chp, offset, addr, count) \ 106 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 107#define rp_writech1(chp, offset, data) \ 108 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data)) 109#define rp_writech2(chp, offset, data) \ 110 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data)) 111#define rp_writech4(chp, offset, data) \ 112 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data)) 113#define rp_writemultich1(chp, offset, addr, count) \ 114 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 115#define rp_writemultich2(chp, offset, addr, count) \ 116 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 117#define rp_writemultich4(chp, offset, addr, count) \ 118 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 119 120/* 121 * End of OS-specific defines 122 */ 123 124#define ROCKET_H 125 126#define CTL_SIZE 4 127#define AIOP_CTL_SIZE 4 128#define CHAN_AIOP_SIZE 8 129#define MAX_PORTS_PER_AIOP 8 130#define MAX_AIOPS_PER_BOARD 4 131#define MAX_PORTS_PER_BOARD 32 132 133/* Controller ID numbers */ 134#define CTLID_NULL -1 /* no controller exists */ 135#define CTLID_0001 0x0001 /* controller release 1 */ 136 137/* AIOP ID numbers, identifies AIOP type implementing channel */ 138#define AIOPID_NULL -1 /* no AIOP or channel exists */ 139#define AIOPID_0001 0x0001 /* AIOP release 1 */ 140 141#define NULLDEV -1 /* identifies non-existant device */ 142#define NULLCTL -1 /* identifies non-existant controller */ 143#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 144#define NULLAIOP -1 /* identifies non-existant AIOP */ 145#define NULLCHAN -1 /* identifies non-existant channel */ 146 147/************************************************************************ 148 Global Register Offsets - Direct Access - Fixed values 149************************************************************************/ 150 151#define _CMD_REG 0x38 /* Command Register 8 Write */ 152#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 153#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 154#define _UNUSED 0x3B /* Unused 8 */ 155#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 156#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 157 158/************************************************************************ 159 Channel Register Offsets for 1st channel in AIOP - Direct Access 160************************************************************************/ 161#define _TD0 0x00 /* Transmit Data 16 Write */ 162#define _RD0 0x00 /* Receive Data 16 Read */ 163#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 164#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 165#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 166 167/************************************************************************ 168 Tx Control Register Offsets - Indexed - External - Fixed 169************************************************************************/ 170#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 171#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 172#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 173#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 174#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 175#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 176 177/************************************************************************ 178 Receive FIFO 179************************************************************************/ 180#define RXFIFO_DATA 0x5f 181#define RXFIFO_OUT 0x5c 182#define RXFIFO_EN 0x08 183#define RXFIFO_DIS 0xa7 184 185/************************************************************************ 186Memory Controller Register Offsets - Indexed - External - Fixed 187************************************************************************/ 188#define _RX_FIFO 0x000 /* Rx FIFO */ 189#define _TX_FIFO 0x800 /* Tx FIFO */ 190#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 191#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 192#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 193#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 194#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 195#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 196 197#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 198#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 199#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 200 201/************************************************************************ 202Tx Priority Buffer - Indexed - External - Fixed 203************************************************************************/ 204#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 205#define TXP_SIZE 0x20 /* 32 bytes */ 206 207/************************************************************************ 208Channel Register Offsets - Indexed - Internal - Fixed 209************************************************************************/ 210 211#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 212#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 213#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 214#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 215 216#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 217 218#define BRD50 4607 219#define BRD75 3071 220#define BRD110 2094 221#define BRD134 1712 222#define BRD150 1535 223#define BRD200 1151 224#define BRD300 767 225#define BRD600 383 226#define BRD1200 191 227#define BRD1800 127 228#define BRD2000 114 229#define BRD2400 95 230#define BRD3600 64 231#define BRD4800 47 232#define BRD7200 31 233#define BRD9600 23 234#define BRD14400 15 235#define BRD19200 11 236#define BRD38400 5 237#define BRD57600 3 238#define BRD76800 2 239#define BRD115200 1 240#define BRD230400 0 241 242#define STMBREAK 0x08 /* BREAK */ 243#define STMFRAME 0x04 /* framing error */ 244#define STMRCVROVR 0x02 /* receiver over run error */ 245#define STMPARITY 0x01 /* parity error */ 246#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 247#define STMBREAKH 0x800 /* BREAK */ 248#define STMFRAMEH 0x400 /* framing error */ 249#define STMRCVROVRH 0x200 /* receiver over run error */ 250#define STMPARITYH 0x100 /* parity error */ 251#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 252 253#define CTS_ACT 0x20 /* CTS input asserted */ 254#define DSR_ACT 0x10 /* DSR input asserted */ 255#define CD_ACT 0x08 /* CD input asserted */ 256#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 257#define TXSHRMT 0x02 /* Tx shift register is empty */ 258#define RDA 0x01 /* Rx data available */ 259#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 260 261#define STATMODE 0x8000 /* status mode enable bit */ 262#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 263#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 264#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 265#define RXBREAK 0x0400 /* received BREAK */ 266#define RXFRAME 0x0200 /* received framing error */ 267#define RXPARITY 0x0100 /* received parity error */ 268#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 269 270#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 271#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 272#define TXINT_EN 0x10 /* transmit interrupt enable */ 273#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 274#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 275#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 276#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 277 278#define SETBREAK 0x10 /* send break condition (must clear) */ 279#define LOCALLOOP 0x08 /* local loopback set for test */ 280#define SET_DTR 0x04 /* assert DTR */ 281#define SET_RTS 0x02 /* assert RTS */ 282#define TX_ENABLE 0x01 /* enable transmitter */ 283 284#define RTSFC_EN 0x40 /* RTS flow control enable */ 285#define RXPROC_EN 0x20 /* receive processor enable */ 286#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 287#define TRIG_1 0x08 /* trigger level 1 char */ 288#define TRIG_1_2 0x10 /* trigger level 1/2 */ 289#define TRIG_7_8 0x18 /* trigger level 7/8 */ 290#define TRIG_MASK 0x18 /* trigger level mask */ 291#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 292#define RXINT_EN 0x02 /* Rx interrupt enable */ 293#define MCINT_EN 0x01 /* modem change interrupt enable */ 294 295#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 296#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 297#define SRC_INT 0x08 /* special receive condition interrupt */ 298#define DELTA_CD 0x04 /* CD change interrupt */ 299#define DELTA_CTS 0x02 /* CTS change interrupt */ 300#define DELTA_DSR 0x01 /* DSR change interrupt */ 301 302#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 303#define IGN2_EN 0x08 /* ignore byte 2 enable */ 304#define IGN1_EN 0x04 /* ignore byte 1 enable */ 305#define COMP2_EN 0x02 /* compare byte 2 enable */ 306#define COMP1_EN 0x01 /* compare byte 1 enable */ 307 308#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 309#define TXOVERIDE 0x40 /* Transmit software off override */ 310#define RESETUART 0x20 /* reset channel's UART */ 311#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 312#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 313 314#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 315#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 316#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 317#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 318 319#define INTR_EN 0x08 /* allow interrupts to host */ 320#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 321 322#define CHAN3_EN 0x08 /* enable AIOP 3 */ 323#define CHAN2_EN 0x04 /* enable AIOP 2 */ 324#define CHAN1_EN 0x02 /* enable AIOP 1 */ 325#define CHAN0_EN 0x01 /* enable AIOP 0 */ 326#define FREQ_DIS 0x00 327#define FREQ_274HZ 0x60 328#define FREQ_137HZ 0x50 329#define FREQ_69HZ 0x40 330#define FREQ_34HZ 0x30 331#define FREQ_17HZ 0x20 332#define FREQ_9HZ 0x10 333#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 334 335#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 336 337#define RDATASIZE 72 338#define RREGDATASIZE 52 339 340#ifndef TRUE 341#define TRUE 1 342#endif 343 344#ifndef FALSE 345#define FALSE 0 346#endif 347 348struct CONTROLLER_str; 349struct CHANNEL_str; 350 351/* The types of bus-specific methods */ 352typedef int rp_aiop2rid_t(int, int); 353typedef int rp_aiop2off_t(int, int); 354typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *); 355 356/* Controller level information structure */ 357struct CONTROLLER_str 358{ 359 int CtlID; 360 int NumAiop; 361 int AiopID[AIOP_CTL_SIZE]; 362 int AiopNumChan[AIOP_CTL_SIZE]; 363 364 struct mtx hwmtx; /* Spinlock protecting hardware. */ 365 int hwmtx_init; 366 int free; 367 368 /* Device and resource management */ 369 device_t dev; /* device */ 370 int io_num; /* Number of IO resources */ 371 int *io_rid; /* IO resource IDs */ 372 struct resource **io; /* IO resources */ 373 374 struct rp_port *rp; /* port */ 375 376 /* Device nodes */ 377 struct cdev **dev_nodes; 378 379 /* Bus-specific properties */ 380 void *bus_ctlp; 381 382 /* Bus-specific methods */ 383 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */ 384 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */ 385 rp_ctlmask_t *ctlmask; /* Int status */ 386}; 387typedef struct CONTROLLER_str CONTROLLER_T; 388typedef CONTROLLER_T CONTROLLER_t; 389 390/* Channel level information structure */ 391struct CHANNEL_str 392{ 393 CONTROLLER_t *CtlP; 394 int AiopNum; 395 int ChanID; 396 int ChanNum; 397 398 Word_t TxFIFO; 399 Word_t TxFIFOPtrs; 400 Word_t RxFIFO; 401 Word_t RxFIFOPtrs; 402 Word_t TxPrioCnt; 403 Word_t TxPrioPtr; 404 Word_t TxPrioBuf; 405 406 Byte_t R[RREGDATASIZE]; 407 408 Byte_t BaudDiv[4]; 409 Byte_t TxControl[4]; 410 Byte_t RxControl[4]; 411 Byte_t TxEnables[4]; 412 Byte_t TxCompare[4]; 413 Byte_t TxReplace1[4]; 414 Byte_t TxReplace2[4]; 415}; 416 417typedef struct CHANNEL_str CHANNEL_T; 418typedef CHANNEL_T CHANNEL_t; 419typedef CHANNEL_T * CHANPTR_T; 420 421#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0) 422#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0) 423#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0) 424#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0) 425 426/*************************************************************************** 427Function: sClrBreak 428Purpose: Stop sending a transmit BREAK signal 429Call: sClrBreak(ChP) 430 CHANNEL_T *ChP; Ptr to channel structure 431*/ 432#define sClrBreak(ChP) \ 433{ \ 434 (ChP)->TxControl[3] &= ~SETBREAK; \ 435 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 436} 437 438/*************************************************************************** 439Function: sClrDTR 440Purpose: Clr the DTR output 441Call: sClrDTR(ChP) 442 CHANNEL_T *ChP; Ptr to channel structure 443*/ 444#define sClrDTR(ChP) \ 445{ \ 446 (ChP)->TxControl[3] &= ~SET_DTR; \ 447 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 448} 449 450/*************************************************************************** 451Function: sClrRTS 452Purpose: Clr the RTS output 453Call: sClrRTS(ChP) 454 CHANNEL_T *ChP; Ptr to channel structure 455*/ 456#define sClrRTS(ChP) \ 457{ \ 458 (ChP)->TxControl[3] &= ~SET_RTS; \ 459 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 460} 461 462/*************************************************************************** 463Function: sClrTxXOFF 464Purpose: Clear any existing transmit software flow control off condition 465Call: sClrTxXOFF(ChP) 466 CHANNEL_T *ChP; Ptr to channel structure 467*/ 468#define sClrTxXOFF(ChP) \ 469{ \ 470 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 471 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \ 472} 473 474/*************************************************************************** 475Function: sDisCTSFlowCtl 476Purpose: Disable output flow control using CTS 477Call: sDisCTSFlowCtl(ChP) 478 CHANNEL_T *ChP; Ptr to channel structure 479*/ 480#define sDisCTSFlowCtl(ChP) \ 481{ \ 482 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 483 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 484} 485 486/*************************************************************************** 487Function: DisParity 488Purpose: Disable parity 489Call: sDisParity(ChP) 490 CHANNEL_T *ChP; Ptr to channel structure 491Comments: Function sSetParity() can be used in place of functions sEnParity(), 492 sDisParity(), sSetOddParity(), and sSetEvenParity(). 493*/ 494#define sDisParity(ChP) \ 495{ \ 496 (ChP)->TxControl[2] &= ~PARITY_EN; \ 497 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 498} 499 500/*************************************************************************** 501Function: sDisRxFIFO 502Purpose: Disable Rx FIFO 503Call: sDisRxFIFO(ChP) 504 CHANNEL_T *ChP; Ptr to channel structure 505*/ 506#define sDisRxFIFO(ChP) \ 507{ \ 508 (ChP)->R[0x32] = 0x0a; \ 509 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 510} 511 512/*************************************************************************** 513Function: sDisRxStatusMode 514Purpose: Disable the Rx status mode 515Call: sDisRxStatusMode(ChP) 516 CHANNEL_T *ChP; Ptr to channel structure 517Comments: This takes the channel out of the receive status mode. All 518 subsequent reads of receive data using sReadRxWord() will return 519 two data bytes. 520*/ 521#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0) 522 523/*************************************************************************** 524Function: sDisTransmit 525Purpose: Disable transmit 526Call: sDisTransmit(ChP) 527 CHANNEL_T *ChP; Ptr to channel structure 528 This disables movement of Tx data from the Tx FIFO into the 1 byte 529 Tx buffer. Therefore there could be up to a 2 byte latency 530 between the time sDisTransmit() is called and the transmit buffer 531 and transmit shift register going completely empty. 532*/ 533#define sDisTransmit(ChP) \ 534{ \ 535 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 536 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 537} 538 539/*************************************************************************** 540Function: sDisTxSoftFlowCtl 541Purpose: Disable Tx Software Flow Control 542Call: sDisTxSoftFlowCtl(ChP) 543 CHANNEL_T *ChP; Ptr to channel structure 544*/ 545#define sDisTxSoftFlowCtl(ChP) \ 546{ \ 547 (ChP)->R[0x06] = 0x8a; \ 548 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x04)); \ 549} 550 551/*************************************************************************** 552Function: sEnCTSFlowCtl 553Purpose: Enable output flow control using CTS 554Call: sEnCTSFlowCtl(ChP) 555 CHANNEL_T *ChP; Ptr to channel structure 556*/ 557#define sEnCTSFlowCtl(ChP) \ 558{ \ 559 (ChP)->TxControl[2] |= CTSFC_EN; \ 560 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 561} 562 563/*************************************************************************** 564Function: EnParity 565Purpose: Enable parity 566Call: sEnParity(ChP) 567 CHANNEL_T *ChP; Ptr to channel structure 568Comments: Function sSetParity() can be used in place of functions sEnParity(), 569 sDisParity(), sSetOddParity(), and sSetEvenParity(). 570 571Warnings: Before enabling parity odd or even parity should be chosen using 572 functions sSetOddParity() or sSetEvenParity(). 573*/ 574#define sEnParity(ChP) \ 575{ \ 576 (ChP)->TxControl[2] |= PARITY_EN; \ 577 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 578} 579 580/*************************************************************************** 581Function: sEnRTSFlowCtl 582Return: void 583*/ 584#define sEnRTSFlowCtl(ChP) \ 585{ \ 586 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 587 (ChP)->TxControl[3] &= ~SET_RTS; \ 588 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 589 (ChP)->RxControl[2] |= RTSFC_EN; \ 590 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 591} 592 593/*************************************************************************** 594Function: sDisRTSFlowCtl 595Return: void 596*/ 597#define sDisRTSFlowCtl(ChP) \ 598{ \ 599 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 600 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 601} 602 603/*************************************************************************** 604Function: sEnRxFIFO 605Purpose: Enable Rx FIFO 606Call: sEnRxFIFO(ChP) 607 CHANNEL_T *ChP; Ptr to channel structure 608*/ 609#define sEnRxFIFO(ChP) \ 610{ \ 611 (ChP)->R[0x32] = 0x08; \ 612 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 613} 614 615/*************************************************************************** 616Function: sEnRxProcessor 617Purpose: Enable the receive processor 618Call: sEnRxProcessor(ChP) 619 CHANNEL_T *ChP; Ptr to channel structure 620Comments: This function is used to start the receive processor. When 621 the channel is in the reset state the receive processor is not 622 running. This is done to prevent the receive processor from 623 executing invalid microcode instructions prior to the 624 downloading of the microcode. 625 626Warnings: This function must be called after valid microcode has been 627 downloaded to the AIOP, and it must not be called before the 628 microcode has been downloaded. 629*/ 630#define sEnRxProcessor(ChP) \ 631{ \ 632 (ChP)->RxControl[2] |= RXPROC_EN; \ 633 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 634} 635 636/*************************************************************************** 637Function: sEnRxStatusMode 638Purpose: Enable the Rx status mode 639Call: sEnRxStatusMode(ChP) 640 CHANNEL_T *ChP; Ptr to channel structure 641Comments: This places the channel in the receive status mode. All subsequent 642 reads of receive data using sReadRxWord() will return a data byte 643 in the low word and a status byte in the high word. 644 645*/ 646#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE) 647 648/*************************************************************************** 649Function: sEnTransmit 650Purpose: Enable transmit 651Call: sEnTransmit(ChP) 652 CHANNEL_T *ChP; Ptr to channel structure 653*/ 654#define sEnTransmit(ChP) \ 655{ \ 656 (ChP)->TxControl[3] |= TX_ENABLE; \ 657 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 658} 659 660/*************************************************************************** 661Function: sGetAiopIntStatus 662Purpose: Get the AIOP interrupt status 663Call: sGetAiopIntStatus(CtlP,AiopNum) 664 CONTROLLER_T *CtlP; Ptr to controller structure 665 int AiopNum; AIOP number 666Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 667 represent channels 0 through 7 respectively. If a 668 bit is set that channel is interrupting. 669*/ 670#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN) 671 672/*************************************************************************** 673Function: sGetAiopNumChan 674Purpose: Get the number of channels supported by an AIOP 675Call: sGetAiopNumChan(CtlP,AiopNum) 676 CONTROLLER_T *CtlP; Ptr to controller structure 677 int AiopNum; AIOP number 678Return: int: The number of channels supported by the AIOP 679*/ 680#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM] 681 682/*************************************************************************** 683Function: sGetChanIntID 684Purpose: Get a channel's interrupt identification byte 685Call: sGetChanIntID(ChP) 686 CHANNEL_T *ChP; Ptr to channel structure 687Return: Byte_t: The channel interrupt ID. Can be any 688 combination of the following flags: 689 RXF_TRIG: Rx FIFO trigger level interrupt 690 TXFIFO_MT: Tx FIFO empty interrupt 691 SRC_INT: Special receive condition interrupt 692 DELTA_CD: CD change interrupt 693 DELTA_CTS: CTS change interrupt 694 DELTA_DSR: DSR change interrupt 695*/ 696#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 697 698/*************************************************************************** 699Function: sGetChanNum 700Purpose: Get the number of a channel within an AIOP 701Call: sGetChanNum(ChP) 702 CHANNEL_T *ChP; Ptr to channel structure 703Return: int: Channel number within AIOP, or NULLCHAN if channel does 704 not exist. 705*/ 706#define sGetChanNum(ChP) (ChP)->ChanNum 707 708/*************************************************************************** 709Function: sGetChanStatus 710Purpose: Get the channel status 711Call: sGetChanStatus(ChP) 712 CHANNEL_T *ChP; Ptr to channel structure 713Return: Word_t: The channel status. Can be any combination of 714 the following flags: 715 LOW BYTE FLAGS 716 CTS_ACT: CTS input asserted 717 DSR_ACT: DSR input asserted 718 CD_ACT: CD input asserted 719 TXFIFOMT: Tx FIFO is empty 720 TXSHRMT: Tx shift register is empty 721 RDA: Rx data available 722 723 HIGH BYTE FLAGS 724 STATMODE: status mode enable bit 725 RXFOVERFL: receive FIFO overflow 726 RX2MATCH: receive compare byte 2 match 727 RX1MATCH: receive compare byte 1 match 728 RXBREAK: received BREAK 729 RXFRAME: received framing error 730 RXPARITY: received parity error 731Warnings: This function will clear the high byte flags in the Channel 732 Status Register. 733*/ 734#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP)) 735 736/*************************************************************************** 737Function: sGetChanStatusLo 738Purpose: Get the low byte only of the channel status 739Call: sGetChanStatusLo(ChP) 740 CHANNEL_T *ChP; Ptr to channel structure 741Return: Byte_t: The channel status low byte. Can be any combination 742 of the following flags: 743 CTS_ACT: CTS input asserted 744 DSR_ACT: DSR input asserted 745 CD_ACT: CD input asserted 746 TXFIFOMT: Tx FIFO is empty 747 TXSHRMT: Tx shift register is empty 748 RDA: Rx data available 749*/ 750#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP)) 751 752/*************************************************************************** 753Function: sGetRxCnt 754Purpose: Get the number of data bytes in the Rx FIFO 755Call: sGetRxCnt(ChP) 756 CHANNEL_T *ChP; Ptr to channel structure 757Return: int: The number of data bytes in the Rx FIFO. 758Comments: Byte read of count register is required to obtain Rx count. 759 760*/ 761#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP)) 762 763/*************************************************************************** 764Function: sGetTxCnt 765Purpose: Get the number of data bytes in the Tx FIFO 766Call: sGetTxCnt(ChP) 767 CHANNEL_T *ChP; Ptr to channel structure 768Return: Byte_t: The number of data bytes in the Tx FIFO. 769Comments: Byte read of count register is required to obtain Tx count. 770 771*/ 772#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP)) 773 774/***************************************************************************** 775Function: sGetTxRxDataIO 776Purpose: Get the offset of a channel's TxRx Data register 777Call: sGetTxRxDataIO(ChP) 778 CHANNEL_T *ChP; Ptr to channel structure 779Return: WordIO_t: offset of a channel's TxRx Data register 780*/ 781#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP) 782 783/*************************************************************************** 784Function: sInitChanDefaults 785Purpose: Initialize a channel structure to its default state. 786Call: sInitChanDefaults(ChP) 787 CHANNEL_T *ChP; Ptr to the channel structure 788Comments: This function must be called once for every channel structure 789 that exists before any other SSCI calls can be made. 790 791*/ 792#define sInitChanDefaults(ChP) \ 793{ \ 794 (ChP)->CtlP = NULLCTLPTR; \ 795 (ChP)->AiopNum = NULLAIOP; \ 796 (ChP)->ChanID = AIOPID_NULL; \ 797 (ChP)->ChanNum = NULLCHAN; \ 798} 799 800/*************************************************************************** 801Function: sResetAiopByNum 802Purpose: Reset the AIOP by number 803Call: sResetAiopByNum(CTLP,AIOPNUM) 804 CONTROLLER_T CTLP; Ptr to controller structure 805 AIOPNUM; AIOP index 806*/ 807#define sResetAiopByNum(CTLP,AIOPNUM) \ 808{ \ 809 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \ 810 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \ 811} 812 813/*************************************************************************** 814Function: sSendBreak 815Purpose: Send a transmit BREAK signal 816Call: sSendBreak(ChP) 817 CHANNEL_T *ChP; Ptr to channel structure 818*/ 819#define sSendBreak(ChP) \ 820{ \ 821 (ChP)->TxControl[3] |= SETBREAK; \ 822 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 823} 824 825/*************************************************************************** 826Function: sSetBaud 827Purpose: Set baud rate 828Call: sSetBaud(ChP,Divisor) 829 CHANNEL_T *ChP; Ptr to channel structure 830 Word_t Divisor; 16 bit baud rate divisor for channel 831*/ 832#define sSetBaud(ChP,DIVISOR) \ 833{ \ 834 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 835 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 836 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->BaudDiv)); \ 837} 838 839/*************************************************************************** 840Function: sSetData7 841Purpose: Set data bits to 7 842Call: sSetData7(ChP) 843 CHANNEL_T *ChP; Ptr to channel structure 844*/ 845#define sSetData7(ChP) \ 846{ \ 847 (ChP)->TxControl[2] &= ~DATA8BIT; \ 848 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 849} 850 851/*************************************************************************** 852Function: sSetData8 853Purpose: Set data bits to 8 854Call: sSetData8(ChP) 855 CHANNEL_T *ChP; Ptr to channel structure 856*/ 857#define sSetData8(ChP) \ 858{ \ 859 (ChP)->TxControl[2] |= DATA8BIT; \ 860 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 861} 862 863/*************************************************************************** 864Function: sSetDTR 865Purpose: Set the DTR output 866Call: sSetDTR(ChP) 867 CHANNEL_T *ChP; Ptr to channel structure 868*/ 869#define sSetDTR(ChP) \ 870{ \ 871 (ChP)->TxControl[3] |= SET_DTR; \ 872 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 873} 874 875/*************************************************************************** 876Function: sSetEvenParity 877Purpose: Set even parity 878Call: sSetEvenParity(ChP) 879 CHANNEL_T *ChP; Ptr to channel structure 880Comments: Function sSetParity() can be used in place of functions sEnParity(), 881 sDisParity(), sSetOddParity(), and sSetEvenParity(). 882 883Warnings: This function has no effect unless parity is enabled with function 884 sEnParity(). 885*/ 886#define sSetEvenParity(ChP) \ 887{ \ 888 (ChP)->TxControl[2] |= EVEN_PAR; \ 889 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 890} 891 892/*************************************************************************** 893Function: sSetOddParity 894Purpose: Set odd parity 895Call: sSetOddParity(ChP) 896 CHANNEL_T *ChP; Ptr to channel structure 897Comments: Function sSetParity() can be used in place of functions sEnParity(), 898 sDisParity(), sSetOddParity(), and sSetEvenParity(). 899 900Warnings: This function has no effect unless parity is enabled with function 901 sEnParity(). 902*/ 903#define sSetOddParity(ChP) \ 904{ \ 905 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 906 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 907} 908 909/*************************************************************************** 910Function: sSetRTS 911Purpose: Set the RTS output 912Call: sSetRTS(ChP) 913 CHANNEL_T *ChP; Ptr to channel structure 914*/ 915#define sSetRTS(ChP) \ 916{ \ 917 (ChP)->TxControl[3] |= SET_RTS; \ 918 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 919} 920 921/*************************************************************************** 922Function: sSetRxTrigger 923Purpose: Set the Rx FIFO trigger level 924Call: sSetRxProcessor(ChP,Level) 925 CHANNEL_T *ChP; Ptr to channel structure 926 Byte_t Level; Number of characters in Rx FIFO at which the 927 interrupt will be generated. Can be any of the following flags: 928 929 TRIG_NO: no trigger 930 TRIG_1: 1 character in FIFO 931 TRIG_1_2: FIFO 1/2 full 932 TRIG_7_8: FIFO 7/8 full 933Comments: An interrupt will be generated when the trigger level is reached 934 only if function sEnInterrupt() has been called with flag 935 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 936 register will be set whenever the trigger level is reached 937 regardless of the setting of RXINT_EN. 938 939*/ 940#define sSetRxTrigger(ChP,LEVEL) \ 941{ \ 942 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 943 (ChP)->RxControl[2] |= LEVEL; \ 944 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 945} 946 947/*************************************************************************** 948Function: sSetStop1 949Purpose: Set stop bits to 1 950Call: sSetStop1(ChP) 951 CHANNEL_T *ChP; Ptr to channel structure 952*/ 953#define sSetStop1(ChP) \ 954{ \ 955 (ChP)->TxControl[2] &= ~STOP2; \ 956 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 957} 958 959/*************************************************************************** 960Function: sSetStop2 961Purpose: Set stop bits to 2 962Call: sSetStop2(ChP) 963 CHANNEL_T *ChP; Ptr to channel structure 964*/ 965#define sSetStop2(ChP) \ 966{ \ 967 (ChP)->TxControl[2] |= STOP2; \ 968 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 969} 970 971/*************************************************************************** 972Function: sStartRxProcessor 973Purpose: Start a channel's receive processor 974Call: sStartRxProcessor(ChP) 975 CHANNEL_T *ChP; Ptr to channel structure 976Comments: This function is used to start a Rx processor after it was 977 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 978 will restart both the Rx processor and software input flow control. 979 980*/ 981#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R)) 982 983/*************************************************************************** 984Function: sWriteTxByte 985Purpose: Write a transmit data byte to a channel. 986 CHANNEL_T *ChP; Ptr to channel structure 987 ByteIO_t io: Channel transmit register I/O address. This can 988 be obtained with sGetTxRxDataIO(). 989 Byte_t Data; The transmit data byte. 990Warnings: This function writes the data byte without checking to see if 991 sMaxTxSize is exceeded in the Tx FIFO. 992*/ 993#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA) 994 995int sReadAiopID(CONTROLLER_T *CtlP, int aiop); 996int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop); 997int sInitChan( CONTROLLER_T *CtlP, 998 CHANNEL_T *ChP, 999 int AiopNum, 1000 int ChanNum); 1001Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 1002void sStopRxProcessor(CHANNEL_T *ChP); 1003void sStopSWInFlowCtl(CHANNEL_T *ChP); 1004void sFlushRxFIFO(CHANNEL_T *ChP); 1005void sFlushTxFIFO(CHANNEL_T *ChP); 1006int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1007void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1008void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1009int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports); 1010void rp_releaseresource(CONTROLLER_t *ctlp); 1011void rp_untimeout(void); 1012static __inline void 1013rp_lock(CONTROLLER_T *CtlP) 1014{ 1015 if (CtlP->hwmtx_init != 0) 1016 mtx_lock_spin(&CtlP->hwmtx); 1017} 1018static __inline void 1019rp_unlock(CONTROLLER_T *CtlP) 1020{ 1021 if (CtlP->hwmtx_init != 0) 1022 mtx_unlock_spin(&CtlP->hwmtx); 1023} 1024 1025#ifndef ROCKET_C 1026extern Byte_t R[RDATASIZE]; 1027extern CONTROLLER_T sController[CTL_SIZE]; 1028extern Byte_t sIRQMap[16]; 1029#endif 1030extern Byte_t rp_sBitMapClrTbl[8]; 1031extern Byte_t rp_sBitMapSetTbl[8]; 1032