rpreg.h revision 164439
1/*- 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted prodived that the follwoing conditions 7 * are met. 8 * 1. Redistributions of source code must retain the above copyright 9 * notive, this list of conditions and the following disclainer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials prodided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Comtrol Corporation. 16 * 4. The name of Comtrol Corporation may not be used to endorse or 17 * promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/rp/rpreg.h 164439 2006-11-20 12:59:27Z marius $ 33 */ 34 35/* 36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 37 */ 38 39typedef uint8_t Byte_t; 40typedef uint8_t ByteIO_t; 41 42typedef uint16_t Word_t; 43typedef uint16_t WordIO_t; 44 45typedef uint32_t DWord_t; 46typedef uint32_t DWordIO_t; 47 48#define rp_readio(size, ctlp, rid, offset) \ 49 (bus_read_##size(ctlp->io[rid], offset)) 50#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \ 51 (bus_read_multi_##size(ctlp->io[rid], offset, addr, count)) 52#define rp_writeio(size, ctlp, rid, offset, data) \ 53 (bus_write_##size(ctlp->io[rid], offset, data)) 54#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \ 55 (bus_write_multi_##size(ctlp->io[rid], offset, addr, count)) 56 57#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset) 58#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset) 59#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset) 60#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data) 61#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data) 62#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data) 63#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count) 64#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count) 65#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count) 66#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count) 67#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count) 68#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count) 69 70#define rp_readaiop1(ctlp, aiop, offset) \ 71 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 72#define rp_readaiop2(ctlp, aiop, offset) \ 73 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 74#define rp_readaiop4(ctlp, aiop, offset) \ 75 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 76#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \ 77 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 78#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \ 79 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 80#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \ 81 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 82#define rp_writeaiop1(ctlp, aiop, offset, data) \ 83 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 84#define rp_writeaiop2(ctlp, aiop, offset, data) \ 85 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 86#define rp_writeaiop4(ctlp, aiop, offset, data) \ 87 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 88#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \ 89 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 90#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \ 91 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 92#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \ 93 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 94 95#define rp_readch1(chp, offset) \ 96 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset)) 97#define rp_readch2(chp, offset) \ 98 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset)) 99#define rp_readch4(chp, offset) \ 100 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset)) 101#define rp_readmultich1(chp, offset, addr, count) \ 102 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 103#define rp_readmultich2(chp, offset, addr, count) \ 104 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 105#define rp_readmultich4(chp, offset, addr, count) \ 106 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 107#define rp_writech1(chp, offset, data) \ 108 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data)) 109#define rp_writech2(chp, offset, data) \ 110 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data)) 111#define rp_writech4(chp, offset, data) \ 112 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data)) 113#define rp_writemultich1(chp, offset, addr, count) \ 114 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 115#define rp_writemultich2(chp, offset, addr, count) \ 116 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 117#define rp_writemultich4(chp, offset, addr, count) \ 118 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 119 120/* 121 * End of OS-specific defines 122 */ 123 124#define ROCKET_H 125 126#define CTL_SIZE 4 127#define AIOP_CTL_SIZE 4 128#define CHAN_AIOP_SIZE 8 129#define MAX_PORTS_PER_AIOP 8 130#define MAX_AIOPS_PER_BOARD 4 131#define MAX_PORTS_PER_BOARD 32 132 133/* Controller ID numbers */ 134#define CTLID_NULL -1 /* no controller exists */ 135#define CTLID_0001 0x0001 /* controller release 1 */ 136 137/* AIOP ID numbers, identifies AIOP type implementing channel */ 138#define AIOPID_NULL -1 /* no AIOP or channel exists */ 139#define AIOPID_0001 0x0001 /* AIOP release 1 */ 140 141#define NULLDEV -1 /* identifies non-existant device */ 142#define NULLCTL -1 /* identifies non-existant controller */ 143#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 144#define NULLAIOP -1 /* identifies non-existant AIOP */ 145#define NULLCHAN -1 /* identifies non-existant channel */ 146 147/************************************************************************ 148 Global Register Offsets - Direct Access - Fixed values 149************************************************************************/ 150 151#define _CMD_REG 0x38 /* Command Register 8 Write */ 152#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 153#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 154#define _UNUSED 0x3B /* Unused 8 */ 155#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 156#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 157 158/************************************************************************ 159 Channel Register Offsets for 1st channel in AIOP - Direct Access 160************************************************************************/ 161#define _TD0 0x00 /* Transmit Data 16 Write */ 162#define _RD0 0x00 /* Receive Data 16 Read */ 163#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 164#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 165#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 166 167/************************************************************************ 168 Tx Control Register Offsets - Indexed - External - Fixed 169************************************************************************/ 170#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 171#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 172#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 173#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 174#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 175#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 176 177/************************************************************************ 178 Receive FIFO 179************************************************************************/ 180#define RXFIFO_DATA 0x5f 181#define RXFIFO_OUT 0x5c 182#define RXFIFO_EN 0x08 183#define RXFIFO_DIS 0xa7 184 185/************************************************************************ 186Memory Controller Register Offsets - Indexed - External - Fixed 187************************************************************************/ 188#define _RX_FIFO 0x000 /* Rx FIFO */ 189#define _TX_FIFO 0x800 /* Tx FIFO */ 190#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 191#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 192#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 193#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 194#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 195#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 196 197#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 198#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 199#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 200 201/************************************************************************ 202Tx Priority Buffer - Indexed - External - Fixed 203************************************************************************/ 204#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 205#define TXP_SIZE 0x20 /* 32 bytes */ 206 207/************************************************************************ 208Channel Register Offsets - Indexed - Internal - Fixed 209************************************************************************/ 210 211#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 212#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 213#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 214#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 215 216#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 217 218#define BRD50 4607 219#define BRD75 3071 220#define BRD110 2094 221#define BRD134 1712 222#define BRD150 1535 223#define BRD200 1151 224#define BRD300 767 225#define BRD600 383 226#define BRD1200 191 227#define BRD1800 127 228#define BRD2000 114 229#define BRD2400 95 230#define BRD3600 64 231#define BRD4800 47 232#define BRD7200 31 233#define BRD9600 23 234#define BRD14400 15 235#define BRD19200 11 236#define BRD38400 5 237#define BRD57600 3 238#define BRD76800 2 239#define BRD115200 1 240#define BRD230400 0 241 242#define STMBREAK 0x08 /* BREAK */ 243#define STMFRAME 0x04 /* framing error */ 244#define STMRCVROVR 0x02 /* receiver over run error */ 245#define STMPARITY 0x01 /* parity error */ 246#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 247#define STMBREAKH 0x800 /* BREAK */ 248#define STMFRAMEH 0x400 /* framing error */ 249#define STMRCVROVRH 0x200 /* receiver over run error */ 250#define STMPARITYH 0x100 /* parity error */ 251#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 252 253#define CTS_ACT 0x20 /* CTS input asserted */ 254#define DSR_ACT 0x10 /* DSR input asserted */ 255#define CD_ACT 0x08 /* CD input asserted */ 256#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 257#define TXSHRMT 0x02 /* Tx shift register is empty */ 258#define RDA 0x01 /* Rx data available */ 259#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 260 261#define STATMODE 0x8000 /* status mode enable bit */ 262#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 263#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 264#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 265#define RXBREAK 0x0400 /* received BREAK */ 266#define RXFRAME 0x0200 /* received framing error */ 267#define RXPARITY 0x0100 /* received parity error */ 268#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 269 270#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 271#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 272#define TXINT_EN 0x10 /* transmit interrupt enable */ 273#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 274#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 275#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 276#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 277 278#define SETBREAK 0x10 /* send break condition (must clear) */ 279#define LOCALLOOP 0x08 /* local loopback set for test */ 280#define SET_DTR 0x04 /* assert DTR */ 281#define SET_RTS 0x02 /* assert RTS */ 282#define TX_ENABLE 0x01 /* enable transmitter */ 283 284#define RTSFC_EN 0x40 /* RTS flow control enable */ 285#define RXPROC_EN 0x20 /* receive processor enable */ 286#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 287#define TRIG_1 0x08 /* trigger level 1 char */ 288#define TRIG_1_2 0x10 /* trigger level 1/2 */ 289#define TRIG_7_8 0x18 /* trigger level 7/8 */ 290#define TRIG_MASK 0x18 /* trigger level mask */ 291#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 292#define RXINT_EN 0x02 /* Rx interrupt enable */ 293#define MCINT_EN 0x01 /* modem change interrupt enable */ 294 295#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 296#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 297#define SRC_INT 0x08 /* special receive condition interrupt */ 298#define DELTA_CD 0x04 /* CD change interrupt */ 299#define DELTA_CTS 0x02 /* CTS change interrupt */ 300#define DELTA_DSR 0x01 /* DSR change interrupt */ 301 302#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 303#define IGN2_EN 0x08 /* ignore byte 2 enable */ 304#define IGN1_EN 0x04 /* ignore byte 1 enable */ 305#define COMP2_EN 0x02 /* compare byte 2 enable */ 306#define COMP1_EN 0x01 /* compare byte 1 enable */ 307 308#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 309#define TXOVERIDE 0x40 /* Transmit software off override */ 310#define RESETUART 0x20 /* reset channel's UART */ 311#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 312#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 313 314#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 315#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 316#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 317#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 318 319#define INTR_EN 0x08 /* allow interrupts to host */ 320#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 321 322#define CHAN3_EN 0x08 /* enable AIOP 3 */ 323#define CHAN2_EN 0x04 /* enable AIOP 2 */ 324#define CHAN1_EN 0x02 /* enable AIOP 1 */ 325#define CHAN0_EN 0x01 /* enable AIOP 0 */ 326#define FREQ_DIS 0x00 327#define FREQ_274HZ 0x60 328#define FREQ_137HZ 0x50 329#define FREQ_69HZ 0x40 330#define FREQ_34HZ 0x30 331#define FREQ_17HZ 0x20 332#define FREQ_9HZ 0x10 333#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 334 335#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 336 337#define RDATASIZE 72 338#define RREGDATASIZE 52 339 340#ifndef TRUE 341#define TRUE 1 342#endif 343 344#ifndef FALSE 345#define FALSE 0 346#endif 347 348struct CONTROLLER_str; 349struct CHANNEL_str; 350 351/* The types of bus-specific methods */ 352typedef int rp_aiop2rid_t(int, int); 353typedef int rp_aiop2off_t(int, int); 354typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *); 355 356/* Controller level information structure */ 357struct CONTROLLER_str 358{ 359 int CtlID; 360 int NumAiop; 361 int AiopID[AIOP_CTL_SIZE]; 362 int AiopNumChan[AIOP_CTL_SIZE]; 363 364 /* Device and resource management */ 365 device_t dev; /* device */ 366 int io_num; /* Number of IO resources */ 367 int *io_rid; /* IO resource IDs */ 368 struct resource **io; /* IO resources */ 369 370 struct rp_port *rp; /* port */ 371 372 /* Device nodes */ 373 struct cdev **dev_nodes; 374 375 /* Bus-specific properties */ 376 void *bus_ctlp; 377 378 /* Bus-specific methods */ 379 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */ 380 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */ 381 rp_ctlmask_t *ctlmask; /* Int status */ 382}; 383typedef struct CONTROLLER_str CONTROLLER_T; 384typedef CONTROLLER_T CONTROLLER_t; 385 386/* Channel level information structure */ 387struct CHANNEL_str 388{ 389 CONTROLLER_t *CtlP; 390 int AiopNum; 391 int ChanID; 392 int ChanNum; 393 394 Word_t TxFIFO; 395 Word_t TxFIFOPtrs; 396 Word_t RxFIFO; 397 Word_t RxFIFOPtrs; 398 Word_t TxPrioCnt; 399 Word_t TxPrioPtr; 400 Word_t TxPrioBuf; 401 402 Byte_t R[RREGDATASIZE]; 403 404 Byte_t BaudDiv[4]; 405 Byte_t TxControl[4]; 406 Byte_t RxControl[4]; 407 Byte_t TxEnables[4]; 408 Byte_t TxCompare[4]; 409 Byte_t TxReplace1[4]; 410 Byte_t TxReplace2[4]; 411}; 412 413typedef struct CHANNEL_str CHANNEL_T; 414typedef CHANNEL_T CHANNEL_t; 415typedef CHANNEL_T * CHANPTR_T; 416 417#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0) 418#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0) 419#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0) 420#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0) 421 422/*************************************************************************** 423Function: sClrBreak 424Purpose: Stop sending a transmit BREAK signal 425Call: sClrBreak(ChP) 426 CHANNEL_T *ChP; Ptr to channel structure 427*/ 428#define sClrBreak(ChP) \ 429{ \ 430 (ChP)->TxControl[3] &= ~SETBREAK; \ 431 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 432} 433 434/*************************************************************************** 435Function: sClrDTR 436Purpose: Clr the DTR output 437Call: sClrDTR(ChP) 438 CHANNEL_T *ChP; Ptr to channel structure 439*/ 440#define sClrDTR(ChP) \ 441{ \ 442 (ChP)->TxControl[3] &= ~SET_DTR; \ 443 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 444} 445 446/*************************************************************************** 447Function: sClrRTS 448Purpose: Clr the RTS output 449Call: sClrRTS(ChP) 450 CHANNEL_T *ChP; Ptr to channel structure 451*/ 452#define sClrRTS(ChP) \ 453{ \ 454 (ChP)->TxControl[3] &= ~SET_RTS; \ 455 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 456} 457 458/*************************************************************************** 459Function: sClrTxXOFF 460Purpose: Clear any existing transmit software flow control off condition 461Call: sClrTxXOFF(ChP) 462 CHANNEL_T *ChP; Ptr to channel structure 463*/ 464#define sClrTxXOFF(ChP) \ 465{ \ 466 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 467 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \ 468} 469 470/*************************************************************************** 471Function: sDisCTSFlowCtl 472Purpose: Disable output flow control using CTS 473Call: sDisCTSFlowCtl(ChP) 474 CHANNEL_T *ChP; Ptr to channel structure 475*/ 476#define sDisCTSFlowCtl(ChP) \ 477{ \ 478 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 479 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 480} 481 482/*************************************************************************** 483Function: DisParity 484Purpose: Disable parity 485Call: sDisParity(ChP) 486 CHANNEL_T *ChP; Ptr to channel structure 487Comments: Function sSetParity() can be used in place of functions sEnParity(), 488 sDisParity(), sSetOddParity(), and sSetEvenParity(). 489*/ 490#define sDisParity(ChP) \ 491{ \ 492 (ChP)->TxControl[2] &= ~PARITY_EN; \ 493 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 494} 495 496/*************************************************************************** 497Function: sDisRxFIFO 498Purpose: Disable Rx FIFO 499Call: sDisRxFIFO(ChP) 500 CHANNEL_T *ChP; Ptr to channel structure 501*/ 502#define sDisRxFIFO(ChP) \ 503{ \ 504 (ChP)->R[0x32] = 0x0a; \ 505 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 506} 507 508/*************************************************************************** 509Function: sDisRxStatusMode 510Purpose: Disable the Rx status mode 511Call: sDisRxStatusMode(ChP) 512 CHANNEL_T *ChP; Ptr to channel structure 513Comments: This takes the channel out of the receive status mode. All 514 subsequent reads of receive data using sReadRxWord() will return 515 two data bytes. 516*/ 517#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0) 518 519/*************************************************************************** 520Function: sDisTransmit 521Purpose: Disable transmit 522Call: sDisTransmit(ChP) 523 CHANNEL_T *ChP; Ptr to channel structure 524 This disables movement of Tx data from the Tx FIFO into the 1 byte 525 Tx buffer. Therefore there could be up to a 2 byte latency 526 between the time sDisTransmit() is called and the transmit buffer 527 and transmit shift register going completely empty. 528*/ 529#define sDisTransmit(ChP) \ 530{ \ 531 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 532 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 533} 534 535/*************************************************************************** 536Function: sDisTxSoftFlowCtl 537Purpose: Disable Tx Software Flow Control 538Call: sDisTxSoftFlowCtl(ChP) 539 CHANNEL_T *ChP; Ptr to channel structure 540*/ 541#define sDisTxSoftFlowCtl(ChP) \ 542{ \ 543 (ChP)->R[0x06] = 0x8a; \ 544 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x04)); \ 545} 546 547/*************************************************************************** 548Function: sEnCTSFlowCtl 549Purpose: Enable output flow control using CTS 550Call: sEnCTSFlowCtl(ChP) 551 CHANNEL_T *ChP; Ptr to channel structure 552*/ 553#define sEnCTSFlowCtl(ChP) \ 554{ \ 555 (ChP)->TxControl[2] |= CTSFC_EN; \ 556 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 557} 558 559/*************************************************************************** 560Function: EnParity 561Purpose: Enable parity 562Call: sEnParity(ChP) 563 CHANNEL_T *ChP; Ptr to channel structure 564Comments: Function sSetParity() can be used in place of functions sEnParity(), 565 sDisParity(), sSetOddParity(), and sSetEvenParity(). 566 567Warnings: Before enabling parity odd or even parity should be chosen using 568 functions sSetOddParity() or sSetEvenParity(). 569*/ 570#define sEnParity(ChP) \ 571{ \ 572 (ChP)->TxControl[2] |= PARITY_EN; \ 573 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 574} 575 576/*************************************************************************** 577Function: sEnRTSFlowCtl 578Return: void 579*/ 580#define sEnRTSFlowCtl(ChP) \ 581{ \ 582 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 583 (ChP)->TxControl[3] &= ~SET_RTS; \ 584 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 585 (ChP)->RxControl[2] |= RTSFC_EN; \ 586 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 587} 588 589/*************************************************************************** 590Function: sDisRTSFlowCtl 591Return: void 592*/ 593#define sDisRTSFlowCtl(ChP) \ 594{ \ 595 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 596 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 597} 598 599/*************************************************************************** 600Function: sEnRxFIFO 601Purpose: Enable Rx FIFO 602Call: sEnRxFIFO(ChP) 603 CHANNEL_T *ChP; Ptr to channel structure 604*/ 605#define sEnRxFIFO(ChP) \ 606{ \ 607 (ChP)->R[0x32] = 0x08; \ 608 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 609} 610 611/*************************************************************************** 612Function: sEnRxProcessor 613Purpose: Enable the receive processor 614Call: sEnRxProcessor(ChP) 615 CHANNEL_T *ChP; Ptr to channel structure 616Comments: This function is used to start the receive processor. When 617 the channel is in the reset state the receive processor is not 618 running. This is done to prevent the receive processor from 619 executing invalid microcode instructions prior to the 620 downloading of the microcode. 621 622Warnings: This function must be called after valid microcode has been 623 downloaded to the AIOP, and it must not be called before the 624 microcode has been downloaded. 625*/ 626#define sEnRxProcessor(ChP) \ 627{ \ 628 (ChP)->RxControl[2] |= RXPROC_EN; \ 629 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 630} 631 632/*************************************************************************** 633Function: sEnRxStatusMode 634Purpose: Enable the Rx status mode 635Call: sEnRxStatusMode(ChP) 636 CHANNEL_T *ChP; Ptr to channel structure 637Comments: This places the channel in the receive status mode. All subsequent 638 reads of receive data using sReadRxWord() will return a data byte 639 in the low word and a status byte in the high word. 640 641*/ 642#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE) 643 644/*************************************************************************** 645Function: sEnTransmit 646Purpose: Enable transmit 647Call: sEnTransmit(ChP) 648 CHANNEL_T *ChP; Ptr to channel structure 649*/ 650#define sEnTransmit(ChP) \ 651{ \ 652 (ChP)->TxControl[3] |= TX_ENABLE; \ 653 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 654} 655 656/*************************************************************************** 657Function: sGetAiopIntStatus 658Purpose: Get the AIOP interrupt status 659Call: sGetAiopIntStatus(CtlP,AiopNum) 660 CONTROLLER_T *CtlP; Ptr to controller structure 661 int AiopNum; AIOP number 662Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 663 represent channels 0 through 7 respectively. If a 664 bit is set that channel is interrupting. 665*/ 666#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN) 667 668/*************************************************************************** 669Function: sGetAiopNumChan 670Purpose: Get the number of channels supported by an AIOP 671Call: sGetAiopNumChan(CtlP,AiopNum) 672 CONTROLLER_T *CtlP; Ptr to controller structure 673 int AiopNum; AIOP number 674Return: int: The number of channels supported by the AIOP 675*/ 676#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM] 677 678/*************************************************************************** 679Function: sGetChanIntID 680Purpose: Get a channel's interrupt identification byte 681Call: sGetChanIntID(ChP) 682 CHANNEL_T *ChP; Ptr to channel structure 683Return: Byte_t: The channel interrupt ID. Can be any 684 combination of the following flags: 685 RXF_TRIG: Rx FIFO trigger level interrupt 686 TXFIFO_MT: Tx FIFO empty interrupt 687 SRC_INT: Special receive condition interrupt 688 DELTA_CD: CD change interrupt 689 DELTA_CTS: CTS change interrupt 690 DELTA_DSR: DSR change interrupt 691*/ 692#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 693 694/*************************************************************************** 695Function: sGetChanNum 696Purpose: Get the number of a channel within an AIOP 697Call: sGetChanNum(ChP) 698 CHANNEL_T *ChP; Ptr to channel structure 699Return: int: Channel number within AIOP, or NULLCHAN if channel does 700 not exist. 701*/ 702#define sGetChanNum(ChP) (ChP)->ChanNum 703 704/*************************************************************************** 705Function: sGetChanStatus 706Purpose: Get the channel status 707Call: sGetChanStatus(ChP) 708 CHANNEL_T *ChP; Ptr to channel structure 709Return: Word_t: The channel status. Can be any combination of 710 the following flags: 711 LOW BYTE FLAGS 712 CTS_ACT: CTS input asserted 713 DSR_ACT: DSR input asserted 714 CD_ACT: CD input asserted 715 TXFIFOMT: Tx FIFO is empty 716 TXSHRMT: Tx shift register is empty 717 RDA: Rx data available 718 719 HIGH BYTE FLAGS 720 STATMODE: status mode enable bit 721 RXFOVERFL: receive FIFO overflow 722 RX2MATCH: receive compare byte 2 match 723 RX1MATCH: receive compare byte 1 match 724 RXBREAK: received BREAK 725 RXFRAME: received framing error 726 RXPARITY: received parity error 727Warnings: This function will clear the high byte flags in the Channel 728 Status Register. 729*/ 730#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP)) 731 732/*************************************************************************** 733Function: sGetChanStatusLo 734Purpose: Get the low byte only of the channel status 735Call: sGetChanStatusLo(ChP) 736 CHANNEL_T *ChP; Ptr to channel structure 737Return: Byte_t: The channel status low byte. Can be any combination 738 of the following flags: 739 CTS_ACT: CTS input asserted 740 DSR_ACT: DSR input asserted 741 CD_ACT: CD input asserted 742 TXFIFOMT: Tx FIFO is empty 743 TXSHRMT: Tx shift register is empty 744 RDA: Rx data available 745*/ 746#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP)) 747 748/*************************************************************************** 749Function: sGetRxCnt 750Purpose: Get the number of data bytes in the Rx FIFO 751Call: sGetRxCnt(ChP) 752 CHANNEL_T *ChP; Ptr to channel structure 753Return: int: The number of data bytes in the Rx FIFO. 754Comments: Byte read of count register is required to obtain Rx count. 755 756*/ 757#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP)) 758 759/*************************************************************************** 760Function: sGetTxCnt 761Purpose: Get the number of data bytes in the Tx FIFO 762Call: sGetTxCnt(ChP) 763 CHANNEL_T *ChP; Ptr to channel structure 764Return: Byte_t: The number of data bytes in the Tx FIFO. 765Comments: Byte read of count register is required to obtain Tx count. 766 767*/ 768#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP)) 769 770/***************************************************************************** 771Function: sGetTxRxDataIO 772Purpose: Get the offset of a channel's TxRx Data register 773Call: sGetTxRxDataIO(ChP) 774 CHANNEL_T *ChP; Ptr to channel structure 775Return: WordIO_t: offset of a channel's TxRx Data register 776*/ 777#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP) 778 779/*************************************************************************** 780Function: sInitChanDefaults 781Purpose: Initialize a channel structure to its default state. 782Call: sInitChanDefaults(ChP) 783 CHANNEL_T *ChP; Ptr to the channel structure 784Comments: This function must be called once for every channel structure 785 that exists before any other SSCI calls can be made. 786 787*/ 788#define sInitChanDefaults(ChP) \ 789{ \ 790 (ChP)->CtlP = NULLCTLPTR; \ 791 (ChP)->AiopNum = NULLAIOP; \ 792 (ChP)->ChanID = AIOPID_NULL; \ 793 (ChP)->ChanNum = NULLCHAN; \ 794} 795 796/*************************************************************************** 797Function: sResetAiopByNum 798Purpose: Reset the AIOP by number 799Call: sResetAiopByNum(CTLP,AIOPNUM) 800 CONTROLLER_T CTLP; Ptr to controller structure 801 AIOPNUM; AIOP index 802*/ 803#define sResetAiopByNum(CTLP,AIOPNUM) \ 804{ \ 805 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \ 806 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \ 807} 808 809/*************************************************************************** 810Function: sSendBreak 811Purpose: Send a transmit BREAK signal 812Call: sSendBreak(ChP) 813 CHANNEL_T *ChP; Ptr to channel structure 814*/ 815#define sSendBreak(ChP) \ 816{ \ 817 (ChP)->TxControl[3] |= SETBREAK; \ 818 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 819} 820 821/*************************************************************************** 822Function: sSetBaud 823Purpose: Set baud rate 824Call: sSetBaud(ChP,Divisor) 825 CHANNEL_T *ChP; Ptr to channel structure 826 Word_t Divisor; 16 bit baud rate divisor for channel 827*/ 828#define sSetBaud(ChP,DIVISOR) \ 829{ \ 830 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 831 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 832 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->BaudDiv)); \ 833} 834 835/*************************************************************************** 836Function: sSetData7 837Purpose: Set data bits to 7 838Call: sSetData7(ChP) 839 CHANNEL_T *ChP; Ptr to channel structure 840*/ 841#define sSetData7(ChP) \ 842{ \ 843 (ChP)->TxControl[2] &= ~DATA8BIT; \ 844 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 845} 846 847/*************************************************************************** 848Function: sSetData8 849Purpose: Set data bits to 8 850Call: sSetData8(ChP) 851 CHANNEL_T *ChP; Ptr to channel structure 852*/ 853#define sSetData8(ChP) \ 854{ \ 855 (ChP)->TxControl[2] |= DATA8BIT; \ 856 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 857} 858 859/*************************************************************************** 860Function: sSetDTR 861Purpose: Set the DTR output 862Call: sSetDTR(ChP) 863 CHANNEL_T *ChP; Ptr to channel structure 864*/ 865#define sSetDTR(ChP) \ 866{ \ 867 (ChP)->TxControl[3] |= SET_DTR; \ 868 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 869} 870 871/*************************************************************************** 872Function: sSetEvenParity 873Purpose: Set even parity 874Call: sSetEvenParity(ChP) 875 CHANNEL_T *ChP; Ptr to channel structure 876Comments: Function sSetParity() can be used in place of functions sEnParity(), 877 sDisParity(), sSetOddParity(), and sSetEvenParity(). 878 879Warnings: This function has no effect unless parity is enabled with function 880 sEnParity(). 881*/ 882#define sSetEvenParity(ChP) \ 883{ \ 884 (ChP)->TxControl[2] |= EVEN_PAR; \ 885 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 886} 887 888/*************************************************************************** 889Function: sSetOddParity 890Purpose: Set odd parity 891Call: sSetOddParity(ChP) 892 CHANNEL_T *ChP; Ptr to channel structure 893Comments: Function sSetParity() can be used in place of functions sEnParity(), 894 sDisParity(), sSetOddParity(), and sSetEvenParity(). 895 896Warnings: This function has no effect unless parity is enabled with function 897 sEnParity(). 898*/ 899#define sSetOddParity(ChP) \ 900{ \ 901 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 902 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 903} 904 905/*************************************************************************** 906Function: sSetRTS 907Purpose: Set the RTS output 908Call: sSetRTS(ChP) 909 CHANNEL_T *ChP; Ptr to channel structure 910*/ 911#define sSetRTS(ChP) \ 912{ \ 913 (ChP)->TxControl[3] |= SET_RTS; \ 914 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 915} 916 917/*************************************************************************** 918Function: sSetRxTrigger 919Purpose: Set the Rx FIFO trigger level 920Call: sSetRxProcessor(ChP,Level) 921 CHANNEL_T *ChP; Ptr to channel structure 922 Byte_t Level; Number of characters in Rx FIFO at which the 923 interrupt will be generated. Can be any of the following flags: 924 925 TRIG_NO: no trigger 926 TRIG_1: 1 character in FIFO 927 TRIG_1_2: FIFO 1/2 full 928 TRIG_7_8: FIFO 7/8 full 929Comments: An interrupt will be generated when the trigger level is reached 930 only if function sEnInterrupt() has been called with flag 931 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 932 register will be set whenever the trigger level is reached 933 regardless of the setting of RXINT_EN. 934 935*/ 936#define sSetRxTrigger(ChP,LEVEL) \ 937{ \ 938 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 939 (ChP)->RxControl[2] |= LEVEL; \ 940 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 941} 942 943/*************************************************************************** 944Function: sSetStop1 945Purpose: Set stop bits to 1 946Call: sSetStop1(ChP) 947 CHANNEL_T *ChP; Ptr to channel structure 948*/ 949#define sSetStop1(ChP) \ 950{ \ 951 (ChP)->TxControl[2] &= ~STOP2; \ 952 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 953} 954 955/*************************************************************************** 956Function: sSetStop2 957Purpose: Set stop bits to 2 958Call: sSetStop2(ChP) 959 CHANNEL_T *ChP; Ptr to channel structure 960*/ 961#define sSetStop2(ChP) \ 962{ \ 963 (ChP)->TxControl[2] |= STOP2; \ 964 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 965} 966 967/*************************************************************************** 968Function: sStartRxProcessor 969Purpose: Start a channel's receive processor 970Call: sStartRxProcessor(ChP) 971 CHANNEL_T *ChP; Ptr to channel structure 972Comments: This function is used to start a Rx processor after it was 973 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 974 will restart both the Rx processor and software input flow control. 975 976*/ 977#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R)) 978 979/*************************************************************************** 980Function: sWriteTxByte 981Purpose: Write a transmit data byte to a channel. 982 CHANNEL_T *ChP; Ptr to channel structure 983 ByteIO_t io: Channel transmit register I/O address. This can 984 be obtained with sGetTxRxDataIO(). 985 Byte_t Data; The transmit data byte. 986Warnings: This function writes the data byte without checking to see if 987 sMaxTxSize is exceeded in the Tx FIFO. 988*/ 989#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA) 990 991int sReadAiopID(CONTROLLER_T *CtlP, int aiop); 992int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop); 993int sInitChan( CONTROLLER_T *CtlP, 994 CHANNEL_T *ChP, 995 int AiopNum, 996 int ChanNum); 997Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 998void sStopRxProcessor(CHANNEL_T *ChP); 999void sStopSWInFlowCtl(CHANNEL_T *ChP); 1000void sFlushRxFIFO(CHANNEL_T *ChP); 1001void sFlushTxFIFO(CHANNEL_T *ChP); 1002int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1003void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1004void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1005int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports); 1006void rp_releaseresource(CONTROLLER_t *ctlp); 1007void rp_untimeout(void); 1008 1009#ifndef ROCKET_C 1010extern Byte_t R[RDATASIZE]; 1011extern CONTROLLER_T sController[CTL_SIZE]; 1012extern Byte_t sIRQMap[16]; 1013#endif 1014extern Byte_t rp_sBitMapClrTbl[8]; 1015extern Byte_t rp_sBitMapSetTbl[8]; 1016