rpreg.h revision 61541
1/* 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted prodived that the follwoing conditions 7 * are met. 8 * 1. Redistributions of source code must retain the above copyright 9 * notive, this list of conditions and the following disclainer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials prodided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Comtrol Corporation. 16 * 4. The name of Comtrol Corporation may not be used to endorse or 17 * promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/rp/rpreg.h 61541 2000-06-11 06:43:16Z tanimura $ 33 */ 34 35/* 36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 37 */ 38 39typedef unsigned char Byte_t; 40typedef unsigned int ByteIO_t; 41 42typedef unsigned int Word_t; 43typedef unsigned int WordIO_t; 44 45typedef unsigned long DWord_t; 46typedef unsigned int DWordIO_t; 47 48#define rp_readio(size, ctlp, rid, offset) \ 49 (bus_space_read_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset)) 50#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \ 51 (bus_space_read_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count)) 52#define rp_writeio(size, ctlp, rid, offset, data) \ 53 (bus_space_write_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, data)) 54#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \ 55 (bus_space_write_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count)) 56 57#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset) 58#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset) 59#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset) 60#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data) 61#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data) 62#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data) 63#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count) 64#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count) 65#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count) 66#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count) 67#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count) 68#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count) 69 70#define rp_readaiop1(ctlp, aiop, offset) \ 71 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 72#define rp_readaiop2(ctlp, aiop, offset) \ 73 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 74#define rp_readaiop4(ctlp, aiop, offset) \ 75 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 76#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \ 77 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 78#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \ 79 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 80#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \ 81 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 82#define rp_writeaiop1(ctlp, aiop, offset, data) \ 83 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 84#define rp_writeaiop2(ctlp, aiop, offset, data) \ 85 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 86#define rp_writeaiop4(ctlp, aiop, offset, data) \ 87 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 88#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \ 89 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 90#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \ 91 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 92#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \ 93 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 94 95#define rp_readch1(chp, offset) \ 96 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset)) 97#define rp_readch2(chp, offset) \ 98 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset)) 99#define rp_readch4(chp, offset) \ 100 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset)) 101#define rp_readmultich1(chp, offset, addr, count) \ 102 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 103#define rp_readmultich2(chp, offset, addr, count) \ 104 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 105#define rp_readmultich4(chp, offset, addr, count) \ 106 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 107#define rp_writech1(chp, offset, data) \ 108 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data)) 109#define rp_writech2(chp, offset, data) \ 110 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data)) 111#define rp_writech4(chp, offset, data) \ 112 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data)) 113#define rp_writemultich1(chp, offset, addr, count) \ 114 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 115#define rp_writemultich2(chp, offset, addr, count) \ 116 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 117#define rp_writemultich4(chp, offset, addr, count) \ 118 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 119 120/* 121 * End of OS-specific defines 122 */ 123 124#define ROCKET_H 125 126#define CTL_SIZE 4 127#define AIOP_CTL_SIZE 4 128#define CHAN_AIOP_SIZE 8 129#define MAX_PORTS_PER_AIOP 8 130#define MAX_AIOPS_PER_BOARD 4 131#define MAX_PORTS_PER_BOARD 32 132 133/* Controller ID numbers */ 134#define CTLID_NULL -1 /* no controller exists */ 135#define CTLID_0001 0x0001 /* controller release 1 */ 136 137/* AIOP ID numbers, identifies AIOP type implementing channel */ 138#define AIOPID_NULL -1 /* no AIOP or channel exists */ 139#define AIOPID_0001 0x0001 /* AIOP release 1 */ 140 141#define NULLDEV -1 /* identifies non-existant device */ 142#define NULLCTL -1 /* identifies non-existant controller */ 143#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 144#define NULLAIOP -1 /* identifies non-existant AIOP */ 145#define NULLCHAN -1 /* identifies non-existant channel */ 146 147/************************************************************************ 148 Global Register Offsets - Direct Access - Fixed values 149************************************************************************/ 150 151#define _CMD_REG 0x38 /* Command Register 8 Write */ 152#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 153#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 154#define _UNUSED 0x3B /* Unused 8 */ 155#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 156#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 157 158/************************************************************************ 159 Channel Register Offsets for 1st channel in AIOP - Direct Access 160************************************************************************/ 161#define _TD0 0x00 /* Transmit Data 16 Write */ 162#define _RD0 0x00 /* Receive Data 16 Read */ 163#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 164#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 165#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 166 167/************************************************************************ 168 Tx Control Register Offsets - Indexed - External - Fixed 169************************************************************************/ 170#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 171#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 172#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 173#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 174#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 175#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 176 177/************************************************************************ 178 Receive FIFO 179************************************************************************/ 180#define RXFIFO_DATA 0x5f 181#define RXFIFO_OUT 0x5c 182#define RXFIFO_EN 0x08 183#define RXFIFO_DIS 0xa7 184 185/************************************************************************ 186Memory Controller Register Offsets - Indexed - External - Fixed 187************************************************************************/ 188#define _RX_FIFO 0x000 /* Rx FIFO */ 189#define _TX_FIFO 0x800 /* Tx FIFO */ 190#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 191#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 192#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 193#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 194#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 195#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 196 197#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 198#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 199#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 200 201/************************************************************************ 202Tx Priority Buffer - Indexed - External - Fixed 203************************************************************************/ 204#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 205#define TXP_SIZE 0x20 /* 32 bytes */ 206 207/************************************************************************ 208Channel Register Offsets - Indexed - Internal - Fixed 209************************************************************************/ 210 211#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 212#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 213#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 214#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 215 216#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 217 218#define BRD50 4607 219#define BRD75 3071 220#define BRD110 2094 221#define BRD134 1712 222#define BRD150 1535 223#define BRD200 1151 224#define BRD300 767 225#define BRD600 383 226#define BRD1200 191 227#define BRD1800 127 228#define BRD2000 114 229#define BRD2400 95 230#define BRD3600 64 231#define BRD4800 47 232#define BRD7200 31 233#define BRD9600 23 234#define BRD14400 15 235#define BRD19200 11 236#define BRD38400 5 237#define BRD57600 3 238#define BRD76800 2 239#define BRD115200 1 240#define BRD230400 0 241 242#define STMBREAK 0x08 /* BREAK */ 243#define STMFRAME 0x04 /* framing error */ 244#define STMRCVROVR 0x02 /* receiver over run error */ 245#define STMPARITY 0x01 /* parity error */ 246#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 247#define STMBREAKH 0x800 /* BREAK */ 248#define STMFRAMEH 0x400 /* framing error */ 249#define STMRCVROVRH 0x200 /* receiver over run error */ 250#define STMPARITYH 0x100 /* parity error */ 251#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 252 253#define CTS_ACT 0x20 /* CTS input asserted */ 254#define DSR_ACT 0x10 /* DSR input asserted */ 255#define CD_ACT 0x08 /* CD input asserted */ 256#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 257#define TXSHRMT 0x02 /* Tx shift register is empty */ 258#define RDA 0x01 /* Rx data available */ 259#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 260 261#define STATMODE 0x8000 /* status mode enable bit */ 262#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 263#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 264#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 265#define RXBREAK 0x0400 /* received BREAK */ 266#define RXFRAME 0x0200 /* received framing error */ 267#define RXPARITY 0x0100 /* received parity error */ 268#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 269 270#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 271#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 272#define TXINT_EN 0x10 /* transmit interrupt enable */ 273#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 274#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 275#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 276#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 277 278#define SETBREAK 0x10 /* send break condition (must clear) */ 279#define LOCALLOOP 0x08 /* local loopback set for test */ 280#define SET_DTR 0x04 /* assert DTR */ 281#define SET_RTS 0x02 /* assert RTS */ 282#define TX_ENABLE 0x01 /* enable transmitter */ 283 284#define RTSFC_EN 0x40 /* RTS flow control enable */ 285#define RXPROC_EN 0x20 /* receive processor enable */ 286#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 287#define TRIG_1 0x08 /* trigger level 1 char */ 288#define TRIG_1_2 0x10 /* trigger level 1/2 */ 289#define TRIG_7_8 0x18 /* trigger level 7/8 */ 290#define TRIG_MASK 0x18 /* trigger level mask */ 291#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 292#define RXINT_EN 0x02 /* Rx interrupt enable */ 293#define MCINT_EN 0x01 /* modem change interrupt enable */ 294 295#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 296#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 297#define SRC_INT 0x08 /* special receive condition interrupt */ 298#define DELTA_CD 0x04 /* CD change interrupt */ 299#define DELTA_CTS 0x02 /* CTS change interrupt */ 300#define DELTA_DSR 0x01 /* DSR change interrupt */ 301 302#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 303#define IGN2_EN 0x08 /* ignore byte 2 enable */ 304#define IGN1_EN 0x04 /* ignore byte 1 enable */ 305#define COMP2_EN 0x02 /* compare byte 2 enable */ 306#define COMP1_EN 0x01 /* compare byte 1 enable */ 307 308#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 309#define TXOVERIDE 0x40 /* Transmit software off override */ 310#define RESETUART 0x20 /* reset channel's UART */ 311#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 312#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 313 314#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 315#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 316#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 317#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 318 319#define INTR_EN 0x08 /* allow interrupts to host */ 320#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 321 322#define CHAN3_EN 0x08 /* enable AIOP 3 */ 323#define CHAN2_EN 0x04 /* enable AIOP 2 */ 324#define CHAN1_EN 0x02 /* enable AIOP 1 */ 325#define CHAN0_EN 0x01 /* enable AIOP 0 */ 326#define FREQ_DIS 0x00 327#define FREQ_274HZ 0x60 328#define FREQ_137HZ 0x50 329#define FREQ_69HZ 0x40 330#define FREQ_34HZ 0x30 331#define FREQ_17HZ 0x20 332#define FREQ_9HZ 0x10 333#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 334 335#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 336 337#define RDATASIZE 72 338#define RREGDATASIZE 52 339 340#ifndef TRUE 341#define TRUE 1 342#endif 343 344#ifndef FALSE 345#define FALSE 0 346#endif 347 348struct CONTROLLER_str; 349struct CHANNEL_str; 350 351/* The types of bus-specific methods */ 352typedef int rp_aiop2rid_t(int, int); 353typedef int rp_aiop2off_t(int, int); 354typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *); 355 356/* Controller level information structure */ 357struct CONTROLLER_str 358{ 359 int CtlID; 360 int NumAiop; 361 int AiopID[AIOP_CTL_SIZE]; 362 int AiopNumChan[AIOP_CTL_SIZE]; 363 364 /* Device and resource management */ 365 device_t dev; /* device */ 366 int io_num; /* Number of IO resources */ 367 int *io_rid; /* IO resource IDs */ 368 struct resource **io; /* IO resources */ 369 370 struct rp_port *rp; /* port */ 371 struct tty *tty; /* tty */ 372 373 /* Device nodes */ 374 dev_t *dev_nodes; 375 376 /* Bus-specific properties */ 377 void *bus_ctlp; 378 379 /* Bus-specific methods */ 380 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */ 381 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */ 382 rp_ctlmask_t *ctlmask; /* Int status */ 383}; 384typedef struct CONTROLLER_str CONTROLLER_T; 385typedef CONTROLLER_T CONTROLLER_t; 386 387/* Channel level information structure */ 388struct CHANNEL_str 389{ 390 CONTROLLER_t *CtlP; 391 int AiopNum; 392 int ChanID; 393 int ChanNum; 394 395 Word_t TxFIFO; 396 Word_t TxFIFOPtrs; 397 Word_t RxFIFO; 398 Word_t RxFIFOPtrs; 399 Word_t TxPrioCnt; 400 Word_t TxPrioPtr; 401 Word_t TxPrioBuf; 402 403 Byte_t R[RREGDATASIZE]; 404 405 Byte_t BaudDiv[4]; 406 Byte_t TxControl[4]; 407 Byte_t RxControl[4]; 408 Byte_t TxEnables[4]; 409 Byte_t TxCompare[4]; 410 Byte_t TxReplace1[4]; 411 Byte_t TxReplace2[4]; 412}; 413 414typedef struct CHANNEL_str CHANNEL_T; 415typedef CHANNEL_T CHANNEL_t; 416typedef CHANNEL_T * CHANPTR_T; 417 418#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0) 419#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0) 420#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0) 421#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0) 422 423/*************************************************************************** 424Function: sClrBreak 425Purpose: Stop sending a transmit BREAK signal 426Call: sClrBreak(ChP) 427 CHANNEL_T *ChP; Ptr to channel structure 428*/ 429#define sClrBreak(ChP) \ 430{ \ 431 (ChP)->TxControl[3] &= ~SETBREAK; \ 432 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 433} 434 435/*************************************************************************** 436Function: sClrDTR 437Purpose: Clr the DTR output 438Call: sClrDTR(ChP) 439 CHANNEL_T *ChP; Ptr to channel structure 440*/ 441#define sClrDTR(ChP) \ 442{ \ 443 (ChP)->TxControl[3] &= ~SET_DTR; \ 444 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 445} 446 447/*************************************************************************** 448Function: sClrRTS 449Purpose: Clr the RTS output 450Call: sClrRTS(ChP) 451 CHANNEL_T *ChP; Ptr to channel structure 452*/ 453#define sClrRTS(ChP) \ 454{ \ 455 (ChP)->TxControl[3] &= ~SET_RTS; \ 456 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 457} 458 459/*************************************************************************** 460Function: sClrTxXOFF 461Purpose: Clear any existing transmit software flow control off condition 462Call: sClrTxXOFF(ChP) 463 CHANNEL_T *ChP; Ptr to channel structure 464*/ 465#define sClrTxXOFF(ChP) \ 466{ \ 467 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 468 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \ 469} 470 471/*************************************************************************** 472Function: sDisCTSFlowCtl 473Purpose: Disable output flow control using CTS 474Call: sDisCTSFlowCtl(ChP) 475 CHANNEL_T *ChP; Ptr to channel structure 476*/ 477#define sDisCTSFlowCtl(ChP) \ 478{ \ 479 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 480 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 481} 482 483/*************************************************************************** 484Function: DisParity 485Purpose: Disable parity 486Call: sDisParity(ChP) 487 CHANNEL_T *ChP; Ptr to channel structure 488Comments: Function sSetParity() can be used in place of functions sEnParity(), 489 sDisParity(), sSetOddParity(), and sSetEvenParity(). 490*/ 491#define sDisParity(ChP) \ 492{ \ 493 (ChP)->TxControl[2] &= ~PARITY_EN; \ 494 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 495} 496 497/*************************************************************************** 498Function: sDisRxFIFO 499Purpose: Disable Rx FIFO 500Call: sDisRxFIFO(ChP) 501 CHANNEL_T *ChP; Ptr to channel structure 502*/ 503#define sDisRxFIFO(ChP) \ 504{ \ 505 (ChP)->R[0x32] = 0x0a; \ 506 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \ 507} 508 509/*************************************************************************** 510Function: sDisRxStatusMode 511Purpose: Disable the Rx status mode 512Call: sDisRxStatusMode(ChP) 513 CHANNEL_T *ChP; Ptr to channel structure 514Comments: This takes the channel out of the receive status mode. All 515 subsequent reads of receive data using sReadRxWord() will return 516 two data bytes. 517*/ 518#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0) 519 520/*************************************************************************** 521Function: sDisTransmit 522Purpose: Disable transmit 523Call: sDisTransmit(ChP) 524 CHANNEL_T *ChP; Ptr to channel structure 525 This disables movement of Tx data from the Tx FIFO into the 1 byte 526 Tx buffer. Therefore there could be up to a 2 byte latency 527 between the time sDisTransmit() is called and the transmit buffer 528 and transmit shift register going completely empty. 529*/ 530#define sDisTransmit(ChP) \ 531{ \ 532 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 533 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 534} 535 536/*************************************************************************** 537Function: sDisTxSoftFlowCtl 538Purpose: Disable Tx Software Flow Control 539Call: sDisTxSoftFlowCtl(ChP) 540 CHANNEL_T *ChP; Ptr to channel structure 541*/ 542#define sDisTxSoftFlowCtl(ChP) \ 543{ \ 544 (ChP)->R[0x06] = 0x8a; \ 545 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x04]); \ 546} 547 548/*************************************************************************** 549Function: sEnCTSFlowCtl 550Purpose: Enable output flow control using CTS 551Call: sEnCTSFlowCtl(ChP) 552 CHANNEL_T *ChP; Ptr to channel structure 553*/ 554#define sEnCTSFlowCtl(ChP) \ 555{ \ 556 (ChP)->TxControl[2] |= CTSFC_EN; \ 557 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 558} 559 560/*************************************************************************** 561Function: EnParity 562Purpose: Enable parity 563Call: sEnParity(ChP) 564 CHANNEL_T *ChP; Ptr to channel structure 565Comments: Function sSetParity() can be used in place of functions sEnParity(), 566 sDisParity(), sSetOddParity(), and sSetEvenParity(). 567 568Warnings: Before enabling parity odd or even parity should be chosen using 569 functions sSetOddParity() or sSetEvenParity(). 570*/ 571#define sEnParity(ChP) \ 572{ \ 573 (ChP)->TxControl[2] |= PARITY_EN; \ 574 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 575} 576 577/*************************************************************************** 578Function: sEnRTSFlowCtl 579Return: void 580*/ 581#define sEnRTSFlowCtl(ChP) \ 582{ \ 583 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 584 (ChP)->TxControl[3] &= ~SET_RTS; \ 585 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 586 (ChP)->RxControl[2] |= RTSFC_EN; \ 587 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \ 588} 589 590/*************************************************************************** 591Function: sDisRTSFlowCtl 592Return: void 593*/ 594#define sDisRTSFlowCtl(ChP) \ 595{ \ 596 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 597 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \ 598} 599 600/*************************************************************************** 601Function: sEnRxFIFO 602Purpose: Enable Rx FIFO 603Call: sEnRxFIFO(ChP) 604 CHANNEL_T *ChP; Ptr to channel structure 605*/ 606#define sEnRxFIFO(ChP) \ 607{ \ 608 (ChP)->R[0x32] = 0x08; \ 609 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \ 610} 611 612/*************************************************************************** 613Function: sEnRxProcessor 614Purpose: Enable the receive processor 615Call: sEnRxProcessor(ChP) 616 CHANNEL_T *ChP; Ptr to channel structure 617Comments: This function is used to start the receive processor. When 618 the channel is in the reset state the receive processor is not 619 running. This is done to prevent the receive processor from 620 executing invalid microcode instructions prior to the 621 downloading of the microcode. 622 623Warnings: This function must be called after valid microcode has been 624 downloaded to the AIOP, and it must not be called before the 625 microcode has been downloaded. 626*/ 627#define sEnRxProcessor(ChP) \ 628{ \ 629 (ChP)->RxControl[2] |= RXPROC_EN; \ 630 rp_writech2(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \ 631} 632 633/*************************************************************************** 634Function: sEnRxStatusMode 635Purpose: Enable the Rx status mode 636Call: sEnRxStatusMode(ChP) 637 CHANNEL_T *ChP; Ptr to channel structure 638Comments: This places the channel in the receive status mode. All subsequent 639 reads of receive data using sReadRxWord() will return a data byte 640 in the low word and a status byte in the high word. 641 642*/ 643#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE) 644 645/*************************************************************************** 646Function: sEnTransmit 647Purpose: Enable transmit 648Call: sEnTransmit(ChP) 649 CHANNEL_T *ChP; Ptr to channel structure 650*/ 651#define sEnTransmit(ChP) \ 652{ \ 653 (ChP)->TxControl[3] |= TX_ENABLE; \ 654 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 655} 656 657/*************************************************************************** 658Function: sGetAiopIntStatus 659Purpose: Get the AIOP interrupt status 660Call: sGetAiopIntStatus(CtlP,AiopNum) 661 CONTROLLER_T *CtlP; Ptr to controller structure 662 int AiopNum; AIOP number 663Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 664 represent channels 0 through 7 respectively. If a 665 bit is set that channel is interrupting. 666*/ 667#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN) 668 669/*************************************************************************** 670Function: sGetAiopNumChan 671Purpose: Get the number of channels supported by an AIOP 672Call: sGetAiopNumChan(CtlP,AiopNum) 673 CONTROLLER_T *CtlP; Ptr to controller structure 674 int AiopNum; AIOP number 675Return: int: The number of channels supported by the AIOP 676*/ 677#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM] 678 679/*************************************************************************** 680Function: sGetChanIntID 681Purpose: Get a channel's interrupt identification byte 682Call: sGetChanIntID(ChP) 683 CHANNEL_T *ChP; Ptr to channel structure 684Return: Byte_t: The channel interrupt ID. Can be any 685 combination of the following flags: 686 RXF_TRIG: Rx FIFO trigger level interrupt 687 TXFIFO_MT: Tx FIFO empty interrupt 688 SRC_INT: Special receive condition interrupt 689 DELTA_CD: CD change interrupt 690 DELTA_CTS: CTS change interrupt 691 DELTA_DSR: DSR change interrupt 692*/ 693#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 694 695/*************************************************************************** 696Function: sGetChanNum 697Purpose: Get the number of a channel within an AIOP 698Call: sGetChanNum(ChP) 699 CHANNEL_T *ChP; Ptr to channel structure 700Return: int: Channel number within AIOP, or NULLCHAN if channel does 701 not exist. 702*/ 703#define sGetChanNum(ChP) (ChP)->ChanNum 704 705/*************************************************************************** 706Function: sGetChanStatus 707Purpose: Get the channel status 708Call: sGetChanStatus(ChP) 709 CHANNEL_T *ChP; Ptr to channel structure 710Return: Word_t: The channel status. Can be any combination of 711 the following flags: 712 LOW BYTE FLAGS 713 CTS_ACT: CTS input asserted 714 DSR_ACT: DSR input asserted 715 CD_ACT: CD input asserted 716 TXFIFOMT: Tx FIFO is empty 717 TXSHRMT: Tx shift register is empty 718 RDA: Rx data available 719 720 HIGH BYTE FLAGS 721 STATMODE: status mode enable bit 722 RXFOVERFL: receive FIFO overflow 723 RX2MATCH: receive compare byte 2 match 724 RX1MATCH: receive compare byte 1 match 725 RXBREAK: received BREAK 726 RXFRAME: received framing error 727 RXPARITY: received parity error 728Warnings: This function will clear the high byte flags in the Channel 729 Status Register. 730*/ 731#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP)) 732 733/*************************************************************************** 734Function: sGetChanStatusLo 735Purpose: Get the low byte only of the channel status 736Call: sGetChanStatusLo(ChP) 737 CHANNEL_T *ChP; Ptr to channel structure 738Return: Byte_t: The channel status low byte. Can be any combination 739 of the following flags: 740 CTS_ACT: CTS input asserted 741 DSR_ACT: DSR input asserted 742 CD_ACT: CD input asserted 743 TXFIFOMT: Tx FIFO is empty 744 TXSHRMT: Tx shift register is empty 745 RDA: Rx data available 746*/ 747#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP)) 748 749/*************************************************************************** 750Function: sGetRxCnt 751Purpose: Get the number of data bytes in the Rx FIFO 752Call: sGetRxCnt(ChP) 753 CHANNEL_T *ChP; Ptr to channel structure 754Return: int: The number of data bytes in the Rx FIFO. 755Comments: Byte read of count register is required to obtain Rx count. 756 757*/ 758#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP)) 759 760/*************************************************************************** 761Function: sGetTxCnt 762Purpose: Get the number of data bytes in the Tx FIFO 763Call: sGetTxCnt(ChP) 764 CHANNEL_T *ChP; Ptr to channel structure 765Return: Byte_t: The number of data bytes in the Tx FIFO. 766Comments: Byte read of count register is required to obtain Tx count. 767 768*/ 769#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP)) 770 771/***************************************************************************** 772Function: sGetTxRxDataIO 773Purpose: Get the offset of a channel's TxRx Data register 774Call: sGetTxRxDataIO(ChP) 775 CHANNEL_T *ChP; Ptr to channel structure 776Return: WordIO_t: offset of a channel's TxRx Data register 777*/ 778#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP) 779 780/*************************************************************************** 781Function: sInitChanDefaults 782Purpose: Initialize a channel structure to its default state. 783Call: sInitChanDefaults(ChP) 784 CHANNEL_T *ChP; Ptr to the channel structure 785Comments: This function must be called once for every channel structure 786 that exists before any other SSCI calls can be made. 787 788*/ 789#define sInitChanDefaults(ChP) \ 790{ \ 791 (ChP)->CtlP = NULLCTLPTR; \ 792 (ChP)->AiopNum = NULLAIOP; \ 793 (ChP)->ChanID = AIOPID_NULL; \ 794 (ChP)->ChanNum = NULLCHAN; \ 795} 796 797/*************************************************************************** 798Function: sResetAiopByNum 799Purpose: Reset the AIOP by number 800Call: sResetAiopByNum(CTLP,AIOPNUM) 801 CONTROLLER_T CTLP; Ptr to controller structure 802 AIOPNUM; AIOP index 803*/ 804#define sResetAiopByNum(CTLP,AIOPNUM) \ 805{ \ 806 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \ 807 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \ 808} 809 810/*************************************************************************** 811Function: sSendBreak 812Purpose: Send a transmit BREAK signal 813Call: sSendBreak(ChP) 814 CHANNEL_T *ChP; Ptr to channel structure 815*/ 816#define sSendBreak(ChP) \ 817{ \ 818 (ChP)->TxControl[3] |= SETBREAK; \ 819 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 820} 821 822/*************************************************************************** 823Function: sSetBaud 824Purpose: Set baud rate 825Call: sSetBaud(ChP,Divisor) 826 CHANNEL_T *ChP; Ptr to channel structure 827 Word_t Divisor; 16 bit baud rate divisor for channel 828*/ 829#define sSetBaud(ChP,DIVISOR) \ 830{ \ 831 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 832 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 833 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 834} 835 836/*************************************************************************** 837Function: sSetData7 838Purpose: Set data bits to 7 839Call: sSetData7(ChP) 840 CHANNEL_T *ChP; Ptr to channel structure 841*/ 842#define sSetData7(ChP) \ 843{ \ 844 (ChP)->TxControl[2] &= ~DATA8BIT; \ 845 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 846} 847 848/*************************************************************************** 849Function: sSetData8 850Purpose: Set data bits to 8 851Call: sSetData8(ChP) 852 CHANNEL_T *ChP; Ptr to channel structure 853*/ 854#define sSetData8(ChP) \ 855{ \ 856 (ChP)->TxControl[2] |= DATA8BIT; \ 857 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 858} 859 860/*************************************************************************** 861Function: sSetDTR 862Purpose: Set the DTR output 863Call: sSetDTR(ChP) 864 CHANNEL_T *ChP; Ptr to channel structure 865*/ 866#define sSetDTR(ChP) \ 867{ \ 868 (ChP)->TxControl[3] |= SET_DTR; \ 869 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 870} 871 872/*************************************************************************** 873Function: sSetEvenParity 874Purpose: Set even parity 875Call: sSetEvenParity(ChP) 876 CHANNEL_T *ChP; Ptr to channel structure 877Comments: Function sSetParity() can be used in place of functions sEnParity(), 878 sDisParity(), sSetOddParity(), and sSetEvenParity(). 879 880Warnings: This function has no effect unless parity is enabled with function 881 sEnParity(). 882*/ 883#define sSetEvenParity(ChP) \ 884{ \ 885 (ChP)->TxControl[2] |= EVEN_PAR; \ 886 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 887} 888 889/*************************************************************************** 890Function: sSetOddParity 891Purpose: Set odd parity 892Call: sSetOddParity(ChP) 893 CHANNEL_T *ChP; Ptr to channel structure 894Comments: Function sSetParity() can be used in place of functions sEnParity(), 895 sDisParity(), sSetOddParity(), and sSetEvenParity(). 896 897Warnings: This function has no effect unless parity is enabled with function 898 sEnParity(). 899*/ 900#define sSetOddParity(ChP) \ 901{ \ 902 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 903 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 904} 905 906/*************************************************************************** 907Function: sSetRTS 908Purpose: Set the RTS output 909Call: sSetRTS(ChP) 910 CHANNEL_T *ChP; Ptr to channel structure 911*/ 912#define sSetRTS(ChP) \ 913{ \ 914 (ChP)->TxControl[3] |= SET_RTS; \ 915 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 916} 917 918/*************************************************************************** 919Function: sSetRxTrigger 920Purpose: Set the Rx FIFO trigger level 921Call: sSetRxProcessor(ChP,Level) 922 CHANNEL_T *ChP; Ptr to channel structure 923 Byte_t Level; Number of characters in Rx FIFO at which the 924 interrupt will be generated. Can be any of the following flags: 925 926 TRIG_NO: no trigger 927 TRIG_1: 1 character in FIFO 928 TRIG_1_2: FIFO 1/2 full 929 TRIG_7_8: FIFO 7/8 full 930Comments: An interrupt will be generated when the trigger level is reached 931 only if function sEnInterrupt() has been called with flag 932 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 933 register will be set whenever the trigger level is reached 934 regardless of the setting of RXINT_EN. 935 936*/ 937#define sSetRxTrigger(ChP,LEVEL) \ 938{ \ 939 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 940 (ChP)->RxControl[2] |= LEVEL; \ 941 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \ 942} 943 944/*************************************************************************** 945Function: sSetStop1 946Purpose: Set stop bits to 1 947Call: sSetStop1(ChP) 948 CHANNEL_T *ChP; Ptr to channel structure 949*/ 950#define sSetStop1(ChP) \ 951{ \ 952 (ChP)->TxControl[2] &= ~STOP2; \ 953 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 954} 955 956/*************************************************************************** 957Function: sSetStop2 958Purpose: Set stop bits to 2 959Call: sSetStop2(ChP) 960 CHANNEL_T *ChP; Ptr to channel structure 961*/ 962#define sSetStop2(ChP) \ 963{ \ 964 (ChP)->TxControl[2] |= STOP2; \ 965 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \ 966} 967 968/*************************************************************************** 969Function: sStartRxProcessor 970Purpose: Start a channel's receive processor 971Call: sStartRxProcessor(ChP) 972 CHANNEL_T *ChP; Ptr to channel structure 973Comments: This function is used to start a Rx processor after it was 974 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 975 will restart both the Rx processor and software input flow control. 976 977*/ 978#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0]) 979 980/*************************************************************************** 981Function: sWriteTxByte 982Purpose: Write a transmit data byte to a channel. 983 CHANNEL_T *ChP; Ptr to channel structure 984 ByteIO_t io: Channel transmit register I/O address. This can 985 be obtained with sGetTxRxDataIO(). 986 Byte_t Data; The transmit data byte. 987Warnings: This function writes the data byte without checking to see if 988 sMaxTxSize is exceeded in the Tx FIFO. 989*/ 990#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA) 991 992int sReadAiopID(CONTROLLER_T *CtlP, int aiop); 993int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop); 994int sInitChan( CONTROLLER_T *CtlP, 995 CHANNEL_T *ChP, 996 int AiopNum, 997 int ChanNum); 998Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 999void sStopRxProcessor(CHANNEL_T *ChP); 1000void sStopSWInFlowCtl(CHANNEL_T *ChP); 1001void sFlushRxFIFO(CHANNEL_T *ChP); 1002void sFlushTxFIFO(CHANNEL_T *ChP); 1003int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1004void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1005void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1006int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports); 1007void rp_releaseresource(CONTROLLER_t *ctlp); 1008 1009#ifndef ROCKET_C 1010extern Byte_t R[RDATASIZE]; 1011extern CONTROLLER_T sController[CTL_SIZE]; 1012extern Byte_t sIRQMap[16]; 1013#endif 1014extern Byte_t rp_sBitMapClrTbl[8]; 1015extern Byte_t rp_sBitMapSetTbl[8]; 1016