1139749Simp/*- 228868Sjkh * Copyright (c) Comtrol Corporation <support@comtrol.com> 328868Sjkh * All rights reserved. 428868Sjkh * 528868Sjkh * Redistribution and use in source and binary forms, with or without 628868Sjkh * modification, are permitted prodived that the follwoing conditions 728868Sjkh * are met. 828868Sjkh * 1. Redistributions of source code must retain the above copyright 928868Sjkh * notive, this list of conditions and the following disclainer. 1028868Sjkh * 2. Redistributions in binary form must reproduce the above copyright 1128868Sjkh * notice, this list of conditions and the following disclaimer in the 1228868Sjkh * documentation and/or other materials prodided with the distribution. 1328868Sjkh * 3. All advertising materials mentioning features or use of this software 1428868Sjkh * must display the following acknowledgement: 1528868Sjkh * This product includes software developed by Comtrol Corporation. 1628868Sjkh * 4. The name of Comtrol Corporation may not be used to endorse or 1728868Sjkh * promote products derived from this software without specific 1828868Sjkh * prior written permission. 1928868Sjkh * 2028868Sjkh * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 2128868Sjkh * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2228868Sjkh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2328868Sjkh * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 2428868Sjkh * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2528868Sjkh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2628868Sjkh * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 2728868Sjkh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2828868Sjkh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2928868Sjkh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3028868Sjkh * SUCH DAMAGE. 3159874Speter * 3259874Speter * $FreeBSD$ 3328868Sjkh */ 3428868Sjkh 3528868Sjkh/* 3628868Sjkh * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD 3728868Sjkh */ 3828868Sjkh 39164439Smariustypedef uint8_t Byte_t; 40164439Smariustypedef uint8_t ByteIO_t; 4128868Sjkh 42164439Smariustypedef uint16_t Word_t; 43164439Smariustypedef uint16_t WordIO_t; 4428868Sjkh 45164439Smariustypedef uint32_t DWord_t; 46164439Smariustypedef uint32_t DWordIO_t; 4728868Sjkh 4861541Stanimura#define rp_readio(size, ctlp, rid, offset) \ 49164439Smarius (bus_read_##size(ctlp->io[rid], offset)) 5061541Stanimura#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \ 51164439Smarius (bus_read_multi_##size(ctlp->io[rid], offset, addr, count)) 5261541Stanimura#define rp_writeio(size, ctlp, rid, offset, data) \ 53164439Smarius (bus_write_##size(ctlp->io[rid], offset, data)) 5461541Stanimura#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \ 55164439Smarius (bus_write_multi_##size(ctlp->io[rid], offset, addr, count)) 5628868Sjkh 5761541Stanimura#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset) 5861541Stanimura#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset) 5961541Stanimura#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset) 6061541Stanimura#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data) 6161541Stanimura#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data) 6261541Stanimura#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data) 6361541Stanimura#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count) 6461541Stanimura#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count) 6561541Stanimura#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count) 6661541Stanimura#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count) 6761541Stanimura#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count) 6861541Stanimura#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count) 6961541Stanimura 7061541Stanimura#define rp_readaiop1(ctlp, aiop, offset) \ 7161541Stanimura (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 7261541Stanimura#define rp_readaiop2(ctlp, aiop, offset) \ 7361541Stanimura (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 7461541Stanimura#define rp_readaiop4(ctlp, aiop, offset) \ 7561541Stanimura (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset))) 7661541Stanimura#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \ 7761541Stanimura (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 7861541Stanimura#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \ 7961541Stanimura (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 8061541Stanimura#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \ 8161541Stanimura (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 8261541Stanimura#define rp_writeaiop1(ctlp, aiop, offset, data) \ 8361541Stanimura (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 8461541Stanimura#define rp_writeaiop2(ctlp, aiop, offset, data) \ 8561541Stanimura (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 8661541Stanimura#define rp_writeaiop4(ctlp, aiop, offset, data) \ 8761541Stanimura (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data)) 8861541Stanimura#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \ 8961541Stanimura (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 9061541Stanimura#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \ 9161541Stanimura (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 9261541Stanimura#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \ 9361541Stanimura (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count)) 9461541Stanimura 9561541Stanimura#define rp_readch1(chp, offset) \ 9661541Stanimura (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset)) 9761541Stanimura#define rp_readch2(chp, offset) \ 9861541Stanimura (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset)) 9961541Stanimura#define rp_readch4(chp, offset) \ 10061541Stanimura (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset)) 10161541Stanimura#define rp_readmultich1(chp, offset, addr, count) \ 10261541Stanimura (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 10361541Stanimura#define rp_readmultich2(chp, offset, addr, count) \ 10461541Stanimura (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 10561541Stanimura#define rp_readmultich4(chp, offset, addr, count) \ 10661541Stanimura (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 10761541Stanimura#define rp_writech1(chp, offset, data) \ 10861541Stanimura (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data)) 10961541Stanimura#define rp_writech2(chp, offset, data) \ 11061541Stanimura (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data)) 11161541Stanimura#define rp_writech4(chp, offset, data) \ 11261541Stanimura (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data)) 11361541Stanimura#define rp_writemultich1(chp, offset, addr, count) \ 11461541Stanimura (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 11561541Stanimura#define rp_writemultich2(chp, offset, addr, count) \ 11661541Stanimura (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 11761541Stanimura#define rp_writemultich4(chp, offset, addr, count) \ 11861541Stanimura (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count)) 11961541Stanimura 12028868Sjkh/* 12128868Sjkh * End of OS-specific defines 12228868Sjkh */ 12328868Sjkh 12428868Sjkh#define ROCKET_H 12528868Sjkh 12628868Sjkh#define CTL_SIZE 4 12728868Sjkh#define AIOP_CTL_SIZE 4 12828868Sjkh#define CHAN_AIOP_SIZE 8 12928868Sjkh#define MAX_PORTS_PER_AIOP 8 13028868Sjkh#define MAX_AIOPS_PER_BOARD 4 13128868Sjkh#define MAX_PORTS_PER_BOARD 32 13228868Sjkh 13328868Sjkh/* Controller ID numbers */ 13428868Sjkh#define CTLID_NULL -1 /* no controller exists */ 13528868Sjkh#define CTLID_0001 0x0001 /* controller release 1 */ 13628868Sjkh 13728868Sjkh/* AIOP ID numbers, identifies AIOP type implementing channel */ 13828868Sjkh#define AIOPID_NULL -1 /* no AIOP or channel exists */ 13928868Sjkh#define AIOPID_0001 0x0001 /* AIOP release 1 */ 14028868Sjkh 14128868Sjkh#define NULLDEV -1 /* identifies non-existant device */ 14228868Sjkh#define NULLCTL -1 /* identifies non-existant controller */ 14328868Sjkh#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 14428868Sjkh#define NULLAIOP -1 /* identifies non-existant AIOP */ 14528868Sjkh#define NULLCHAN -1 /* identifies non-existant channel */ 14628868Sjkh 14728868Sjkh/************************************************************************ 14828868Sjkh Global Register Offsets - Direct Access - Fixed values 14928868Sjkh************************************************************************/ 15028868Sjkh 15128868Sjkh#define _CMD_REG 0x38 /* Command Register 8 Write */ 15228868Sjkh#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 15328868Sjkh#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 15428868Sjkh#define _UNUSED 0x3B /* Unused 8 */ 15528868Sjkh#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 15628868Sjkh#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 15728868Sjkh 15828868Sjkh/************************************************************************ 15928868Sjkh Channel Register Offsets for 1st channel in AIOP - Direct Access 16028868Sjkh************************************************************************/ 16128868Sjkh#define _TD0 0x00 /* Transmit Data 16 Write */ 16228868Sjkh#define _RD0 0x00 /* Receive Data 16 Read */ 16328868Sjkh#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 16428868Sjkh#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 16528868Sjkh#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 16628868Sjkh 16728868Sjkh/************************************************************************ 16828868Sjkh Tx Control Register Offsets - Indexed - External - Fixed 16928868Sjkh************************************************************************/ 17028868Sjkh#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 17128868Sjkh#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 17228868Sjkh#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 17328868Sjkh#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 17428868Sjkh#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 17528868Sjkh#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 17628868Sjkh 17728868Sjkh/************************************************************************ 17828868Sjkh Receive FIFO 17928868Sjkh************************************************************************/ 18028868Sjkh#define RXFIFO_DATA 0x5f 18128868Sjkh#define RXFIFO_OUT 0x5c 18228868Sjkh#define RXFIFO_EN 0x08 18328868Sjkh#define RXFIFO_DIS 0xa7 18428868Sjkh 18528868Sjkh/************************************************************************ 18628868SjkhMemory Controller Register Offsets - Indexed - External - Fixed 18728868Sjkh************************************************************************/ 18828868Sjkh#define _RX_FIFO 0x000 /* Rx FIFO */ 18928868Sjkh#define _TX_FIFO 0x800 /* Tx FIFO */ 19028868Sjkh#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 19128868Sjkh#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 19228868Sjkh#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 19328868Sjkh#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 19428868Sjkh#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 19528868Sjkh#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 19628868Sjkh 19728868Sjkh#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 19828868Sjkh#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 19928868Sjkh#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 20028868Sjkh 20128868Sjkh/************************************************************************ 20228868SjkhTx Priority Buffer - Indexed - External - Fixed 20328868Sjkh************************************************************************/ 20428868Sjkh#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 20528868Sjkh#define TXP_SIZE 0x20 /* 32 bytes */ 20628868Sjkh 20728868Sjkh/************************************************************************ 20828868SjkhChannel Register Offsets - Indexed - Internal - Fixed 20928868Sjkh************************************************************************/ 21028868Sjkh 21128868Sjkh#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 21228868Sjkh#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 21328868Sjkh#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 21428868Sjkh#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 21528868Sjkh 21628868Sjkh#define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 21728868Sjkh 21828868Sjkh#define BRD50 4607 21928868Sjkh#define BRD75 3071 22028868Sjkh#define BRD110 2094 22128868Sjkh#define BRD134 1712 22228868Sjkh#define BRD150 1535 22328868Sjkh#define BRD200 1151 22428868Sjkh#define BRD300 767 22528868Sjkh#define BRD600 383 22628868Sjkh#define BRD1200 191 22728868Sjkh#define BRD1800 127 22828868Sjkh#define BRD2000 114 22928868Sjkh#define BRD2400 95 23028868Sjkh#define BRD3600 64 23128868Sjkh#define BRD4800 47 23228868Sjkh#define BRD7200 31 23328868Sjkh#define BRD9600 23 23428868Sjkh#define BRD14400 15 23528868Sjkh#define BRD19200 11 23628868Sjkh#define BRD38400 5 23728868Sjkh#define BRD57600 3 23828868Sjkh#define BRD76800 2 23928868Sjkh#define BRD115200 1 24028868Sjkh#define BRD230400 0 24128868Sjkh 24228868Sjkh#define STMBREAK 0x08 /* BREAK */ 24328868Sjkh#define STMFRAME 0x04 /* framing error */ 24428868Sjkh#define STMRCVROVR 0x02 /* receiver over run error */ 24528868Sjkh#define STMPARITY 0x01 /* parity error */ 24628868Sjkh#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 24728868Sjkh#define STMBREAKH 0x800 /* BREAK */ 24828868Sjkh#define STMFRAMEH 0x400 /* framing error */ 24928868Sjkh#define STMRCVROVRH 0x200 /* receiver over run error */ 25028868Sjkh#define STMPARITYH 0x100 /* parity error */ 25128868Sjkh#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 25228868Sjkh 25328868Sjkh#define CTS_ACT 0x20 /* CTS input asserted */ 25428868Sjkh#define DSR_ACT 0x10 /* DSR input asserted */ 25528868Sjkh#define CD_ACT 0x08 /* CD input asserted */ 25628868Sjkh#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 25728868Sjkh#define TXSHRMT 0x02 /* Tx shift register is empty */ 25828868Sjkh#define RDA 0x01 /* Rx data available */ 25928868Sjkh#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 26028868Sjkh 26128868Sjkh#define STATMODE 0x8000 /* status mode enable bit */ 26228868Sjkh#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 26328868Sjkh#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 26428868Sjkh#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 26528868Sjkh#define RXBREAK 0x0400 /* received BREAK */ 26628868Sjkh#define RXFRAME 0x0200 /* received framing error */ 26728868Sjkh#define RXPARITY 0x0100 /* received parity error */ 26828868Sjkh#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 26928868Sjkh 27028868Sjkh#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 27128868Sjkh#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 27228868Sjkh#define TXINT_EN 0x10 /* transmit interrupt enable */ 27328868Sjkh#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 27428868Sjkh#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 27528868Sjkh#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 27628868Sjkh#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 27728868Sjkh 27828868Sjkh#define SETBREAK 0x10 /* send break condition (must clear) */ 27928868Sjkh#define LOCALLOOP 0x08 /* local loopback set for test */ 28028868Sjkh#define SET_DTR 0x04 /* assert DTR */ 28128868Sjkh#define SET_RTS 0x02 /* assert RTS */ 28228868Sjkh#define TX_ENABLE 0x01 /* enable transmitter */ 28328868Sjkh 28428868Sjkh#define RTSFC_EN 0x40 /* RTS flow control enable */ 28528868Sjkh#define RXPROC_EN 0x20 /* receive processor enable */ 28628868Sjkh#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 28728868Sjkh#define TRIG_1 0x08 /* trigger level 1 char */ 28828868Sjkh#define TRIG_1_2 0x10 /* trigger level 1/2 */ 28928868Sjkh#define TRIG_7_8 0x18 /* trigger level 7/8 */ 29028868Sjkh#define TRIG_MASK 0x18 /* trigger level mask */ 29128868Sjkh#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 29228868Sjkh#define RXINT_EN 0x02 /* Rx interrupt enable */ 29328868Sjkh#define MCINT_EN 0x01 /* modem change interrupt enable */ 29428868Sjkh 29528868Sjkh#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 29628868Sjkh#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 29728868Sjkh#define SRC_INT 0x08 /* special receive condition interrupt */ 29828868Sjkh#define DELTA_CD 0x04 /* CD change interrupt */ 29928868Sjkh#define DELTA_CTS 0x02 /* CTS change interrupt */ 30028868Sjkh#define DELTA_DSR 0x01 /* DSR change interrupt */ 30128868Sjkh 30228868Sjkh#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 30328868Sjkh#define IGN2_EN 0x08 /* ignore byte 2 enable */ 30428868Sjkh#define IGN1_EN 0x04 /* ignore byte 1 enable */ 30528868Sjkh#define COMP2_EN 0x02 /* compare byte 2 enable */ 30628868Sjkh#define COMP1_EN 0x01 /* compare byte 1 enable */ 30728868Sjkh 30828868Sjkh#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 30928868Sjkh#define TXOVERIDE 0x40 /* Transmit software off override */ 31028868Sjkh#define RESETUART 0x20 /* reset channel's UART */ 31128868Sjkh#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 31228868Sjkh#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 31328868Sjkh 31428868Sjkh#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 31528868Sjkh#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 31628868Sjkh#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 31728868Sjkh#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 31828868Sjkh 31928868Sjkh#define INTR_EN 0x08 /* allow interrupts to host */ 32028868Sjkh#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 32128868Sjkh 32228868Sjkh#define CHAN3_EN 0x08 /* enable AIOP 3 */ 32328868Sjkh#define CHAN2_EN 0x04 /* enable AIOP 2 */ 32428868Sjkh#define CHAN1_EN 0x02 /* enable AIOP 1 */ 32528868Sjkh#define CHAN0_EN 0x01 /* enable AIOP 0 */ 32628868Sjkh#define FREQ_DIS 0x00 32728868Sjkh#define FREQ_274HZ 0x60 32828868Sjkh#define FREQ_137HZ 0x50 32928868Sjkh#define FREQ_69HZ 0x40 33028868Sjkh#define FREQ_34HZ 0x30 33128868Sjkh#define FREQ_17HZ 0x20 33228868Sjkh#define FREQ_9HZ 0x10 33328868Sjkh#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 33428868Sjkh 33528868Sjkh#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 33628868Sjkh 33728868Sjkh#define RDATASIZE 72 33828868Sjkh#define RREGDATASIZE 52 33928868Sjkh 34061541Stanimura#ifndef TRUE 34161541Stanimura#define TRUE 1 34261541Stanimura#endif 34361541Stanimura 34461541Stanimura#ifndef FALSE 34561541Stanimura#define FALSE 0 34661541Stanimura#endif 34761541Stanimura 34861541Stanimurastruct CONTROLLER_str; 34961541Stanimurastruct CHANNEL_str; 35061541Stanimura 35161541Stanimura/* The types of bus-specific methods */ 35261541Stanimuratypedef int rp_aiop2rid_t(int, int); 35361541Stanimuratypedef int rp_aiop2off_t(int, int); 35461541Stanimuratypedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *); 35561541Stanimura 35628868Sjkh/* Controller level information structure */ 35761541Stanimurastruct CONTROLLER_str 35828868Sjkh{ 35928868Sjkh int CtlID; 36028868Sjkh int NumAiop; 36128868Sjkh int AiopID[AIOP_CTL_SIZE]; 36228868Sjkh int AiopNumChan[AIOP_CTL_SIZE]; 36328868Sjkh 364191563Sambrisko struct mtx hwmtx; /* Spinlock protecting hardware. */ 365191563Sambrisko int hwmtx_init; 366191563Sambrisko int free; 367274390Sjhb int num_ports; 368191563Sambrisko 36961541Stanimura /* Device and resource management */ 37061541Stanimura device_t dev; /* device */ 37161541Stanimura int io_num; /* Number of IO resources */ 37261541Stanimura int *io_rid; /* IO resource IDs */ 37361541Stanimura struct resource **io; /* IO resources */ 37461541Stanimura 37561541Stanimura struct rp_port *rp; /* port */ 37661541Stanimura 37761541Stanimura /* Device nodes */ 378130585Sphk struct cdev **dev_nodes; 37961541Stanimura 38061541Stanimura /* Bus-specific properties */ 38161541Stanimura void *bus_ctlp; 38261541Stanimura 38361541Stanimura /* Bus-specific methods */ 38461541Stanimura rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */ 38561541Stanimura rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */ 38661541Stanimura rp_ctlmask_t *ctlmask; /* Int status */ 38761541Stanimura}; 38861541Stanimuratypedef struct CONTROLLER_str CONTROLLER_T; 38928868Sjkhtypedef CONTROLLER_T CONTROLLER_t; 39028868Sjkh 39128868Sjkh/* Channel level information structure */ 39261541Stanimurastruct CHANNEL_str 39328868Sjkh{ 39461541Stanimura CONTROLLER_t *CtlP; 39528868Sjkh int AiopNum; 39628868Sjkh int ChanID; 39728868Sjkh int ChanNum; 39828868Sjkh 39928868Sjkh Word_t TxFIFO; 40028868Sjkh Word_t TxFIFOPtrs; 40128868Sjkh Word_t RxFIFO; 40228868Sjkh Word_t RxFIFOPtrs; 40328868Sjkh Word_t TxPrioCnt; 40428868Sjkh Word_t TxPrioPtr; 40528868Sjkh Word_t TxPrioBuf; 40628868Sjkh 40728868Sjkh Byte_t R[RREGDATASIZE]; 40828868Sjkh 40928868Sjkh Byte_t BaudDiv[4]; 41028868Sjkh Byte_t TxControl[4]; 41128868Sjkh Byte_t RxControl[4]; 41228868Sjkh Byte_t TxEnables[4]; 41328868Sjkh Byte_t TxCompare[4]; 41428868Sjkh Byte_t TxReplace1[4]; 41528868Sjkh Byte_t TxReplace2[4]; 41661541Stanimura}; 41728868Sjkh 41861541Stanimuratypedef struct CHANNEL_str CHANNEL_T; 41928868Sjkhtypedef CHANNEL_T CHANNEL_t; 42028868Sjkhtypedef CHANNEL_T * CHANPTR_T; 42128868Sjkh 42261541Stanimura#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0) 42361541Stanimura#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0) 42461541Stanimura#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0) 42561541Stanimura#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0) 42661541Stanimura 42728868Sjkh/*************************************************************************** 42828868SjkhFunction: sClrBreak 42928868SjkhPurpose: Stop sending a transmit BREAK signal 43028868SjkhCall: sClrBreak(ChP) 43128868Sjkh CHANNEL_T *ChP; Ptr to channel structure 43228868Sjkh*/ 43328868Sjkh#define sClrBreak(ChP) \ 43428868Sjkh{ \ 43528868Sjkh (ChP)->TxControl[3] &= ~SETBREAK; \ 436164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 43728868Sjkh} 43828868Sjkh 43928868Sjkh/*************************************************************************** 44028868SjkhFunction: sClrDTR 44128868SjkhPurpose: Clr the DTR output 44228868SjkhCall: sClrDTR(ChP) 44328868Sjkh CHANNEL_T *ChP; Ptr to channel structure 44428868Sjkh*/ 44528868Sjkh#define sClrDTR(ChP) \ 44628868Sjkh{ \ 44728868Sjkh (ChP)->TxControl[3] &= ~SET_DTR; \ 448164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 44928868Sjkh} 45028868Sjkh 45128868Sjkh/*************************************************************************** 45228868SjkhFunction: sClrRTS 45328868SjkhPurpose: Clr the RTS output 45428868SjkhCall: sClrRTS(ChP) 45528868Sjkh CHANNEL_T *ChP; Ptr to channel structure 45628868Sjkh*/ 45728868Sjkh#define sClrRTS(ChP) \ 45828868Sjkh{ \ 45928868Sjkh (ChP)->TxControl[3] &= ~SET_RTS; \ 460164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 46128868Sjkh} 46228868Sjkh 46328868Sjkh/*************************************************************************** 46428868SjkhFunction: sClrTxXOFF 46528868SjkhPurpose: Clear any existing transmit software flow control off condition 46628868SjkhCall: sClrTxXOFF(ChP) 46728868Sjkh CHANNEL_T *ChP; Ptr to channel structure 46828868Sjkh*/ 46928868Sjkh#define sClrTxXOFF(ChP) \ 47028868Sjkh{ \ 47161541Stanimura rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 47261541Stanimura rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \ 47328868Sjkh} 47428868Sjkh 47528868Sjkh/*************************************************************************** 47628868SjkhFunction: sDisCTSFlowCtl 47728868SjkhPurpose: Disable output flow control using CTS 47828868SjkhCall: sDisCTSFlowCtl(ChP) 47928868Sjkh CHANNEL_T *ChP; Ptr to channel structure 48028868Sjkh*/ 48128868Sjkh#define sDisCTSFlowCtl(ChP) \ 48228868Sjkh{ \ 48328868Sjkh (ChP)->TxControl[2] &= ~CTSFC_EN; \ 484164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 48528868Sjkh} 48628868Sjkh 48728868Sjkh/*************************************************************************** 48828868SjkhFunction: DisParity 48928868SjkhPurpose: Disable parity 49028868SjkhCall: sDisParity(ChP) 49128868Sjkh CHANNEL_T *ChP; Ptr to channel structure 49228868SjkhComments: Function sSetParity() can be used in place of functions sEnParity(), 49328868Sjkh sDisParity(), sSetOddParity(), and sSetEvenParity(). 49428868Sjkh*/ 49528868Sjkh#define sDisParity(ChP) \ 49628868Sjkh{ \ 49728868Sjkh (ChP)->TxControl[2] &= ~PARITY_EN; \ 498164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 49928868Sjkh} 50028868Sjkh 50128868Sjkh/*************************************************************************** 50228868SjkhFunction: sDisRxFIFO 50328868SjkhPurpose: Disable Rx FIFO 50428868SjkhCall: sDisRxFIFO(ChP) 50528868Sjkh CHANNEL_T *ChP; Ptr to channel structure 50628868Sjkh*/ 50728868Sjkh#define sDisRxFIFO(ChP) \ 50828868Sjkh{ \ 50928868Sjkh (ChP)->R[0x32] = 0x0a; \ 510164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 51128868Sjkh} 51228868Sjkh 51328868Sjkh/*************************************************************************** 51428868SjkhFunction: sDisRxStatusMode 51528868SjkhPurpose: Disable the Rx status mode 51628868SjkhCall: sDisRxStatusMode(ChP) 51728868Sjkh CHANNEL_T *ChP; Ptr to channel structure 51828868SjkhComments: This takes the channel out of the receive status mode. All 51928868Sjkh subsequent reads of receive data using sReadRxWord() will return 52028868Sjkh two data bytes. 52128868Sjkh*/ 52261541Stanimura#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0) 52328868Sjkh 52428868Sjkh/*************************************************************************** 52528868SjkhFunction: sDisTransmit 52628868SjkhPurpose: Disable transmit 52728868SjkhCall: sDisTransmit(ChP) 52828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 52928868Sjkh This disables movement of Tx data from the Tx FIFO into the 1 byte 53028868Sjkh Tx buffer. Therefore there could be up to a 2 byte latency 53128868Sjkh between the time sDisTransmit() is called and the transmit buffer 53228868Sjkh and transmit shift register going completely empty. 53328868Sjkh*/ 53428868Sjkh#define sDisTransmit(ChP) \ 53528868Sjkh{ \ 53628868Sjkh (ChP)->TxControl[3] &= ~TX_ENABLE; \ 537164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 53828868Sjkh} 53928868Sjkh 54028868Sjkh/*************************************************************************** 54128868SjkhFunction: sDisTxSoftFlowCtl 54228868SjkhPurpose: Disable Tx Software Flow Control 54328868SjkhCall: sDisTxSoftFlowCtl(ChP) 54428868Sjkh CHANNEL_T *ChP; Ptr to channel structure 54528868Sjkh*/ 54628868Sjkh#define sDisTxSoftFlowCtl(ChP) \ 54728868Sjkh{ \ 54828868Sjkh (ChP)->R[0x06] = 0x8a; \ 549164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x04)); \ 55028868Sjkh} 55128868Sjkh 55228868Sjkh/*************************************************************************** 55328868SjkhFunction: sEnCTSFlowCtl 55428868SjkhPurpose: Enable output flow control using CTS 55528868SjkhCall: sEnCTSFlowCtl(ChP) 55628868Sjkh CHANNEL_T *ChP; Ptr to channel structure 55728868Sjkh*/ 55828868Sjkh#define sEnCTSFlowCtl(ChP) \ 55928868Sjkh{ \ 56028868Sjkh (ChP)->TxControl[2] |= CTSFC_EN; \ 561164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 56228868Sjkh} 56328868Sjkh 56428868Sjkh/*************************************************************************** 56528868SjkhFunction: EnParity 56628868SjkhPurpose: Enable parity 56728868SjkhCall: sEnParity(ChP) 56828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 56928868SjkhComments: Function sSetParity() can be used in place of functions sEnParity(), 57028868Sjkh sDisParity(), sSetOddParity(), and sSetEvenParity(). 57128868Sjkh 57228868SjkhWarnings: Before enabling parity odd or even parity should be chosen using 57328868Sjkh functions sSetOddParity() or sSetEvenParity(). 57428868Sjkh*/ 57528868Sjkh#define sEnParity(ChP) \ 57628868Sjkh{ \ 57728868Sjkh (ChP)->TxControl[2] |= PARITY_EN; \ 578164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 57928868Sjkh} 58028868Sjkh 58128868Sjkh/*************************************************************************** 58228868SjkhFunction: sEnRTSFlowCtl 58328868SjkhReturn: void 58428868Sjkh*/ 58528868Sjkh#define sEnRTSFlowCtl(ChP) \ 58628868Sjkh{ \ 58728868Sjkh (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 58828868Sjkh (ChP)->TxControl[3] &= ~SET_RTS; \ 589164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 59028868Sjkh (ChP)->RxControl[2] |= RTSFC_EN; \ 591164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 59228868Sjkh} 59328868Sjkh 59428868Sjkh/*************************************************************************** 59528868SjkhFunction: sDisRTSFlowCtl 59628868SjkhReturn: void 59728868Sjkh*/ 59828868Sjkh#define sDisRTSFlowCtl(ChP) \ 59928868Sjkh{ \ 60028868Sjkh (ChP)->RxControl[2] &= ~RTSFC_EN; \ 601164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 60228868Sjkh} 60328868Sjkh 60428868Sjkh/*************************************************************************** 60528868SjkhFunction: sEnRxFIFO 60628868SjkhPurpose: Enable Rx FIFO 60728868SjkhCall: sEnRxFIFO(ChP) 60828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 60928868Sjkh*/ 61028868Sjkh#define sEnRxFIFO(ChP) \ 61128868Sjkh{ \ 61228868Sjkh (ChP)->R[0x32] = 0x08; \ 613164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \ 61428868Sjkh} 61528868Sjkh 61628868Sjkh/*************************************************************************** 61728868SjkhFunction: sEnRxProcessor 61828868SjkhPurpose: Enable the receive processor 61928868SjkhCall: sEnRxProcessor(ChP) 62028868Sjkh CHANNEL_T *ChP; Ptr to channel structure 62128868SjkhComments: This function is used to start the receive processor. When 62228868Sjkh the channel is in the reset state the receive processor is not 62328868Sjkh running. This is done to prevent the receive processor from 62428868Sjkh executing invalid microcode instructions prior to the 62528868Sjkh downloading of the microcode. 62628868Sjkh 62728868SjkhWarnings: This function must be called after valid microcode has been 62828868Sjkh downloaded to the AIOP, and it must not be called before the 62928868Sjkh microcode has been downloaded. 63028868Sjkh*/ 63128868Sjkh#define sEnRxProcessor(ChP) \ 63228868Sjkh{ \ 63328868Sjkh (ChP)->RxControl[2] |= RXPROC_EN; \ 634164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 63528868Sjkh} 63628868Sjkh 63728868Sjkh/*************************************************************************** 63828868SjkhFunction: sEnRxStatusMode 63928868SjkhPurpose: Enable the Rx status mode 64028868SjkhCall: sEnRxStatusMode(ChP) 64128868Sjkh CHANNEL_T *ChP; Ptr to channel structure 64228868SjkhComments: This places the channel in the receive status mode. All subsequent 64328868Sjkh reads of receive data using sReadRxWord() will return a data byte 64428868Sjkh in the low word and a status byte in the high word. 64528868Sjkh 64628868Sjkh*/ 64761541Stanimura#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE) 64828868Sjkh 64928868Sjkh/*************************************************************************** 65028868SjkhFunction: sEnTransmit 65128868SjkhPurpose: Enable transmit 65228868SjkhCall: sEnTransmit(ChP) 65328868Sjkh CHANNEL_T *ChP; Ptr to channel structure 65428868Sjkh*/ 65528868Sjkh#define sEnTransmit(ChP) \ 65628868Sjkh{ \ 65728868Sjkh (ChP)->TxControl[3] |= TX_ENABLE; \ 658164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 65928868Sjkh} 66028868Sjkh 66128868Sjkh/*************************************************************************** 66228868SjkhFunction: sGetAiopIntStatus 66328868SjkhPurpose: Get the AIOP interrupt status 66428868SjkhCall: sGetAiopIntStatus(CtlP,AiopNum) 66528868Sjkh CONTROLLER_T *CtlP; Ptr to controller structure 66628868Sjkh int AiopNum; AIOP number 66728868SjkhReturn: Byte_t: The AIOP interrupt status. Bits 0 through 7 66828868Sjkh represent channels 0 through 7 respectively. If a 66928868Sjkh bit is set that channel is interrupting. 67028868Sjkh*/ 67161541Stanimura#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN) 67228868Sjkh 67328868Sjkh/*************************************************************************** 67428868SjkhFunction: sGetAiopNumChan 67528868SjkhPurpose: Get the number of channels supported by an AIOP 67628868SjkhCall: sGetAiopNumChan(CtlP,AiopNum) 67728868Sjkh CONTROLLER_T *CtlP; Ptr to controller structure 67828868Sjkh int AiopNum; AIOP number 67928868SjkhReturn: int: The number of channels supported by the AIOP 68028868Sjkh*/ 68161541Stanimura#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM] 68228868Sjkh 68328868Sjkh/*************************************************************************** 68428868SjkhFunction: sGetChanIntID 68528868SjkhPurpose: Get a channel's interrupt identification byte 68628868SjkhCall: sGetChanIntID(ChP) 68728868Sjkh CHANNEL_T *ChP; Ptr to channel structure 68828868SjkhReturn: Byte_t: The channel interrupt ID. Can be any 68928868Sjkh combination of the following flags: 69028868Sjkh RXF_TRIG: Rx FIFO trigger level interrupt 69128868Sjkh TXFIFO_MT: Tx FIFO empty interrupt 69228868Sjkh SRC_INT: Special receive condition interrupt 69328868Sjkh DELTA_CD: CD change interrupt 69428868Sjkh DELTA_CTS: CTS change interrupt 69528868Sjkh DELTA_DSR: DSR change interrupt 69628868Sjkh*/ 69761541Stanimura#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 69828868Sjkh 69928868Sjkh/*************************************************************************** 70028868SjkhFunction: sGetChanNum 70128868SjkhPurpose: Get the number of a channel within an AIOP 70228868SjkhCall: sGetChanNum(ChP) 70328868Sjkh CHANNEL_T *ChP; Ptr to channel structure 70428868SjkhReturn: int: Channel number within AIOP, or NULLCHAN if channel does 70528868Sjkh not exist. 70628868Sjkh*/ 70728868Sjkh#define sGetChanNum(ChP) (ChP)->ChanNum 70828868Sjkh 70928868Sjkh/*************************************************************************** 71028868SjkhFunction: sGetChanStatus 71128868SjkhPurpose: Get the channel status 71228868SjkhCall: sGetChanStatus(ChP) 71328868Sjkh CHANNEL_T *ChP; Ptr to channel structure 71428868SjkhReturn: Word_t: The channel status. Can be any combination of 71528868Sjkh the following flags: 71628868Sjkh LOW BYTE FLAGS 71728868Sjkh CTS_ACT: CTS input asserted 71828868Sjkh DSR_ACT: DSR input asserted 71928868Sjkh CD_ACT: CD input asserted 72028868Sjkh TXFIFOMT: Tx FIFO is empty 72128868Sjkh TXSHRMT: Tx shift register is empty 72228868Sjkh RDA: Rx data available 72328868Sjkh 72428868Sjkh HIGH BYTE FLAGS 72528868Sjkh STATMODE: status mode enable bit 72628868Sjkh RXFOVERFL: receive FIFO overflow 72728868Sjkh RX2MATCH: receive compare byte 2 match 72828868Sjkh RX1MATCH: receive compare byte 1 match 72928868Sjkh RXBREAK: received BREAK 73028868Sjkh RXFRAME: received framing error 73128868Sjkh RXPARITY: received parity error 73228868SjkhWarnings: This function will clear the high byte flags in the Channel 73328868Sjkh Status Register. 73428868Sjkh*/ 73561541Stanimura#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP)) 73628868Sjkh 73728868Sjkh/*************************************************************************** 73828868SjkhFunction: sGetChanStatusLo 73928868SjkhPurpose: Get the low byte only of the channel status 74028868SjkhCall: sGetChanStatusLo(ChP) 74128868Sjkh CHANNEL_T *ChP; Ptr to channel structure 74228868SjkhReturn: Byte_t: The channel status low byte. Can be any combination 74328868Sjkh of the following flags: 74428868Sjkh CTS_ACT: CTS input asserted 74528868Sjkh DSR_ACT: DSR input asserted 74628868Sjkh CD_ACT: CD input asserted 74728868Sjkh TXFIFOMT: Tx FIFO is empty 74828868Sjkh TXSHRMT: Tx shift register is empty 74928868Sjkh RDA: Rx data available 75028868Sjkh*/ 75161541Stanimura#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP)) 75228868Sjkh 75328868Sjkh/*************************************************************************** 75428868SjkhFunction: sGetRxCnt 75528868SjkhPurpose: Get the number of data bytes in the Rx FIFO 75628868SjkhCall: sGetRxCnt(ChP) 75728868Sjkh CHANNEL_T *ChP; Ptr to channel structure 75828868SjkhReturn: int: The number of data bytes in the Rx FIFO. 75928868SjkhComments: Byte read of count register is required to obtain Rx count. 76028868Sjkh 76128868Sjkh*/ 76261541Stanimura#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP)) 76328868Sjkh 76428868Sjkh/*************************************************************************** 76528868SjkhFunction: sGetTxCnt 76628868SjkhPurpose: Get the number of data bytes in the Tx FIFO 76728868SjkhCall: sGetTxCnt(ChP) 76828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 76928868SjkhReturn: Byte_t: The number of data bytes in the Tx FIFO. 77028868SjkhComments: Byte read of count register is required to obtain Tx count. 77128868Sjkh 77228868Sjkh*/ 77361541Stanimura#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP)) 77428868Sjkh 77528868Sjkh/***************************************************************************** 77628868SjkhFunction: sGetTxRxDataIO 77761541StanimuraPurpose: Get the offset of a channel's TxRx Data register 77828868SjkhCall: sGetTxRxDataIO(ChP) 77928868Sjkh CHANNEL_T *ChP; Ptr to channel structure 78061541StanimuraReturn: WordIO_t: offset of a channel's TxRx Data register 78128868Sjkh*/ 78261541Stanimura#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP) 78328868Sjkh 78428868Sjkh/*************************************************************************** 78528868SjkhFunction: sInitChanDefaults 78635256SdesPurpose: Initialize a channel structure to its default state. 78728868SjkhCall: sInitChanDefaults(ChP) 78828868Sjkh CHANNEL_T *ChP; Ptr to the channel structure 78928868SjkhComments: This function must be called once for every channel structure 79028868Sjkh that exists before any other SSCI calls can be made. 79128868Sjkh 79228868Sjkh*/ 79328868Sjkh#define sInitChanDefaults(ChP) \ 79428868Sjkh{ \ 79528868Sjkh (ChP)->CtlP = NULLCTLPTR; \ 79628868Sjkh (ChP)->AiopNum = NULLAIOP; \ 79728868Sjkh (ChP)->ChanID = AIOPID_NULL; \ 79828868Sjkh (ChP)->ChanNum = NULLCHAN; \ 79928868Sjkh} 80028868Sjkh 80128868Sjkh/*************************************************************************** 80228868SjkhFunction: sResetAiopByNum 80328868SjkhPurpose: Reset the AIOP by number 80428868SjkhCall: sResetAiopByNum(CTLP,AIOPNUM) 80528868Sjkh CONTROLLER_T CTLP; Ptr to controller structure 80628868Sjkh AIOPNUM; AIOP index 80728868Sjkh*/ 80828868Sjkh#define sResetAiopByNum(CTLP,AIOPNUM) \ 80928868Sjkh{ \ 81061541Stanimura rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \ 81161541Stanimura rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \ 81228868Sjkh} 81328868Sjkh 81428868Sjkh/*************************************************************************** 81528868SjkhFunction: sSendBreak 81628868SjkhPurpose: Send a transmit BREAK signal 81728868SjkhCall: sSendBreak(ChP) 81828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 81928868Sjkh*/ 82028868Sjkh#define sSendBreak(ChP) \ 82128868Sjkh{ \ 82228868Sjkh (ChP)->TxControl[3] |= SETBREAK; \ 823164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 82428868Sjkh} 82528868Sjkh 82628868Sjkh/*************************************************************************** 82728868SjkhFunction: sSetBaud 82828868SjkhPurpose: Set baud rate 82928868SjkhCall: sSetBaud(ChP,Divisor) 83028868Sjkh CHANNEL_T *ChP; Ptr to channel structure 83128868Sjkh Word_t Divisor; 16 bit baud rate divisor for channel 83228868Sjkh*/ 83328868Sjkh#define sSetBaud(ChP,DIVISOR) \ 83428868Sjkh{ \ 83528868Sjkh (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 83628868Sjkh (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 837164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->BaudDiv)); \ 83828868Sjkh} 83928868Sjkh 84028868Sjkh/*************************************************************************** 84128868SjkhFunction: sSetData7 84228868SjkhPurpose: Set data bits to 7 84328868SjkhCall: sSetData7(ChP) 84428868Sjkh CHANNEL_T *ChP; Ptr to channel structure 84528868Sjkh*/ 84628868Sjkh#define sSetData7(ChP) \ 84728868Sjkh{ \ 84828868Sjkh (ChP)->TxControl[2] &= ~DATA8BIT; \ 849164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 85028868Sjkh} 85128868Sjkh 85228868Sjkh/*************************************************************************** 85328868SjkhFunction: sSetData8 85428868SjkhPurpose: Set data bits to 8 85528868SjkhCall: sSetData8(ChP) 85628868Sjkh CHANNEL_T *ChP; Ptr to channel structure 85728868Sjkh*/ 85828868Sjkh#define sSetData8(ChP) \ 85928868Sjkh{ \ 86028868Sjkh (ChP)->TxControl[2] |= DATA8BIT; \ 861164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 86228868Sjkh} 86328868Sjkh 86428868Sjkh/*************************************************************************** 86528868SjkhFunction: sSetDTR 86628868SjkhPurpose: Set the DTR output 86728868SjkhCall: sSetDTR(ChP) 86828868Sjkh CHANNEL_T *ChP; Ptr to channel structure 86928868Sjkh*/ 87028868Sjkh#define sSetDTR(ChP) \ 87128868Sjkh{ \ 87228868Sjkh (ChP)->TxControl[3] |= SET_DTR; \ 873164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 87428868Sjkh} 87528868Sjkh 87628868Sjkh/*************************************************************************** 87728868SjkhFunction: sSetEvenParity 87828868SjkhPurpose: Set even parity 87928868SjkhCall: sSetEvenParity(ChP) 88028868Sjkh CHANNEL_T *ChP; Ptr to channel structure 88128868SjkhComments: Function sSetParity() can be used in place of functions sEnParity(), 88228868Sjkh sDisParity(), sSetOddParity(), and sSetEvenParity(). 88328868Sjkh 88428868SjkhWarnings: This function has no effect unless parity is enabled with function 88528868Sjkh sEnParity(). 88628868Sjkh*/ 88728868Sjkh#define sSetEvenParity(ChP) \ 88828868Sjkh{ \ 88928868Sjkh (ChP)->TxControl[2] |= EVEN_PAR; \ 890164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 89128868Sjkh} 89228868Sjkh 89328868Sjkh/*************************************************************************** 89428868SjkhFunction: sSetOddParity 89528868SjkhPurpose: Set odd parity 89628868SjkhCall: sSetOddParity(ChP) 89728868Sjkh CHANNEL_T *ChP; Ptr to channel structure 89828868SjkhComments: Function sSetParity() can be used in place of functions sEnParity(), 89928868Sjkh sDisParity(), sSetOddParity(), and sSetEvenParity(). 90028868Sjkh 90128868SjkhWarnings: This function has no effect unless parity is enabled with function 90228868Sjkh sEnParity(). 90328868Sjkh*/ 90428868Sjkh#define sSetOddParity(ChP) \ 90528868Sjkh{ \ 90628868Sjkh (ChP)->TxControl[2] &= ~EVEN_PAR; \ 907164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 90828868Sjkh} 90928868Sjkh 91028868Sjkh/*************************************************************************** 91128868SjkhFunction: sSetRTS 91228868SjkhPurpose: Set the RTS output 91328868SjkhCall: sSetRTS(ChP) 91428868Sjkh CHANNEL_T *ChP; Ptr to channel structure 91528868Sjkh*/ 91628868Sjkh#define sSetRTS(ChP) \ 91728868Sjkh{ \ 91828868Sjkh (ChP)->TxControl[3] |= SET_RTS; \ 919164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 92028868Sjkh} 92128868Sjkh 92228868Sjkh/*************************************************************************** 92328868SjkhFunction: sSetRxTrigger 92428868SjkhPurpose: Set the Rx FIFO trigger level 92528868SjkhCall: sSetRxProcessor(ChP,Level) 92628868Sjkh CHANNEL_T *ChP; Ptr to channel structure 92728868Sjkh Byte_t Level; Number of characters in Rx FIFO at which the 92828868Sjkh interrupt will be generated. Can be any of the following flags: 92928868Sjkh 93028868Sjkh TRIG_NO: no trigger 93128868Sjkh TRIG_1: 1 character in FIFO 93228868Sjkh TRIG_1_2: FIFO 1/2 full 93328868Sjkh TRIG_7_8: FIFO 7/8 full 93428868SjkhComments: An interrupt will be generated when the trigger level is reached 93528868Sjkh only if function sEnInterrupt() has been called with flag 93628868Sjkh RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 93728868Sjkh register will be set whenever the trigger level is reached 93828868Sjkh regardless of the setting of RXINT_EN. 93928868Sjkh 94028868Sjkh*/ 94128868Sjkh#define sSetRxTrigger(ChP,LEVEL) \ 94228868Sjkh{ \ 94328868Sjkh (ChP)->RxControl[2] &= ~TRIG_MASK; \ 94428868Sjkh (ChP)->RxControl[2] |= LEVEL; \ 945164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \ 94628868Sjkh} 94728868Sjkh 94828868Sjkh/*************************************************************************** 94928868SjkhFunction: sSetStop1 95028868SjkhPurpose: Set stop bits to 1 95128868SjkhCall: sSetStop1(ChP) 95228868Sjkh CHANNEL_T *ChP; Ptr to channel structure 95328868Sjkh*/ 95428868Sjkh#define sSetStop1(ChP) \ 95528868Sjkh{ \ 95628868Sjkh (ChP)->TxControl[2] &= ~STOP2; \ 957164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 95828868Sjkh} 95928868Sjkh 96028868Sjkh/*************************************************************************** 96128868SjkhFunction: sSetStop2 96228868SjkhPurpose: Set stop bits to 2 96328868SjkhCall: sSetStop2(ChP) 96428868Sjkh CHANNEL_T *ChP; Ptr to channel structure 96528868Sjkh*/ 96628868Sjkh#define sSetStop2(ChP) \ 96728868Sjkh{ \ 96828868Sjkh (ChP)->TxControl[2] |= STOP2; \ 969164439Smarius rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \ 97028868Sjkh} 97128868Sjkh 97228868Sjkh/*************************************************************************** 97328868SjkhFunction: sStartRxProcessor 97428868SjkhPurpose: Start a channel's receive processor 97528868SjkhCall: sStartRxProcessor(ChP) 97628868Sjkh CHANNEL_T *ChP; Ptr to channel structure 97728868SjkhComments: This function is used to start a Rx processor after it was 97828868Sjkh stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 97928868Sjkh will restart both the Rx processor and software input flow control. 98028868Sjkh 98128868Sjkh*/ 982164439Smarius#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R)) 98328868Sjkh 98428868Sjkh/*************************************************************************** 98528868SjkhFunction: sWriteTxByte 98628868SjkhPurpose: Write a transmit data byte to a channel. 98761541Stanimura CHANNEL_T *ChP; Ptr to channel structure 98828868Sjkh ByteIO_t io: Channel transmit register I/O address. This can 98928868Sjkh be obtained with sGetTxRxDataIO(). 99028868Sjkh Byte_t Data; The transmit data byte. 99128868SjkhWarnings: This function writes the data byte without checking to see if 99228868Sjkh sMaxTxSize is exceeded in the Tx FIFO. 99328868Sjkh*/ 99461541Stanimura#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA) 99528868Sjkh 99661541Stanimuraint sReadAiopID(CONTROLLER_T *CtlP, int aiop); 99761541Stanimuraint sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop); 99828868Sjkhint sInitChan( CONTROLLER_T *CtlP, 99928868Sjkh CHANNEL_T *ChP, 100028868Sjkh int AiopNum, 100128868Sjkh int ChanNum); 100228868SjkhByte_t sGetRxErrStatus(CHANNEL_T *ChP); 100328868Sjkhvoid sStopRxProcessor(CHANNEL_T *ChP); 100428868Sjkhvoid sStopSWInFlowCtl(CHANNEL_T *ChP); 100528868Sjkhvoid sFlushRxFIFO(CHANNEL_T *ChP); 100628868Sjkhvoid sFlushTxFIFO(CHANNEL_T *ChP); 100728868Sjkhint sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 100828868Sjkhvoid sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 100928868Sjkhvoid sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 101061541Stanimuraint rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports); 101161541Stanimuravoid rp_releaseresource(CONTROLLER_t *ctlp); 1012191563Sambriskostatic __inline void 1013191563Sambriskorp_lock(CONTROLLER_T *CtlP) 1014191563Sambrisko{ 1015191563Sambrisko if (CtlP->hwmtx_init != 0) 1016274390Sjhb mtx_lock(&CtlP->hwmtx); 1017191563Sambrisko} 1018191563Sambriskostatic __inline void 1019191563Sambriskorp_unlock(CONTROLLER_T *CtlP) 1020191563Sambrisko{ 1021191563Sambrisko if (CtlP->hwmtx_init != 0) 1022274390Sjhb mtx_unlock(&CtlP->hwmtx); 1023191563Sambrisko} 102428868Sjkh 102528868Sjkh#ifndef ROCKET_C 102628868Sjkhextern Byte_t R[RDATASIZE]; 102728868Sjkhextern CONTROLLER_T sController[CTL_SIZE]; 102828868Sjkhextern Byte_t sIRQMap[16]; 102928868Sjkh#endif 103061541Stanimuraextern Byte_t rp_sBitMapClrTbl[8]; 103161541Stanimuraextern Byte_t rp_sBitMapSetTbl[8]; 1032