rc.c revision 9855
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/user.h> 44#include <sys/conf.h> 45#include <sys/dkstat.h> 46#include <sys/file.h> 47#include <sys/uio.h> 48#include <sys/kernel.h> 49#include <sys/syslog.h> 50#include <sys/devconf.h> 51 52#include <machine/clock.h> 53 54#include <i386/isa/isa.h> 55#include <i386/isa/isa_device.h> 56#include <i386/isa/sioreg.h> 57 58#include <i386/isa/ic/cd180.h> 59#include <i386/isa/rcreg.h> 60 61/* Prototypes */ 62int rcprobe __P((struct isa_device *)); 63int rcattach __P((struct isa_device *)); 64 65int rcopen __P((dev_t, int, int, struct proc *)); 66int rcclose __P((dev_t, int, int, struct proc *)); 67int rcread __P((dev_t, struct uio *, int)); 68int rcwrite __P((dev_t, struct uio *, int)); 69void rcintr __P((int)); 70void rcpoll __P((void)); 71void rcstop __P((struct tty *, int)); 72int rcioctl __P((dev_t, int, caddr_t, int, struct proc *)); 73 74#define rcin(port) RC_IN (nec, port) 75#define rcout(port,v) RC_OUT (nec, port, v) 76 77#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 78#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 79 80#define RC_IBUFSIZE 256 81#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 82#define RC_OBUFSIZE 512 83#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 84#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 85#define LOTS_OF_EVENTS 64 86 87#define RC_FAKEID 0x10 88 89#define RC_PROBED 1 90#define RC_ATTACHED 2 91 92#define GET_UNIT(dev) (minor(dev) & 0x3F) 93#define CALLOUT(dev) (minor(dev) & 0x80) 94 95/* For isa routines */ 96struct isa_driver rcdriver = { 97 rcprobe, rcattach, "rc" 98}; 99 100/* Per-board structure */ 101static struct rc_softc { 102 u_int rcb_probed; /* 1 - probed, 2 - attached */ 103 u_int rcb_addr; /* Base I/O addr */ 104 u_int rcb_unit; /* unit # */ 105 u_char rcb_dtr; /* DTR status */ 106 struct rc_chans *rcb_baserc; /* base rc ptr */ 107} rc_softc[NRC]; 108 109/* Per-channel structure */ 110static struct rc_chans { 111 struct rc_softc *rc_rcb; /* back ptr */ 112 u_short rc_flags; /* Misc. flags */ 113 int rc_chan; /* Channel # */ 114 u_char rc_ier; /* intr. enable reg */ 115 u_char rc_msvr; /* modem sig. status */ 116 u_char rc_cor2; /* options reg */ 117 u_char rc_pendcmd; /* special cmd pending */ 118 u_int rc_dtrwait; /* dtr timeout */ 119 u_int rc_dcdwaits; /* how many waits DCD in open */ 120 u_char rc_hotchar; /* end packed optimize */ 121 struct tty *rc_tp; /* tty struct */ 122 u_char *rc_iptr; /* Chars input buffer */ 123 u_char *rc_hiwat; /* hi-water mark */ 124 u_char *rc_bufend; /* end of buffer */ 125 u_char *rc_optr; /* ptr in output buf */ 126 u_char *rc_obufend; /* end of output buf */ 127 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 128 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 129} rc_chans[NRC * CD180_NCHAN]; 130 131static int rc_scheduled_event = 0; 132 133/* for pstat -t */ 134struct tty rc_tty[NRC * CD180_NCHAN]; 135int nrc_tty = NRC * CD180_NCHAN; 136 137/* Flags */ 138#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 139#define RC_ACTOUT 0x0002 /* Dial-out port active */ 140#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 141#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 142#define RC_DORXFER 0x0010 /* RXFER event planned */ 143#define RC_DOXXFER 0x0020 /* XXFER event planned */ 144#define RC_MODCHG 0x0040 /* Modem status changed */ 145#define RC_OSUSP 0x0080 /* Output suspended */ 146#define RC_OSBUSY 0x0100 /* start() routine in progress */ 147#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 148#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 149#define RC_SEND_RDY 0x0800 /* ready to send */ 150 151/* Table for translation of RCSR status bits to internal form */ 152static int rc_rcsrt[16] = { 153 0, TTY_OE, TTY_FE, 154 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 155 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 156 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 157 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 158 TTY_BI|TTY_PE|TTY_FE|TTY_OE 159}; 160 161/* Static prototypes */ 162static void rc_hwreset __P((int, int, unsigned int)); 163static int rc_test __P((int, int)); 164static void rc_discard_output __P((struct rc_chans *)); 165static void rc_hardclose __P((struct rc_chans *)); 166static int rc_modctl __P((struct rc_chans *, int, int)); 167static void rc_start __P((struct tty *)); 168static int rc_param __P((struct tty *, struct termios *)); 169static void rc_registerdev __P((struct isa_device *id)); 170static void rc_reinit __P((struct rc_softc *)); 171#ifdef RCDEBUG 172static void printrcflags(); 173#endif 174static timeout_t rc_dtrwakeup; 175static timeout_t rc_wakeup; 176static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 177static void rc_wait0 __P((int nec, int unit, int chan, int line)); 178 179/**********************************************/ 180 181/* Quick device probing */ 182int rcprobe(dvp) 183 struct isa_device *dvp; 184{ 185 int irq = ffs(dvp->id_irq) - 1; 186 register int nec = dvp->id_iobase; 187 188 if (dvp->id_unit > NRC) 189 return 0; 190 if (!RC_VALIDADDR(nec)) { 191 printf("rc%d: illegal base address %x\n", nec); 192 return 0; 193 } 194 if (!RC_VALIDIRQ(irq)) { 195 printf("rc%d: illegal IRQ value %d\n", irq); 196 return 0; 197 } 198 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 199 rcout(CD180_PPRH, 0x11); 200 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 201 return 0; 202 /* Now, test the board more thoroughly, with diagnostic */ 203 if (rc_test(nec, dvp->id_unit)) 204 return 0; 205 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 206 207 return 0xF; 208} 209 210static struct kern_devconf kdc_rc[NRC] = { { 211 0, 0, 0, /* filled in by dev_attach */ 212 "rc", 0, { MDDT_ISA, 0, "tty" }, 213 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 214 &kdc_isa0, /* parent */ 215 0, /* parentdata */ 216 DC_UNCONFIGURED, /* state */ 217 "RISCom/8 multiport card", 218 DC_CLS_SERIAL /* class */ 219} }; 220 221static void 222rc_registerdev(id) 223 struct isa_device *id; 224{ 225 int unit; 226 227 unit = id->id_unit; 228 if (unit != 0) 229 kdc_rc[unit] = kdc_rc[0]; 230 kdc_rc[unit].kdc_unit = unit; 231 kdc_rc[unit].kdc_isa = id; 232 kdc_rc[unit].kdc_state = DC_UNKNOWN; 233 dev_attach(&kdc_rc[unit]); 234} 235 236int rcattach(dvp) 237 struct isa_device *dvp; 238{ 239 register int i, chan, nec = dvp->id_iobase; 240 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 241 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 242 static int rc_wakeup_started = 0; 243 struct tty *tp; 244 245 /* Thorooughly test the device */ 246 if (rcb->rcb_probed != RC_PROBED) 247 return 0; 248 rcb->rcb_addr = nec; 249 rcb->rcb_dtr = 0; 250 rcb->rcb_baserc = rc; 251 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 252 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 253 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 254 255 rc_registerdev(dvp); 256 257 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 258 rc->rc_rcb = rcb; 259 rc->rc_chan = chan; 260 rc->rc_iptr = rc->rc_ibuf; 261 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 262 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 263 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 264 rc->rc_cor2 = rc->rc_pendcmd = 0; 265 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 266 rc->rc_dtrwait = 3 * hz; 267 rc->rc_dcdwaits= 0; 268 rc->rc_hotchar = 0; 269 tp = rc->rc_tp = &rc_tty[chan]; 270 ttychars(tp); 271 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 272 tp->t_cflag = TTYDEF_CFLAG; 273 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 274 } 275 rcb->rcb_probed = RC_ATTACHED; 276 if (!rc_wakeup_started) { 277 rc_wakeup((void *)NULL); 278 rc_wakeup_started = 0; 279 } 280 return 1; 281} 282 283/* RC interrupt handling */ 284void rcintr(unit) 285 int unit; 286{ 287 register struct rc_softc *rcb = &rc_softc[unit]; 288 register struct rc_chans *rc; 289 register int nec, resid; 290 register u_char val, iack, bsr, ucnt, *optr; 291 int good_data, t_state; 292 293 if (rcb->rcb_probed != RC_ATTACHED) { 294 printf("rc%d: bogus interrupt\n", unit); 295 return; 296 } 297 nec = rcb->rcb_addr; 298 299 bsr = ~(rcin(RC_BSR)); 300 301 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 302 printf("rc%d: extra interrupt\n", unit); 303 rcout(CD180_EOIR, 0); 304 return; 305 } 306 307 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 308#ifdef RCDEBUG_DETAILED 309 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 310 (bsr & RC_BSR_TOUT)?"TOUT ":"", 311 (bsr & RC_BSR_RXINT)?"RXINT ":"", 312 (bsr & RC_BSR_TXINT)?"TXINT ":"", 313 (bsr & RC_BSR_MOINT)?"MOINT":""); 314#endif 315 if (bsr & RC_BSR_TOUT) { 316 printf("rc%d: hardware failure, reset board\n", unit); 317 rcout(RC_CTOUT, 0); 318 rc_reinit(rcb); 319 return; 320 } 321 if (bsr & RC_BSR_RXINT) { 322 iack = rcin(RC_PILR_RX); 323 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 324 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 325 printf("rc%d: fake rxint: %02x\n", unit, iack); 326 goto more_intrs; 327 } 328 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 329 t_state = rc->rc_tp->t_state; 330 /* Do RTS flow control stuff */ 331 if ( (rc->rc_flags & RC_RTSFLOW) 332 || !(t_state & TS_ISOPEN) 333 ) { 334 if ( ( !(t_state & TS_ISOPEN) 335 || (t_state & TS_TBLOCK) 336 ) 337 && (rc->rc_msvr & MSVR_RTS) 338 ) 339 rcout(CD180_MSVR, 340 rc->rc_msvr &= ~MSVR_RTS); 341 else if (!(rc->rc_msvr & MSVR_RTS)) 342 rcout(CD180_MSVR, 343 rc->rc_msvr |= MSVR_RTS); 344 } 345 ucnt = rcin(CD180_RDCR) & 0xF; 346 resid = 0; 347 348 if (t_state & TS_ISOPEN) { 349 /* check for input buffer overflow */ 350 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 351 resid = ucnt; 352 ucnt = rc->rc_bufend - rc->rc_iptr; 353 resid -= ucnt; 354 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 355 rc->rc_flags |= RC_WAS_BUFOVFL; 356 rc_scheduled_event++; 357 } 358 } 359 optr = rc->rc_iptr; 360 /* check foor good data */ 361 if (good_data) { 362 while (ucnt-- > 0) { 363 val = rcin(CD180_RDR); 364 optr[0] = val; 365 optr[INPUT_FLAGS_SHIFT] = 0; 366 optr++; 367 rc_scheduled_event++; 368 if (val != 0 && val == rc->rc_hotchar) 369 setsofttty(); 370 } 371 } else { 372 /* Store also status data */ 373 while (ucnt-- > 0) { 374 iack = rcin(CD180_RCSR); 375 if (iack & RCSR_Timeout) 376 break; 377 if ( (iack & RCSR_OE) 378 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 379 rc->rc_flags |= RC_WAS_SILOVFL; 380 rc_scheduled_event++; 381 } 382 val = rcin(CD180_RDR); 383 /* 384 Don't store PE if IGNPAR and BREAK if IGNBRK, 385 this hack allows "raw" tty optimization 386 works even if IGN* is set. 387 */ 388 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 389 || (!(iack & (RCSR_PE|RCSR_FE)) 390 || !(rc->rc_tp->t_iflag & IGNPAR)) 391 && (!(iack & RCSR_Break) 392 || !(rc->rc_tp->t_iflag & IGNBRK))) { 393 if ( (iack & (RCSR_PE|RCSR_FE)) 394 && (t_state & TS_CAN_BYPASS_L_RINT) 395 && ((iack & RCSR_FE) 396 || (iack & RCSR_PE) 397 && (rc->rc_tp->t_iflag & INPCK))) 398 val = 0; 399 else if (val != 0 && val == rc->rc_hotchar) 400 setsofttty(); 401 optr[0] = val; 402 optr[INPUT_FLAGS_SHIFT] = iack; 403 optr++; 404 rc_scheduled_event++; 405 } 406 } 407 } 408 rc->rc_iptr = optr; 409 rc->rc_flags |= RC_DORXFER; 410 } else 411 resid = ucnt; 412 /* Clear FIFO if necessary */ 413 while (resid-- > 0) { 414 if (!good_data) 415 iack = rcin(CD180_RCSR); 416 else 417 iack = 0; 418 if (iack & RCSR_Timeout) 419 break; 420 (void) rcin(CD180_RDR); 421 } 422 goto more_intrs; 423 } 424 if (bsr & RC_BSR_MOINT) { 425 iack = rcin(RC_PILR_MODEM); 426 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 427 printf("rc%d: fake moint: %02x\n", unit, iack); 428 goto more_intrs; 429 } 430 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 431 iack = rcin(CD180_MCR); 432 rc->rc_msvr = rcin(CD180_MSVR); 433 rcout(CD180_MCR, 0); 434#ifdef RCDEBUG 435 printrcflags(rc, "moint"); 436#endif 437 if (rc->rc_flags & RC_CTSFLOW) { 438 if (rc->rc_msvr & MSVR_CTS) 439 rc->rc_flags |= RC_SEND_RDY; 440 else 441 rc->rc_flags &= ~RC_SEND_RDY; 442 } else 443 rc->rc_flags |= RC_SEND_RDY; 444 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 445 rc_scheduled_event += LOTS_OF_EVENTS; 446 rc->rc_flags |= RC_MODCHG; 447 setsofttty(); 448 } 449 goto more_intrs; 450 } 451 if (bsr & RC_BSR_TXINT) { 452 iack = rcin(RC_PILR_TX); 453 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 454 printf("rc%d: fake txint: %02x\n", unit, iack); 455 goto more_intrs; 456 } 457 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 458 if ( (rc->rc_flags & RC_OSUSP) 459 || !(rc->rc_flags & RC_SEND_RDY) 460 ) 461 goto more_intrs; 462 /* Handle breaks and other stuff */ 463 if (rc->rc_pendcmd) { 464 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 465 rcout(CD180_TDR, CD180_C_ESC); 466 rcout(CD180_TDR, rc->rc_pendcmd); 467 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 468 rc->rc_pendcmd = 0; 469 goto more_intrs; 470 } 471 optr = rc->rc_optr; 472 resid = rc->rc_obufend - optr; 473 if (resid > CD180_NFIFO) 474 resid = CD180_NFIFO; 475 while (resid-- > 0) 476 rcout(CD180_TDR, *optr++); 477 rc->rc_optr = optr; 478 479 /* output completed? */ 480 if (optr >= rc->rc_obufend) { 481 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 482#ifdef RCDEBUG 483 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 484#endif 485 if (!(rc->rc_flags & RC_DOXXFER)) { 486 rc_scheduled_event += LOTS_OF_EVENTS; 487 rc->rc_flags |= RC_DOXXFER; 488 setsofttty(); 489 } 490 } 491 } 492 more_intrs: 493 rcout(CD180_EOIR, 0); /* end of interrupt */ 494 rcout(RC_CTOUT, 0); 495 bsr = ~(rcin(RC_BSR)); 496 } 497} 498 499/* Feed characters to output buffer */ 500static void rc_start(tp) 501register struct tty *tp; 502{ 503 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 504 register int nec = rc->rc_rcb->rcb_addr, s; 505 506 if (rc->rc_flags & RC_OSBUSY) 507 return; 508 s = spltty(); 509 rc->rc_flags |= RC_OSBUSY; 510 disable_intr(); 511 if (tp->t_state & TS_TTSTOP) 512 rc->rc_flags |= RC_OSUSP; 513 else 514 rc->rc_flags &= ~RC_OSUSP; 515 /* Do RTS flow control stuff */ 516 if ( (rc->rc_flags & RC_RTSFLOW) 517 && (tp->t_state & TS_TBLOCK) 518 && (rc->rc_msvr & MSVR_RTS) 519 ) { 520 rcout(CD180_CAR, rc->rc_chan); 521 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 522 } else if (!(rc->rc_msvr & MSVR_RTS)) { 523 rcout(CD180_CAR, rc->rc_chan); 524 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 525 } 526 enable_intr(); 527 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 528 goto out; 529#ifdef RCDEBUG 530 printrcflags(rc, "rcstart"); 531#endif 532 ttwwakeup(tp); 533#ifdef RCDEBUG 534 printf("rcstart: outq = %d obuf = %d\n", 535 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 536#endif 537 if (tp->t_state & TS_BUSY) 538 goto out; /* output still in progress ... */ 539 540 if (tp->t_outq.c_cc > 0) { 541 u_int ocnt; 542 543 tp->t_state |= TS_BUSY; 544 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 545 disable_intr(); 546 rc->rc_optr = rc->rc_obuf; 547 rc->rc_obufend = rc->rc_optr + ocnt; 548 enable_intr(); 549 if (!(rc->rc_ier & IER_TxRdy)) { 550#ifdef RCDEBUG 551 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 552#endif 553 rcout(CD180_CAR, rc->rc_chan); 554 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 555 } 556 } 557out: 558 rc->rc_flags &= ~RC_OSBUSY; 559 (void) splx(s); 560} 561 562/* Handle delayed events. */ 563void rcpoll() 564{ 565 register struct rc_chans *rc; 566 register struct rc_softc *rcb; 567 register u_char *tptr, *eptr; 568 register int s; 569 register struct tty *tp; 570 register int chan, icnt, c, nec, unit; 571 572 if (rc_scheduled_event == 0) 573 return; 574repeat: 575 for (unit = 0; unit < NRC; unit++) { 576 rcb = &rc_softc[unit]; 577 rc = rcb->rcb_baserc; 578 nec = rc->rc_rcb->rcb_addr; 579 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 580 tp = rc->rc_tp; 581#ifdef RCDEBUG 582 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 583 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 584 printrcflags(rc, "rcevent"); 585#endif 586 if (rc->rc_flags & RC_WAS_BUFOVFL) { 587 disable_intr(); 588 rc->rc_flags &= ~RC_WAS_BUFOVFL; 589 rc_scheduled_event--; 590 enable_intr(); 591 printf("rc%d/%d: interrupt-level buffer overflow\n", 592 unit, chan); 593 } 594 if (rc->rc_flags & RC_WAS_SILOVFL) { 595 disable_intr(); 596 rc->rc_flags &= ~RC_WAS_SILOVFL; 597 rc_scheduled_event--; 598 enable_intr(); 599 printf("rc%d/%d: silo overflow\n", 600 unit, chan); 601 } 602 if (rc->rc_flags & RC_MODCHG) { 603 disable_intr(); 604 rc->rc_flags &= ~RC_MODCHG; 605 rc_scheduled_event -= LOTS_OF_EVENTS; 606 enable_intr(); 607 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 608 } 609 if (rc->rc_flags & RC_DORXFER) { 610 disable_intr(); 611 rc->rc_flags &= ~RC_DORXFER; 612 eptr = rc->rc_iptr; 613 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 614 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 615 else 616 tptr = rc->rc_ibuf; 617 icnt = eptr - tptr; 618 if (icnt > 0) { 619 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 620 rc->rc_iptr = rc->rc_ibuf; 621 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 622 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 623 } else { 624 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 625 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 626 rc->rc_hiwat = 627 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 628 } 629 if ( (rc->rc_flags & RC_RTSFLOW) 630 && (tp->t_state & TS_ISOPEN) 631 && !(tp->t_state & TS_TBLOCK) 632 && !(rc->rc_msvr & MSVR_RTS) 633 ) { 634 rcout(CD180_CAR, chan); 635 rcout(CD180_MSVR, 636 rc->rc_msvr |= MSVR_RTS); 637 } 638 rc_scheduled_event -= icnt; 639 } 640 enable_intr(); 641 642 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 643 goto done1; 644 645 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 646 && !(tp->t_state & TS_LOCAL)) { 647 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 648 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 649 && !(tp->t_state & TS_TBLOCK)) 650 ttyblock(tp); 651 tk_nin += icnt; 652 tk_rawcc += icnt; 653 tp->t_rawcc += icnt; 654 if (b_to_q(tptr, icnt, &tp->t_rawq)) 655 printf("rc%d/%d: tty-level buffer overflow\n", 656 unit, chan); 657 ttwakeup(tp); 658 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 659 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 660 tp->t_state &= ~TS_TTSTOP; 661 tp->t_lflag &= ~FLUSHO; 662 rc_start(tp); 663 } 664 } else { 665 for (; tptr < eptr; tptr++) 666 (*linesw[tp->t_line].l_rint) 667 (tptr[0] | 668 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 669 } 670done1: 671 } 672 if (rc->rc_flags & RC_DOXXFER) { 673 disable_intr(); 674 rc_scheduled_event -= LOTS_OF_EVENTS; 675 rc->rc_flags &= ~RC_DOXXFER; 676 rc->rc_tp->t_state &= ~TS_BUSY; 677 enable_intr(); 678 (*linesw[tp->t_line].l_start)(tp); 679 } 680 } 681 if (rc_scheduled_event == 0) 682 break; 683 } 684 if (rc_scheduled_event >= LOTS_OF_EVENTS) 685 goto repeat; 686} 687 688void rcstop(tp, rw) 689 register struct tty *tp; 690 int rw; 691{ 692 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 693 u_char *tptr, *eptr; 694 695#ifdef RCDEBUG 696 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 697 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 698#endif 699 if (rw & FWRITE) 700 rc_discard_output(rc); 701 disable_intr(); 702 if (rw & FREAD) { 703 rc->rc_flags &= ~RC_DORXFER; 704 eptr = rc->rc_iptr; 705 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 706 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 707 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 708 } else { 709 tptr = rc->rc_ibuf; 710 rc->rc_iptr = rc->rc_ibuf; 711 } 712 rc_scheduled_event -= eptr - tptr; 713 } 714 if (tp->t_state & TS_TTSTOP) 715 rc->rc_flags |= RC_OSUSP; 716 else 717 rc->rc_flags &= ~RC_OSUSP; 718 enable_intr(); 719} 720 721int rcopen(dev, flag, mode, p) 722 dev_t dev; 723 int flag, mode; 724 struct proc *p; 725{ 726 register struct rc_chans *rc; 727 register struct tty *tp; 728 int unit, nec, s, error = 0; 729 730 unit = GET_UNIT(dev); 731 if (unit >= NRC * CD180_NCHAN) 732 return ENXIO; 733 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 734 return ENXIO; 735 rc = &rc_chans[unit]; 736 tp = rc->rc_tp; 737 nec = rc->rc_rcb->rcb_addr; 738#ifdef RCDEBUG 739 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 740#endif 741 s = spltty(); 742 743again: 744 while (rc->rc_flags & RC_DTR_OFF) { 745 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 746 if (error != 0) 747 goto out; 748 } 749 if (tp->t_state & TS_ISOPEN) { 750 if (CALLOUT(dev)) { 751 if (!(rc->rc_flags & RC_ACTOUT)) { 752 error = EBUSY; 753 goto out; 754 } 755 } else { 756 if (rc->rc_flags & RC_ACTOUT) { 757 if (flag & O_NONBLOCK) { 758 error = EBUSY; 759 goto out; 760 } 761 if (error = tsleep(&rc->rc_rcb, 762 TTIPRI|PCATCH, "rcbi", 0)) 763 goto out; 764 goto again; 765 } 766 } 767 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 768 error = EBUSY; 769 goto out; 770 } 771 } else { 772 tp->t_oproc = rc_start; 773 tp->t_param = rc_param; 774 tp->t_dev = dev; 775 776 if (CALLOUT(dev)) 777 tp->t_cflag |= CLOCAL; 778 else 779 tp->t_cflag &= ~CLOCAL; 780 781 error = rc_param(tp, &tp->t_termios); 782 if (error) 783 goto out; 784 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 785 786 ttsetwater(tp); 787 788 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 789 (*linesw[tp->t_line].l_modem)(tp, 1); 790 } 791 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 792 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 793 rc->rc_dcdwaits++; 794 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 795 rc->rc_dcdwaits--; 796 if (error != 0) 797 goto out; 798 goto again; 799 } 800 error = (*linesw[tp->t_line].l_open)(dev, tp); 801 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 802 rc->rc_flags |= RC_ACTOUT; 803out: 804 (void) splx(s); 805 806 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 807 rc_hardclose(rc); 808 809 return error; 810} 811 812int rcclose(dev, flag, mode, p) 813 dev_t dev; 814 int flag, mode; 815 struct proc *p; 816{ 817 register struct rc_chans *rc; 818 register struct tty *tp; 819 int s, unit = GET_UNIT(dev); 820 821 if (unit >= NRC * CD180_NCHAN) 822 return ENXIO; 823 rc = &rc_chans[unit]; 824 tp = rc->rc_tp; 825#ifdef RCDEBUG 826 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 827#endif 828 s = spltty(); 829 (*linesw[tp->t_line].l_close)(tp, flag); 830 rcstop(tp, FREAD | FWRITE); 831 rc_hardclose(rc); 832 ttyclose(tp); 833 splx(s); 834 return 0; 835} 836 837static void rc_hardclose(rc) 838register struct rc_chans *rc; 839{ 840 register int s, nec = rc->rc_rcb->rcb_addr; 841 register struct tty *tp = rc->rc_tp; 842 843 s = spltty(); 844 rcout(CD180_CAR, rc->rc_chan); 845 846 /* Disable rx/tx intrs */ 847 rcout(CD180_IER, rc->rc_ier = 0); 848 if ( (tp->t_cflag & HUPCL) 849 || !(rc->rc_flags & RC_ACTOUT) 850 && !(rc->rc_msvr & MSVR_CD) 851 && !(tp->t_cflag & CLOCAL) 852 || !(tp->t_state & TS_ISOPEN) 853 ) { 854 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 855 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 856 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 857 if (rc->rc_dtrwait) { 858 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 859 rc->rc_flags |= RC_DTR_OFF; 860 } 861 } 862 rc->rc_flags &= ~RC_ACTOUT; 863 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 864 wakeup(TSA_CARR_ON(tp)); 865 (void) splx(s); 866} 867 868/* Read from line */ 869int rcread(dev, uio, flag) 870 dev_t dev; 871 struct uio *uio; 872 int flag; 873{ 874 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 875 876 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 877} 878 879/* Write to line */ 880int rcwrite(dev, uio, flag) 881 dev_t dev; 882 struct uio *uio; 883 int flag; 884{ 885 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 886 887 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 888} 889 890/* Reset the bastard */ 891static void rc_hwreset(unit, nec, chipid) 892 register int unit, nec; 893 unsigned int chipid; 894{ 895 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 896 DELAY(20000); 897 WAITFORCCR(unit, -1); 898 899 rcout(RC_CTOUT, 0); /* Clear timeout */ 900 rcout(CD180_GIVR, chipid); 901 rcout(CD180_GICR, 0); 902 903 /* Set Prescaler Registers (1 msec) */ 904 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 905 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 906 907 /* Initialize Priority Interrupt Level Registers */ 908 rcout(CD180_PILR1, RC_PILR_MODEM); 909 rcout(CD180_PILR2, RC_PILR_TX); 910 rcout(CD180_PILR3, RC_PILR_RX); 911 912 /* Reset DTR */ 913 rcout(RC_DTREG, ~0); 914} 915 916/* Set channel parameters */ 917static int rc_param(tp, ts) 918 register struct tty *tp; 919 struct termios *ts; 920{ 921 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 922 register int nec = rc->rc_rcb->rcb_addr; 923 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 924 925 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 926 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 927 ) 928 return (EINVAL); 929 if (ts->c_ispeed == 0) 930 ts->c_ispeed = ts->c_ospeed; 931 odivs = RC_BRD(ts->c_ospeed); 932 idivs = RC_BRD(ts->c_ispeed); 933 934 s = spltty(); 935 936 /* Select channel */ 937 rcout(CD180_CAR, rc->rc_chan); 938 939 /* If speed == 0, hangup line */ 940 if (ts->c_ospeed == 0) { 941 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 942 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 943 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 944 } 945 946 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 947 cflag = ts->c_cflag; 948 iflag = ts->c_iflag; 949 lflag = ts->c_lflag; 950 951 if (idivs > 0) { 952 rcout(CD180_RBPRL, idivs & 0xFF); 953 rcout(CD180_RBPRH, idivs >> 8); 954 } 955 if (odivs > 0) { 956 rcout(CD180_TBPRL, odivs & 0xFF); 957 rcout(CD180_TBPRH, odivs >> 8); 958 } 959 960 /* set timeout value */ 961 if (ts->c_ispeed > 0) { 962 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 963 964 if ( !(lflag & ICANON) 965 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 966 && ts->c_cc[VTIME] * 10 > itm) 967 itm = ts->c_cc[VTIME] * 10; 968 969 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 970 } 971 972 switch (cflag & CSIZE) { 973 case CS5: val = COR1_5BITS; break; 974 case CS6: val = COR1_6BITS; break; 975 case CS7: val = COR1_7BITS; break; 976 default: 977 case CS8: val = COR1_8BITS; break; 978 } 979 if (cflag & PARENB) { 980 val |= COR1_NORMPAR; 981 if (cflag & PARODD) 982 val |= COR1_ODDP; 983 if (!(cflag & INPCK)) 984 val |= COR1_Ignore; 985 } else 986 val |= COR1_Ignore; 987 if (cflag & CSTOPB) 988 val |= COR1_2SB; 989 rcout(CD180_COR1, val); 990 991 /* Set FIFO threshold */ 992 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 993 inpflow = 0; 994 if ( (iflag & IXOFF) 995 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 996 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 997 || (iflag & IXANY) 998 ) 999 ) 1000 ) { 1001 inpflow = 1; 1002 val |= COR3_SCDE|COR3_FCT; 1003 } 1004 rcout(CD180_COR3, val); 1005 1006 /* Initialize on-chip automatic flow control */ 1007 val = 0; 1008 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1009 if (cflag & CCTS_OFLOW) { 1010 rc->rc_flags |= RC_CTSFLOW; 1011 val |= COR2_CtsAE; 1012 } else 1013 rc->rc_flags |= RC_SEND_RDY; 1014 if (tp->t_state & TS_TTSTOP) 1015 rc->rc_flags |= RC_OSUSP; 1016 else 1017 rc->rc_flags &= ~RC_OSUSP; 1018 if (cflag & CRTS_IFLOW) 1019 rc->rc_flags |= RC_RTSFLOW; 1020 else 1021 rc->rc_flags &= ~RC_RTSFLOW; 1022 1023 if (inpflow) { 1024 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1025 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1026 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1027 val |= COR2_TxIBE; 1028 if (iflag & IXANY) 1029 val |= COR2_IXM; 1030 } 1031 1032 rcout(CD180_COR2, rc->rc_cor2 = val); 1033 1034 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1035 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1036 1037 disc_optim(tp, ts, rc); 1038 1039 /* modem ctl */ 1040 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1041 if (cflag & CCTS_OFLOW) 1042 val |= MCOR1_CTSzd; 1043 rcout(CD180_MCOR1, val); 1044 1045 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1046 if (cflag & CCTS_OFLOW) 1047 val |= MCOR2_CTSod; 1048 rcout(CD180_MCOR2, val); 1049 1050 /* enable i/o and interrupts */ 1051 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1052 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1053 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1054 1055 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1056 if (cflag & CCTS_OFLOW) 1057 rc->rc_ier |= IER_CTS; 1058 if (cflag & CREAD) 1059 rc->rc_ier |= IER_RxData; 1060 if (tp->t_state & TS_BUSY) 1061 rc->rc_ier |= IER_TxRdy; 1062 if (ts->c_ospeed != 0) 1063 rc_modctl(rc, TIOCM_DTR, DMBIS); 1064 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1065 rc->rc_flags |= RC_SEND_RDY; 1066 rcout(CD180_IER, rc->rc_ier); 1067 (void) splx(s); 1068 return 0; 1069} 1070 1071/* Re-initialize board after bogus interrupts */ 1072static void rc_reinit(rcb) 1073struct rc_softc *rcb; 1074{ 1075 register struct rc_chans *rc, *rce; 1076 register int i, nec; 1077 1078 nec = rcb->rcb_addr; 1079 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1080 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1081 rce = rc + CD180_NCHAN; 1082 for (; rc < rce; rc++) 1083 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1084} 1085 1086int rcioctl(dev, cmd, data, flag, p) 1087dev_t dev; 1088int cmd, flag; 1089caddr_t data; 1090struct proc *p; 1091{ 1092 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1093 register int s, error; 1094 struct tty *tp = rc->rc_tp; 1095 1096 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1097 if (error >= 0) 1098 return (error); 1099 error = ttioctl(tp, cmd, data, flag); 1100 if (error >= 0) 1101 return (error); 1102 s = spltty(); 1103 1104 switch (cmd) { 1105 case TIOCSBRK: 1106 rc->rc_pendcmd = CD180_C_SBRK; 1107 break; 1108 1109 case TIOCCBRK: 1110 rc->rc_pendcmd = CD180_C_EBRK; 1111 break; 1112 1113 case TIOCSDTR: 1114 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1115 break; 1116 1117 case TIOCCDTR: 1118 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1119 break; 1120 1121 case TIOCMGET: 1122 *(int *) data = rc_modctl(rc, 0, DMGET); 1123 break; 1124 1125 case TIOCMSET: 1126 (void) rc_modctl(rc, *(int *) data, DMSET); 1127 break; 1128 1129 case TIOCMBIC: 1130 (void) rc_modctl(rc, *(int *) data, DMBIC); 1131 break; 1132 1133 case TIOCMBIS: 1134 (void) rc_modctl(rc, *(int *) data, DMBIS); 1135 break; 1136 1137 case TIOCMSDTRWAIT: 1138 error = suser(p->p_ucred, &p->p_acflag); 1139 if (error != 0) { 1140 splx(s); 1141 return (error); 1142 } 1143 rc->rc_dtrwait = *(int *)data * hz / 100; 1144 break; 1145 1146 case TIOCMGDTRWAIT: 1147 *(int *)data = rc->rc_dtrwait * 100 / hz; 1148 break; 1149 1150 default: 1151 (void) splx(s); 1152 return ENOTTY; 1153 } 1154 (void) splx(s); 1155 return 0; 1156} 1157 1158 1159/* Modem control routines */ 1160 1161static int rc_modctl(rc, bits, cmd) 1162register struct rc_chans *rc; 1163int bits, cmd; 1164{ 1165 register int nec = rc->rc_rcb->rcb_addr; 1166 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1167 1168 rcout(CD180_CAR, rc->rc_chan); 1169 1170 switch (cmd) { 1171 case DMSET: 1172 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1173 ~(*dtr |= 1 << rc->rc_chan) : 1174 ~(*dtr &= ~(1 << rc->rc_chan))); 1175 msvr = rcin(CD180_MSVR); 1176 if (bits & TIOCM_RTS) 1177 msvr |= MSVR_RTS; 1178 else 1179 msvr &= ~MSVR_RTS; 1180 if (bits & TIOCM_DTR) 1181 msvr |= MSVR_DTR; 1182 else 1183 msvr &= ~MSVR_DTR; 1184 rcout(CD180_MSVR, msvr); 1185 break; 1186 1187 case DMBIS: 1188 if (bits & TIOCM_DTR) 1189 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1190 msvr = rcin(CD180_MSVR); 1191 if (bits & TIOCM_RTS) 1192 msvr |= MSVR_RTS; 1193 if (bits & TIOCM_DTR) 1194 msvr |= MSVR_DTR; 1195 rcout(CD180_MSVR, msvr); 1196 break; 1197 1198 case DMGET: 1199 bits = TIOCM_LE; 1200 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1201 1202 if (msvr & MSVR_RTS) 1203 bits |= TIOCM_RTS; 1204 if (msvr & MSVR_CTS) 1205 bits |= TIOCM_CTS; 1206 if (msvr & MSVR_DSR) 1207 bits |= TIOCM_DSR; 1208 if (msvr & MSVR_DTR) 1209 bits |= TIOCM_DTR; 1210 if (msvr & MSVR_CD) 1211 bits |= TIOCM_CD; 1212 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1213 bits |= TIOCM_RI; 1214 return bits; 1215 1216 case DMBIC: 1217 if (bits & TIOCM_DTR) 1218 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1219 msvr = rcin(CD180_MSVR); 1220 if (bits & TIOCM_RTS) 1221 msvr &= ~MSVR_RTS; 1222 if (bits & TIOCM_DTR) 1223 msvr &= ~MSVR_DTR; 1224 rcout(CD180_MSVR, msvr); 1225 break; 1226 } 1227 rc->rc_msvr = rcin(CD180_MSVR); 1228 return 0; 1229} 1230 1231/* Test the board. */ 1232int rc_test(nec, unit) 1233 register int nec; 1234 int unit; 1235{ 1236 int chan = 0, nopt = 0; 1237 int i = 0, rcnt, old_level; 1238 unsigned int iack, chipid; 1239 unsigned short divs; 1240 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1241#define CTLEN 8 1242#define ERR(s) { \ 1243 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1244 (void) splx(old_level); return 1; } 1245 1246 struct rtest { 1247 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1248 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1249 int rxptr; /* RX pointer */ 1250 int txptr; /* TX pointer */ 1251 } tchans[CD180_NCHAN]; 1252 1253 old_level = spltty(); 1254 1255 chipid = RC_FAKEID; 1256 1257 /* First, reset board to inital state */ 1258 rc_hwreset(unit, nec, chipid); 1259 1260 divs = RC_BRD(19200); 1261 1262 /* Initialize channels */ 1263 for (chan = 0; chan < CD180_NCHAN; chan++) { 1264 1265 /* Select and reset channel */ 1266 rcout(CD180_CAR, chan); 1267 CCRCMD(unit, chan, CCR_ResetChan); 1268 WAITFORCCR(unit, chan); 1269 1270 /* Set speed */ 1271 rcout(CD180_RBPRL, divs & 0xFF); 1272 rcout(CD180_RBPRH, divs >> 8); 1273 rcout(CD180_TBPRL, divs & 0xFF); 1274 rcout(CD180_TBPRH, divs >> 8); 1275 1276 /* set timeout value */ 1277 rcout(CD180_RTPR, 0); 1278 1279 /* Establish local loopback */ 1280 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1281 rcout(CD180_COR2, COR2_LLM); 1282 rcout(CD180_COR3, CD180_NFIFO); 1283 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1284 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1285 WAITFORCCR(unit, chan); 1286 rcout(CD180_MSVR, MSVR_RTS); 1287 1288 /* Fill TXBUF with test data */ 1289 for (i = 0; i < CD180_NFIFO; i++) { 1290 tchans[chan].txbuf[i] = ctest[i]; 1291 tchans[chan].rxbuf[i] = 0; 1292 } 1293 tchans[chan].txptr = tchans[chan].rxptr = 0; 1294 1295 /* Now, start transmit */ 1296 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1297 } 1298 /* Pseudo-interrupt poll stuff */ 1299 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1300 i = ~(rcin(RC_BSR)); 1301 if (i & RC_BSR_TOUT) 1302 ERR(("BSR timeout bit set\n")) 1303 else if (i & RC_BSR_TXINT) { 1304 iack = rcin(RC_PILR_TX); 1305 if (iack != (GIVR_IT_TDI | chipid)) 1306 ERR(("Bad TX intr ack (%02x != %02x)\n", 1307 iack, GIVR_IT_TDI | chipid)); 1308 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1309 /* If no more data to transmit, disable TX intr */ 1310 if (tchans[chan].txptr >= CD180_NFIFO) { 1311 iack = rcin(CD180_IER); 1312 rcout(CD180_IER, iack & ~IER_TxMpty); 1313 } else { 1314 for (iack = tchans[chan].txptr; 1315 iack < CD180_NFIFO; iack++) 1316 rcout(CD180_TDR, 1317 tchans[chan].txbuf[iack]); 1318 tchans[chan].txptr = iack; 1319 } 1320 rcout(CD180_EOIR, 0); 1321 } else if (i & RC_BSR_RXINT) { 1322 u_char ucnt; 1323 1324 iack = rcin(RC_PILR_RX); 1325 if (iack != (GIVR_IT_RGDI | chipid) && 1326 iack != (GIVR_IT_REI | chipid)) 1327 ERR(("Bad RX intr ack (%02x != %02x)\n", 1328 iack, GIVR_IT_RGDI | chipid)) 1329 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1330 ucnt = rcin(CD180_RDCR) & 0xF; 1331 while (ucnt-- > 0) { 1332 iack = rcin(CD180_RCSR); 1333 if (iack & RCSR_Timeout) 1334 break; 1335 if (iack & 0xF) 1336 ERR(("Bad char chan %d (RCSR = %02X)\n", 1337 chan, iack)) 1338 if (tchans[chan].rxptr > CD180_NFIFO) 1339 ERR(("Got extra chars chan %d\n", 1340 chan)) 1341 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1342 rcin(CD180_RDR); 1343 } 1344 rcout(CD180_EOIR, 0); 1345 } 1346 rcout(RC_CTOUT, 0); 1347 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1348 if (tchans[chan].rxptr >= CD180_NFIFO) 1349 iack++; 1350 if (iack == CD180_NCHAN) 1351 break; 1352 } 1353 for (chan = 0; chan < CD180_NCHAN; chan++) { 1354 /* Select and reset channel */ 1355 rcout(CD180_CAR, chan); 1356 CCRCMD(unit, chan, CCR_ResetChan); 1357 } 1358 1359 if (!rcnt) 1360 ERR(("looses characters during local loopback\n")) 1361 /* Now, check data */ 1362 for (chan = 0; chan < CD180_NCHAN; chan++) 1363 for (i = 0; i < CD180_NFIFO; i++) 1364 if (ctest[i] != tchans[chan].rxbuf[i]) 1365 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1366 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1367 (void) splx(old_level); 1368 return 0; 1369} 1370 1371#ifdef RCDEBUG 1372static void printrcflags(rc, comment) 1373struct rc_chans *rc; 1374char *comment; 1375{ 1376 u_short f = rc->rc_flags; 1377 register int nec = rc->rc_rcb->rcb_addr; 1378 1379 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1380 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1381 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1382 (f & RC_ACTOUT) ?"ACTOUT " :"", 1383 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1384 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1385 (f & RC_DORXFER)?"DORXFER " :"", 1386 (f & RC_DOXXFER)?"DOXXFER " :"", 1387 (f & RC_MODCHG) ?"MODCHG " :"", 1388 (f & RC_OSUSP) ?"OSUSP " :"", 1389 (f & RC_OSBUSY) ?"OSBUSY " :"", 1390 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1391 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1392 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1393 1394 rcout(CD180_CAR, rc->rc_chan); 1395 1396 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1397 rc->rc_rcb->rcb_unit, rc->rc_chan, 1398 rcin(CD180_MSVR), 1399 rcin(CD180_IER), 1400 rcin(CD180_CCSR)); 1401} 1402#endif /* RCDEBUG */ 1403 1404struct tty * 1405rcdevtotty(dev) 1406 dev_t dev; 1407{ 1408 int unit; 1409 1410 unit = GET_UNIT(dev); 1411 if (unit >= NRC * CD180_NCHAN) 1412 return NULL; 1413 return (&rc_tty[unit]); 1414} 1415 1416static void 1417rc_dtrwakeup(chan) 1418 void *chan; 1419{ 1420 struct rc_chans *rc; 1421 1422 rc = (struct rc_chans *)chan; 1423 rc->rc_flags &= ~RC_DTR_OFF; 1424 wakeup(&rc->rc_dtrwait); 1425} 1426 1427static void 1428rc_discard_output(rc) 1429 struct rc_chans *rc; 1430{ 1431 disable_intr(); 1432 if (rc->rc_flags & RC_DOXXFER) { 1433 rc_scheduled_event -= LOTS_OF_EVENTS; 1434 rc->rc_flags &= ~RC_DOXXFER; 1435 } 1436 rc->rc_optr = rc->rc_obufend; 1437 rc->rc_tp->t_state &= ~TS_BUSY; 1438 enable_intr(); 1439 ttwwakeup(rc->rc_tp); 1440} 1441 1442static void 1443rc_wakeup(chan) 1444 void *chan; 1445{ 1446 int unit; 1447 1448 timeout(rc_wakeup, (caddr_t)NULL, 1); 1449 1450 if (rc_scheduled_event != 0) { 1451 int s; 1452 1453 s = splsofttty(); 1454 rcpoll(); 1455 splx(s); 1456 } 1457} 1458 1459static void 1460disc_optim(tp, t, rc) 1461 struct tty *tp; 1462 struct termios *t; 1463 struct rc_chans *rc; 1464{ 1465 1466 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1467 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1468 && (!(t->c_iflag & PARMRK) 1469 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1470 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1471 && linesw[tp->t_line].l_rint == ttyinput) 1472 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1473 else 1474 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1475 if (tp->t_line == SLIPDISC) 1476 rc->rc_hotchar = 0xc0; 1477 else if (tp->t_line == PPPDISC) 1478 rc->rc_hotchar = 0x7e; 1479 else 1480 rc->rc_hotchar = 0; 1481} 1482 1483static void 1484rc_wait0(nec, unit, chan, line) 1485 int nec, unit, chan, line; 1486{ 1487 int rcnt; 1488 1489 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 1490 DELAY(15); 1491 if (rcnt == 0) 1492 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1493 unit, chan, line); 1494} 1495#endif /* NRC */ 1496