rc.c revision 9757
17332Sjkh/* 27332Sjkh * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 37332Sjkh * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 47332Sjkh * All rights reserved. 57332Sjkh * 67332Sjkh * Redistribution and use in source and binary forms, with or without 77332Sjkh * modification, are permitted provided that the following conditions 87332Sjkh * are met: 97332Sjkh * 1. Redistributions of source code must retain the above copyright 107332Sjkh * notice, this list of conditions and the following disclaimer. 117332Sjkh * 2. Redistributions in binary form must reproduce the above copyright 127332Sjkh * notice, this list of conditions and the following disclaimer in the 137332Sjkh * documentation and/or other materials provided with the distribution. 147332Sjkh * 157332Sjkh * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 167332Sjkh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 177332Sjkh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 187332Sjkh * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 197332Sjkh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 207332Sjkh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 217332Sjkh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 227332Sjkh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 237332Sjkh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 247332Sjkh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 257332Sjkh * SUCH DAMAGE. 267332Sjkh */ 277332Sjkh 287332Sjkh/* 297332Sjkh * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 307332Sjkh * 317332Sjkh */ 327332Sjkh 337332Sjkh#include "rc.h" 347332Sjkh#if NRC > 0 357332Sjkh 367332Sjkh/*#define RCDEBUG*/ 377332Sjkh 387332Sjkh#include <sys/param.h> 397332Sjkh#include <sys/systm.h> 407332Sjkh#include <sys/ioctl.h> 417332Sjkh#include <sys/tty.h> 427332Sjkh#include <sys/proc.h> 437332Sjkh#include <sys/user.h> 4415574Sphk#include <sys/conf.h> 457332Sjkh#include <sys/dkstat.h> 467332Sjkh#include <sys/file.h> 477332Sjkh#include <sys/uio.h> 487332Sjkh#include <sys/kernel.h> 497332Sjkh#include <sys/syslog.h> 507332Sjkh#include <sys/devconf.h> 517332Sjkh 527332Sjkh#include <machine/clock.h> 537332Sjkh 547332Sjkh#include <i386/isa/isa.h> 557332Sjkh#include <i386/isa/isa_device.h> 567332Sjkh#include <i386/isa/sioreg.h> 577332Sjkh 587369Sbde#include <i386/isa/ic/cd180.h> 597332Sjkh#include <i386/isa/rcreg.h> 607332Sjkh 617332Sjkh/* Prototypes */ 627332Sjkhint rcprobe __P((struct isa_device *)); 637332Sjkhint rcattach __P((struct isa_device *)); 647332Sjkh 657332Sjkhint rcopen __P((dev_t, int, int, struct proc *)); 667332Sjkhint rcclose __P((dev_t, int, int, struct proc *)); 6712675Sjulianint rcread __P((dev_t, struct uio *, int)); 6812675Sjulianint rcwrite __P((dev_t, struct uio *, int)); 6912675Sjulianvoid rcintr __P((int)); 7012675Sjulianvoid rcpoll __P((void)); 717369Sbdevoid rcstop __P((struct tty *, int)); 727369Sbdeint rcioctl __P((dev_t, int, caddr_t, int, struct proc *)); 737332Sjkh 747332Sjkh#define rcin(port) RC_IN (nec, port) 757332Sjkh#define rcout(port,v) RC_OUT (nec, port, v) 767332Sjkh 777369Sbde#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 787332Sjkh#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 7912502Sjulian 807332Sjkh#define RC_IBUFSIZE 256 817332Sjkh#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 827332Sjkh#define RC_OBUFSIZE 512 837332Sjkh#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 847332Sjkh#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 857332Sjkh#define LOTS_OF_EVENTS 64 867332Sjkh 877332Sjkh#define RC_FAKEID 0x10 887332Sjkh 897332Sjkh#define RC_PROBED 1 907332Sjkh#define RC_ATTACHED 2 917332Sjkh 927332Sjkh#define GET_UNIT(dev) (minor(dev) & 0x3F) 937332Sjkh#define CALLOUT(dev) (minor(dev) & 0x80) 947332Sjkh 957332Sjkh/* For isa routines */ 967332Sjkhstruct isa_driver rcdriver = { 977332Sjkh rcprobe, rcattach, "rc" 987332Sjkh}; 997332Sjkh 1007332Sjkh/* Per-board structure */ 1017332Sjkhstatic struct rc_softc { 1027332Sjkh u_int rcb_probed; /* 1 - probed, 2 - attached */ 1037332Sjkh u_int rcb_addr; /* Base I/O addr */ 1047332Sjkh u_int rcb_unit; /* unit # */ 1057332Sjkh u_char rcb_dtr; /* DTR status */ 1067332Sjkh struct rc_chans *rcb_baserc; /* base rc ptr */ 1077332Sjkh} rc_softc[NRC]; 10811872Sphk 1097332Sjkh/* Per-channel structure */ 1107332Sjkhstatic struct rc_chans { 1117332Sjkh struct rc_softc *rc_rcb; /* back ptr */ 1127332Sjkh u_short rc_flags; /* Misc. flags */ 1137332Sjkh int rc_chan; /* Channel # */ 1147332Sjkh u_char rc_ier; /* intr. enable reg */ 1157332Sjkh u_char rc_msvr; /* modem sig. status */ 1167332Sjkh u_char rc_cor2; /* options reg */ 1177332Sjkh u_char rc_pendcmd; /* special cmd pending */ 1187332Sjkh u_int rc_dtrwait; /* dtr timeout */ 1197332Sjkh u_int rc_dcdwaits; /* how many waits DCD in open */ 1207332Sjkh u_char rc_hotchar; /* end packed optimize */ 1217332Sjkh struct tty *rc_tp; /* tty struct */ 1227332Sjkh u_char *rc_iptr; /* Chars input buffer */ 1237332Sjkh u_char *rc_hiwat; /* hi-water mark */ 1247332Sjkh u_char *rc_bufend; /* end of buffer */ 1257332Sjkh u_char *rc_optr; /* ptr in output buf */ 12611872Sphk u_char *rc_obufend; /* end of output buf */ 1277332Sjkh u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1287332Sjkh u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 1297332Sjkh} rc_chans[NRC * CD180_NCHAN]; 1307332Sjkh 1317332Sjkhstatic int rc_scheduled_event = 0; 1327332Sjkh 1337332Sjkh/* for pstat -t */ 1347332Sjkhstruct tty rc_tty[NRC * CD180_NCHAN]; 1357332Sjkhint nrc_tty = NRC * CD180_NCHAN; 1367332Sjkh 1377332Sjkh/* Flags */ 1387332Sjkh#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 1397332Sjkh#define RC_ACTOUT 0x0002 /* Dial-out port active */ 1407332Sjkh#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 1417332Sjkh#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 1427332Sjkh#define RC_DORXFER 0x0010 /* RXFER event planned */ 1438876Srgrimes#define RC_DOXXFER 0x0020 /* XXFER event planned */ 1447332Sjkh#define RC_MODCHG 0x0040 /* Modem status changed */ 14515574Sphk#define RC_OSUSP 0x0080 /* Output suspended */ 1467332Sjkh#define RC_OSBUSY 0x0100 /* start() routine in progress */ 14712675Sjulian#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 14812675Sjulian#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 14912675Sjulian#define RC_SEND_RDY 0x0800 /* ready to send */ 15012675Sjulian 15112675Sjulianstatic struct speedtab rc_speedtab[] = { 15212675Sjulian 0, 0, 1537332Sjkh 50, RC_BRD(50), 1547332Sjkh 75, RC_BRD(75), 1557332Sjkh 110, RC_BRD(110), 1567332Sjkh 134, RC_BRD(134), 1577332Sjkh 150, RC_BRD(150), 1587332Sjkh 200, RC_BRD(200), 1597332Sjkh 300, RC_BRD(300), 1607332Sjkh 600, RC_BRD(600), 1617332Sjkh 1200, RC_BRD(1200), 1627332Sjkh 1800, RC_BRD(1800), 1637332Sjkh 2400, RC_BRD(2400), 1647332Sjkh 4800, RC_BRD(4800), 1657332Sjkh 9600, RC_BRD(9600), 1667332Sjkh 19200, RC_BRD(19200), 1677332Sjkh 38400, RC_BRD(38400), 1687332Sjkh 57600, RC_BRD(57600), 1697332Sjkh /* real max value is 76800 with 9.8304 MHz clock */ 1707332Sjkh -1, -1 1717332Sjkh}; 1727332Sjkh 1737332Sjkh/* Table for translation of RCSR status bits to internal form */ 1747332Sjkhstatic int rc_rcsrt[16] = { 1757332Sjkh 0, TTY_OE, TTY_FE, 1767332Sjkh TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1777332Sjkh TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1787332Sjkh TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1797332Sjkh TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1807332Sjkh TTY_BI|TTY_PE|TTY_FE|TTY_OE 1817332Sjkh}; 1827332Sjkh 1837332Sjkh/* Static prototypes */ 1847332Sjkhstatic void rc_hwreset __P((int, int, unsigned int)); 1857332Sjkhstatic int rc_test __P((int, int)); 1867332Sjkhstatic void rc_discard_output __P((struct rc_chans *)); 18711872Sphkstatic void rc_hardclose __P((struct rc_chans *)); 18811872Sphkstatic int rc_modctl __P((struct rc_chans *, int, int)); 1897332Sjkhstatic void rc_start __P((struct tty *)); 1907332Sjkhstatic int rc_param __P((struct tty *, struct termios *)); 19112675Sjulianstatic void rc_registerdev __P((struct isa_device *id)); 19212675Sjulianstatic void rc_reinit __P((struct rc_softc *)); 19312675Sjulian#ifdef RCDEBUG 19412675Sjulianstatic void printrcflags(); 19512675Sjulian#endif 19612675Sjulianstatic timeout_t rc_dtrwakeup; 19712675Sjulianstatic timeout_t rc_wakeup; 19812675Sjulianstatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 19912678Sphkstatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 20012675Sjulian 20112740Sbde/**********************************************/ 20212675Sjulian 20312678Sphk/* Quick device probing */ 20412675Sjulianint rcprobe(dvp) 20512675Sjulian struct isa_device *dvp; 20612675Sjulian{ 20712675Sjulian int irq = ffs(dvp->id_irq) - 1; 20812675Sjulian register int nec = dvp->id_iobase; 20912675Sjulian 2107332Sjkh if (dvp->id_unit > NRC) 2117332Sjkh return 0; 2127332Sjkh if (!RC_VALIDADDR(nec)) { 2137332Sjkh printf("rc%d: illegal base address %x\n", nec); 2147332Sjkh return 0; 2157332Sjkh } 2167780Swollman if (!RC_VALIDIRQ(irq)) { 2177780Swollman printf("rc%d: illegal IRQ value %d\n", irq); 2187780Swollman return 0; 2197332Sjkh } 2207332Sjkh rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2217332Sjkh rcout(CD180_PPRH, 0x11); 2227332Sjkh if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2237332Sjkh return 0; 2247332Sjkh /* Now, test the board more thoroughly, with diagnostic */ 2257332Sjkh if (rc_test(nec, dvp->id_unit)) 2267332Sjkh return 0; 2277332Sjkh rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 2287332Sjkh 2297332Sjkh return 0xF; 2307332Sjkh} 2317332Sjkh 2327332Sjkhstatic struct kern_devconf kdc_rc[NRC] = { { 23312675Sjulian 0, 0, 0, /* filled in by dev_attach */ 23412675Sjulian "rc", 0, { MDDT_ISA, 0, "tty" }, 2358876Srgrimes isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 2367332Sjkh &kdc_isa0, /* parent */ 2377332Sjkh 0, /* parentdata */ 2387780Swollman DC_UNCONFIGURED, /* state */ 2397332Sjkh "RISCom/8 multiport card", 2407332Sjkh DC_CLS_SERIAL /* class */ 2417332Sjkh} }; 2427332Sjkh 2437332Sjkhstatic void 2447332Sjkhrc_registerdev(id) 2457332Sjkh struct isa_device *id; 2467332Sjkh{ 2477332Sjkh int unit; 24812675Sjulian 24912675Sjulian unit = id->id_unit; 25012675Sjulian if (unit != 0) 25114873Sscrappy kdc_rc[unit] = kdc_rc[0]; 25214873Sscrappy kdc_rc[unit].kdc_unit = unit; 25314873Sscrappy kdc_rc[unit].kdc_isa = id; 25414873Sscrappy kdc_rc[unit].kdc_state = DC_UNKNOWN; 25514873Sscrappy dev_attach(&kdc_rc[unit]); 25614873Sscrappy} 25714873Sscrappy 25814873Sscrappyint rcattach(dvp) 25914873Sscrappy struct isa_device *dvp; 26014873Sscrappy{ 26114873Sscrappy register int i, chan, nec = dvp->id_iobase; 26214873Sscrappy struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 26312675Sjulian struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2647332Sjkh static int rc_wakeup_started = 0; 2657332Sjkh struct tty *tp; 2667332Sjkh 26712675Sjulian /* Thorooughly test the device */ 26810624Sbde if (rcb->rcb_probed != RC_PROBED) 2697332Sjkh return 0; 2707332Sjkh rcb->rcb_addr = nec; 2717332Sjkh rcb->rcb_dtr = 0; 2727332Sjkh rcb->rcb_baserc = rc; 2738876Srgrimes /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2747332Sjkh printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2757332Sjkh CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2767332Sjkh 2777332Sjkh rc_registerdev(dvp); 2787332Sjkh 2797332Sjkh for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 2807332Sjkh rc->rc_rcb = rcb; 2818876Srgrimes rc->rc_chan = chan; 2827332Sjkh rc->rc_iptr = rc->rc_ibuf; 2837332Sjkh rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2847332Sjkh rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2857332Sjkh rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 2867332Sjkh rc->rc_cor2 = rc->rc_pendcmd = 0; 2877332Sjkh rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2887332Sjkh rc->rc_dtrwait = 3 * hz; 2897332Sjkh rc->rc_dcdwaits= 0; 2907332Sjkh rc->rc_hotchar = 0; 2917332Sjkh tp = rc->rc_tp = &rc_tty[chan]; 2927332Sjkh ttychars(tp); 2937332Sjkh tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 2947332Sjkh tp->t_cflag = TTYDEF_CFLAG; 2957332Sjkh tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 2967332Sjkh } 2977332Sjkh rcb->rcb_probed = RC_ATTACHED; 2987332Sjkh if (!rc_wakeup_started) { 2997332Sjkh rc_wakeup((void *)NULL); 3007332Sjkh rc_wakeup_started = 0; 3017332Sjkh } 3027332Sjkh return 1; 3037332Sjkh} 3047332Sjkh 3057332Sjkh/* RC interrupt handling */ 3067332Sjkhvoid rcintr(unit) 3077332Sjkh int unit; 3087332Sjkh{ 3097332Sjkh register struct rc_softc *rcb = &rc_softc[unit]; 3107332Sjkh register struct rc_chans *rc; 3117332Sjkh register int nec, resid; 3127332Sjkh register u_char val, iack, bsr, ucnt, *optr; 3137332Sjkh int good_data, t_state; 3147332Sjkh 3157332Sjkh if (rcb->rcb_probed != RC_ATTACHED) { 3167332Sjkh printf("rc%d: bogus interrupt\n", unit); 3177332Sjkh return; 3187332Sjkh } 3197332Sjkh nec = rcb->rcb_addr; 32012675Sjulian 32110624Sbde bsr = ~(rcin(RC_BSR)); 3227332Sjkh 3237332Sjkh if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 3247332Sjkh printf("rc%d: extra interrupt\n", unit); 3258876Srgrimes rcout(CD180_EOIR, 0); 3267332Sjkh return; 3277332Sjkh } 3287332Sjkh 3297332Sjkh while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 3307332Sjkh#ifdef RCDEBUG_DETAILED 3317332Sjkh printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 3327332Sjkh (bsr & RC_BSR_TOUT)?"TOUT ":"", 3338876Srgrimes (bsr & RC_BSR_RXINT)?"RXINT ":"", 3348876Srgrimes (bsr & RC_BSR_TXINT)?"TXINT ":"", 3357332Sjkh (bsr & RC_BSR_MOINT)?"MOINT":""); 3367332Sjkh#endif 3377332Sjkh if (bsr & RC_BSR_TOUT) { 3387332Sjkh printf("rc%d: hardware failure, reset board\n", unit); 3397332Sjkh rcout(RC_CTOUT, 0); 3407332Sjkh rc_reinit(rcb); 3417332Sjkh return; 3427332Sjkh } 3437332Sjkh if (bsr & RC_BSR_RXINT) { 3447332Sjkh iack = rcin(RC_PILR_RX); 3457332Sjkh good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3467332Sjkh if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 3477332Sjkh printf("rc%d: fake rxint: %02x\n", unit, iack); 3487332Sjkh goto more_intrs; 3497332Sjkh } 35012675Sjulian rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 3517332Sjkh t_state = rc->rc_tp->t_state; 3527332Sjkh /* Do RTS flow control stuff */ 3537332Sjkh if ( (rc->rc_flags & RC_RTSFLOW) 3547332Sjkh || !(t_state & TS_ISOPEN) 3557332Sjkh ) { 3567332Sjkh if ( ( !(t_state & TS_ISOPEN) 3577332Sjkh || (t_state & TS_TBLOCK) 3587332Sjkh ) 3597332Sjkh && (rc->rc_msvr & MSVR_RTS) 3607332Sjkh ) 3617332Sjkh rcout(CD180_MSVR, 3628376Srgrimes rc->rc_msvr &= ~MSVR_RTS); 3637332Sjkh else if (!(rc->rc_msvr & MSVR_RTS)) 3647332Sjkh rcout(CD180_MSVR, 3657332Sjkh rc->rc_msvr |= MSVR_RTS); 3667332Sjkh } 3677332Sjkh ucnt = rcin(CD180_RDCR) & 0xF; 3687332Sjkh resid = 0; 3697332Sjkh 3707332Sjkh if (t_state & TS_ISOPEN) { 3717332Sjkh /* check for input buffer overflow */ 3727332Sjkh if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3737332Sjkh resid = ucnt; 3747332Sjkh ucnt = rc->rc_bufend - rc->rc_iptr; 3757332Sjkh resid -= ucnt; 3767332Sjkh if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3777332Sjkh rc->rc_flags |= RC_WAS_BUFOVFL; 3787332Sjkh rc_scheduled_event++; 3797332Sjkh } 3807332Sjkh } 3818876Srgrimes optr = rc->rc_iptr; 3827332Sjkh /* check foor good data */ 3837332Sjkh if (good_data) { 3847332Sjkh while (ucnt-- > 0) { 3858876Srgrimes val = rcin(CD180_RDR); 3867332Sjkh optr[0] = val; 3877332Sjkh optr[INPUT_FLAGS_SHIFT] = 0; 3887332Sjkh optr++; 3897332Sjkh rc_scheduled_event++; 3907332Sjkh if (val != 0 && val == rc->rc_hotchar) 3917332Sjkh setsofttty(); 3927332Sjkh } 3937332Sjkh } else { 3947332Sjkh /* Store also status data */ 3957332Sjkh while (ucnt-- > 0) { 3968876Srgrimes iack = rcin(CD180_RCSR); 3977332Sjkh if (iack & RCSR_Timeout) 3987332Sjkh break; 39915574Sphk if ( (iack & RCSR_OE) 4007332Sjkh && !(rc->rc_flags & RC_WAS_SILOVFL)) { 4018876Srgrimes rc->rc_flags |= RC_WAS_SILOVFL; 4027332Sjkh rc_scheduled_event++; 4037332Sjkh } 4047332Sjkh val = rcin(CD180_RDR); 4057332Sjkh /* 4067332Sjkh Don't store PE if IGNPAR and BREAK if IGNBRK, 4077332Sjkh this hack allows "raw" tty optimization 4087332Sjkh works even if IGN* is set. 4097332Sjkh */ 4107332Sjkh if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 4117332Sjkh || (!(iack & (RCSR_PE|RCSR_FE)) 4127332Sjkh || !(rc->rc_tp->t_iflag & IGNPAR)) 4137332Sjkh && (!(iack & RCSR_Break) 4147332Sjkh || !(rc->rc_tp->t_iflag & IGNBRK))) { 4157332Sjkh if ( (iack & (RCSR_PE|RCSR_FE)) 4167332Sjkh && (t_state & TS_CAN_BYPASS_L_RINT) 4177332Sjkh && ((iack & RCSR_FE) 41815574Sphk || (iack & RCSR_PE) 4197332Sjkh && (rc->rc_tp->t_iflag & INPCK))) 4207332Sjkh val = 0; 4218876Srgrimes else if (val != 0 && val == rc->rc_hotchar) 4227332Sjkh setsofttty(); 4237332Sjkh optr[0] = val; 4247332Sjkh optr[INPUT_FLAGS_SHIFT] = iack; 4257332Sjkh optr++; 4267332Sjkh rc_scheduled_event++; 42715574Sphk } 42815574Sphk } 4297332Sjkh } 43015574Sphk rc->rc_iptr = optr; 4317332Sjkh rc->rc_flags |= RC_DORXFER; 4327332Sjkh } else 4337332Sjkh resid = ucnt; 4347332Sjkh /* Clear FIFO if necessary */ 4357332Sjkh while (resid-- > 0) { 4367332Sjkh if (!good_data) 4377332Sjkh iack = rcin(CD180_RCSR); 4387332Sjkh else 4397332Sjkh iack = 0; 4407332Sjkh if (iack & RCSR_Timeout) 4417332Sjkh break; 4427332Sjkh (void) rcin(CD180_RDR); 4437332Sjkh } 4447332Sjkh goto more_intrs; 4457332Sjkh } 4467332Sjkh if (bsr & RC_BSR_MOINT) { 4477332Sjkh iack = rcin(RC_PILR_MODEM); 4487332Sjkh if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 4497332Sjkh printf("rc%d: fake moint: %02x\n", unit, iack); 4507332Sjkh goto more_intrs; 4517332Sjkh } 45212675Sjulian rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 45310624Sbde iack = rcin(CD180_MCR); 4547332Sjkh rc->rc_msvr = rcin(CD180_MSVR); 4557332Sjkh rcout(CD180_MCR, 0); 4567332Sjkh#ifdef RCDEBUG 4578876Srgrimes printrcflags(rc, "moint"); 4587332Sjkh#endif 4597332Sjkh if (rc->rc_flags & RC_CTSFLOW) { 4607332Sjkh if (rc->rc_msvr & MSVR_CTS) 4617332Sjkh rc->rc_flags |= RC_SEND_RDY; 4628376Srgrimes else 4637332Sjkh rc->rc_flags &= ~RC_SEND_RDY; 4647332Sjkh } else 4657332Sjkh rc->rc_flags |= RC_SEND_RDY; 4667332Sjkh if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 4677332Sjkh rc_scheduled_event += LOTS_OF_EVENTS; 4687332Sjkh rc->rc_flags |= RC_MODCHG; 4697332Sjkh setsofttty(); 4707332Sjkh } 4717332Sjkh goto more_intrs; 4727332Sjkh } 4737332Sjkh if (bsr & RC_BSR_TXINT) { 4747332Sjkh iack = rcin(RC_PILR_TX); 4757332Sjkh if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 4767332Sjkh printf("rc%d: fake txint: %02x\n", unit, iack); 4777332Sjkh goto more_intrs; 4787332Sjkh } 4797332Sjkh rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4807332Sjkh if ( (rc->rc_flags & RC_OSUSP) 4817332Sjkh || !(rc->rc_flags & RC_SEND_RDY) 4827332Sjkh ) 4837332Sjkh goto more_intrs; 4847332Sjkh /* Handle breaks and other stuff */ 4857332Sjkh if (rc->rc_pendcmd) { 4867332Sjkh rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4877332Sjkh rcout(CD180_TDR, CD180_C_ESC); 4887332Sjkh rcout(CD180_TDR, rc->rc_pendcmd); 4897332Sjkh rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4907332Sjkh rc->rc_pendcmd = 0; 4917332Sjkh goto more_intrs; 4927332Sjkh } 4937332Sjkh optr = rc->rc_optr; 4947332Sjkh resid = rc->rc_obufend - optr; 4957332Sjkh if (resid > CD180_NFIFO) 4967332Sjkh resid = CD180_NFIFO; 4977332Sjkh while (resid-- > 0) 4987332Sjkh rcout(CD180_TDR, *optr++); 4997332Sjkh rc->rc_optr = optr; 5007332Sjkh 5017332Sjkh /* output completed? */ 5027332Sjkh if (optr >= rc->rc_obufend) { 5037332Sjkh rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 5047332Sjkh#ifdef RCDEBUG 5057332Sjkh printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 5067332Sjkh#endif 5077332Sjkh if (!(rc->rc_flags & RC_DOXXFER)) { 5087332Sjkh rc_scheduled_event += LOTS_OF_EVENTS; 5097332Sjkh rc->rc_flags |= RC_DOXXFER; 5107332Sjkh setsofttty(); 5117332Sjkh } 5127332Sjkh } 5137332Sjkh } 5147332Sjkh more_intrs: 5157332Sjkh rcout(CD180_EOIR, 0); /* end of interrupt */ 5167332Sjkh rcout(RC_CTOUT, 0); 5177332Sjkh bsr = ~(rcin(RC_BSR)); 5187332Sjkh } 5197332Sjkh} 5207332Sjkh 5217332Sjkh/* Feed characters to output buffer */ 5227332Sjkhstatic void rc_start(tp) 5238376Srgrimesregister struct tty *tp; 5247332Sjkh{ 5257332Sjkh register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 5267332Sjkh register int nec = rc->rc_rcb->rcb_addr, s; 5277332Sjkh 5287332Sjkh if (rc->rc_flags & RC_OSBUSY) 5297332Sjkh return; 5307332Sjkh s = spltty(); 5317332Sjkh rc->rc_flags |= RC_OSBUSY; 5327332Sjkh disable_intr(); 5337332Sjkh if (tp->t_state & TS_TTSTOP) 5347332Sjkh rc->rc_flags |= RC_OSUSP; 5357332Sjkh else 5367332Sjkh rc->rc_flags &= ~RC_OSUSP; 5377332Sjkh /* Do RTS flow control stuff */ 5387332Sjkh if ( (rc->rc_flags & RC_RTSFLOW) 53911872Sphk && (tp->t_state & TS_TBLOCK) 5407332Sjkh && (rc->rc_msvr & MSVR_RTS) 5417332Sjkh ) { 5427332Sjkh rcout(CD180_CAR, rc->rc_chan); 5437332Sjkh rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 5447332Sjkh } else if (!(rc->rc_msvr & MSVR_RTS)) { 5457332Sjkh rcout(CD180_CAR, rc->rc_chan); 5467332Sjkh rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 5477332Sjkh } 5487332Sjkh enable_intr(); 5497332Sjkh if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5507332Sjkh goto out; 5517332Sjkh#ifdef RCDEBUG 5527332Sjkh printrcflags(rc, "rcstart"); 5537332Sjkh#endif 5547332Sjkh ttwwakeup(tp); 5557332Sjkh#ifdef RCDEBUG 5567332Sjkh printf("rcstart: outq = %d obuf = %d\n", 5577332Sjkh tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5587332Sjkh#endif 5597332Sjkh if (tp->t_state & TS_BUSY) 5607332Sjkh goto out; /* output still in progress ... */ 5617332Sjkh 5627332Sjkh if (tp->t_outq.c_cc > 0) { 5637332Sjkh u_int ocnt; 5647332Sjkh 5657332Sjkh tp->t_state |= TS_BUSY; 5667332Sjkh ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 5677332Sjkh disable_intr(); 5687332Sjkh rc->rc_optr = rc->rc_obuf; 5697332Sjkh rc->rc_obufend = rc->rc_optr + ocnt; 5707332Sjkh enable_intr(); 5717332Sjkh if (!(rc->rc_ier & IER_TxRdy)) { 5727332Sjkh#ifdef RCDEBUG 5737332Sjkh printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 5747332Sjkh#endif 5757332Sjkh rcout(CD180_CAR, rc->rc_chan); 5767332Sjkh rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 5777332Sjkh } 5787332Sjkh } 5797332Sjkhout: 5807332Sjkh rc->rc_flags &= ~RC_OSBUSY; 5817332Sjkh (void) splx(s); 5827332Sjkh} 5837332Sjkh 5847332Sjkh/* Handle delayed events. */ 5857332Sjkhvoid rcpoll() 5867332Sjkh{ 5877332Sjkh register struct rc_chans *rc; 5887332Sjkh register struct rc_softc *rcb; 5897332Sjkh register u_char *tptr, *eptr; 5907332Sjkh register int s; 5917332Sjkh register struct tty *tp; 5927332Sjkh register int chan, icnt, c, nec, unit; 5937332Sjkh 5947332Sjkh if (rc_scheduled_event == 0) 5957332Sjkh return; 5967332Sjkhrepeat: 5977332Sjkh for (unit = 0; unit < NRC; unit++) { 5987332Sjkh rcb = &rc_softc[unit]; 5997332Sjkh rc = rcb->rcb_baserc; 6007332Sjkh nec = rc->rc_rcb->rcb_addr; 6017332Sjkh for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 6027332Sjkh tp = rc->rc_tp; 6037332Sjkh#ifdef RCDEBUG 6047332Sjkh if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 6057332Sjkh RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 6067332Sjkh printrcflags(rc, "rcevent"); 6077332Sjkh#endif 6087332Sjkh if (rc->rc_flags & RC_WAS_BUFOVFL) { 6097332Sjkh disable_intr(); 6107332Sjkh rc->rc_flags &= ~RC_WAS_BUFOVFL; 6117332Sjkh rc_scheduled_event--; 6127332Sjkh enable_intr(); 6137332Sjkh printf("rc%d/%d: interrupt-level buffer overflow\n", 6147332Sjkh unit, chan); 6157332Sjkh } 6167332Sjkh if (rc->rc_flags & RC_WAS_SILOVFL) { 6177332Sjkh disable_intr(); 6187332Sjkh rc->rc_flags &= ~RC_WAS_SILOVFL; 6197332Sjkh rc_scheduled_event--; 6207332Sjkh enable_intr(); 6217332Sjkh printf("rc%d/%d: silo overflow\n", 6227332Sjkh unit, chan); 6237332Sjkh } 6247332Sjkh if (rc->rc_flags & RC_MODCHG) { 6257332Sjkh disable_intr(); 6267332Sjkh rc->rc_flags &= ~RC_MODCHG; 6277332Sjkh rc_scheduled_event -= LOTS_OF_EVENTS; 6287332Sjkh enable_intr(); 6297332Sjkh (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 6307332Sjkh } 6317332Sjkh if (rc->rc_flags & RC_DORXFER) { 6327332Sjkh disable_intr(); 6337332Sjkh rc->rc_flags &= ~RC_DORXFER; 6347332Sjkh eptr = rc->rc_iptr; 6357332Sjkh if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 6367332Sjkh tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6377332Sjkh else 6387332Sjkh tptr = rc->rc_ibuf; 6397332Sjkh icnt = eptr - tptr; 6408876Srgrimes if (icnt > 0) { 6417332Sjkh if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 6427332Sjkh rc->rc_iptr = rc->rc_ibuf; 6437332Sjkh rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 6447332Sjkh rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 6457332Sjkh } else { 6467332Sjkh rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6477332Sjkh rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 6487332Sjkh rc->rc_hiwat = 6497332Sjkh &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 6507332Sjkh } 6517332Sjkh if ( (rc->rc_flags & RC_RTSFLOW) 6527332Sjkh && (tp->t_state & TS_ISOPEN) 6537332Sjkh && !(tp->t_state & TS_TBLOCK) 6547332Sjkh && !(rc->rc_msvr & MSVR_RTS) 6557332Sjkh ) { 6567332Sjkh rcout(CD180_CAR, chan); 6577332Sjkh rcout(CD180_MSVR, 6587332Sjkh rc->rc_msvr |= MSVR_RTS); 6597332Sjkh } 6607332Sjkh rc_scheduled_event -= icnt; 6617332Sjkh } 6627332Sjkh enable_intr(); 6637332Sjkh 6647332Sjkh if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 6657332Sjkh goto done1; 6667332Sjkh 6677332Sjkh if ( linesw[tp->t_line].l_rint == ttyinput 6687332Sjkh && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 6697332Sjkh && !(tp->t_state & TS_TBLOCK) 6707332Sjkh && (tp->t_rawq.c_cc + icnt) > RB_I_HIGH_WATER) { 6717332Sjkh int queue_full = 0; 6727332Sjkh 6737332Sjkh if ((tp->t_iflag & IXOFF) && 6747332Sjkh tp->t_cc[VSTOP] != _POSIX_VDISABLE && 6757332Sjkh (queue_full = putc(tp->t_cc[VSTOP], &tp->t_outq)) == 0 || 6767332Sjkh (rc->rc_flags & RC_RTSFLOW)) { 6777332Sjkh tp->t_state |= TS_TBLOCK; 6787332Sjkh ttstart(tp); 6797332Sjkh if (queue_full) /* try again */ 6807332Sjkh tp->t_state &= ~TS_TBLOCK; 6817332Sjkh } 6827332Sjkh } 6837332Sjkh if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 6847332Sjkh && !(tp->t_state & TS_LOCAL)) { 6857332Sjkh tk_nin += icnt; 6867332Sjkh tk_rawcc += icnt; 6877332Sjkh tp->t_rawcc += icnt; 6887332Sjkh if (b_to_q(tptr, icnt, &tp->t_rawq)) 6897332Sjkh printf("rc%d/%d: tty-level buffer overflow\n", 6907332Sjkh unit, chan); 6917332Sjkh ttwakeup(tp); 6927332Sjkh if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 6937332Sjkh || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 6947332Sjkh tp->t_state &= ~TS_TTSTOP; 6957332Sjkh tp->t_lflag &= ~FLUSHO; 6967332Sjkh rc_start(tp); 6977332Sjkh } 6987332Sjkh } else { 6997332Sjkh for (; tptr < eptr; tptr++) 7007332Sjkh (*linesw[tp->t_line].l_rint) 7017332Sjkh (tptr[0] | 7027332Sjkh rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 7037332Sjkh } 7047332Sjkhdone1: 7057332Sjkh } 7067332Sjkh if (rc->rc_flags & RC_DOXXFER) { 7077332Sjkh disable_intr(); 7087332Sjkh rc_scheduled_event -= LOTS_OF_EVENTS; 7097332Sjkh rc->rc_flags &= ~RC_DOXXFER; 7107332Sjkh rc->rc_tp->t_state &= ~TS_BUSY; 7117332Sjkh enable_intr(); 7127332Sjkh (*linesw[tp->t_line].l_start)(tp); 7137332Sjkh } 7147332Sjkh } 7157332Sjkh if (rc_scheduled_event == 0) 7167332Sjkh break; 7177332Sjkh } 7187332Sjkh if (rc_scheduled_event >= LOTS_OF_EVENTS) 7197332Sjkh goto repeat; 7207332Sjkh} 7217332Sjkh 7227332Sjkhvoid rcstop(tp, rw) 7237332Sjkh register struct tty *tp; 7247332Sjkh int rw; 7257332Sjkh{ 7267332Sjkh register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 7277332Sjkh u_char *tptr, *eptr; 7287332Sjkh 7297332Sjkh#ifdef RCDEBUG 7307332Sjkh printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 7317780Swollman (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 7327780Swollman#endif 7337332Sjkh if (rw & FWRITE) 7347332Sjkh rc_discard_output(rc); 7357332Sjkh disable_intr(); 7367332Sjkh if (rw & FREAD) { 7377332Sjkh rc->rc_flags &= ~RC_DORXFER; 7387332Sjkh eptr = rc->rc_iptr; 7397332Sjkh if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 7407332Sjkh tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7417332Sjkh rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7427332Sjkh } else { 7437332Sjkh tptr = rc->rc_ibuf; 7447332Sjkh rc->rc_iptr = rc->rc_ibuf; 7457332Sjkh } 7467332Sjkh rc_scheduled_event -= eptr - tptr; 7477332Sjkh } 7487332Sjkh if (tp->t_state & TS_TTSTOP) 7497332Sjkh rc->rc_flags |= RC_OSUSP; 7507332Sjkh else 7517332Sjkh rc->rc_flags &= ~RC_OSUSP; 7527332Sjkh enable_intr(); 7537332Sjkh} 7547332Sjkh 7557332Sjkhint rcopen(dev, flag, mode, p) 7567332Sjkh dev_t dev; 7577332Sjkh int flag, mode; 7587332Sjkh struct proc *p; 7597332Sjkh{ 7607332Sjkh register struct rc_chans *rc; 7617332Sjkh register struct tty *tp; 7627332Sjkh int unit, nec, s, error = 0; 7637332Sjkh 7647332Sjkh unit = GET_UNIT(dev); 7657332Sjkh if (unit >= NRC * CD180_NCHAN) 7667332Sjkh return ENXIO; 7677332Sjkh if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 7687332Sjkh return ENXIO; 7697332Sjkh rc = &rc_chans[unit]; 7707332Sjkh tp = rc->rc_tp; 7717332Sjkh nec = rc->rc_rcb->rcb_addr; 7727332Sjkh#ifdef RCDEBUG 7737332Sjkh printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 7747332Sjkh#endif 7757332Sjkh s = spltty(); 7767332Sjkh 7777332Sjkhagain: 7787332Sjkh while (rc->rc_flags & RC_DTR_OFF) { 7797332Sjkh error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 7807332Sjkh if (error != 0) 7817332Sjkh goto out; 7827332Sjkh } 7837332Sjkh if (tp->t_state & TS_ISOPEN) { 7847332Sjkh if (CALLOUT(dev)) { 7857332Sjkh if (!(rc->rc_flags & RC_ACTOUT)) { 7867332Sjkh error = EBUSY; 7877332Sjkh goto out; 7887332Sjkh } 7897332Sjkh } else { 7907332Sjkh if (rc->rc_flags & RC_ACTOUT) { 7917332Sjkh if (flag & O_NONBLOCK) { 7927332Sjkh error = EBUSY; 7937332Sjkh goto out; 7947332Sjkh } 7957332Sjkh if (error = tsleep(&rc->rc_rcb, 7967332Sjkh TTIPRI|PCATCH, "rcbi", 0)) 7977332Sjkh goto out; 7987332Sjkh goto again; 7997332Sjkh } 8007332Sjkh } 8017332Sjkh if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 8027332Sjkh error = EBUSY; 8037332Sjkh goto out; 8047332Sjkh } 8057332Sjkh } else { 8067332Sjkh tp->t_oproc = rc_start; 8077332Sjkh tp->t_param = rc_param; 8087332Sjkh tp->t_dev = dev; 8097332Sjkh 8107332Sjkh if (CALLOUT(dev)) 8117332Sjkh tp->t_cflag |= CLOCAL; 8127332Sjkh else 8137332Sjkh tp->t_cflag &= ~CLOCAL; 8147332Sjkh 8157332Sjkh error = rc_param(tp, &tp->t_termios); 8167332Sjkh if (error) 8177332Sjkh goto out; 8187332Sjkh (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 8197332Sjkh 8207332Sjkh ttsetwater(tp); 82111872Sphk 8227332Sjkh if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 8237332Sjkh (*linesw[tp->t_line].l_modem)(tp, 1); 8247332Sjkh } 8257332Sjkh if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 8267332Sjkh && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 8277332Sjkh rc->rc_dcdwaits++; 8287332Sjkh error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 8297332Sjkh rc->rc_dcdwaits--; 8307332Sjkh if (error != 0) 8317332Sjkh goto out; 8327332Sjkh goto again; 8337332Sjkh } 8347332Sjkh error = (*linesw[tp->t_line].l_open)(dev, tp); 8357332Sjkh if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 8367332Sjkh rc->rc_flags |= RC_ACTOUT; 8377332Sjkhout: 8387332Sjkh (void) splx(s); 8397332Sjkh 8407332Sjkh if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 8417332Sjkh rc_hardclose(rc); 8427332Sjkh 8437332Sjkh return error; 8447332Sjkh} 8457332Sjkh 8467332Sjkhint rcclose(dev, flag, mode, p) 8477332Sjkh dev_t dev; 8487332Sjkh int flag, mode; 8497332Sjkh struct proc *p; 8507332Sjkh{ 8518876Srgrimes register struct rc_chans *rc; 8527332Sjkh register struct tty *tp; 8537332Sjkh int s, unit = GET_UNIT(dev); 8547332Sjkh 8557332Sjkh if (unit >= NRC * CD180_NCHAN) 8567332Sjkh return ENXIO; 8577332Sjkh rc = &rc_chans[unit]; 8587332Sjkh tp = rc->rc_tp; 8597332Sjkh#ifdef RCDEBUG 8607332Sjkh printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 8617332Sjkh#endif 8627332Sjkh s = spltty(); 8637332Sjkh (*linesw[tp->t_line].l_close)(tp, flag); 8647332Sjkh rcstop(tp, FREAD | FWRITE); 8657332Sjkh rc_hardclose(rc); 8667332Sjkh ttyclose(tp); 8677332Sjkh splx(s); 8687332Sjkh return 0; 8697332Sjkh} 8707332Sjkh 8717332Sjkhstatic void rc_hardclose(rc) 8727332Sjkhregister struct rc_chans *rc; 8737332Sjkh{ 8747332Sjkh register int s, nec = rc->rc_rcb->rcb_addr; 8757332Sjkh register struct tty *tp = rc->rc_tp; 8767332Sjkh 8777332Sjkh s = spltty(); 8787332Sjkh rcout(CD180_CAR, rc->rc_chan); 8797332Sjkh 8807332Sjkh /* Disable rx/tx intrs */ 8817332Sjkh rcout(CD180_IER, rc->rc_ier = 0); 8827332Sjkh if ( (tp->t_cflag & HUPCL) 8837332Sjkh || !(rc->rc_flags & RC_ACTOUT) 8847332Sjkh && !(rc->rc_msvr & MSVR_CD) 8857332Sjkh && !(tp->t_cflag & CLOCAL) 8867332Sjkh || !(tp->t_state & TS_ISOPEN) 8877332Sjkh ) { 8887332Sjkh CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 8897332Sjkh WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 8907332Sjkh (void) rc_modctl(rc, TIOCM_RTS, DMSET); 8917332Sjkh if (rc->rc_dtrwait) { 8927332Sjkh timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 8937332Sjkh rc->rc_flags |= RC_DTR_OFF; 8947332Sjkh } 8957332Sjkh } 8967332Sjkh rc->rc_flags &= ~RC_ACTOUT; 8977332Sjkh wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 8987332Sjkh wakeup(TSA_CARR_ON(tp)); 8997332Sjkh (void) splx(s); 9007332Sjkh} 9017332Sjkh 9027332Sjkh/* Read from line */ 9037332Sjkhint rcread(dev, uio, flag) 9047332Sjkh dev_t dev; 9057332Sjkh struct uio *uio; 9067332Sjkh int flag; 9077332Sjkh{ 9087332Sjkh struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9097332Sjkh 9107332Sjkh return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 9117332Sjkh} 9127332Sjkh 9137332Sjkh/* Write to line */ 9147332Sjkhint rcwrite(dev, uio, flag) 9157332Sjkh dev_t dev; 9167332Sjkh struct uio *uio; 9177332Sjkh int flag; 9187332Sjkh{ 9197332Sjkh struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9207332Sjkh 9217332Sjkh return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 9227332Sjkh} 9237332Sjkh 9247332Sjkh/* Reset the bastard */ 9257332Sjkhstatic void rc_hwreset(unit, nec, chipid) 9267332Sjkh register int unit, nec; 9277332Sjkh unsigned int chipid; 9287332Sjkh{ 9297332Sjkh CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 9307332Sjkh DELAY(20000); 9317332Sjkh WAITFORCCR(unit, -1); 9327332Sjkh 9337332Sjkh rcout(RC_CTOUT, 0); /* Clear timeout */ 9347332Sjkh rcout(CD180_GIVR, chipid); 9357332Sjkh rcout(CD180_GICR, 0); 9367332Sjkh 9377332Sjkh /* Set Prescaler Registers (1 msec) */ 9387332Sjkh rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 9397332Sjkh rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 9407332Sjkh 9417332Sjkh /* Initialize Priority Interrupt Level Registers */ 9427332Sjkh rcout(CD180_PILR1, RC_PILR_MODEM); 9437332Sjkh rcout(CD180_PILR2, RC_PILR_TX); 9447332Sjkh rcout(CD180_PILR3, RC_PILR_RX); 9457332Sjkh 9467332Sjkh /* Reset DTR */ 9477332Sjkh rcout(RC_DTREG, ~0); 9487332Sjkh} 9497332Sjkh 9507332Sjkh/* Set channel parameters */ 9517332Sjkhstatic int rc_param(tp, ts) 9527332Sjkh register struct tty *tp; 9537332Sjkh struct termios *ts; 9547332Sjkh{ 9557332Sjkh register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 9567332Sjkh register int nec = rc->rc_rcb->rcb_addr; 9577332Sjkh int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 9587332Sjkh 9597332Sjkh odivs = ttspeedtab(ts->c_ospeed, rc_speedtab); 9607332Sjkh if (ts->c_ispeed == 0) 9617332Sjkh ts->c_ispeed = ts->c_ospeed; 9627332Sjkh idivs = ttspeedtab(ts->c_ispeed, rc_speedtab); 9637332Sjkh if (idivs < 0 || odivs < 0) 9647332Sjkh return (EINVAL); 9657332Sjkh 9667332Sjkh s = spltty(); 9677332Sjkh 9687332Sjkh /* Select channel */ 9697332Sjkh rcout(CD180_CAR, rc->rc_chan); 9707332Sjkh 9717332Sjkh /* If speed == 0, hangup line */ 9727332Sjkh if (ts->c_ospeed == 0) { 9737332Sjkh CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 9747332Sjkh WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 9757332Sjkh (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 9767332Sjkh } 9777332Sjkh 9787332Sjkh tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 9797332Sjkh cflag = ts->c_cflag; 9807332Sjkh iflag = ts->c_iflag; 9817332Sjkh lflag = ts->c_lflag; 9827332Sjkh 9837332Sjkh if (idivs > 0) { 9847332Sjkh rcout(CD180_RBPRL, idivs & 0xFF); 9857332Sjkh rcout(CD180_RBPRH, idivs >> 8); 9867332Sjkh } 9877332Sjkh if (odivs > 0) { 9887332Sjkh rcout(CD180_TBPRL, odivs & 0xFF); 9897332Sjkh rcout(CD180_TBPRH, odivs >> 8); 9907332Sjkh } 9917332Sjkh 9927332Sjkh /* set timeout value */ 9937332Sjkh if (ts->c_ispeed > 0) { 9947332Sjkh int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 9957332Sjkh 9967332Sjkh if ( !(lflag & ICANON) 9977332Sjkh && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 9987332Sjkh && ts->c_cc[VTIME] * 10 > itm) 9997332Sjkh itm = ts->c_cc[VTIME] * 10; 10007332Sjkh 10017332Sjkh rcout(CD180_RTPR, itm <= 255 ? itm : 255); 10027332Sjkh } 10037332Sjkh 10047332Sjkh switch (cflag & CSIZE) { 10057332Sjkh case CS5: val = COR1_5BITS; break; 10067332Sjkh case CS6: val = COR1_6BITS; break; 10077332Sjkh case CS7: val = COR1_7BITS; break; 10087332Sjkh default: 10097332Sjkh case CS8: val = COR1_8BITS; break; 10107332Sjkh } 10117332Sjkh if (cflag & PARENB) { 10127332Sjkh val |= COR1_NORMPAR; 10137332Sjkh if (cflag & PARODD) 10147332Sjkh val |= COR1_ODDP; 10157332Sjkh if (!(cflag & INPCK)) 10167332Sjkh val |= COR1_Ignore; 10177332Sjkh } else 10187332Sjkh val |= COR1_Ignore; 10197332Sjkh if (cflag & CSTOPB) 10207332Sjkh val |= COR1_2SB; 10217332Sjkh rcout(CD180_COR1, val); 10227332Sjkh 10237332Sjkh /* Set FIFO threshold */ 10247332Sjkh val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 10257332Sjkh inpflow = 0; 10267332Sjkh if ( (iflag & IXOFF) 10277332Sjkh && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 10287332Sjkh && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 10297332Sjkh || (iflag & IXANY) 10307332Sjkh ) 10317332Sjkh ) 10327332Sjkh ) { 10337332Sjkh inpflow = 1; 10347332Sjkh val |= COR3_SCDE|COR3_FCT; 10357332Sjkh } 10367332Sjkh rcout(CD180_COR3, val); 10377332Sjkh 10387332Sjkh /* Initialize on-chip automatic flow control */ 10397332Sjkh val = 0; 10407332Sjkh rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 10417332Sjkh if (cflag & CCTS_OFLOW) { 10427332Sjkh rc->rc_flags |= RC_CTSFLOW; 10437332Sjkh val |= COR2_CtsAE; 10447332Sjkh } else 10457332Sjkh rc->rc_flags |= RC_SEND_RDY; 10467332Sjkh if (tp->t_state & TS_TTSTOP) 10477332Sjkh rc->rc_flags |= RC_OSUSP; 10487332Sjkh else 10497332Sjkh rc->rc_flags &= ~RC_OSUSP; 10507332Sjkh if (cflag & CRTS_IFLOW) 10517332Sjkh rc->rc_flags |= RC_RTSFLOW; 10527332Sjkh else 10537332Sjkh rc->rc_flags &= ~RC_RTSFLOW; 10547332Sjkh 10557332Sjkh if (inpflow) { 10567332Sjkh if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 10577332Sjkh rcout(CD180_SCHR1, ts->c_cc[VSTART]); 10587332Sjkh rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 10597332Sjkh val |= COR2_TxIBE; 10607332Sjkh if (iflag & IXANY) 10617332Sjkh val |= COR2_IXM; 10627332Sjkh } 10637332Sjkh 10647332Sjkh rcout(CD180_COR2, rc->rc_cor2 = val); 10657332Sjkh 10667332Sjkh CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10677332Sjkh CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 10687332Sjkh 10697332Sjkh disc_optim(tp, ts, rc); 10707332Sjkh 10717332Sjkh /* modem ctl */ 10727332Sjkh val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 10737332Sjkh if (cflag & CCTS_OFLOW) 10747332Sjkh val |= MCOR1_CTSzd; 10757332Sjkh rcout(CD180_MCOR1, val); 10767332Sjkh 10777332Sjkh val = cflag & CLOCAL ? 0 : MCOR2_CDod; 10787332Sjkh if (cflag & CCTS_OFLOW) 10797332Sjkh val |= MCOR2_CTSod; 10807332Sjkh rcout(CD180_MCOR2, val); 10817332Sjkh 10827332Sjkh /* enable i/o and interrupts */ 10837332Sjkh CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10847332Sjkh CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 10857332Sjkh WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 10867332Sjkh 10877332Sjkh rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 10887332Sjkh if (cflag & CCTS_OFLOW) 10897332Sjkh rc->rc_ier |= IER_CTS; 10907332Sjkh if (cflag & CREAD) 10917332Sjkh rc->rc_ier |= IER_RxData; 10927332Sjkh if (tp->t_state & TS_BUSY) 10937332Sjkh rc->rc_ier |= IER_TxRdy; 10947332Sjkh if (ts->c_ospeed != 0) 10957332Sjkh rc_modctl(rc, TIOCM_DTR, DMBIS); 10967332Sjkh if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 10977332Sjkh rc->rc_flags |= RC_SEND_RDY; 10987332Sjkh rcout(CD180_IER, rc->rc_ier); 10997332Sjkh (void) splx(s); 11007332Sjkh return 0; 11017332Sjkh} 11027332Sjkh 11037332Sjkh/* Re-initialize board after bogus interrupts */ 11047332Sjkhstatic void rc_reinit(rcb) 11057332Sjkhstruct rc_softc *rcb; 11067332Sjkh{ 11077332Sjkh register struct rc_chans *rc, *rce; 11087332Sjkh register int i, nec; 11097332Sjkh 11107332Sjkh nec = rcb->rcb_addr; 11117332Sjkh rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 11127332Sjkh rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 11137332Sjkh rce = rc + CD180_NCHAN; 11147332Sjkh for (; rc < rce; rc++) 11157332Sjkh (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 11167332Sjkh} 11177332Sjkh 11187332Sjkhint rcioctl(dev, cmd, data, flag, p) 11197332Sjkhdev_t dev; 11207332Sjkhint cmd, flag; 11217332Sjkhcaddr_t data; 11227332Sjkhstruct proc *p; 11237332Sjkh{ 11247332Sjkh register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 11257332Sjkh register int s, error; 11267332Sjkh struct tty *tp = rc->rc_tp; 11277332Sjkh 11287332Sjkh error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 11297332Sjkh if (error >= 0) 11307332Sjkh return (error); 11317332Sjkh error = ttioctl(tp, cmd, data, flag); 11327332Sjkh if (error >= 0) 11337332Sjkh return (error); 11347332Sjkh s = spltty(); 11357332Sjkh 11367332Sjkh switch (cmd) { 11377332Sjkh case TIOCSBRK: 11387332Sjkh rc->rc_pendcmd = CD180_C_SBRK; 11397332Sjkh break; 11407332Sjkh 11417332Sjkh case TIOCCBRK: 11427332Sjkh rc->rc_pendcmd = CD180_C_EBRK; 11437332Sjkh break; 11447332Sjkh 11457332Sjkh case TIOCSDTR: 11467332Sjkh (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 11477332Sjkh break; 11487332Sjkh 11497332Sjkh case TIOCCDTR: 11507332Sjkh (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 11517332Sjkh break; 11527332Sjkh 11537332Sjkh case TIOCMGET: 11547332Sjkh *(int *) data = rc_modctl(rc, 0, DMGET); 11557332Sjkh break; 11567332Sjkh 11577332Sjkh case TIOCMSET: 11587332Sjkh (void) rc_modctl(rc, *(int *) data, DMSET); 11597332Sjkh break; 11607332Sjkh 11617332Sjkh case TIOCMBIC: 11627332Sjkh (void) rc_modctl(rc, *(int *) data, DMBIC); 11637332Sjkh break; 11647332Sjkh 11657332Sjkh case TIOCMBIS: 11667332Sjkh (void) rc_modctl(rc, *(int *) data, DMBIS); 11677332Sjkh break; 11687332Sjkh 11697332Sjkh case TIOCMSDTRWAIT: 11707332Sjkh error = suser(p->p_ucred, &p->p_acflag); 11717332Sjkh if (error != 0) { 11727332Sjkh splx(s); 11737332Sjkh return (error); 11747332Sjkh } 11757332Sjkh rc->rc_dtrwait = *(int *)data * hz / 100; 11767332Sjkh break; 11777332Sjkh 11787332Sjkh case TIOCMGDTRWAIT: 11797332Sjkh *(int *)data = rc->rc_dtrwait * 100 / hz; 11807332Sjkh break; 11817332Sjkh 11827332Sjkh default: 11837332Sjkh (void) splx(s); 11847332Sjkh return ENOTTY; 11857332Sjkh } 11867332Sjkh (void) splx(s); 11877332Sjkh return 0; 11887332Sjkh} 11897332Sjkh 11908876Srgrimes 11917332Sjkh/* Modem control routines */ 11927332Sjkh 11938876Srgrimesstatic int rc_modctl(rc, bits, cmd) 11947332Sjkhregister struct rc_chans *rc; 11957332Sjkhint bits, cmd; 11968876Srgrimes{ 11977332Sjkh register int nec = rc->rc_rcb->rcb_addr; 11987332Sjkh u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 11998876Srgrimes 12007332Sjkh rcout(CD180_CAR, rc->rc_chan); 12017332Sjkh 12028876Srgrimes switch (cmd) { 12037332Sjkh case DMSET: 12047332Sjkh rcout(RC_DTREG, (bits & TIOCM_DTR) ? 12057332Sjkh ~(*dtr |= 1 << rc->rc_chan) : 12067332Sjkh ~(*dtr &= ~(1 << rc->rc_chan))); 12077332Sjkh msvr = rcin(CD180_MSVR); 12087332Sjkh if (bits & TIOCM_RTS) 12097332Sjkh msvr |= MSVR_RTS; 12107332Sjkh else 12117332Sjkh msvr &= ~MSVR_RTS; 12127332Sjkh if (bits & TIOCM_DTR) 12137332Sjkh msvr |= MSVR_DTR; 12147332Sjkh else 12157332Sjkh msvr &= ~MSVR_DTR; 12167332Sjkh rcout(CD180_MSVR, msvr); 12177332Sjkh break; 12187332Sjkh 12197332Sjkh case DMBIS: 12207332Sjkh if (bits & TIOCM_DTR) 12217332Sjkh rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 12227332Sjkh msvr = rcin(CD180_MSVR); 12237332Sjkh if (bits & TIOCM_RTS) 12247332Sjkh msvr |= MSVR_RTS; 12257332Sjkh if (bits & TIOCM_DTR) 12267332Sjkh msvr |= MSVR_DTR; 12277332Sjkh rcout(CD180_MSVR, msvr); 12287332Sjkh break; 12297332Sjkh 12307332Sjkh case DMGET: 12317332Sjkh bits = TIOCM_LE; 12327332Sjkh msvr = rc->rc_msvr = rcin(CD180_MSVR); 12337332Sjkh 12347332Sjkh if (msvr & MSVR_RTS) 12357332Sjkh bits |= TIOCM_RTS; 12367332Sjkh if (msvr & MSVR_CTS) 12377332Sjkh bits |= TIOCM_CTS; 12387332Sjkh if (msvr & MSVR_DSR) 12397332Sjkh bits |= TIOCM_DSR; 12408376Srgrimes if (msvr & MSVR_DTR) 12417332Sjkh bits |= TIOCM_DTR; 12427332Sjkh if (msvr & MSVR_CD) 12437332Sjkh bits |= TIOCM_CD; 12447332Sjkh if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 12457332Sjkh bits |= TIOCM_RI; 12467332Sjkh return bits; 12477332Sjkh 12487332Sjkh case DMBIC: 12497332Sjkh if (bits & TIOCM_DTR) 12507332Sjkh rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 12517332Sjkh msvr = rcin(CD180_MSVR); 12527332Sjkh if (bits & TIOCM_RTS) 12537332Sjkh msvr &= ~MSVR_RTS; 12547332Sjkh if (bits & TIOCM_DTR) 12557332Sjkh msvr &= ~MSVR_DTR; 12567332Sjkh rcout(CD180_MSVR, msvr); 12577332Sjkh break; 12587332Sjkh } 12597332Sjkh rc->rc_msvr = rcin(CD180_MSVR); 12607332Sjkh return 0; 12617332Sjkh} 12627332Sjkh 12637332Sjkh/* Test the board. */ 12647332Sjkhint rc_test(nec, unit) 12657332Sjkh register int nec; 12667332Sjkh int unit; 12677332Sjkh{ 12687332Sjkh int chan = 0, nopt = 0; 12697332Sjkh int i = 0, rcnt, old_level; 12707332Sjkh unsigned int iack, chipid; 12717332Sjkh unsigned short divs; 12727332Sjkh static u_char ctest[] = "\377\125\252\045\244\0\377"; 12737332Sjkh#define CTLEN 8 12747332Sjkh#define ERR(s) { \ 12757332Sjkh printf("rc%d: ", unit); printf s ; printf("\n"); \ 12767332Sjkh (void) splx(old_level); return 1; } 12777332Sjkh 12787332Sjkh struct rtest { 12797332Sjkh u_char txbuf[CD180_NFIFO]; /* TX buffer */ 12807332Sjkh u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 12817332Sjkh int rxptr; /* RX pointer */ 12827332Sjkh int txptr; /* TX pointer */ 12837332Sjkh } tchans[CD180_NCHAN]; 12847332Sjkh 12857332Sjkh old_level = spltty(); 12867332Sjkh 12877332Sjkh chipid = RC_FAKEID; 12887332Sjkh 12897332Sjkh /* First, reset board to inital state */ 12907332Sjkh rc_hwreset(unit, nec, chipid); 12917332Sjkh 12927332Sjkh divs = RC_BRD(19200); 12937332Sjkh 12947332Sjkh /* Initialize channels */ 12957332Sjkh for (chan = 0; chan < CD180_NCHAN; chan++) { 12967332Sjkh 12977332Sjkh /* Select and reset channel */ 12987332Sjkh rcout(CD180_CAR, chan); 12997332Sjkh CCRCMD(unit, chan, CCR_ResetChan); 13007332Sjkh WAITFORCCR(unit, chan); 13017332Sjkh 13027332Sjkh /* Set speed */ 13037332Sjkh rcout(CD180_RBPRL, divs & 0xFF); 13047332Sjkh rcout(CD180_RBPRH, divs >> 8); 13057332Sjkh rcout(CD180_TBPRL, divs & 0xFF); 13067332Sjkh rcout(CD180_TBPRH, divs >> 8); 13077332Sjkh 13087332Sjkh /* set timeout value */ 13097332Sjkh rcout(CD180_RTPR, 0); 13107332Sjkh 13117332Sjkh /* Establish local loopback */ 13127332Sjkh rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 13137332Sjkh rcout(CD180_COR2, COR2_LLM); 13147332Sjkh rcout(CD180_COR3, CD180_NFIFO); 13157332Sjkh CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 13167332Sjkh CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 13177332Sjkh WAITFORCCR(unit, chan); 13187332Sjkh rcout(CD180_MSVR, MSVR_RTS); 13197332Sjkh 13207332Sjkh /* Fill TXBUF with test data */ 13217332Sjkh for (i = 0; i < CD180_NFIFO; i++) { 13227332Sjkh tchans[chan].txbuf[i] = ctest[i]; 13237332Sjkh tchans[chan].rxbuf[i] = 0; 13247332Sjkh } 13257332Sjkh tchans[chan].txptr = tchans[chan].rxptr = 0; 13267332Sjkh 13277332Sjkh /* Now, start transmit */ 13287332Sjkh rcout(CD180_IER, IER_TxMpty|IER_RxData); 13297332Sjkh } 13307332Sjkh /* Pseudo-interrupt poll stuff */ 13317332Sjkh for (rcnt = 10000; rcnt-- > 0; rcnt--) { 13327332Sjkh i = ~(rcin(RC_BSR)); 13337332Sjkh if (i & RC_BSR_TOUT) 13347332Sjkh ERR(("BSR timeout bit set\n")) 13357332Sjkh else if (i & RC_BSR_TXINT) { 13367332Sjkh iack = rcin(RC_PILR_TX); 13377332Sjkh if (iack != (GIVR_IT_TDI | chipid)) 13387332Sjkh ERR(("Bad TX intr ack (%02x != %02x)\n", 13397332Sjkh iack, GIVR_IT_TDI | chipid)); 13407332Sjkh chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13417332Sjkh /* If no more data to transmit, disable TX intr */ 13427332Sjkh if (tchans[chan].txptr >= CD180_NFIFO) { 13437332Sjkh iack = rcin(CD180_IER); 13447332Sjkh rcout(CD180_IER, iack & ~IER_TxMpty); 13457332Sjkh } else { 13467332Sjkh for (iack = tchans[chan].txptr; 13477332Sjkh iack < CD180_NFIFO; iack++) 13487332Sjkh rcout(CD180_TDR, 13497332Sjkh tchans[chan].txbuf[iack]); 13507332Sjkh tchans[chan].txptr = iack; 13517332Sjkh } 13527332Sjkh rcout(CD180_EOIR, 0); 13537332Sjkh } else if (i & RC_BSR_RXINT) { 13547332Sjkh u_char ucnt; 13557332Sjkh 13567332Sjkh iack = rcin(RC_PILR_RX); 13577332Sjkh if (iack != (GIVR_IT_RGDI | chipid) && 13587332Sjkh iack != (GIVR_IT_REI | chipid)) 13597332Sjkh ERR(("Bad RX intr ack (%02x != %02x)\n", 13607332Sjkh iack, GIVR_IT_RGDI | chipid)) 13617332Sjkh chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13627332Sjkh ucnt = rcin(CD180_RDCR) & 0xF; 13637332Sjkh while (ucnt-- > 0) { 13647332Sjkh iack = rcin(CD180_RCSR); 13657332Sjkh if (iack & RCSR_Timeout) 13667332Sjkh break; 13677332Sjkh if (iack & 0xF) 13687332Sjkh ERR(("Bad char chan %d (RCSR = %02X)\n", 13697332Sjkh chan, iack)) 13707332Sjkh if (tchans[chan].rxptr > CD180_NFIFO) 13717332Sjkh ERR(("Got extra chars chan %d\n", 13727332Sjkh chan)) 13738876Srgrimes tchans[chan].rxbuf[tchans[chan].rxptr++] = 13747332Sjkh rcin(CD180_RDR); 13757332Sjkh } 13767332Sjkh rcout(CD180_EOIR, 0); 13777332Sjkh } 13787332Sjkh rcout(RC_CTOUT, 0); 13797332Sjkh for (iack = chan = 0; chan < CD180_NCHAN; chan++) 13807332Sjkh if (tchans[chan].rxptr >= CD180_NFIFO) 13817332Sjkh iack++; 13827332Sjkh if (iack == CD180_NCHAN) 13837332Sjkh break; 13847332Sjkh } 13857332Sjkh for (chan = 0; chan < CD180_NCHAN; chan++) { 138611872Sphk /* Select and reset channel */ 138711872Sphk rcout(CD180_CAR, chan); 13887332Sjkh CCRCMD(unit, chan, CCR_ResetChan); 13897332Sjkh } 13907332Sjkh 13917332Sjkh if (!rcnt) 13927332Sjkh ERR(("looses characters during local loopback\n")) 13937332Sjkh /* Now, check data */ 13947332Sjkh for (chan = 0; chan < CD180_NCHAN; chan++) 13957332Sjkh for (i = 0; i < CD180_NFIFO; i++) 13967332Sjkh if (ctest[i] != tchans[chan].rxbuf[i]) 13977332Sjkh ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 13987332Sjkh chan, i, ctest[i], tchans[chan].rxbuf[i])) 13997332Sjkh (void) splx(old_level); 14007332Sjkh return 0; 14017332Sjkh} 14027332Sjkh 14037332Sjkh#ifdef RCDEBUG 14047332Sjkhstatic void printrcflags(rc, comment) 14057332Sjkhstruct rc_chans *rc; 14067332Sjkhchar *comment; 14077332Sjkh{ 14087332Sjkh u_short f = rc->rc_flags; 14097332Sjkh register int nec = rc->rc_rcb->rcb_addr; 14107332Sjkh 14117332Sjkh printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 14127332Sjkh rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 14137332Sjkh (f & RC_DTR_OFF)?"DTR_OFF " :"", 14147332Sjkh (f & RC_ACTOUT) ?"ACTOUT " :"", 14157332Sjkh (f & RC_RTSFLOW)?"RTSFLOW " :"", 14167332Sjkh (f & RC_CTSFLOW)?"CTSFLOW " :"", 14177332Sjkh (f & RC_DORXFER)?"DORXFER " :"", 14187332Sjkh (f & RC_DOXXFER)?"DOXXFER " :"", 14197332Sjkh (f & RC_MODCHG) ?"MODCHG " :"", 14207332Sjkh (f & RC_OSUSP) ?"OSUSP " :"", 14217332Sjkh (f & RC_OSBUSY) ?"OSBUSY " :"", 14227332Sjkh (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 14237332Sjkh (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 14247332Sjkh (f & RC_SEND_RDY) ?"SEND_RDY":""); 14257332Sjkh 14267332Sjkh rcout(CD180_CAR, rc->rc_chan); 14277332Sjkh 14287332Sjkh printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 14297332Sjkh rc->rc_rcb->rcb_unit, rc->rc_chan, 14307332Sjkh rcin(CD180_MSVR), 14317332Sjkh rcin(CD180_IER), 14327332Sjkh rcin(CD180_CCSR)); 14337332Sjkh} 14347332Sjkh#endif /* RCDEBUG */ 14357332Sjkh 14367332Sjkhstruct tty * 14377332Sjkhrcdevtotty(dev) 14387332Sjkh dev_t dev; 14397332Sjkh{ 14407332Sjkh int unit; 14417332Sjkh 14427332Sjkh unit = GET_UNIT(dev); 14437332Sjkh if (unit >= NRC * CD180_NCHAN) 14447332Sjkh return NULL; 14457332Sjkh return (&rc_tty[unit]); 14467332Sjkh} 14477332Sjkh 14487332Sjkhstatic void 14497332Sjkhrc_dtrwakeup(chan) 14507332Sjkh void *chan; 14517332Sjkh{ 14527332Sjkh struct rc_chans *rc; 14537332Sjkh 14547332Sjkh rc = (struct rc_chans *)chan; 14557332Sjkh rc->rc_flags &= ~RC_DTR_OFF; 14567332Sjkh wakeup(&rc->rc_dtrwait); 14577332Sjkh} 14587332Sjkh 14597332Sjkhstatic void 14607332Sjkhrc_discard_output(rc) 14617332Sjkh struct rc_chans *rc; 14627332Sjkh{ 14637332Sjkh disable_intr(); 14647332Sjkh if (rc->rc_flags & RC_DOXXFER) { 14657332Sjkh rc_scheduled_event -= LOTS_OF_EVENTS; 14667332Sjkh rc->rc_flags &= ~RC_DOXXFER; 14677332Sjkh } 14687332Sjkh rc->rc_optr = rc->rc_obufend; 14697332Sjkh rc->rc_tp->t_state &= ~TS_BUSY; 14707332Sjkh enable_intr(); 14717332Sjkh ttwwakeup(rc->rc_tp); 14727332Sjkh} 14737332Sjkh 14747332Sjkhstatic void 14757332Sjkhrc_wakeup(chan) 14767332Sjkh void *chan; 14777332Sjkh{ 14787332Sjkh int unit; 14797332Sjkh 14807332Sjkh timeout(rc_wakeup, (caddr_t)NULL, 1); 14817332Sjkh 14827332Sjkh if (rc_scheduled_event != 0) { 14837332Sjkh int s; 14847332Sjkh 14857332Sjkh s = splsofttty(); 14867332Sjkh rcpoll(); 14877332Sjkh splx(s); 14887332Sjkh } 14897332Sjkh} 14907332Sjkh 14917332Sjkhstatic void 14927332Sjkhdisc_optim(tp, t, rc) 14937332Sjkh struct tty *tp; 14947332Sjkh struct termios *t; 14957332Sjkh struct rc_chans *rc; 14967332Sjkh{ 14977332Sjkh 14987332Sjkh if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 14997332Sjkh && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 15007332Sjkh && (!(t->c_iflag & PARMRK) 15017332Sjkh || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 15027332Sjkh && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 15037332Sjkh && linesw[tp->t_line].l_rint == ttyinput) 15047332Sjkh tp->t_state |= TS_CAN_BYPASS_L_RINT; 15057332Sjkh else 15067332Sjkh tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 15077332Sjkh if (tp->t_line == SLIPDISC) 15087332Sjkh rc->rc_hotchar = 0xc0; 15097332Sjkh else if (tp->t_line == PPPDISC) 15107332Sjkh rc->rc_hotchar = 0x7e; 15117332Sjkh else 15127332Sjkh rc->rc_hotchar = 0; 15137332Sjkh} 15147332Sjkh 15157332Sjkhstatic void 15167332Sjkhrc_wait0(nec, unit, chan, line) 15177332Sjkh int nec, unit, chan, line; 15188876Srgrimes{ 15197332Sjkh int rcnt; 15207332Sjkh 15217332Sjkh for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 15227332Sjkh DELAY(15); 15237332Sjkh if (rcnt == 0) 15247332Sjkh printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 15257332Sjkh unit, chan, line); 15267332Sjkh} 15277332Sjkh#endif /* NRC */ 15287332Sjkh