rc.c revision 83366
1212700Sjkim/* 2212700Sjkim * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3212700Sjkim * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4212700Sjkim * All rights reserved. 5212700Sjkim * 6212700Sjkim * Redistribution and use in source and binary forms, with or without 7217365Sjkim * modification, are permitted provided that the following conditions 8217365Sjkim * are met: 9212700Sjkim * 1. Redistributions of source code must retain the above copyright 10212700Sjkim * notice, this list of conditions and the following disclaimer. 11217365Sjkim * 2. Redistributions in binary form must reproduce the above copyright 12217365Sjkim * notice, this list of conditions and the following disclaimer in the 13217365Sjkim * documentation and/or other materials provided with the distribution. 14217365Sjkim * 15217365Sjkim * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16217365Sjkim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17217365Sjkim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18217365Sjkim * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19217365Sjkim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20217365Sjkim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21217365Sjkim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22217365Sjkim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23217365Sjkim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24217365Sjkim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25212700Sjkim * SUCH DAMAGE. 26217365Sjkim * 27217365Sjkim * $FreeBSD: head/sys/dev/rc/rc.c 83366 2001-09-12 08:38:13Z julian $ 28217365Sjkim * 29212700Sjkim */ 30217365Sjkim 31217365Sjkim/* 32217365Sjkim * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33217365Sjkim * 34217365Sjkim */ 35217365Sjkim 36217365Sjkim#include "rc.h" 37217365Sjkim 38217365Sjkim/*#define RCDEBUG*/ 39217365Sjkim 40217365Sjkim#include <sys/param.h> 41217365Sjkim#include <sys/systm.h> 42217365Sjkim#include <sys/kernel.h> 43212700Sjkim#include <sys/tty.h> 44212700Sjkim#include <sys/conf.h> 45212700Sjkim#include <sys/dkstat.h> 46212761Sjkim#include <sys/fcntl.h> 47212761Sjkim#include <sys/bus.h> 48212761Sjkim#include <sys/interrupt.h> 49212700Sjkim 50212700Sjkim 51212700Sjkim#include <i386/isa/isa_device.h> 52212700Sjkim 53212700Sjkim#include <i386/isa/ic/cd180.h> 54212700Sjkim#include <i386/isa/rcreg.h> 55212700Sjkim 56212700Sjkim/* Prototypes */ 57212700Sjkimstatic int rcprobe __P((struct isa_device *)); 58212700Sjkimstatic int rcattach __P((struct isa_device *)); 59212700Sjkim 60212700Sjkim#define rcin(port) RC_IN (nec, port) 61212700Sjkim#define rcout(port,v) RC_OUT (nec, port, v) 62212700Sjkim 63212700Sjkim#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 64212700Sjkim#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 65212700Sjkim 66212700Sjkim#define RC_IBUFSIZE 256 67212700Sjkim#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 68212700Sjkim#define RC_OBUFSIZE 512 69212700Sjkim#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 70212700Sjkim#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 71212700Sjkim#define LOTS_OF_EVENTS 64 72212700Sjkim 73212700Sjkim#define RC_FAKEID 0x10 74212700Sjkim 75212700Sjkim#define RC_PROBED 1 76212700Sjkim#define RC_ATTACHED 2 77212700Sjkim 78212700Sjkim#define GET_UNIT(dev) (minor(dev) & 0x3F) 79212700Sjkim#define CALLOUT(dev) (minor(dev) & 0x80) 80212700Sjkim 81212700Sjkim/* For isa routines */ 82212700Sjkimstruct isa_driver rcdriver = { 83212700Sjkim INTR_TYPE_TTY, 84212700Sjkim rcprobe, 85212700Sjkim rcattach, 86212700Sjkim "rc" 87212700Sjkim}; 88212700SjkimCOMPAT_ISA_DRIVER(rc, rcdriver); 89212700Sjkim 90212700Sjkimstatic d_open_t rcopen; 91212700Sjkimstatic d_close_t rcclose; 92212700Sjkimstatic d_ioctl_t rcioctl; 93212700Sjkim 94212700Sjkim#define CDEV_MAJOR 63 95212700Sjkimstatic struct cdevsw rc_cdevsw = { 96212700Sjkim /* open */ rcopen, 97212700Sjkim /* close */ rcclose, 98212700Sjkim /* read */ ttyread, 99212700Sjkim /* write */ ttywrite, 100212700Sjkim /* ioctl */ rcioctl, 101212700Sjkim /* poll */ ttypoll, 102212700Sjkim /* mmap */ nommap, 103212700Sjkim /* strategy */ nostrategy, 104212700Sjkim /* name */ "rc", 105212700Sjkim /* maj */ CDEV_MAJOR, 106212700Sjkim /* dump */ nodump, 107212700Sjkim /* psize */ nopsize, 108212700Sjkim /* flags */ D_TTY | D_KQFILTER, 109212700Sjkim /* kqfilter */ ttykqfilter, 110212700Sjkim}; 111212700Sjkim 112212700Sjkim/* Per-board structure */ 113212700Sjkimstatic struct rc_softc { 114212700Sjkim u_int rcb_probed; /* 1 - probed, 2 - attached */ 115212700Sjkim u_int rcb_addr; /* Base I/O addr */ 116212700Sjkim u_int rcb_unit; /* unit # */ 117212700Sjkim u_char rcb_dtr; /* DTR status */ 118212700Sjkim struct rc_chans *rcb_baserc; /* base rc ptr */ 119212700Sjkim} rc_softc[NRC]; 120212700Sjkim 121212700Sjkim/* Per-channel structure */ 122212700Sjkimstatic struct rc_chans { 123212700Sjkim struct rc_softc *rc_rcb; /* back ptr */ 124212700Sjkim u_short rc_flags; /* Misc. flags */ 125212700Sjkim int rc_chan; /* Channel # */ 126212700Sjkim u_char rc_ier; /* intr. enable reg */ 127212700Sjkim u_char rc_msvr; /* modem sig. status */ 128212700Sjkim u_char rc_cor2; /* options reg */ 129212700Sjkim u_char rc_pendcmd; /* special cmd pending */ 130212700Sjkim u_int rc_dtrwait; /* dtr timeout */ 131212700Sjkim u_int rc_dcdwaits; /* how many waits DCD in open */ 132212700Sjkim u_char rc_hotchar; /* end packed optimize */ 133212700Sjkim struct tty *rc_tp; /* tty struct */ 134212700Sjkim u_char *rc_iptr; /* Chars input buffer */ 135212700Sjkim u_char *rc_hiwat; /* hi-water mark */ 136212700Sjkim u_char *rc_bufend; /* end of buffer */ 137212700Sjkim u_char *rc_optr; /* ptr in output buf */ 138212700Sjkim u_char *rc_obufend; /* end of output buf */ 139212700Sjkim u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 140212700Sjkim u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 141212700Sjkim} rc_chans[NRC * CD180_NCHAN]; 142212700Sjkim 143212700Sjkimstatic int rc_scheduled_event = 0; 144212700Sjkim 145212700Sjkim/* for pstat -t */ 146212700Sjkimstatic struct tty rc_tty[NRC * CD180_NCHAN]; 147212700Sjkimstatic const int nrc_tty = NRC * CD180_NCHAN; 148212700Sjkim 149212700Sjkim/* Flags */ 150212700Sjkim#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 151212700Sjkim#define RC_ACTOUT 0x0002 /* Dial-out port active */ 152212700Sjkim#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 153212700Sjkim#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 154212700Sjkim#define RC_DORXFER 0x0010 /* RXFER event planned */ 155212700Sjkim#define RC_DOXXFER 0x0020 /* XXFER event planned */ 156212700Sjkim#define RC_MODCHG 0x0040 /* Modem status changed */ 157212700Sjkim#define RC_OSUSP 0x0080 /* Output suspended */ 158212700Sjkim#define RC_OSBUSY 0x0100 /* start() routine in progress */ 159212700Sjkim#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 160212700Sjkim#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 161212700Sjkim#define RC_SEND_RDY 0x0800 /* ready to send */ 162212700Sjkim 163212700Sjkim/* Table for translation of RCSR status bits to internal form */ 164212700Sjkimstatic int rc_rcsrt[16] = { 165212700Sjkim 0, TTY_OE, TTY_FE, 166212700Sjkim TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 167212700Sjkim TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 168212700Sjkim TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 169212700Sjkim TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 170212700Sjkim TTY_BI|TTY_PE|TTY_FE|TTY_OE 171212700Sjkim}; 172212700Sjkim 173212700Sjkimstatic void *rc_ih; 174212700Sjkim 175212700Sjkim/* Static prototypes */ 176212700Sjkimstatic ointhand2_t rcintr; 177212700Sjkimstatic void rc_hwreset __P((int, int, unsigned int)); 178212700Sjkimstatic int rc_test __P((int, int)); 179212700Sjkimstatic void rc_discard_output __P((struct rc_chans *)); 180212700Sjkimstatic void rc_hardclose __P((struct rc_chans *)); 181212700Sjkimstatic int rc_modctl __P((struct rc_chans *, int, int)); 182212700Sjkimstatic void rc_start __P((struct tty *)); 183212700Sjkimstatic void rc_stop __P((struct tty *, int rw)); 184212700Sjkimstatic int rc_param __P((struct tty *, struct termios *)); 185212700Sjkimstatic void rcpoll __P((void *)); 186212700Sjkimstatic void rc_reinit __P((struct rc_softc *)); 187212700Sjkim#ifdef RCDEBUG 188212700Sjkimstatic void printrcflags(); 189212700Sjkim#endif 190212700Sjkimstatic timeout_t rc_dtrwakeup; 191212700Sjkimstatic timeout_t rc_wakeup; 192212700Sjkimstatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 193212700Sjkimstatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 194212700Sjkim 195212700Sjkim/**********************************************/ 196212700Sjkim 197212700Sjkim/* Quick device probing */ 198212700Sjkimstatic int 199212700Sjkimrcprobe(dvp) 200212700Sjkim struct isa_device *dvp; 201212700Sjkim{ 202212700Sjkim int irq = ffs(dvp->id_irq) - 1; 203212700Sjkim register int nec = dvp->id_iobase; 204212700Sjkim 205212700Sjkim if (dvp->id_unit > NRC) 206212700Sjkim return 0; 207212700Sjkim if (!RC_VALIDADDR(nec)) { 208212700Sjkim printf("rc%d: illegal base address %x\n", dvp->id_unit, nec); 209212700Sjkim return 0; 210212700Sjkim } 211212700Sjkim if (!RC_VALIDIRQ(irq)) { 212212700Sjkim printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq); 213212700Sjkim return 0; 214212700Sjkim } 215212700Sjkim rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 216212700Sjkim rcout(CD180_PPRH, 0x11); 217212700Sjkim if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 218212700Sjkim return 0; 219212700Sjkim /* Now, test the board more thoroughly, with diagnostic */ 220212700Sjkim if (rc_test(nec, dvp->id_unit)) 221212700Sjkim return 0; 222212700Sjkim rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 223212700Sjkim 224212700Sjkim return 0xF; 225212700Sjkim} 226212700Sjkim 227212700Sjkimstatic int 228212700Sjkimrcattach(dvp) 229212700Sjkim struct isa_device *dvp; 230212700Sjkim{ 231212700Sjkim register int chan, nec = dvp->id_iobase; 232212700Sjkim struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 233212700Sjkim struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 234212700Sjkim static int rc_started = 0; 235212700Sjkim struct tty *tp; 236212700Sjkim 237212700Sjkim dvp->id_ointr = rcintr; 238212700Sjkim 239212700Sjkim /* Thorooughly test the device */ 240212761Sjkim if (rcb->rcb_probed != RC_PROBED) 241212761Sjkim return 0; 242212761Sjkim rcb->rcb_addr = nec; 243212761Sjkim rcb->rcb_dtr = 0; 244212761Sjkim rcb->rcb_baserc = rc; 245212700Sjkim rcb->rcb_unit = dvp->id_unit; 246212700Sjkim /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 247212700Sjkim printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit, 248212700Sjkim CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 249212700Sjkim 250212700Sjkim for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 251212700Sjkim rc->rc_rcb = rcb; 252212700Sjkim rc->rc_chan = chan; 253212700Sjkim rc->rc_iptr = rc->rc_ibuf; 254212700Sjkim rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 255212700Sjkim rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 256212700Sjkim rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 257212700Sjkim rc->rc_cor2 = rc->rc_pendcmd = 0; 258212700Sjkim rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 259212700Sjkim rc->rc_dtrwait = 3 * hz; 260212700Sjkim rc->rc_dcdwaits= 0; 261212700Sjkim rc->rc_hotchar = 0; 262212700Sjkim tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)]; 263212700Sjkim ttychars(tp); 264212700Sjkim tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 265212700Sjkim tp->t_cflag = TTYDEF_CFLAG; 266212700Sjkim tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 267212700Sjkim } 268212700Sjkim rcb->rcb_probed = RC_ATTACHED; 269212700Sjkim if (!rc_started) { 270212700Sjkim cdevsw_add(&rc_cdevsw); 271212700Sjkim swi_add(&tty_ithd, "tty:rc", rcpoll, NULL, SWI_TTY, 0, &rc_ih); 272212700Sjkim rc_wakeup((void *)NULL); 273212700Sjkim rc_started = 1; 274212700Sjkim } 275212700Sjkim return 1; 276212700Sjkim} 277212700Sjkim 278212700Sjkim/* RC interrupt handling */ 279212700Sjkimstatic void 280212700Sjkimrcintr(unit) 281212700Sjkim int unit; 282212700Sjkim{ 283212700Sjkim register struct rc_softc *rcb = &rc_softc[unit]; 284212700Sjkim register struct rc_chans *rc; 285212700Sjkim register int nec, resid; 286212700Sjkim register u_char val, iack, bsr, ucnt, *optr; 287212700Sjkim int good_data, t_state; 288212700Sjkim 289212700Sjkim if (rcb->rcb_probed != RC_ATTACHED) { 290212700Sjkim printf("rc%d: bogus interrupt\n", unit); 291212700Sjkim return; 292212700Sjkim } 293212700Sjkim nec = rcb->rcb_addr; 294212700Sjkim 295212700Sjkim bsr = ~(rcin(RC_BSR)); 296212700Sjkim 297212700Sjkim if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 298212700Sjkim printf("rc%d: extra interrupt\n", unit); 299212700Sjkim rcout(CD180_EOIR, 0); 300212700Sjkim return; 301212700Sjkim } 302212700Sjkim 303212700Sjkim while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 304212700Sjkim#ifdef RCDEBUG_DETAILED 305212700Sjkim printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 306212700Sjkim (bsr & RC_BSR_TOUT)?"TOUT ":"", 307212700Sjkim (bsr & RC_BSR_RXINT)?"RXINT ":"", 308212700Sjkim (bsr & RC_BSR_TXINT)?"TXINT ":"", 309212700Sjkim (bsr & RC_BSR_MOINT)?"MOINT":""); 310212700Sjkim#endif 311212700Sjkim if (bsr & RC_BSR_TOUT) { 312212700Sjkim printf("rc%d: hardware failure, reset board\n", unit); 313212700Sjkim rcout(RC_CTOUT, 0); 314212700Sjkim rc_reinit(rcb); 315212700Sjkim return; 316212700Sjkim } 317212700Sjkim if (bsr & RC_BSR_RXINT) { 318212700Sjkim iack = rcin(RC_PILR_RX); 319212700Sjkim good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 320212700Sjkim if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 321212700Sjkim printf("rc%d: fake rxint: %02x\n", unit, iack); 322212700Sjkim goto more_intrs; 323212700Sjkim } 324212700Sjkim rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 325212700Sjkim t_state = rc->rc_tp->t_state; 326212700Sjkim /* Do RTS flow control stuff */ 327212700Sjkim if ( (rc->rc_flags & RC_RTSFLOW) 328212700Sjkim || !(t_state & TS_ISOPEN) 329212700Sjkim ) { 330212700Sjkim if ( ( !(t_state & TS_ISOPEN) 331212700Sjkim || (t_state & TS_TBLOCK) 332212700Sjkim ) 333212700Sjkim && (rc->rc_msvr & MSVR_RTS) 334212700Sjkim ) 335212700Sjkim rcout(CD180_MSVR, 336212700Sjkim rc->rc_msvr &= ~MSVR_RTS); 337212700Sjkim else if (!(rc->rc_msvr & MSVR_RTS)) 338212700Sjkim rcout(CD180_MSVR, 339212700Sjkim rc->rc_msvr |= MSVR_RTS); 340212700Sjkim } 341212700Sjkim ucnt = rcin(CD180_RDCR) & 0xF; 342212700Sjkim resid = 0; 343212700Sjkim 344212700Sjkim if (t_state & TS_ISOPEN) { 345212700Sjkim /* check for input buffer overflow */ 346212700Sjkim if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 347212700Sjkim resid = ucnt; 348212700Sjkim ucnt = rc->rc_bufend - rc->rc_iptr; 349212700Sjkim resid -= ucnt; 350212700Sjkim if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 351212700Sjkim rc->rc_flags |= RC_WAS_BUFOVFL; 352212700Sjkim rc_scheduled_event++; 353212700Sjkim } 354212700Sjkim } 355212700Sjkim optr = rc->rc_iptr; 356212700Sjkim /* check foor good data */ 357212700Sjkim if (good_data) { 358212700Sjkim while (ucnt-- > 0) { 359212700Sjkim val = rcin(CD180_RDR); 360212700Sjkim optr[0] = val; 361212700Sjkim optr[INPUT_FLAGS_SHIFT] = 0; 362212700Sjkim optr++; 363212700Sjkim rc_scheduled_event++; 364212700Sjkim if (val != 0 && val == rc->rc_hotchar) 365212700Sjkim swi_sched(rc_ih, SWI_NOSWITCH); 366212700Sjkim } 367212700Sjkim } else { 368212700Sjkim /* Store also status data */ 369212700Sjkim while (ucnt-- > 0) { 370212700Sjkim iack = rcin(CD180_RCSR); 371212700Sjkim if (iack & RCSR_Timeout) 372212700Sjkim break; 373212700Sjkim if ( (iack & RCSR_OE) 374212700Sjkim && !(rc->rc_flags & RC_WAS_SILOVFL)) { 375212700Sjkim rc->rc_flags |= RC_WAS_SILOVFL; 376212700Sjkim rc_scheduled_event++; 377212700Sjkim } 378212700Sjkim val = rcin(CD180_RDR); 379212700Sjkim /* 380212700Sjkim Don't store PE if IGNPAR and BREAK if IGNBRK, 381212700Sjkim this hack allows "raw" tty optimization 382212700Sjkim works even if IGN* is set. 383212700Sjkim */ 384212700Sjkim if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 385212700Sjkim || ((!(iack & (RCSR_PE|RCSR_FE)) 386212700Sjkim || !(rc->rc_tp->t_iflag & IGNPAR)) 387212700Sjkim && (!(iack & RCSR_Break) 388212700Sjkim || !(rc->rc_tp->t_iflag & IGNBRK)))) { 389212700Sjkim if ( (iack & (RCSR_PE|RCSR_FE)) 390212700Sjkim && (t_state & TS_CAN_BYPASS_L_RINT) 391212700Sjkim && ((iack & RCSR_FE) 392212700Sjkim || ((iack & RCSR_PE) 393212700Sjkim && (rc->rc_tp->t_iflag & INPCK)))) 394212700Sjkim val = 0; 395212700Sjkim else if (val != 0 && val == rc->rc_hotchar) 396212700Sjkim swi_sched(rc_ih, SWI_NOSWITCH); 397212700Sjkim optr[0] = val; 398212700Sjkim optr[INPUT_FLAGS_SHIFT] = iack; 399212700Sjkim optr++; 400212700Sjkim rc_scheduled_event++; 401212700Sjkim } 402212700Sjkim } 403212700Sjkim } 404212700Sjkim rc->rc_iptr = optr; 405212700Sjkim rc->rc_flags |= RC_DORXFER; 406212700Sjkim } else 407212700Sjkim resid = ucnt; 408212700Sjkim /* Clear FIFO if necessary */ 409212700Sjkim while (resid-- > 0) { 410212700Sjkim if (!good_data) 411212700Sjkim iack = rcin(CD180_RCSR); 412212700Sjkim else 413212700Sjkim iack = 0; 414212700Sjkim if (iack & RCSR_Timeout) 415212700Sjkim break; 416212700Sjkim (void) rcin(CD180_RDR); 417212700Sjkim } 418212700Sjkim goto more_intrs; 419212700Sjkim } 420212700Sjkim if (bsr & RC_BSR_MOINT) { 421212700Sjkim iack = rcin(RC_PILR_MODEM); 422212700Sjkim if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 423212700Sjkim printf("rc%d: fake moint: %02x\n", unit, iack); 424212700Sjkim goto more_intrs; 425212700Sjkim } 426212700Sjkim rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 427212700Sjkim iack = rcin(CD180_MCR); 428212700Sjkim rc->rc_msvr = rcin(CD180_MSVR); 429212700Sjkim rcout(CD180_MCR, 0); 430212700Sjkim#ifdef RCDEBUG 431212700Sjkim printrcflags(rc, "moint"); 432212700Sjkim#endif 433212700Sjkim if (rc->rc_flags & RC_CTSFLOW) { 434212700Sjkim if (rc->rc_msvr & MSVR_CTS) 435212700Sjkim rc->rc_flags |= RC_SEND_RDY; 436212700Sjkim else 437212700Sjkim rc->rc_flags &= ~RC_SEND_RDY; 438212700Sjkim } else 439212700Sjkim rc->rc_flags |= RC_SEND_RDY; 440212700Sjkim if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 441212700Sjkim rc_scheduled_event += LOTS_OF_EVENTS; 442212700Sjkim rc->rc_flags |= RC_MODCHG; 443212700Sjkim swi_sched(rc_ih, SWI_NOSWITCH); 444212700Sjkim } 445212700Sjkim goto more_intrs; 446212700Sjkim } 447212700Sjkim if (bsr & RC_BSR_TXINT) { 448212700Sjkim iack = rcin(RC_PILR_TX); 449212700Sjkim if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 450212700Sjkim printf("rc%d: fake txint: %02x\n", unit, iack); 451212700Sjkim goto more_intrs; 452212700Sjkim } 453212700Sjkim rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 454212700Sjkim if ( (rc->rc_flags & RC_OSUSP) 455212700Sjkim || !(rc->rc_flags & RC_SEND_RDY) 456212700Sjkim ) 457212700Sjkim goto more_intrs; 458212700Sjkim /* Handle breaks and other stuff */ 459212700Sjkim if (rc->rc_pendcmd) { 460212700Sjkim rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 461212700Sjkim rcout(CD180_TDR, CD180_C_ESC); 462212700Sjkim rcout(CD180_TDR, rc->rc_pendcmd); 463212700Sjkim rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 464212700Sjkim rc->rc_pendcmd = 0; 465212700Sjkim goto more_intrs; 466212700Sjkim } 467212700Sjkim optr = rc->rc_optr; 468212700Sjkim resid = rc->rc_obufend - optr; 469212700Sjkim if (resid > CD180_NFIFO) 470212700Sjkim resid = CD180_NFIFO; 471212700Sjkim while (resid-- > 0) 472212700Sjkim rcout(CD180_TDR, *optr++); 473212700Sjkim rc->rc_optr = optr; 474212700Sjkim 475212700Sjkim /* output completed? */ 476212700Sjkim if (optr >= rc->rc_obufend) { 477212700Sjkim rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 478212700Sjkim#ifdef RCDEBUG 479212700Sjkim printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 480212700Sjkim#endif 481212700Sjkim if (!(rc->rc_flags & RC_DOXXFER)) { 482212700Sjkim rc_scheduled_event += LOTS_OF_EVENTS; 483212700Sjkim rc->rc_flags |= RC_DOXXFER; 484 swi_sched(rc_ih, SWI_NOSWITCH); 485 } 486 } 487 } 488 more_intrs: 489 rcout(CD180_EOIR, 0); /* end of interrupt */ 490 rcout(RC_CTOUT, 0); 491 bsr = ~(rcin(RC_BSR)); 492 } 493} 494 495/* Feed characters to output buffer */ 496static void rc_start(tp) 497register struct tty *tp; 498{ 499 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 500 register int nec = rc->rc_rcb->rcb_addr, s; 501 502 if (rc->rc_flags & RC_OSBUSY) 503 return; 504 s = spltty(); 505 rc->rc_flags |= RC_OSBUSY; 506 disable_intr(); 507 if (tp->t_state & TS_TTSTOP) 508 rc->rc_flags |= RC_OSUSP; 509 else 510 rc->rc_flags &= ~RC_OSUSP; 511 /* Do RTS flow control stuff */ 512 if ( (rc->rc_flags & RC_RTSFLOW) 513 && (tp->t_state & TS_TBLOCK) 514 && (rc->rc_msvr & MSVR_RTS) 515 ) { 516 rcout(CD180_CAR, rc->rc_chan); 517 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 518 } else if (!(rc->rc_msvr & MSVR_RTS)) { 519 rcout(CD180_CAR, rc->rc_chan); 520 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 521 } 522 enable_intr(); 523 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 524 goto out; 525#ifdef RCDEBUG 526 printrcflags(rc, "rcstart"); 527#endif 528 ttwwakeup(tp); 529#ifdef RCDEBUG 530 printf("rcstart: outq = %d obuf = %d\n", 531 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 532#endif 533 if (tp->t_state & TS_BUSY) 534 goto out; /* output still in progress ... */ 535 536 if (tp->t_outq.c_cc > 0) { 537 u_int ocnt; 538 539 tp->t_state |= TS_BUSY; 540 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 541 disable_intr(); 542 rc->rc_optr = rc->rc_obuf; 543 rc->rc_obufend = rc->rc_optr + ocnt; 544 enable_intr(); 545 if (!(rc->rc_ier & IER_TxRdy)) { 546#ifdef RCDEBUG 547 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 548#endif 549 rcout(CD180_CAR, rc->rc_chan); 550 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 551 } 552 } 553out: 554 rc->rc_flags &= ~RC_OSBUSY; 555 (void) splx(s); 556} 557 558/* Handle delayed events. */ 559void rcpoll(void *arg) 560{ 561 register struct rc_chans *rc; 562 register struct rc_softc *rcb; 563 register u_char *tptr, *eptr; 564 register struct tty *tp; 565 register int chan, icnt, nec, unit; 566 567 if (rc_scheduled_event == 0) 568 return; 569repeat: 570 for (unit = 0; unit < NRC; unit++) { 571 rcb = &rc_softc[unit]; 572 rc = rcb->rcb_baserc; 573 nec = rc->rc_rcb->rcb_addr; 574 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 575 tp = rc->rc_tp; 576#ifdef RCDEBUG 577 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 578 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 579 printrcflags(rc, "rcevent"); 580#endif 581 if (rc->rc_flags & RC_WAS_BUFOVFL) { 582 disable_intr(); 583 rc->rc_flags &= ~RC_WAS_BUFOVFL; 584 rc_scheduled_event--; 585 enable_intr(); 586 printf("rc%d/%d: interrupt-level buffer overflow\n", 587 unit, chan); 588 } 589 if (rc->rc_flags & RC_WAS_SILOVFL) { 590 disable_intr(); 591 rc->rc_flags &= ~RC_WAS_SILOVFL; 592 rc_scheduled_event--; 593 enable_intr(); 594 printf("rc%d/%d: silo overflow\n", 595 unit, chan); 596 } 597 if (rc->rc_flags & RC_MODCHG) { 598 disable_intr(); 599 rc->rc_flags &= ~RC_MODCHG; 600 rc_scheduled_event -= LOTS_OF_EVENTS; 601 enable_intr(); 602 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 603 } 604 if (rc->rc_flags & RC_DORXFER) { 605 disable_intr(); 606 rc->rc_flags &= ~RC_DORXFER; 607 eptr = rc->rc_iptr; 608 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 609 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 610 else 611 tptr = rc->rc_ibuf; 612 icnt = eptr - tptr; 613 if (icnt > 0) { 614 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 615 rc->rc_iptr = rc->rc_ibuf; 616 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 617 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 618 } else { 619 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 620 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 621 rc->rc_hiwat = 622 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 623 } 624 if ( (rc->rc_flags & RC_RTSFLOW) 625 && (tp->t_state & TS_ISOPEN) 626 && !(tp->t_state & TS_TBLOCK) 627 && !(rc->rc_msvr & MSVR_RTS) 628 ) { 629 rcout(CD180_CAR, chan); 630 rcout(CD180_MSVR, 631 rc->rc_msvr |= MSVR_RTS); 632 } 633 rc_scheduled_event -= icnt; 634 } 635 enable_intr(); 636 637 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 638 goto done1; 639 640 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 641 && !(tp->t_state & TS_LOCAL)) { 642 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 643 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 644 && !(tp->t_state & TS_TBLOCK)) 645 ttyblock(tp); 646 tk_nin += icnt; 647 tk_rawcc += icnt; 648 tp->t_rawcc += icnt; 649 if (b_to_q(tptr, icnt, &tp->t_rawq)) 650 printf("rc%d/%d: tty-level buffer overflow\n", 651 unit, chan); 652 ttwakeup(tp); 653 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 654 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 655 tp->t_state &= ~TS_TTSTOP; 656 tp->t_lflag &= ~FLUSHO; 657 rc_start(tp); 658 } 659 } else { 660 for (; tptr < eptr; tptr++) 661 (*linesw[tp->t_line].l_rint) 662 (tptr[0] | 663 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 664 } 665done1: ; 666 } 667 if (rc->rc_flags & RC_DOXXFER) { 668 disable_intr(); 669 rc_scheduled_event -= LOTS_OF_EVENTS; 670 rc->rc_flags &= ~RC_DOXXFER; 671 rc->rc_tp->t_state &= ~TS_BUSY; 672 enable_intr(); 673 (*linesw[tp->t_line].l_start)(tp); 674 } 675 } 676 if (rc_scheduled_event == 0) 677 break; 678 } 679 if (rc_scheduled_event >= LOTS_OF_EVENTS) 680 goto repeat; 681} 682 683static void 684rc_stop(tp, rw) 685 register struct tty *tp; 686 int rw; 687{ 688 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 689 u_char *tptr, *eptr; 690 691#ifdef RCDEBUG 692 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 693 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 694#endif 695 if (rw & FWRITE) 696 rc_discard_output(rc); 697 disable_intr(); 698 if (rw & FREAD) { 699 rc->rc_flags &= ~RC_DORXFER; 700 eptr = rc->rc_iptr; 701 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 702 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 703 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 704 } else { 705 tptr = rc->rc_ibuf; 706 rc->rc_iptr = rc->rc_ibuf; 707 } 708 rc_scheduled_event -= eptr - tptr; 709 } 710 if (tp->t_state & TS_TTSTOP) 711 rc->rc_flags |= RC_OSUSP; 712 else 713 rc->rc_flags &= ~RC_OSUSP; 714 enable_intr(); 715} 716 717static int 718rcopen(dev, flag, mode, td) 719 dev_t dev; 720 int flag, mode; 721 struct thread *td; 722{ 723 register struct rc_chans *rc; 724 register struct tty *tp; 725 int unit, nec, s, error = 0; 726 727 unit = GET_UNIT(dev); 728 if (unit >= NRC * CD180_NCHAN) 729 return ENXIO; 730 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 731 return ENXIO; 732 rc = &rc_chans[unit]; 733 tp = rc->rc_tp; 734 dev->si_tty = tp; 735 nec = rc->rc_rcb->rcb_addr; 736#ifdef RCDEBUG 737 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 738#endif 739 s = spltty(); 740 741again: 742 while (rc->rc_flags & RC_DTR_OFF) { 743 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 744 if (error != 0) 745 goto out; 746 } 747 if (tp->t_state & TS_ISOPEN) { 748 if (CALLOUT(dev)) { 749 if (!(rc->rc_flags & RC_ACTOUT)) { 750 error = EBUSY; 751 goto out; 752 } 753 } else { 754 if (rc->rc_flags & RC_ACTOUT) { 755 if (flag & O_NONBLOCK) { 756 error = EBUSY; 757 goto out; 758 } 759 error = tsleep(&rc->rc_rcb, 760 TTIPRI|PCATCH, "rcbi", 0); 761 if (error) 762 goto out; 763 goto again; 764 } 765 } 766 if (tp->t_state & TS_XCLUDE && 767 suser_td(td)) { 768 error = EBUSY; 769 goto out; 770 } 771 } else { 772 tp->t_oproc = rc_start; 773 tp->t_param = rc_param; 774 tp->t_stop = rc_stop; 775 tp->t_dev = dev; 776 777 if (CALLOUT(dev)) 778 tp->t_cflag |= CLOCAL; 779 else 780 tp->t_cflag &= ~CLOCAL; 781 782 error = rc_param(tp, &tp->t_termios); 783 if (error) 784 goto out; 785 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 786 787 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 788 (*linesw[tp->t_line].l_modem)(tp, 1); 789 } 790 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 791 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 792 rc->rc_dcdwaits++; 793 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 794 rc->rc_dcdwaits--; 795 if (error != 0) 796 goto out; 797 goto again; 798 } 799 error = (*linesw[tp->t_line].l_open)(dev, tp); 800 disc_optim(tp, &tp->t_termios, rc); 801 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 802 rc->rc_flags |= RC_ACTOUT; 803out: 804 (void) splx(s); 805 806 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 807 rc_hardclose(rc); 808 809 return error; 810} 811 812static int 813rcclose(dev, flag, mode, td) 814 dev_t dev; 815 int flag, mode; 816 struct thread *td; 817{ 818 register struct rc_chans *rc; 819 register struct tty *tp; 820 int s, unit = GET_UNIT(dev); 821 822 if (unit >= NRC * CD180_NCHAN) 823 return ENXIO; 824 rc = &rc_chans[unit]; 825 tp = rc->rc_tp; 826#ifdef RCDEBUG 827 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 828#endif 829 s = spltty(); 830 (*linesw[tp->t_line].l_close)(tp, flag); 831 disc_optim(tp, &tp->t_termios, rc); 832 rc_stop(tp, FREAD | FWRITE); 833 rc_hardclose(rc); 834 ttyclose(tp); 835 splx(s); 836 return 0; 837} 838 839static void rc_hardclose(rc) 840register struct rc_chans *rc; 841{ 842 register int s, nec = rc->rc_rcb->rcb_addr; 843 register struct tty *tp = rc->rc_tp; 844 845 s = spltty(); 846 rcout(CD180_CAR, rc->rc_chan); 847 848 /* Disable rx/tx intrs */ 849 rcout(CD180_IER, rc->rc_ier = 0); 850 if ( (tp->t_cflag & HUPCL) 851 || (!(rc->rc_flags & RC_ACTOUT) 852 && !(rc->rc_msvr & MSVR_CD) 853 && !(tp->t_cflag & CLOCAL)) 854 || !(tp->t_state & TS_ISOPEN) 855 ) { 856 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 857 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 858 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 859 if (rc->rc_dtrwait) { 860 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 861 rc->rc_flags |= RC_DTR_OFF; 862 } 863 } 864 rc->rc_flags &= ~RC_ACTOUT; 865 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 866 wakeup(TSA_CARR_ON(tp)); 867 (void) splx(s); 868} 869 870/* Reset the bastard */ 871static void rc_hwreset(unit, nec, chipid) 872 register int unit, nec; 873 unsigned int chipid; 874{ 875 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 876 DELAY(20000); 877 WAITFORCCR(unit, -1); 878 879 rcout(RC_CTOUT, 0); /* Clear timeout */ 880 rcout(CD180_GIVR, chipid); 881 rcout(CD180_GICR, 0); 882 883 /* Set Prescaler Registers (1 msec) */ 884 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 885 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 886 887 /* Initialize Priority Interrupt Level Registers */ 888 rcout(CD180_PILR1, RC_PILR_MODEM); 889 rcout(CD180_PILR2, RC_PILR_TX); 890 rcout(CD180_PILR3, RC_PILR_RX); 891 892 /* Reset DTR */ 893 rcout(RC_DTREG, ~0); 894} 895 896/* Set channel parameters */ 897static int rc_param(tp, ts) 898 register struct tty *tp; 899 struct termios *ts; 900{ 901 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 902 register int nec = rc->rc_rcb->rcb_addr; 903 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 904 905 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 906 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 907 ) 908 return (EINVAL); 909 if (ts->c_ispeed == 0) 910 ts->c_ispeed = ts->c_ospeed; 911 odivs = RC_BRD(ts->c_ospeed); 912 idivs = RC_BRD(ts->c_ispeed); 913 914 s = spltty(); 915 916 /* Select channel */ 917 rcout(CD180_CAR, rc->rc_chan); 918 919 /* If speed == 0, hangup line */ 920 if (ts->c_ospeed == 0) { 921 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 922 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 923 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 924 } 925 926 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 927 cflag = ts->c_cflag; 928 iflag = ts->c_iflag; 929 lflag = ts->c_lflag; 930 931 if (idivs > 0) { 932 rcout(CD180_RBPRL, idivs & 0xFF); 933 rcout(CD180_RBPRH, idivs >> 8); 934 } 935 if (odivs > 0) { 936 rcout(CD180_TBPRL, odivs & 0xFF); 937 rcout(CD180_TBPRH, odivs >> 8); 938 } 939 940 /* set timeout value */ 941 if (ts->c_ispeed > 0) { 942 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 943 944 if ( !(lflag & ICANON) 945 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 946 && ts->c_cc[VTIME] * 10 > itm) 947 itm = ts->c_cc[VTIME] * 10; 948 949 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 950 } 951 952 switch (cflag & CSIZE) { 953 case CS5: val = COR1_5BITS; break; 954 case CS6: val = COR1_6BITS; break; 955 case CS7: val = COR1_7BITS; break; 956 default: 957 case CS8: val = COR1_8BITS; break; 958 } 959 if (cflag & PARENB) { 960 val |= COR1_NORMPAR; 961 if (cflag & PARODD) 962 val |= COR1_ODDP; 963 if (!(cflag & INPCK)) 964 val |= COR1_Ignore; 965 } else 966 val |= COR1_Ignore; 967 if (cflag & CSTOPB) 968 val |= COR1_2SB; 969 rcout(CD180_COR1, val); 970 971 /* Set FIFO threshold */ 972 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 973 inpflow = 0; 974 if ( (iflag & IXOFF) 975 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 976 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 977 || (iflag & IXANY) 978 ) 979 ) 980 ) { 981 inpflow = 1; 982 val |= COR3_SCDE|COR3_FCT; 983 } 984 rcout(CD180_COR3, val); 985 986 /* Initialize on-chip automatic flow control */ 987 val = 0; 988 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 989 if (cflag & CCTS_OFLOW) { 990 rc->rc_flags |= RC_CTSFLOW; 991 val |= COR2_CtsAE; 992 } else 993 rc->rc_flags |= RC_SEND_RDY; 994 if (tp->t_state & TS_TTSTOP) 995 rc->rc_flags |= RC_OSUSP; 996 else 997 rc->rc_flags &= ~RC_OSUSP; 998 if (cflag & CRTS_IFLOW) 999 rc->rc_flags |= RC_RTSFLOW; 1000 else 1001 rc->rc_flags &= ~RC_RTSFLOW; 1002 1003 if (inpflow) { 1004 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1005 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1006 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1007 val |= COR2_TxIBE; 1008 if (iflag & IXANY) 1009 val |= COR2_IXM; 1010 } 1011 1012 rcout(CD180_COR2, rc->rc_cor2 = val); 1013 1014 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1015 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1016 1017 disc_optim(tp, ts, rc); 1018 1019 /* modem ctl */ 1020 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1021 if (cflag & CCTS_OFLOW) 1022 val |= MCOR1_CTSzd; 1023 rcout(CD180_MCOR1, val); 1024 1025 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1026 if (cflag & CCTS_OFLOW) 1027 val |= MCOR2_CTSod; 1028 rcout(CD180_MCOR2, val); 1029 1030 /* enable i/o and interrupts */ 1031 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1032 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1033 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1034 1035 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1036 if (cflag & CCTS_OFLOW) 1037 rc->rc_ier |= IER_CTS; 1038 if (cflag & CREAD) 1039 rc->rc_ier |= IER_RxData; 1040 if (tp->t_state & TS_BUSY) 1041 rc->rc_ier |= IER_TxRdy; 1042 if (ts->c_ospeed != 0) 1043 rc_modctl(rc, TIOCM_DTR, DMBIS); 1044 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1045 rc->rc_flags |= RC_SEND_RDY; 1046 rcout(CD180_IER, rc->rc_ier); 1047 (void) splx(s); 1048 return 0; 1049} 1050 1051/* Re-initialize board after bogus interrupts */ 1052static void rc_reinit(rcb) 1053struct rc_softc *rcb; 1054{ 1055 register struct rc_chans *rc, *rce; 1056 register int nec; 1057 1058 nec = rcb->rcb_addr; 1059 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1060 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1061 rce = rc + CD180_NCHAN; 1062 for (; rc < rce; rc++) 1063 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1064} 1065 1066static int 1067rcioctl(dev, cmd, data, flag, td) 1068dev_t dev; 1069u_long cmd; 1070int flag; 1071caddr_t data; 1072struct thread *td; 1073{ 1074 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1075 register int s, error; 1076 struct tty *tp = rc->rc_tp; 1077 1078 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1079 if (error != ENOIOCTL) 1080 return (error); 1081 error = ttioctl(tp, cmd, data, flag); 1082 disc_optim(tp, &tp->t_termios, rc); 1083 if (error != ENOIOCTL) 1084 return (error); 1085 s = spltty(); 1086 1087 switch (cmd) { 1088 case TIOCSBRK: 1089 rc->rc_pendcmd = CD180_C_SBRK; 1090 break; 1091 1092 case TIOCCBRK: 1093 rc->rc_pendcmd = CD180_C_EBRK; 1094 break; 1095 1096 case TIOCSDTR: 1097 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1098 break; 1099 1100 case TIOCCDTR: 1101 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1102 break; 1103 1104 case TIOCMGET: 1105 *(int *) data = rc_modctl(rc, 0, DMGET); 1106 break; 1107 1108 case TIOCMSET: 1109 (void) rc_modctl(rc, *(int *) data, DMSET); 1110 break; 1111 1112 case TIOCMBIC: 1113 (void) rc_modctl(rc, *(int *) data, DMBIC); 1114 break; 1115 1116 case TIOCMBIS: 1117 (void) rc_modctl(rc, *(int *) data, DMBIS); 1118 break; 1119 1120 case TIOCMSDTRWAIT: 1121 error = suser_td(td); 1122 if (error != 0) { 1123 splx(s); 1124 return (error); 1125 } 1126 rc->rc_dtrwait = *(int *)data * hz / 100; 1127 break; 1128 1129 case TIOCMGDTRWAIT: 1130 *(int *)data = rc->rc_dtrwait * 100 / hz; 1131 break; 1132 1133 default: 1134 (void) splx(s); 1135 return ENOTTY; 1136 } 1137 (void) splx(s); 1138 return 0; 1139} 1140 1141 1142/* Modem control routines */ 1143 1144static int rc_modctl(rc, bits, cmd) 1145register struct rc_chans *rc; 1146int bits, cmd; 1147{ 1148 register int nec = rc->rc_rcb->rcb_addr; 1149 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1150 1151 rcout(CD180_CAR, rc->rc_chan); 1152 1153 switch (cmd) { 1154 case DMSET: 1155 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1156 ~(*dtr |= 1 << rc->rc_chan) : 1157 ~(*dtr &= ~(1 << rc->rc_chan))); 1158 msvr = rcin(CD180_MSVR); 1159 if (bits & TIOCM_RTS) 1160 msvr |= MSVR_RTS; 1161 else 1162 msvr &= ~MSVR_RTS; 1163 if (bits & TIOCM_DTR) 1164 msvr |= MSVR_DTR; 1165 else 1166 msvr &= ~MSVR_DTR; 1167 rcout(CD180_MSVR, msvr); 1168 break; 1169 1170 case DMBIS: 1171 if (bits & TIOCM_DTR) 1172 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1173 msvr = rcin(CD180_MSVR); 1174 if (bits & TIOCM_RTS) 1175 msvr |= MSVR_RTS; 1176 if (bits & TIOCM_DTR) 1177 msvr |= MSVR_DTR; 1178 rcout(CD180_MSVR, msvr); 1179 break; 1180 1181 case DMGET: 1182 bits = TIOCM_LE; 1183 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1184 1185 if (msvr & MSVR_RTS) 1186 bits |= TIOCM_RTS; 1187 if (msvr & MSVR_CTS) 1188 bits |= TIOCM_CTS; 1189 if (msvr & MSVR_DSR) 1190 bits |= TIOCM_DSR; 1191 if (msvr & MSVR_DTR) 1192 bits |= TIOCM_DTR; 1193 if (msvr & MSVR_CD) 1194 bits |= TIOCM_CD; 1195 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1196 bits |= TIOCM_RI; 1197 return bits; 1198 1199 case DMBIC: 1200 if (bits & TIOCM_DTR) 1201 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1202 msvr = rcin(CD180_MSVR); 1203 if (bits & TIOCM_RTS) 1204 msvr &= ~MSVR_RTS; 1205 if (bits & TIOCM_DTR) 1206 msvr &= ~MSVR_DTR; 1207 rcout(CD180_MSVR, msvr); 1208 break; 1209 } 1210 rc->rc_msvr = rcin(CD180_MSVR); 1211 return 0; 1212} 1213 1214/* Test the board. */ 1215int rc_test(nec, unit) 1216 register int nec; 1217 int unit; 1218{ 1219 int chan = 0; 1220 int i = 0, rcnt, old_level; 1221 unsigned int iack, chipid; 1222 unsigned short divs; 1223 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1224#define CTLEN 8 1225#define ERR(s) { \ 1226 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1227 (void) splx(old_level); return 1; } 1228 1229 struct rtest { 1230 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1231 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1232 int rxptr; /* RX pointer */ 1233 int txptr; /* TX pointer */ 1234 } tchans[CD180_NCHAN]; 1235 1236 old_level = spltty(); 1237 1238 chipid = RC_FAKEID; 1239 1240 /* First, reset board to inital state */ 1241 rc_hwreset(unit, nec, chipid); 1242 1243 divs = RC_BRD(19200); 1244 1245 /* Initialize channels */ 1246 for (chan = 0; chan < CD180_NCHAN; chan++) { 1247 1248 /* Select and reset channel */ 1249 rcout(CD180_CAR, chan); 1250 CCRCMD(unit, chan, CCR_ResetChan); 1251 WAITFORCCR(unit, chan); 1252 1253 /* Set speed */ 1254 rcout(CD180_RBPRL, divs & 0xFF); 1255 rcout(CD180_RBPRH, divs >> 8); 1256 rcout(CD180_TBPRL, divs & 0xFF); 1257 rcout(CD180_TBPRH, divs >> 8); 1258 1259 /* set timeout value */ 1260 rcout(CD180_RTPR, 0); 1261 1262 /* Establish local loopback */ 1263 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1264 rcout(CD180_COR2, COR2_LLM); 1265 rcout(CD180_COR3, CD180_NFIFO); 1266 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1267 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1268 WAITFORCCR(unit, chan); 1269 rcout(CD180_MSVR, MSVR_RTS); 1270 1271 /* Fill TXBUF with test data */ 1272 for (i = 0; i < CD180_NFIFO; i++) { 1273 tchans[chan].txbuf[i] = ctest[i]; 1274 tchans[chan].rxbuf[i] = 0; 1275 } 1276 tchans[chan].txptr = tchans[chan].rxptr = 0; 1277 1278 /* Now, start transmit */ 1279 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1280 } 1281 /* Pseudo-interrupt poll stuff */ 1282 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1283 i = ~(rcin(RC_BSR)); 1284 if (i & RC_BSR_TOUT) 1285 ERR(("BSR timeout bit set\n")) 1286 else if (i & RC_BSR_TXINT) { 1287 iack = rcin(RC_PILR_TX); 1288 if (iack != (GIVR_IT_TDI | chipid)) 1289 ERR(("Bad TX intr ack (%02x != %02x)\n", 1290 iack, GIVR_IT_TDI | chipid)); 1291 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1292 /* If no more data to transmit, disable TX intr */ 1293 if (tchans[chan].txptr >= CD180_NFIFO) { 1294 iack = rcin(CD180_IER); 1295 rcout(CD180_IER, iack & ~IER_TxMpty); 1296 } else { 1297 for (iack = tchans[chan].txptr; 1298 iack < CD180_NFIFO; iack++) 1299 rcout(CD180_TDR, 1300 tchans[chan].txbuf[iack]); 1301 tchans[chan].txptr = iack; 1302 } 1303 rcout(CD180_EOIR, 0); 1304 } else if (i & RC_BSR_RXINT) { 1305 u_char ucnt; 1306 1307 iack = rcin(RC_PILR_RX); 1308 if (iack != (GIVR_IT_RGDI | chipid) && 1309 iack != (GIVR_IT_REI | chipid)) 1310 ERR(("Bad RX intr ack (%02x != %02x)\n", 1311 iack, GIVR_IT_RGDI | chipid)) 1312 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1313 ucnt = rcin(CD180_RDCR) & 0xF; 1314 while (ucnt-- > 0) { 1315 iack = rcin(CD180_RCSR); 1316 if (iack & RCSR_Timeout) 1317 break; 1318 if (iack & 0xF) 1319 ERR(("Bad char chan %d (RCSR = %02X)\n", 1320 chan, iack)) 1321 if (tchans[chan].rxptr > CD180_NFIFO) 1322 ERR(("Got extra chars chan %d\n", 1323 chan)) 1324 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1325 rcin(CD180_RDR); 1326 } 1327 rcout(CD180_EOIR, 0); 1328 } 1329 rcout(RC_CTOUT, 0); 1330 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1331 if (tchans[chan].rxptr >= CD180_NFIFO) 1332 iack++; 1333 if (iack == CD180_NCHAN) 1334 break; 1335 } 1336 for (chan = 0; chan < CD180_NCHAN; chan++) { 1337 /* Select and reset channel */ 1338 rcout(CD180_CAR, chan); 1339 CCRCMD(unit, chan, CCR_ResetChan); 1340 } 1341 1342 if (!rcnt) 1343 ERR(("looses characters during local loopback\n")) 1344 /* Now, check data */ 1345 for (chan = 0; chan < CD180_NCHAN; chan++) 1346 for (i = 0; i < CD180_NFIFO; i++) 1347 if (ctest[i] != tchans[chan].rxbuf[i]) 1348 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1349 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1350 (void) splx(old_level); 1351 return 0; 1352} 1353 1354#ifdef RCDEBUG 1355static void printrcflags(rc, comment) 1356struct rc_chans *rc; 1357char *comment; 1358{ 1359 u_short f = rc->rc_flags; 1360 register int nec = rc->rc_rcb->rcb_addr; 1361 1362 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1363 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1364 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1365 (f & RC_ACTOUT) ?"ACTOUT " :"", 1366 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1367 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1368 (f & RC_DORXFER)?"DORXFER " :"", 1369 (f & RC_DOXXFER)?"DOXXFER " :"", 1370 (f & RC_MODCHG) ?"MODCHG " :"", 1371 (f & RC_OSUSP) ?"OSUSP " :"", 1372 (f & RC_OSBUSY) ?"OSBUSY " :"", 1373 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1374 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1375 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1376 1377 rcout(CD180_CAR, rc->rc_chan); 1378 1379 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1380 rc->rc_rcb->rcb_unit, rc->rc_chan, 1381 rcin(CD180_MSVR), 1382 rcin(CD180_IER), 1383 rcin(CD180_CCSR)); 1384} 1385#endif /* RCDEBUG */ 1386 1387static void 1388rc_dtrwakeup(chan) 1389 void *chan; 1390{ 1391 struct rc_chans *rc; 1392 1393 rc = (struct rc_chans *)chan; 1394 rc->rc_flags &= ~RC_DTR_OFF; 1395 wakeup(&rc->rc_dtrwait); 1396} 1397 1398static void 1399rc_discard_output(rc) 1400 struct rc_chans *rc; 1401{ 1402 disable_intr(); 1403 if (rc->rc_flags & RC_DOXXFER) { 1404 rc_scheduled_event -= LOTS_OF_EVENTS; 1405 rc->rc_flags &= ~RC_DOXXFER; 1406 } 1407 rc->rc_optr = rc->rc_obufend; 1408 rc->rc_tp->t_state &= ~TS_BUSY; 1409 enable_intr(); 1410 ttwwakeup(rc->rc_tp); 1411} 1412 1413static void 1414rc_wakeup(chan) 1415 void *chan; 1416{ 1417 timeout(rc_wakeup, (caddr_t)NULL, 1); 1418 1419 if (rc_scheduled_event != 0) { 1420 int s; 1421 1422 s = splsofttty(); 1423 rcpoll(NULL); 1424 splx(s); 1425 } 1426} 1427 1428static void 1429disc_optim(tp, t, rc) 1430 struct tty *tp; 1431 struct termios *t; 1432 struct rc_chans *rc; 1433{ 1434 1435 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1436 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1437 && (!(t->c_iflag & PARMRK) 1438 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1439 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1440 && linesw[tp->t_line].l_rint == ttyinput) 1441 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1442 else 1443 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1444 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1445} 1446 1447static void 1448rc_wait0(nec, unit, chan, line) 1449 int nec, unit, chan, line; 1450{ 1451 int rcnt; 1452 1453 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1454 DELAY(30); 1455 if (rcnt == 0) 1456 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1457 unit, chan, line); 1458} 1459