rc.c revision 72244
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/rc/rc.c 72244 2001-02-09 18:35:53Z jhb $ 28 * 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36#include "rc.h" 37 38/*#define RCDEBUG*/ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/ipl.h> 43#include <sys/kernel.h> 44#include <sys/tty.h> 45#include <sys/conf.h> 46#include <sys/dkstat.h> 47#include <sys/fcntl.h> 48#include <sys/bus.h> 49#include <sys/interrupt.h> 50#include <sys/ipl.h> 51 52 53#include <i386/isa/isa_device.h> 54 55#include <i386/isa/ic/cd180.h> 56#include <i386/isa/rcreg.h> 57 58/* Prototypes */ 59static int rcprobe __P((struct isa_device *)); 60static int rcattach __P((struct isa_device *)); 61 62#define rcin(port) RC_IN (nec, port) 63#define rcout(port,v) RC_OUT (nec, port, v) 64 65#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 66#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 67 68#define RC_IBUFSIZE 256 69#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 70#define RC_OBUFSIZE 512 71#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 72#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 73#define LOTS_OF_EVENTS 64 74 75#define RC_FAKEID 0x10 76 77#define RC_PROBED 1 78#define RC_ATTACHED 2 79 80#define GET_UNIT(dev) (minor(dev) & 0x3F) 81#define CALLOUT(dev) (minor(dev) & 0x80) 82 83/* For isa routines */ 84struct isa_driver rcdriver = { 85 INTR_TYPE_TTY, 86 rcprobe, 87 rcattach, 88 "rc" 89}; 90COMPAT_ISA_DRIVER(rc, rcdriver); 91 92static d_open_t rcopen; 93static d_close_t rcclose; 94static d_ioctl_t rcioctl; 95 96#define CDEV_MAJOR 63 97static struct cdevsw rc_cdevsw = { 98 /* open */ rcopen, 99 /* close */ rcclose, 100 /* read */ ttyread, 101 /* write */ ttywrite, 102 /* ioctl */ rcioctl, 103 /* poll */ ttypoll, 104 /* mmap */ nommap, 105 /* strategy */ nostrategy, 106 /* name */ "rc", 107 /* maj */ CDEV_MAJOR, 108 /* dump */ nodump, 109 /* psize */ nopsize, 110 /* flags */ D_TTY, 111 /* bmaj */ -1 112}; 113 114/* Per-board structure */ 115static struct rc_softc { 116 u_int rcb_probed; /* 1 - probed, 2 - attached */ 117 u_int rcb_addr; /* Base I/O addr */ 118 u_int rcb_unit; /* unit # */ 119 u_char rcb_dtr; /* DTR status */ 120 struct rc_chans *rcb_baserc; /* base rc ptr */ 121} rc_softc[NRC]; 122 123/* Per-channel structure */ 124static struct rc_chans { 125 struct rc_softc *rc_rcb; /* back ptr */ 126 u_short rc_flags; /* Misc. flags */ 127 int rc_chan; /* Channel # */ 128 u_char rc_ier; /* intr. enable reg */ 129 u_char rc_msvr; /* modem sig. status */ 130 u_char rc_cor2; /* options reg */ 131 u_char rc_pendcmd; /* special cmd pending */ 132 u_int rc_dtrwait; /* dtr timeout */ 133 u_int rc_dcdwaits; /* how many waits DCD in open */ 134 u_char rc_hotchar; /* end packed optimize */ 135 struct tty *rc_tp; /* tty struct */ 136 u_char *rc_iptr; /* Chars input buffer */ 137 u_char *rc_hiwat; /* hi-water mark */ 138 u_char *rc_bufend; /* end of buffer */ 139 u_char *rc_optr; /* ptr in output buf */ 140 u_char *rc_obufend; /* end of output buf */ 141 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 142 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 143} rc_chans[NRC * CD180_NCHAN]; 144 145static int rc_scheduled_event = 0; 146 147/* for pstat -t */ 148static struct tty rc_tty[NRC * CD180_NCHAN]; 149static const int nrc_tty = NRC * CD180_NCHAN; 150 151/* Flags */ 152#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 153#define RC_ACTOUT 0x0002 /* Dial-out port active */ 154#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 155#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 156#define RC_DORXFER 0x0010 /* RXFER event planned */ 157#define RC_DOXXFER 0x0020 /* XXFER event planned */ 158#define RC_MODCHG 0x0040 /* Modem status changed */ 159#define RC_OSUSP 0x0080 /* Output suspended */ 160#define RC_OSBUSY 0x0100 /* start() routine in progress */ 161#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 162#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 163#define RC_SEND_RDY 0x0800 /* ready to send */ 164 165/* Table for translation of RCSR status bits to internal form */ 166static int rc_rcsrt[16] = { 167 0, TTY_OE, TTY_FE, 168 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 169 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 170 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 171 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 172 TTY_BI|TTY_PE|TTY_FE|TTY_OE 173}; 174 175static void *rc_ih; 176 177/* Static prototypes */ 178static ointhand2_t rcintr; 179static void rc_hwreset __P((int, int, unsigned int)); 180static int rc_test __P((int, int)); 181static void rc_discard_output __P((struct rc_chans *)); 182static void rc_hardclose __P((struct rc_chans *)); 183static int rc_modctl __P((struct rc_chans *, int, int)); 184static void rc_start __P((struct tty *)); 185static void rc_stop __P((struct tty *, int rw)); 186static int rc_param __P((struct tty *, struct termios *)); 187static void rcpoll __P((void *)); 188static void rc_reinit __P((struct rc_softc *)); 189#ifdef RCDEBUG 190static void printrcflags(); 191#endif 192static timeout_t rc_dtrwakeup; 193static timeout_t rc_wakeup; 194static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 195static void rc_wait0 __P((int nec, int unit, int chan, int line)); 196 197/**********************************************/ 198 199/* Quick device probing */ 200static int 201rcprobe(dvp) 202 struct isa_device *dvp; 203{ 204 int irq = ffs(dvp->id_irq) - 1; 205 register int nec = dvp->id_iobase; 206 207 if (dvp->id_unit > NRC) 208 return 0; 209 if (!RC_VALIDADDR(nec)) { 210 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec); 211 return 0; 212 } 213 if (!RC_VALIDIRQ(irq)) { 214 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq); 215 return 0; 216 } 217 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 218 rcout(CD180_PPRH, 0x11); 219 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 220 return 0; 221 /* Now, test the board more thoroughly, with diagnostic */ 222 if (rc_test(nec, dvp->id_unit)) 223 return 0; 224 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 225 226 return 0xF; 227} 228 229static int 230rcattach(dvp) 231 struct isa_device *dvp; 232{ 233 register int chan, nec = dvp->id_iobase; 234 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 235 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 236 static int rc_started = 0; 237 struct tty *tp; 238 239 dvp->id_ointr = rcintr; 240 241 /* Thorooughly test the device */ 242 if (rcb->rcb_probed != RC_PROBED) 243 return 0; 244 rcb->rcb_addr = nec; 245 rcb->rcb_dtr = 0; 246 rcb->rcb_baserc = rc; 247 rcb->rcb_unit = dvp->id_unit; 248 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 249 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit, 250 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 251 252 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 253 rc->rc_rcb = rcb; 254 rc->rc_chan = chan; 255 rc->rc_iptr = rc->rc_ibuf; 256 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 257 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 258 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 259 rc->rc_cor2 = rc->rc_pendcmd = 0; 260 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 261 rc->rc_dtrwait = 3 * hz; 262 rc->rc_dcdwaits= 0; 263 rc->rc_hotchar = 0; 264 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)]; 265 ttychars(tp); 266 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 267 tp->t_cflag = TTYDEF_CFLAG; 268 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 269 } 270 rcb->rcb_probed = RC_ATTACHED; 271 if (!rc_started) { 272 cdevsw_add(&rc_cdevsw); 273 swi_add(&tty_ithd, "tty:rc", rcpoll, NULL, SWI_TTY, 0, &rc_ih); 274 rc_wakeup((void *)NULL); 275 rc_started = 1; 276 } 277 return 1; 278} 279 280/* RC interrupt handling */ 281static void 282rcintr(unit) 283 int unit; 284{ 285 register struct rc_softc *rcb = &rc_softc[unit]; 286 register struct rc_chans *rc; 287 register int nec, resid; 288 register u_char val, iack, bsr, ucnt, *optr; 289 int good_data, t_state; 290 291 if (rcb->rcb_probed != RC_ATTACHED) { 292 printf("rc%d: bogus interrupt\n", unit); 293 return; 294 } 295 nec = rcb->rcb_addr; 296 297 bsr = ~(rcin(RC_BSR)); 298 299 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 300 printf("rc%d: extra interrupt\n", unit); 301 rcout(CD180_EOIR, 0); 302 return; 303 } 304 305 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 306#ifdef RCDEBUG_DETAILED 307 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 308 (bsr & RC_BSR_TOUT)?"TOUT ":"", 309 (bsr & RC_BSR_RXINT)?"RXINT ":"", 310 (bsr & RC_BSR_TXINT)?"TXINT ":"", 311 (bsr & RC_BSR_MOINT)?"MOINT":""); 312#endif 313 if (bsr & RC_BSR_TOUT) { 314 printf("rc%d: hardware failure, reset board\n", unit); 315 rcout(RC_CTOUT, 0); 316 rc_reinit(rcb); 317 return; 318 } 319 if (bsr & RC_BSR_RXINT) { 320 iack = rcin(RC_PILR_RX); 321 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 322 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 323 printf("rc%d: fake rxint: %02x\n", unit, iack); 324 goto more_intrs; 325 } 326 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 327 t_state = rc->rc_tp->t_state; 328 /* Do RTS flow control stuff */ 329 if ( (rc->rc_flags & RC_RTSFLOW) 330 || !(t_state & TS_ISOPEN) 331 ) { 332 if ( ( !(t_state & TS_ISOPEN) 333 || (t_state & TS_TBLOCK) 334 ) 335 && (rc->rc_msvr & MSVR_RTS) 336 ) 337 rcout(CD180_MSVR, 338 rc->rc_msvr &= ~MSVR_RTS); 339 else if (!(rc->rc_msvr & MSVR_RTS)) 340 rcout(CD180_MSVR, 341 rc->rc_msvr |= MSVR_RTS); 342 } 343 ucnt = rcin(CD180_RDCR) & 0xF; 344 resid = 0; 345 346 if (t_state & TS_ISOPEN) { 347 /* check for input buffer overflow */ 348 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 349 resid = ucnt; 350 ucnt = rc->rc_bufend - rc->rc_iptr; 351 resid -= ucnt; 352 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 353 rc->rc_flags |= RC_WAS_BUFOVFL; 354 rc_scheduled_event++; 355 } 356 } 357 optr = rc->rc_iptr; 358 /* check foor good data */ 359 if (good_data) { 360 while (ucnt-- > 0) { 361 val = rcin(CD180_RDR); 362 optr[0] = val; 363 optr[INPUT_FLAGS_SHIFT] = 0; 364 optr++; 365 rc_scheduled_event++; 366 if (val != 0 && val == rc->rc_hotchar) 367 swi_sched(rc_ih, SWI_NOSWITCH); 368 } 369 } else { 370 /* Store also status data */ 371 while (ucnt-- > 0) { 372 iack = rcin(CD180_RCSR); 373 if (iack & RCSR_Timeout) 374 break; 375 if ( (iack & RCSR_OE) 376 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 377 rc->rc_flags |= RC_WAS_SILOVFL; 378 rc_scheduled_event++; 379 } 380 val = rcin(CD180_RDR); 381 /* 382 Don't store PE if IGNPAR and BREAK if IGNBRK, 383 this hack allows "raw" tty optimization 384 works even if IGN* is set. 385 */ 386 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 387 || ((!(iack & (RCSR_PE|RCSR_FE)) 388 || !(rc->rc_tp->t_iflag & IGNPAR)) 389 && (!(iack & RCSR_Break) 390 || !(rc->rc_tp->t_iflag & IGNBRK)))) { 391 if ( (iack & (RCSR_PE|RCSR_FE)) 392 && (t_state & TS_CAN_BYPASS_L_RINT) 393 && ((iack & RCSR_FE) 394 || ((iack & RCSR_PE) 395 && (rc->rc_tp->t_iflag & INPCK)))) 396 val = 0; 397 else if (val != 0 && val == rc->rc_hotchar) 398 swi_sched(rc_ih, SWI_NOSWITCH); 399 optr[0] = val; 400 optr[INPUT_FLAGS_SHIFT] = iack; 401 optr++; 402 rc_scheduled_event++; 403 } 404 } 405 } 406 rc->rc_iptr = optr; 407 rc->rc_flags |= RC_DORXFER; 408 } else 409 resid = ucnt; 410 /* Clear FIFO if necessary */ 411 while (resid-- > 0) { 412 if (!good_data) 413 iack = rcin(CD180_RCSR); 414 else 415 iack = 0; 416 if (iack & RCSR_Timeout) 417 break; 418 (void) rcin(CD180_RDR); 419 } 420 goto more_intrs; 421 } 422 if (bsr & RC_BSR_MOINT) { 423 iack = rcin(RC_PILR_MODEM); 424 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 425 printf("rc%d: fake moint: %02x\n", unit, iack); 426 goto more_intrs; 427 } 428 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 429 iack = rcin(CD180_MCR); 430 rc->rc_msvr = rcin(CD180_MSVR); 431 rcout(CD180_MCR, 0); 432#ifdef RCDEBUG 433 printrcflags(rc, "moint"); 434#endif 435 if (rc->rc_flags & RC_CTSFLOW) { 436 if (rc->rc_msvr & MSVR_CTS) 437 rc->rc_flags |= RC_SEND_RDY; 438 else 439 rc->rc_flags &= ~RC_SEND_RDY; 440 } else 441 rc->rc_flags |= RC_SEND_RDY; 442 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 443 rc_scheduled_event += LOTS_OF_EVENTS; 444 rc->rc_flags |= RC_MODCHG; 445 swi_sched(rc_ih, SWI_NOSWITCH); 446 } 447 goto more_intrs; 448 } 449 if (bsr & RC_BSR_TXINT) { 450 iack = rcin(RC_PILR_TX); 451 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 452 printf("rc%d: fake txint: %02x\n", unit, iack); 453 goto more_intrs; 454 } 455 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 456 if ( (rc->rc_flags & RC_OSUSP) 457 || !(rc->rc_flags & RC_SEND_RDY) 458 ) 459 goto more_intrs; 460 /* Handle breaks and other stuff */ 461 if (rc->rc_pendcmd) { 462 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 463 rcout(CD180_TDR, CD180_C_ESC); 464 rcout(CD180_TDR, rc->rc_pendcmd); 465 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 466 rc->rc_pendcmd = 0; 467 goto more_intrs; 468 } 469 optr = rc->rc_optr; 470 resid = rc->rc_obufend - optr; 471 if (resid > CD180_NFIFO) 472 resid = CD180_NFIFO; 473 while (resid-- > 0) 474 rcout(CD180_TDR, *optr++); 475 rc->rc_optr = optr; 476 477 /* output completed? */ 478 if (optr >= rc->rc_obufend) { 479 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 480#ifdef RCDEBUG 481 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 482#endif 483 if (!(rc->rc_flags & RC_DOXXFER)) { 484 rc_scheduled_event += LOTS_OF_EVENTS; 485 rc->rc_flags |= RC_DOXXFER; 486 swi_sched(rc_ih, SWI_NOSWITCH); 487 } 488 } 489 } 490 more_intrs: 491 rcout(CD180_EOIR, 0); /* end of interrupt */ 492 rcout(RC_CTOUT, 0); 493 bsr = ~(rcin(RC_BSR)); 494 } 495} 496 497/* Feed characters to output buffer */ 498static void rc_start(tp) 499register struct tty *tp; 500{ 501 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 502 register int nec = rc->rc_rcb->rcb_addr, s; 503 504 if (rc->rc_flags & RC_OSBUSY) 505 return; 506 s = spltty(); 507 rc->rc_flags |= RC_OSBUSY; 508 disable_intr(); 509 if (tp->t_state & TS_TTSTOP) 510 rc->rc_flags |= RC_OSUSP; 511 else 512 rc->rc_flags &= ~RC_OSUSP; 513 /* Do RTS flow control stuff */ 514 if ( (rc->rc_flags & RC_RTSFLOW) 515 && (tp->t_state & TS_TBLOCK) 516 && (rc->rc_msvr & MSVR_RTS) 517 ) { 518 rcout(CD180_CAR, rc->rc_chan); 519 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 520 } else if (!(rc->rc_msvr & MSVR_RTS)) { 521 rcout(CD180_CAR, rc->rc_chan); 522 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 523 } 524 enable_intr(); 525 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 526 goto out; 527#ifdef RCDEBUG 528 printrcflags(rc, "rcstart"); 529#endif 530 ttwwakeup(tp); 531#ifdef RCDEBUG 532 printf("rcstart: outq = %d obuf = %d\n", 533 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 534#endif 535 if (tp->t_state & TS_BUSY) 536 goto out; /* output still in progress ... */ 537 538 if (tp->t_outq.c_cc > 0) { 539 u_int ocnt; 540 541 tp->t_state |= TS_BUSY; 542 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 543 disable_intr(); 544 rc->rc_optr = rc->rc_obuf; 545 rc->rc_obufend = rc->rc_optr + ocnt; 546 enable_intr(); 547 if (!(rc->rc_ier & IER_TxRdy)) { 548#ifdef RCDEBUG 549 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 550#endif 551 rcout(CD180_CAR, rc->rc_chan); 552 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 553 } 554 } 555out: 556 rc->rc_flags &= ~RC_OSBUSY; 557 (void) splx(s); 558} 559 560/* Handle delayed events. */ 561void rcpoll(void *arg) 562{ 563 register struct rc_chans *rc; 564 register struct rc_softc *rcb; 565 register u_char *tptr, *eptr; 566 register struct tty *tp; 567 register int chan, icnt, nec, unit; 568 569 if (rc_scheduled_event == 0) 570 return; 571repeat: 572 for (unit = 0; unit < NRC; unit++) { 573 rcb = &rc_softc[unit]; 574 rc = rcb->rcb_baserc; 575 nec = rc->rc_rcb->rcb_addr; 576 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 577 tp = rc->rc_tp; 578#ifdef RCDEBUG 579 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 580 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 581 printrcflags(rc, "rcevent"); 582#endif 583 if (rc->rc_flags & RC_WAS_BUFOVFL) { 584 disable_intr(); 585 rc->rc_flags &= ~RC_WAS_BUFOVFL; 586 rc_scheduled_event--; 587 enable_intr(); 588 printf("rc%d/%d: interrupt-level buffer overflow\n", 589 unit, chan); 590 } 591 if (rc->rc_flags & RC_WAS_SILOVFL) { 592 disable_intr(); 593 rc->rc_flags &= ~RC_WAS_SILOVFL; 594 rc_scheduled_event--; 595 enable_intr(); 596 printf("rc%d/%d: silo overflow\n", 597 unit, chan); 598 } 599 if (rc->rc_flags & RC_MODCHG) { 600 disable_intr(); 601 rc->rc_flags &= ~RC_MODCHG; 602 rc_scheduled_event -= LOTS_OF_EVENTS; 603 enable_intr(); 604 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 605 } 606 if (rc->rc_flags & RC_DORXFER) { 607 disable_intr(); 608 rc->rc_flags &= ~RC_DORXFER; 609 eptr = rc->rc_iptr; 610 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 611 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 612 else 613 tptr = rc->rc_ibuf; 614 icnt = eptr - tptr; 615 if (icnt > 0) { 616 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 617 rc->rc_iptr = rc->rc_ibuf; 618 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 619 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 620 } else { 621 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 622 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 623 rc->rc_hiwat = 624 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 625 } 626 if ( (rc->rc_flags & RC_RTSFLOW) 627 && (tp->t_state & TS_ISOPEN) 628 && !(tp->t_state & TS_TBLOCK) 629 && !(rc->rc_msvr & MSVR_RTS) 630 ) { 631 rcout(CD180_CAR, chan); 632 rcout(CD180_MSVR, 633 rc->rc_msvr |= MSVR_RTS); 634 } 635 rc_scheduled_event -= icnt; 636 } 637 enable_intr(); 638 639 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 640 goto done1; 641 642 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 643 && !(tp->t_state & TS_LOCAL)) { 644 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 645 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 646 && !(tp->t_state & TS_TBLOCK)) 647 ttyblock(tp); 648 tk_nin += icnt; 649 tk_rawcc += icnt; 650 tp->t_rawcc += icnt; 651 if (b_to_q(tptr, icnt, &tp->t_rawq)) 652 printf("rc%d/%d: tty-level buffer overflow\n", 653 unit, chan); 654 ttwakeup(tp); 655 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 656 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 657 tp->t_state &= ~TS_TTSTOP; 658 tp->t_lflag &= ~FLUSHO; 659 rc_start(tp); 660 } 661 } else { 662 for (; tptr < eptr; tptr++) 663 (*linesw[tp->t_line].l_rint) 664 (tptr[0] | 665 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 666 } 667done1: ; 668 } 669 if (rc->rc_flags & RC_DOXXFER) { 670 disable_intr(); 671 rc_scheduled_event -= LOTS_OF_EVENTS; 672 rc->rc_flags &= ~RC_DOXXFER; 673 rc->rc_tp->t_state &= ~TS_BUSY; 674 enable_intr(); 675 (*linesw[tp->t_line].l_start)(tp); 676 } 677 } 678 if (rc_scheduled_event == 0) 679 break; 680 } 681 if (rc_scheduled_event >= LOTS_OF_EVENTS) 682 goto repeat; 683} 684 685static void 686rc_stop(tp, rw) 687 register struct tty *tp; 688 int rw; 689{ 690 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 691 u_char *tptr, *eptr; 692 693#ifdef RCDEBUG 694 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 695 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 696#endif 697 if (rw & FWRITE) 698 rc_discard_output(rc); 699 disable_intr(); 700 if (rw & FREAD) { 701 rc->rc_flags &= ~RC_DORXFER; 702 eptr = rc->rc_iptr; 703 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 704 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 705 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 706 } else { 707 tptr = rc->rc_ibuf; 708 rc->rc_iptr = rc->rc_ibuf; 709 } 710 rc_scheduled_event -= eptr - tptr; 711 } 712 if (tp->t_state & TS_TTSTOP) 713 rc->rc_flags |= RC_OSUSP; 714 else 715 rc->rc_flags &= ~RC_OSUSP; 716 enable_intr(); 717} 718 719static int 720rcopen(dev, flag, mode, p) 721 dev_t dev; 722 int flag, mode; 723 struct proc *p; 724{ 725 register struct rc_chans *rc; 726 register struct tty *tp; 727 int unit, nec, s, error = 0; 728 729 unit = GET_UNIT(dev); 730 if (unit >= NRC * CD180_NCHAN) 731 return ENXIO; 732 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 733 return ENXIO; 734 rc = &rc_chans[unit]; 735 tp = rc->rc_tp; 736 dev->si_tty = tp; 737 nec = rc->rc_rcb->rcb_addr; 738#ifdef RCDEBUG 739 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 740#endif 741 s = spltty(); 742 743again: 744 while (rc->rc_flags & RC_DTR_OFF) { 745 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 746 if (error != 0) 747 goto out; 748 } 749 if (tp->t_state & TS_ISOPEN) { 750 if (CALLOUT(dev)) { 751 if (!(rc->rc_flags & RC_ACTOUT)) { 752 error = EBUSY; 753 goto out; 754 } 755 } else { 756 if (rc->rc_flags & RC_ACTOUT) { 757 if (flag & O_NONBLOCK) { 758 error = EBUSY; 759 goto out; 760 } 761 error = tsleep(&rc->rc_rcb, 762 TTIPRI|PCATCH, "rcbi", 0); 763 if (error) 764 goto out; 765 goto again; 766 } 767 } 768 if (tp->t_state & TS_XCLUDE && 769 suser(p)) { 770 error = EBUSY; 771 goto out; 772 } 773 } else { 774 tp->t_oproc = rc_start; 775 tp->t_param = rc_param; 776 tp->t_stop = rc_stop; 777 tp->t_dev = dev; 778 779 if (CALLOUT(dev)) 780 tp->t_cflag |= CLOCAL; 781 else 782 tp->t_cflag &= ~CLOCAL; 783 784 error = rc_param(tp, &tp->t_termios); 785 if (error) 786 goto out; 787 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 788 789 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 790 (*linesw[tp->t_line].l_modem)(tp, 1); 791 } 792 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 793 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 794 rc->rc_dcdwaits++; 795 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 796 rc->rc_dcdwaits--; 797 if (error != 0) 798 goto out; 799 goto again; 800 } 801 error = (*linesw[tp->t_line].l_open)(dev, tp); 802 disc_optim(tp, &tp->t_termios, rc); 803 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 804 rc->rc_flags |= RC_ACTOUT; 805out: 806 (void) splx(s); 807 808 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 809 rc_hardclose(rc); 810 811 return error; 812} 813 814static int 815rcclose(dev, flag, mode, p) 816 dev_t dev; 817 int flag, mode; 818 struct proc *p; 819{ 820 register struct rc_chans *rc; 821 register struct tty *tp; 822 int s, unit = GET_UNIT(dev); 823 824 if (unit >= NRC * CD180_NCHAN) 825 return ENXIO; 826 rc = &rc_chans[unit]; 827 tp = rc->rc_tp; 828#ifdef RCDEBUG 829 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 830#endif 831 s = spltty(); 832 (*linesw[tp->t_line].l_close)(tp, flag); 833 disc_optim(tp, &tp->t_termios, rc); 834 rc_stop(tp, FREAD | FWRITE); 835 rc_hardclose(rc); 836 ttyclose(tp); 837 splx(s); 838 return 0; 839} 840 841static void rc_hardclose(rc) 842register struct rc_chans *rc; 843{ 844 register int s, nec = rc->rc_rcb->rcb_addr; 845 register struct tty *tp = rc->rc_tp; 846 847 s = spltty(); 848 rcout(CD180_CAR, rc->rc_chan); 849 850 /* Disable rx/tx intrs */ 851 rcout(CD180_IER, rc->rc_ier = 0); 852 if ( (tp->t_cflag & HUPCL) 853 || (!(rc->rc_flags & RC_ACTOUT) 854 && !(rc->rc_msvr & MSVR_CD) 855 && !(tp->t_cflag & CLOCAL)) 856 || !(tp->t_state & TS_ISOPEN) 857 ) { 858 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 859 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 860 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 861 if (rc->rc_dtrwait) { 862 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 863 rc->rc_flags |= RC_DTR_OFF; 864 } 865 } 866 rc->rc_flags &= ~RC_ACTOUT; 867 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 868 wakeup(TSA_CARR_ON(tp)); 869 (void) splx(s); 870} 871 872/* Reset the bastard */ 873static void rc_hwreset(unit, nec, chipid) 874 register int unit, nec; 875 unsigned int chipid; 876{ 877 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 878 DELAY(20000); 879 WAITFORCCR(unit, -1); 880 881 rcout(RC_CTOUT, 0); /* Clear timeout */ 882 rcout(CD180_GIVR, chipid); 883 rcout(CD180_GICR, 0); 884 885 /* Set Prescaler Registers (1 msec) */ 886 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 887 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 888 889 /* Initialize Priority Interrupt Level Registers */ 890 rcout(CD180_PILR1, RC_PILR_MODEM); 891 rcout(CD180_PILR2, RC_PILR_TX); 892 rcout(CD180_PILR3, RC_PILR_RX); 893 894 /* Reset DTR */ 895 rcout(RC_DTREG, ~0); 896} 897 898/* Set channel parameters */ 899static int rc_param(tp, ts) 900 register struct tty *tp; 901 struct termios *ts; 902{ 903 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 904 register int nec = rc->rc_rcb->rcb_addr; 905 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 906 907 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 908 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 909 ) 910 return (EINVAL); 911 if (ts->c_ispeed == 0) 912 ts->c_ispeed = ts->c_ospeed; 913 odivs = RC_BRD(ts->c_ospeed); 914 idivs = RC_BRD(ts->c_ispeed); 915 916 s = spltty(); 917 918 /* Select channel */ 919 rcout(CD180_CAR, rc->rc_chan); 920 921 /* If speed == 0, hangup line */ 922 if (ts->c_ospeed == 0) { 923 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 924 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 925 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 926 } 927 928 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 929 cflag = ts->c_cflag; 930 iflag = ts->c_iflag; 931 lflag = ts->c_lflag; 932 933 if (idivs > 0) { 934 rcout(CD180_RBPRL, idivs & 0xFF); 935 rcout(CD180_RBPRH, idivs >> 8); 936 } 937 if (odivs > 0) { 938 rcout(CD180_TBPRL, odivs & 0xFF); 939 rcout(CD180_TBPRH, odivs >> 8); 940 } 941 942 /* set timeout value */ 943 if (ts->c_ispeed > 0) { 944 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 945 946 if ( !(lflag & ICANON) 947 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 948 && ts->c_cc[VTIME] * 10 > itm) 949 itm = ts->c_cc[VTIME] * 10; 950 951 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 952 } 953 954 switch (cflag & CSIZE) { 955 case CS5: val = COR1_5BITS; break; 956 case CS6: val = COR1_6BITS; break; 957 case CS7: val = COR1_7BITS; break; 958 default: 959 case CS8: val = COR1_8BITS; break; 960 } 961 if (cflag & PARENB) { 962 val |= COR1_NORMPAR; 963 if (cflag & PARODD) 964 val |= COR1_ODDP; 965 if (!(cflag & INPCK)) 966 val |= COR1_Ignore; 967 } else 968 val |= COR1_Ignore; 969 if (cflag & CSTOPB) 970 val |= COR1_2SB; 971 rcout(CD180_COR1, val); 972 973 /* Set FIFO threshold */ 974 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 975 inpflow = 0; 976 if ( (iflag & IXOFF) 977 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 978 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 979 || (iflag & IXANY) 980 ) 981 ) 982 ) { 983 inpflow = 1; 984 val |= COR3_SCDE|COR3_FCT; 985 } 986 rcout(CD180_COR3, val); 987 988 /* Initialize on-chip automatic flow control */ 989 val = 0; 990 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 991 if (cflag & CCTS_OFLOW) { 992 rc->rc_flags |= RC_CTSFLOW; 993 val |= COR2_CtsAE; 994 } else 995 rc->rc_flags |= RC_SEND_RDY; 996 if (tp->t_state & TS_TTSTOP) 997 rc->rc_flags |= RC_OSUSP; 998 else 999 rc->rc_flags &= ~RC_OSUSP; 1000 if (cflag & CRTS_IFLOW) 1001 rc->rc_flags |= RC_RTSFLOW; 1002 else 1003 rc->rc_flags &= ~RC_RTSFLOW; 1004 1005 if (inpflow) { 1006 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1007 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1008 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1009 val |= COR2_TxIBE; 1010 if (iflag & IXANY) 1011 val |= COR2_IXM; 1012 } 1013 1014 rcout(CD180_COR2, rc->rc_cor2 = val); 1015 1016 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1017 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1018 1019 disc_optim(tp, ts, rc); 1020 1021 /* modem ctl */ 1022 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1023 if (cflag & CCTS_OFLOW) 1024 val |= MCOR1_CTSzd; 1025 rcout(CD180_MCOR1, val); 1026 1027 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1028 if (cflag & CCTS_OFLOW) 1029 val |= MCOR2_CTSod; 1030 rcout(CD180_MCOR2, val); 1031 1032 /* enable i/o and interrupts */ 1033 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1034 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1035 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1036 1037 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1038 if (cflag & CCTS_OFLOW) 1039 rc->rc_ier |= IER_CTS; 1040 if (cflag & CREAD) 1041 rc->rc_ier |= IER_RxData; 1042 if (tp->t_state & TS_BUSY) 1043 rc->rc_ier |= IER_TxRdy; 1044 if (ts->c_ospeed != 0) 1045 rc_modctl(rc, TIOCM_DTR, DMBIS); 1046 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1047 rc->rc_flags |= RC_SEND_RDY; 1048 rcout(CD180_IER, rc->rc_ier); 1049 (void) splx(s); 1050 return 0; 1051} 1052 1053/* Re-initialize board after bogus interrupts */ 1054static void rc_reinit(rcb) 1055struct rc_softc *rcb; 1056{ 1057 register struct rc_chans *rc, *rce; 1058 register int nec; 1059 1060 nec = rcb->rcb_addr; 1061 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1062 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1063 rce = rc + CD180_NCHAN; 1064 for (; rc < rce; rc++) 1065 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1066} 1067 1068static int 1069rcioctl(dev, cmd, data, flag, p) 1070dev_t dev; 1071u_long cmd; 1072int flag; 1073caddr_t data; 1074struct proc *p; 1075{ 1076 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1077 register int s, error; 1078 struct tty *tp = rc->rc_tp; 1079 1080 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1081 if (error != ENOIOCTL) 1082 return (error); 1083 error = ttioctl(tp, cmd, data, flag); 1084 disc_optim(tp, &tp->t_termios, rc); 1085 if (error != ENOIOCTL) 1086 return (error); 1087 s = spltty(); 1088 1089 switch (cmd) { 1090 case TIOCSBRK: 1091 rc->rc_pendcmd = CD180_C_SBRK; 1092 break; 1093 1094 case TIOCCBRK: 1095 rc->rc_pendcmd = CD180_C_EBRK; 1096 break; 1097 1098 case TIOCSDTR: 1099 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1100 break; 1101 1102 case TIOCCDTR: 1103 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1104 break; 1105 1106 case TIOCMGET: 1107 *(int *) data = rc_modctl(rc, 0, DMGET); 1108 break; 1109 1110 case TIOCMSET: 1111 (void) rc_modctl(rc, *(int *) data, DMSET); 1112 break; 1113 1114 case TIOCMBIC: 1115 (void) rc_modctl(rc, *(int *) data, DMBIC); 1116 break; 1117 1118 case TIOCMBIS: 1119 (void) rc_modctl(rc, *(int *) data, DMBIS); 1120 break; 1121 1122 case TIOCMSDTRWAIT: 1123 error = suser(p); 1124 if (error != 0) { 1125 splx(s); 1126 return (error); 1127 } 1128 rc->rc_dtrwait = *(int *)data * hz / 100; 1129 break; 1130 1131 case TIOCMGDTRWAIT: 1132 *(int *)data = rc->rc_dtrwait * 100 / hz; 1133 break; 1134 1135 default: 1136 (void) splx(s); 1137 return ENOTTY; 1138 } 1139 (void) splx(s); 1140 return 0; 1141} 1142 1143 1144/* Modem control routines */ 1145 1146static int rc_modctl(rc, bits, cmd) 1147register struct rc_chans *rc; 1148int bits, cmd; 1149{ 1150 register int nec = rc->rc_rcb->rcb_addr; 1151 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1152 1153 rcout(CD180_CAR, rc->rc_chan); 1154 1155 switch (cmd) { 1156 case DMSET: 1157 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1158 ~(*dtr |= 1 << rc->rc_chan) : 1159 ~(*dtr &= ~(1 << rc->rc_chan))); 1160 msvr = rcin(CD180_MSVR); 1161 if (bits & TIOCM_RTS) 1162 msvr |= MSVR_RTS; 1163 else 1164 msvr &= ~MSVR_RTS; 1165 if (bits & TIOCM_DTR) 1166 msvr |= MSVR_DTR; 1167 else 1168 msvr &= ~MSVR_DTR; 1169 rcout(CD180_MSVR, msvr); 1170 break; 1171 1172 case DMBIS: 1173 if (bits & TIOCM_DTR) 1174 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1175 msvr = rcin(CD180_MSVR); 1176 if (bits & TIOCM_RTS) 1177 msvr |= MSVR_RTS; 1178 if (bits & TIOCM_DTR) 1179 msvr |= MSVR_DTR; 1180 rcout(CD180_MSVR, msvr); 1181 break; 1182 1183 case DMGET: 1184 bits = TIOCM_LE; 1185 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1186 1187 if (msvr & MSVR_RTS) 1188 bits |= TIOCM_RTS; 1189 if (msvr & MSVR_CTS) 1190 bits |= TIOCM_CTS; 1191 if (msvr & MSVR_DSR) 1192 bits |= TIOCM_DSR; 1193 if (msvr & MSVR_DTR) 1194 bits |= TIOCM_DTR; 1195 if (msvr & MSVR_CD) 1196 bits |= TIOCM_CD; 1197 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1198 bits |= TIOCM_RI; 1199 return bits; 1200 1201 case DMBIC: 1202 if (bits & TIOCM_DTR) 1203 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1204 msvr = rcin(CD180_MSVR); 1205 if (bits & TIOCM_RTS) 1206 msvr &= ~MSVR_RTS; 1207 if (bits & TIOCM_DTR) 1208 msvr &= ~MSVR_DTR; 1209 rcout(CD180_MSVR, msvr); 1210 break; 1211 } 1212 rc->rc_msvr = rcin(CD180_MSVR); 1213 return 0; 1214} 1215 1216/* Test the board. */ 1217int rc_test(nec, unit) 1218 register int nec; 1219 int unit; 1220{ 1221 int chan = 0; 1222 int i = 0, rcnt, old_level; 1223 unsigned int iack, chipid; 1224 unsigned short divs; 1225 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1226#define CTLEN 8 1227#define ERR(s) { \ 1228 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1229 (void) splx(old_level); return 1; } 1230 1231 struct rtest { 1232 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1233 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1234 int rxptr; /* RX pointer */ 1235 int txptr; /* TX pointer */ 1236 } tchans[CD180_NCHAN]; 1237 1238 old_level = spltty(); 1239 1240 chipid = RC_FAKEID; 1241 1242 /* First, reset board to inital state */ 1243 rc_hwreset(unit, nec, chipid); 1244 1245 divs = RC_BRD(19200); 1246 1247 /* Initialize channels */ 1248 for (chan = 0; chan < CD180_NCHAN; chan++) { 1249 1250 /* Select and reset channel */ 1251 rcout(CD180_CAR, chan); 1252 CCRCMD(unit, chan, CCR_ResetChan); 1253 WAITFORCCR(unit, chan); 1254 1255 /* Set speed */ 1256 rcout(CD180_RBPRL, divs & 0xFF); 1257 rcout(CD180_RBPRH, divs >> 8); 1258 rcout(CD180_TBPRL, divs & 0xFF); 1259 rcout(CD180_TBPRH, divs >> 8); 1260 1261 /* set timeout value */ 1262 rcout(CD180_RTPR, 0); 1263 1264 /* Establish local loopback */ 1265 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1266 rcout(CD180_COR2, COR2_LLM); 1267 rcout(CD180_COR3, CD180_NFIFO); 1268 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1269 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1270 WAITFORCCR(unit, chan); 1271 rcout(CD180_MSVR, MSVR_RTS); 1272 1273 /* Fill TXBUF with test data */ 1274 for (i = 0; i < CD180_NFIFO; i++) { 1275 tchans[chan].txbuf[i] = ctest[i]; 1276 tchans[chan].rxbuf[i] = 0; 1277 } 1278 tchans[chan].txptr = tchans[chan].rxptr = 0; 1279 1280 /* Now, start transmit */ 1281 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1282 } 1283 /* Pseudo-interrupt poll stuff */ 1284 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1285 i = ~(rcin(RC_BSR)); 1286 if (i & RC_BSR_TOUT) 1287 ERR(("BSR timeout bit set\n")) 1288 else if (i & RC_BSR_TXINT) { 1289 iack = rcin(RC_PILR_TX); 1290 if (iack != (GIVR_IT_TDI | chipid)) 1291 ERR(("Bad TX intr ack (%02x != %02x)\n", 1292 iack, GIVR_IT_TDI | chipid)); 1293 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1294 /* If no more data to transmit, disable TX intr */ 1295 if (tchans[chan].txptr >= CD180_NFIFO) { 1296 iack = rcin(CD180_IER); 1297 rcout(CD180_IER, iack & ~IER_TxMpty); 1298 } else { 1299 for (iack = tchans[chan].txptr; 1300 iack < CD180_NFIFO; iack++) 1301 rcout(CD180_TDR, 1302 tchans[chan].txbuf[iack]); 1303 tchans[chan].txptr = iack; 1304 } 1305 rcout(CD180_EOIR, 0); 1306 } else if (i & RC_BSR_RXINT) { 1307 u_char ucnt; 1308 1309 iack = rcin(RC_PILR_RX); 1310 if (iack != (GIVR_IT_RGDI | chipid) && 1311 iack != (GIVR_IT_REI | chipid)) 1312 ERR(("Bad RX intr ack (%02x != %02x)\n", 1313 iack, GIVR_IT_RGDI | chipid)) 1314 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1315 ucnt = rcin(CD180_RDCR) & 0xF; 1316 while (ucnt-- > 0) { 1317 iack = rcin(CD180_RCSR); 1318 if (iack & RCSR_Timeout) 1319 break; 1320 if (iack & 0xF) 1321 ERR(("Bad char chan %d (RCSR = %02X)\n", 1322 chan, iack)) 1323 if (tchans[chan].rxptr > CD180_NFIFO) 1324 ERR(("Got extra chars chan %d\n", 1325 chan)) 1326 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1327 rcin(CD180_RDR); 1328 } 1329 rcout(CD180_EOIR, 0); 1330 } 1331 rcout(RC_CTOUT, 0); 1332 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1333 if (tchans[chan].rxptr >= CD180_NFIFO) 1334 iack++; 1335 if (iack == CD180_NCHAN) 1336 break; 1337 } 1338 for (chan = 0; chan < CD180_NCHAN; chan++) { 1339 /* Select and reset channel */ 1340 rcout(CD180_CAR, chan); 1341 CCRCMD(unit, chan, CCR_ResetChan); 1342 } 1343 1344 if (!rcnt) 1345 ERR(("looses characters during local loopback\n")) 1346 /* Now, check data */ 1347 for (chan = 0; chan < CD180_NCHAN; chan++) 1348 for (i = 0; i < CD180_NFIFO; i++) 1349 if (ctest[i] != tchans[chan].rxbuf[i]) 1350 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1351 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1352 (void) splx(old_level); 1353 return 0; 1354} 1355 1356#ifdef RCDEBUG 1357static void printrcflags(rc, comment) 1358struct rc_chans *rc; 1359char *comment; 1360{ 1361 u_short f = rc->rc_flags; 1362 register int nec = rc->rc_rcb->rcb_addr; 1363 1364 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1365 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1366 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1367 (f & RC_ACTOUT) ?"ACTOUT " :"", 1368 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1369 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1370 (f & RC_DORXFER)?"DORXFER " :"", 1371 (f & RC_DOXXFER)?"DOXXFER " :"", 1372 (f & RC_MODCHG) ?"MODCHG " :"", 1373 (f & RC_OSUSP) ?"OSUSP " :"", 1374 (f & RC_OSBUSY) ?"OSBUSY " :"", 1375 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1376 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1377 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1378 1379 rcout(CD180_CAR, rc->rc_chan); 1380 1381 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1382 rc->rc_rcb->rcb_unit, rc->rc_chan, 1383 rcin(CD180_MSVR), 1384 rcin(CD180_IER), 1385 rcin(CD180_CCSR)); 1386} 1387#endif /* RCDEBUG */ 1388 1389static void 1390rc_dtrwakeup(chan) 1391 void *chan; 1392{ 1393 struct rc_chans *rc; 1394 1395 rc = (struct rc_chans *)chan; 1396 rc->rc_flags &= ~RC_DTR_OFF; 1397 wakeup(&rc->rc_dtrwait); 1398} 1399 1400static void 1401rc_discard_output(rc) 1402 struct rc_chans *rc; 1403{ 1404 disable_intr(); 1405 if (rc->rc_flags & RC_DOXXFER) { 1406 rc_scheduled_event -= LOTS_OF_EVENTS; 1407 rc->rc_flags &= ~RC_DOXXFER; 1408 } 1409 rc->rc_optr = rc->rc_obufend; 1410 rc->rc_tp->t_state &= ~TS_BUSY; 1411 enable_intr(); 1412 ttwwakeup(rc->rc_tp); 1413} 1414 1415static void 1416rc_wakeup(chan) 1417 void *chan; 1418{ 1419 timeout(rc_wakeup, (caddr_t)NULL, 1); 1420 1421 if (rc_scheduled_event != 0) { 1422 int s; 1423 1424 s = splsofttty(); 1425 rcpoll(NULL); 1426 splx(s); 1427 } 1428} 1429 1430static void 1431disc_optim(tp, t, rc) 1432 struct tty *tp; 1433 struct termios *t; 1434 struct rc_chans *rc; 1435{ 1436 1437 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1438 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1439 && (!(t->c_iflag & PARMRK) 1440 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1441 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1442 && linesw[tp->t_line].l_rint == ttyinput) 1443 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1444 else 1445 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1446 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1447} 1448 1449static void 1450rc_wait0(nec, unit, chan, line) 1451 int nec, unit, chan, line; 1452{ 1453 int rcnt; 1454 1455 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1456 DELAY(30); 1457 if (rcnt == 0) 1458 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1459 unit, chan, line); 1460} 1461