rc.c revision 67585
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/rc/rc.c 67585 2000-10-25 21:24:08Z jhb $ 28 * 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36#include "rc.h" 37 38/*#define RCDEBUG*/ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/ipl.h> 43#include <sys/kernel.h> 44#include <sys/tty.h> 45#include <sys/proc.h> 46#include <sys/conf.h> 47#include <sys/dkstat.h> 48#include <sys/fcntl.h> 49#include <sys/bus.h> 50#include <sys/interrupt.h> 51#include <sys/ipl.h> 52 53 54#include <i386/isa/isa_device.h> 55 56#include <i386/isa/ic/cd180.h> 57#include <i386/isa/rcreg.h> 58 59/* Prototypes */ 60static int rcprobe __P((struct isa_device *)); 61static int rcattach __P((struct isa_device *)); 62 63#define rcin(port) RC_IN (nec, port) 64#define rcout(port,v) RC_OUT (nec, port, v) 65 66#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 67#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 68 69#define RC_IBUFSIZE 256 70#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 71#define RC_OBUFSIZE 512 72#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 73#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 74#define LOTS_OF_EVENTS 64 75 76#define RC_FAKEID 0x10 77 78#define RC_PROBED 1 79#define RC_ATTACHED 2 80 81#define GET_UNIT(dev) (minor(dev) & 0x3F) 82#define CALLOUT(dev) (minor(dev) & 0x80) 83 84/* For isa routines */ 85struct isa_driver rcdriver = { 86 INTR_TYPE_TTY, 87 rcprobe, 88 rcattach, 89 "rc" 90}; 91COMPAT_ISA_DRIVER(rc, rcdriver); 92 93static d_open_t rcopen; 94static d_close_t rcclose; 95static d_ioctl_t rcioctl; 96 97#define CDEV_MAJOR 63 98static struct cdevsw rc_cdevsw = { 99 /* open */ rcopen, 100 /* close */ rcclose, 101 /* read */ ttyread, 102 /* write */ ttywrite, 103 /* ioctl */ rcioctl, 104 /* poll */ ttypoll, 105 /* mmap */ nommap, 106 /* strategy */ nostrategy, 107 /* name */ "rc", 108 /* maj */ CDEV_MAJOR, 109 /* dump */ nodump, 110 /* psize */ nopsize, 111 /* flags */ D_TTY, 112 /* bmaj */ -1 113}; 114 115/* Per-board structure */ 116static struct rc_softc { 117 u_int rcb_probed; /* 1 - probed, 2 - attached */ 118 u_int rcb_addr; /* Base I/O addr */ 119 u_int rcb_unit; /* unit # */ 120 u_char rcb_dtr; /* DTR status */ 121 struct rc_chans *rcb_baserc; /* base rc ptr */ 122} rc_softc[NRC]; 123 124/* Per-channel structure */ 125static struct rc_chans { 126 struct rc_softc *rc_rcb; /* back ptr */ 127 u_short rc_flags; /* Misc. flags */ 128 int rc_chan; /* Channel # */ 129 u_char rc_ier; /* intr. enable reg */ 130 u_char rc_msvr; /* modem sig. status */ 131 u_char rc_cor2; /* options reg */ 132 u_char rc_pendcmd; /* special cmd pending */ 133 u_int rc_dtrwait; /* dtr timeout */ 134 u_int rc_dcdwaits; /* how many waits DCD in open */ 135 u_char rc_hotchar; /* end packed optimize */ 136 struct tty *rc_tp; /* tty struct */ 137 u_char *rc_iptr; /* Chars input buffer */ 138 u_char *rc_hiwat; /* hi-water mark */ 139 u_char *rc_bufend; /* end of buffer */ 140 u_char *rc_optr; /* ptr in output buf */ 141 u_char *rc_obufend; /* end of output buf */ 142 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 143 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 144} rc_chans[NRC * CD180_NCHAN]; 145 146static int rc_scheduled_event = 0; 147 148/* for pstat -t */ 149static struct tty rc_tty[NRC * CD180_NCHAN]; 150static const int nrc_tty = NRC * CD180_NCHAN; 151 152/* Flags */ 153#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 154#define RC_ACTOUT 0x0002 /* Dial-out port active */ 155#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 156#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 157#define RC_DORXFER 0x0010 /* RXFER event planned */ 158#define RC_DOXXFER 0x0020 /* XXFER event planned */ 159#define RC_MODCHG 0x0040 /* Modem status changed */ 160#define RC_OSUSP 0x0080 /* Output suspended */ 161#define RC_OSBUSY 0x0100 /* start() routine in progress */ 162#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 163#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 164#define RC_SEND_RDY 0x0800 /* ready to send */ 165 166/* Table for translation of RCSR status bits to internal form */ 167static int rc_rcsrt[16] = { 168 0, TTY_OE, TTY_FE, 169 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 170 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 171 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 172 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 173 TTY_BI|TTY_PE|TTY_FE|TTY_OE 174}; 175 176static struct intrhand *rc_ih; 177 178/* Static prototypes */ 179static ointhand2_t rcintr; 180static void rc_hwreset __P((int, int, unsigned int)); 181static int rc_test __P((int, int)); 182static void rc_discard_output __P((struct rc_chans *)); 183static void rc_hardclose __P((struct rc_chans *)); 184static int rc_modctl __P((struct rc_chans *, int, int)); 185static void rc_start __P((struct tty *)); 186static void rc_stop __P((struct tty *, int rw)); 187static int rc_param __P((struct tty *, struct termios *)); 188static void rcpoll __P((void *)); 189static void rc_reinit __P((struct rc_softc *)); 190#ifdef RCDEBUG 191static void printrcflags(); 192#endif 193static timeout_t rc_dtrwakeup; 194static timeout_t rc_wakeup; 195static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 196static void rc_wait0 __P((int nec, int unit, int chan, int line)); 197 198/**********************************************/ 199 200/* Quick device probing */ 201static int 202rcprobe(dvp) 203 struct isa_device *dvp; 204{ 205 int irq = ffs(dvp->id_irq) - 1; 206 register int nec = dvp->id_iobase; 207 208 if (dvp->id_unit > NRC) 209 return 0; 210 if (!RC_VALIDADDR(nec)) { 211 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec); 212 return 0; 213 } 214 if (!RC_VALIDIRQ(irq)) { 215 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq); 216 return 0; 217 } 218 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 219 rcout(CD180_PPRH, 0x11); 220 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 221 return 0; 222 /* Now, test the board more thoroughly, with diagnostic */ 223 if (rc_test(nec, dvp->id_unit)) 224 return 0; 225 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 226 227 return 0xF; 228} 229 230static int 231rcattach(dvp) 232 struct isa_device *dvp; 233{ 234 register int chan, nec = dvp->id_iobase; 235 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 236 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 237 static int rc_started = 0; 238 struct tty *tp; 239 240 dvp->id_ointr = rcintr; 241 242 /* Thorooughly test the device */ 243 if (rcb->rcb_probed != RC_PROBED) 244 return 0; 245 rcb->rcb_addr = nec; 246 rcb->rcb_dtr = 0; 247 rcb->rcb_baserc = rc; 248 rcb->rcb_unit = dvp->id_unit; 249 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 250 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit, 251 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 252 253 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 254 rc->rc_rcb = rcb; 255 rc->rc_chan = chan; 256 rc->rc_iptr = rc->rc_ibuf; 257 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 258 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 259 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 260 rc->rc_cor2 = rc->rc_pendcmd = 0; 261 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 262 rc->rc_dtrwait = 3 * hz; 263 rc->rc_dcdwaits= 0; 264 rc->rc_hotchar = 0; 265 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)]; 266 ttychars(tp); 267 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 268 tp->t_cflag = TTYDEF_CFLAG; 269 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 270 } 271 rcb->rcb_probed = RC_ATTACHED; 272 if (!rc_started) { 273 cdevsw_add(&rc_cdevsw); 274 rc_ih = sinthand_add("tty:rc", &tty_ithd, rcpoll, NULL, 275 SWI_TTY, 0); 276 rc_wakeup((void *)NULL); 277 rc_started = 1; 278 } 279 return 1; 280} 281 282/* RC interrupt handling */ 283static void 284rcintr(unit) 285 int unit; 286{ 287 register struct rc_softc *rcb = &rc_softc[unit]; 288 register struct rc_chans *rc; 289 register int nec, resid; 290 register u_char val, iack, bsr, ucnt, *optr; 291 int good_data, t_state; 292 293 if (rcb->rcb_probed != RC_ATTACHED) { 294 printf("rc%d: bogus interrupt\n", unit); 295 return; 296 } 297 nec = rcb->rcb_addr; 298 299 bsr = ~(rcin(RC_BSR)); 300 301 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 302 printf("rc%d: extra interrupt\n", unit); 303 rcout(CD180_EOIR, 0); 304 return; 305 } 306 307 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 308#ifdef RCDEBUG_DETAILED 309 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 310 (bsr & RC_BSR_TOUT)?"TOUT ":"", 311 (bsr & RC_BSR_RXINT)?"RXINT ":"", 312 (bsr & RC_BSR_TXINT)?"TXINT ":"", 313 (bsr & RC_BSR_MOINT)?"MOINT":""); 314#endif 315 if (bsr & RC_BSR_TOUT) { 316 printf("rc%d: hardware failure, reset board\n", unit); 317 rcout(RC_CTOUT, 0); 318 rc_reinit(rcb); 319 return; 320 } 321 if (bsr & RC_BSR_RXINT) { 322 iack = rcin(RC_PILR_RX); 323 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 324 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 325 printf("rc%d: fake rxint: %02x\n", unit, iack); 326 goto more_intrs; 327 } 328 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 329 t_state = rc->rc_tp->t_state; 330 /* Do RTS flow control stuff */ 331 if ( (rc->rc_flags & RC_RTSFLOW) 332 || !(t_state & TS_ISOPEN) 333 ) { 334 if ( ( !(t_state & TS_ISOPEN) 335 || (t_state & TS_TBLOCK) 336 ) 337 && (rc->rc_msvr & MSVR_RTS) 338 ) 339 rcout(CD180_MSVR, 340 rc->rc_msvr &= ~MSVR_RTS); 341 else if (!(rc->rc_msvr & MSVR_RTS)) 342 rcout(CD180_MSVR, 343 rc->rc_msvr |= MSVR_RTS); 344 } 345 ucnt = rcin(CD180_RDCR) & 0xF; 346 resid = 0; 347 348 if (t_state & TS_ISOPEN) { 349 /* check for input buffer overflow */ 350 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 351 resid = ucnt; 352 ucnt = rc->rc_bufend - rc->rc_iptr; 353 resid -= ucnt; 354 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 355 rc->rc_flags |= RC_WAS_BUFOVFL; 356 rc_scheduled_event++; 357 } 358 } 359 optr = rc->rc_iptr; 360 /* check foor good data */ 361 if (good_data) { 362 while (ucnt-- > 0) { 363 val = rcin(CD180_RDR); 364 optr[0] = val; 365 optr[INPUT_FLAGS_SHIFT] = 0; 366 optr++; 367 rc_scheduled_event++; 368 if (val != 0 && val == rc->rc_hotchar) 369 sched_swi(rc_ih, SWI_NOSWITCH); 370 } 371 } else { 372 /* Store also status data */ 373 while (ucnt-- > 0) { 374 iack = rcin(CD180_RCSR); 375 if (iack & RCSR_Timeout) 376 break; 377 if ( (iack & RCSR_OE) 378 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 379 rc->rc_flags |= RC_WAS_SILOVFL; 380 rc_scheduled_event++; 381 } 382 val = rcin(CD180_RDR); 383 /* 384 Don't store PE if IGNPAR and BREAK if IGNBRK, 385 this hack allows "raw" tty optimization 386 works even if IGN* is set. 387 */ 388 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 389 || ((!(iack & (RCSR_PE|RCSR_FE)) 390 || !(rc->rc_tp->t_iflag & IGNPAR)) 391 && (!(iack & RCSR_Break) 392 || !(rc->rc_tp->t_iflag & IGNBRK)))) { 393 if ( (iack & (RCSR_PE|RCSR_FE)) 394 && (t_state & TS_CAN_BYPASS_L_RINT) 395 && ((iack & RCSR_FE) 396 || ((iack & RCSR_PE) 397 && (rc->rc_tp->t_iflag & INPCK)))) 398 val = 0; 399 else if (val != 0 && val == rc->rc_hotchar) 400 sched_swi(rc_ih, SWI_NOSWITCH); 401 optr[0] = val; 402 optr[INPUT_FLAGS_SHIFT] = iack; 403 optr++; 404 rc_scheduled_event++; 405 } 406 } 407 } 408 rc->rc_iptr = optr; 409 rc->rc_flags |= RC_DORXFER; 410 } else 411 resid = ucnt; 412 /* Clear FIFO if necessary */ 413 while (resid-- > 0) { 414 if (!good_data) 415 iack = rcin(CD180_RCSR); 416 else 417 iack = 0; 418 if (iack & RCSR_Timeout) 419 break; 420 (void) rcin(CD180_RDR); 421 } 422 goto more_intrs; 423 } 424 if (bsr & RC_BSR_MOINT) { 425 iack = rcin(RC_PILR_MODEM); 426 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 427 printf("rc%d: fake moint: %02x\n", unit, iack); 428 goto more_intrs; 429 } 430 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 431 iack = rcin(CD180_MCR); 432 rc->rc_msvr = rcin(CD180_MSVR); 433 rcout(CD180_MCR, 0); 434#ifdef RCDEBUG 435 printrcflags(rc, "moint"); 436#endif 437 if (rc->rc_flags & RC_CTSFLOW) { 438 if (rc->rc_msvr & MSVR_CTS) 439 rc->rc_flags |= RC_SEND_RDY; 440 else 441 rc->rc_flags &= ~RC_SEND_RDY; 442 } else 443 rc->rc_flags |= RC_SEND_RDY; 444 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 445 rc_scheduled_event += LOTS_OF_EVENTS; 446 rc->rc_flags |= RC_MODCHG; 447 sched_swi(rc_ih, SWI_NOSWITCH); 448 } 449 goto more_intrs; 450 } 451 if (bsr & RC_BSR_TXINT) { 452 iack = rcin(RC_PILR_TX); 453 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 454 printf("rc%d: fake txint: %02x\n", unit, iack); 455 goto more_intrs; 456 } 457 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 458 if ( (rc->rc_flags & RC_OSUSP) 459 || !(rc->rc_flags & RC_SEND_RDY) 460 ) 461 goto more_intrs; 462 /* Handle breaks and other stuff */ 463 if (rc->rc_pendcmd) { 464 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 465 rcout(CD180_TDR, CD180_C_ESC); 466 rcout(CD180_TDR, rc->rc_pendcmd); 467 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 468 rc->rc_pendcmd = 0; 469 goto more_intrs; 470 } 471 optr = rc->rc_optr; 472 resid = rc->rc_obufend - optr; 473 if (resid > CD180_NFIFO) 474 resid = CD180_NFIFO; 475 while (resid-- > 0) 476 rcout(CD180_TDR, *optr++); 477 rc->rc_optr = optr; 478 479 /* output completed? */ 480 if (optr >= rc->rc_obufend) { 481 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 482#ifdef RCDEBUG 483 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 484#endif 485 if (!(rc->rc_flags & RC_DOXXFER)) { 486 rc_scheduled_event += LOTS_OF_EVENTS; 487 rc->rc_flags |= RC_DOXXFER; 488 sched_swi(rc_ih, SWI_NOSWITCH); 489 } 490 } 491 } 492 more_intrs: 493 rcout(CD180_EOIR, 0); /* end of interrupt */ 494 rcout(RC_CTOUT, 0); 495 bsr = ~(rcin(RC_BSR)); 496 } 497} 498 499/* Feed characters to output buffer */ 500static void rc_start(tp) 501register struct tty *tp; 502{ 503 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 504 register int nec = rc->rc_rcb->rcb_addr, s; 505 506 if (rc->rc_flags & RC_OSBUSY) 507 return; 508 s = spltty(); 509 rc->rc_flags |= RC_OSBUSY; 510 disable_intr(); 511 if (tp->t_state & TS_TTSTOP) 512 rc->rc_flags |= RC_OSUSP; 513 else 514 rc->rc_flags &= ~RC_OSUSP; 515 /* Do RTS flow control stuff */ 516 if ( (rc->rc_flags & RC_RTSFLOW) 517 && (tp->t_state & TS_TBLOCK) 518 && (rc->rc_msvr & MSVR_RTS) 519 ) { 520 rcout(CD180_CAR, rc->rc_chan); 521 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 522 } else if (!(rc->rc_msvr & MSVR_RTS)) { 523 rcout(CD180_CAR, rc->rc_chan); 524 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 525 } 526 enable_intr(); 527 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 528 goto out; 529#ifdef RCDEBUG 530 printrcflags(rc, "rcstart"); 531#endif 532 ttwwakeup(tp); 533#ifdef RCDEBUG 534 printf("rcstart: outq = %d obuf = %d\n", 535 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 536#endif 537 if (tp->t_state & TS_BUSY) 538 goto out; /* output still in progress ... */ 539 540 if (tp->t_outq.c_cc > 0) { 541 u_int ocnt; 542 543 tp->t_state |= TS_BUSY; 544 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 545 disable_intr(); 546 rc->rc_optr = rc->rc_obuf; 547 rc->rc_obufend = rc->rc_optr + ocnt; 548 enable_intr(); 549 if (!(rc->rc_ier & IER_TxRdy)) { 550#ifdef RCDEBUG 551 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 552#endif 553 rcout(CD180_CAR, rc->rc_chan); 554 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 555 } 556 } 557out: 558 rc->rc_flags &= ~RC_OSBUSY; 559 (void) splx(s); 560} 561 562/* Handle delayed events. */ 563void rcpoll(void *arg) 564{ 565 register struct rc_chans *rc; 566 register struct rc_softc *rcb; 567 register u_char *tptr, *eptr; 568 register struct tty *tp; 569 register int chan, icnt, nec, unit; 570 571 if (rc_scheduled_event == 0) 572 return; 573repeat: 574 for (unit = 0; unit < NRC; unit++) { 575 rcb = &rc_softc[unit]; 576 rc = rcb->rcb_baserc; 577 nec = rc->rc_rcb->rcb_addr; 578 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 579 tp = rc->rc_tp; 580#ifdef RCDEBUG 581 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 582 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 583 printrcflags(rc, "rcevent"); 584#endif 585 if (rc->rc_flags & RC_WAS_BUFOVFL) { 586 disable_intr(); 587 rc->rc_flags &= ~RC_WAS_BUFOVFL; 588 rc_scheduled_event--; 589 enable_intr(); 590 printf("rc%d/%d: interrupt-level buffer overflow\n", 591 unit, chan); 592 } 593 if (rc->rc_flags & RC_WAS_SILOVFL) { 594 disable_intr(); 595 rc->rc_flags &= ~RC_WAS_SILOVFL; 596 rc_scheduled_event--; 597 enable_intr(); 598 printf("rc%d/%d: silo overflow\n", 599 unit, chan); 600 } 601 if (rc->rc_flags & RC_MODCHG) { 602 disable_intr(); 603 rc->rc_flags &= ~RC_MODCHG; 604 rc_scheduled_event -= LOTS_OF_EVENTS; 605 enable_intr(); 606 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 607 } 608 if (rc->rc_flags & RC_DORXFER) { 609 disable_intr(); 610 rc->rc_flags &= ~RC_DORXFER; 611 eptr = rc->rc_iptr; 612 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 613 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 614 else 615 tptr = rc->rc_ibuf; 616 icnt = eptr - tptr; 617 if (icnt > 0) { 618 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 619 rc->rc_iptr = rc->rc_ibuf; 620 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 621 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 622 } else { 623 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 624 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 625 rc->rc_hiwat = 626 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 627 } 628 if ( (rc->rc_flags & RC_RTSFLOW) 629 && (tp->t_state & TS_ISOPEN) 630 && !(tp->t_state & TS_TBLOCK) 631 && !(rc->rc_msvr & MSVR_RTS) 632 ) { 633 rcout(CD180_CAR, chan); 634 rcout(CD180_MSVR, 635 rc->rc_msvr |= MSVR_RTS); 636 } 637 rc_scheduled_event -= icnt; 638 } 639 enable_intr(); 640 641 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 642 goto done1; 643 644 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 645 && !(tp->t_state & TS_LOCAL)) { 646 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 647 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 648 && !(tp->t_state & TS_TBLOCK)) 649 ttyblock(tp); 650 tk_nin += icnt; 651 tk_rawcc += icnt; 652 tp->t_rawcc += icnt; 653 if (b_to_q(tptr, icnt, &tp->t_rawq)) 654 printf("rc%d/%d: tty-level buffer overflow\n", 655 unit, chan); 656 ttwakeup(tp); 657 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 658 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 659 tp->t_state &= ~TS_TTSTOP; 660 tp->t_lflag &= ~FLUSHO; 661 rc_start(tp); 662 } 663 } else { 664 for (; tptr < eptr; tptr++) 665 (*linesw[tp->t_line].l_rint) 666 (tptr[0] | 667 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 668 } 669done1: ; 670 } 671 if (rc->rc_flags & RC_DOXXFER) { 672 disable_intr(); 673 rc_scheduled_event -= LOTS_OF_EVENTS; 674 rc->rc_flags &= ~RC_DOXXFER; 675 rc->rc_tp->t_state &= ~TS_BUSY; 676 enable_intr(); 677 (*linesw[tp->t_line].l_start)(tp); 678 } 679 } 680 if (rc_scheduled_event == 0) 681 break; 682 } 683 if (rc_scheduled_event >= LOTS_OF_EVENTS) 684 goto repeat; 685} 686 687static void 688rc_stop(tp, rw) 689 register struct tty *tp; 690 int rw; 691{ 692 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 693 u_char *tptr, *eptr; 694 695#ifdef RCDEBUG 696 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 697 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 698#endif 699 if (rw & FWRITE) 700 rc_discard_output(rc); 701 disable_intr(); 702 if (rw & FREAD) { 703 rc->rc_flags &= ~RC_DORXFER; 704 eptr = rc->rc_iptr; 705 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 706 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 707 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 708 } else { 709 tptr = rc->rc_ibuf; 710 rc->rc_iptr = rc->rc_ibuf; 711 } 712 rc_scheduled_event -= eptr - tptr; 713 } 714 if (tp->t_state & TS_TTSTOP) 715 rc->rc_flags |= RC_OSUSP; 716 else 717 rc->rc_flags &= ~RC_OSUSP; 718 enable_intr(); 719} 720 721static int 722rcopen(dev, flag, mode, p) 723 dev_t dev; 724 int flag, mode; 725 struct proc *p; 726{ 727 register struct rc_chans *rc; 728 register struct tty *tp; 729 int unit, nec, s, error = 0; 730 731 unit = GET_UNIT(dev); 732 if (unit >= NRC * CD180_NCHAN) 733 return ENXIO; 734 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 735 return ENXIO; 736 rc = &rc_chans[unit]; 737 tp = rc->rc_tp; 738 dev->si_tty = tp; 739 nec = rc->rc_rcb->rcb_addr; 740#ifdef RCDEBUG 741 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 742#endif 743 s = spltty(); 744 745again: 746 while (rc->rc_flags & RC_DTR_OFF) { 747 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 748 if (error != 0) 749 goto out; 750 } 751 if (tp->t_state & TS_ISOPEN) { 752 if (CALLOUT(dev)) { 753 if (!(rc->rc_flags & RC_ACTOUT)) { 754 error = EBUSY; 755 goto out; 756 } 757 } else { 758 if (rc->rc_flags & RC_ACTOUT) { 759 if (flag & O_NONBLOCK) { 760 error = EBUSY; 761 goto out; 762 } 763 error = tsleep(&rc->rc_rcb, 764 TTIPRI|PCATCH, "rcbi", 0); 765 if (error) 766 goto out; 767 goto again; 768 } 769 } 770 if (tp->t_state & TS_XCLUDE && 771 suser(p)) { 772 error = EBUSY; 773 goto out; 774 } 775 } else { 776 tp->t_oproc = rc_start; 777 tp->t_param = rc_param; 778 tp->t_stop = rc_stop; 779 tp->t_dev = dev; 780 781 if (CALLOUT(dev)) 782 tp->t_cflag |= CLOCAL; 783 else 784 tp->t_cflag &= ~CLOCAL; 785 786 error = rc_param(tp, &tp->t_termios); 787 if (error) 788 goto out; 789 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 790 791 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 792 (*linesw[tp->t_line].l_modem)(tp, 1); 793 } 794 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 795 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 796 rc->rc_dcdwaits++; 797 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 798 rc->rc_dcdwaits--; 799 if (error != 0) 800 goto out; 801 goto again; 802 } 803 error = (*linesw[tp->t_line].l_open)(dev, tp); 804 disc_optim(tp, &tp->t_termios, rc); 805 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 806 rc->rc_flags |= RC_ACTOUT; 807out: 808 (void) splx(s); 809 810 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 811 rc_hardclose(rc); 812 813 return error; 814} 815 816static int 817rcclose(dev, flag, mode, p) 818 dev_t dev; 819 int flag, mode; 820 struct proc *p; 821{ 822 register struct rc_chans *rc; 823 register struct tty *tp; 824 int s, unit = GET_UNIT(dev); 825 826 if (unit >= NRC * CD180_NCHAN) 827 return ENXIO; 828 rc = &rc_chans[unit]; 829 tp = rc->rc_tp; 830#ifdef RCDEBUG 831 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 832#endif 833 s = spltty(); 834 (*linesw[tp->t_line].l_close)(tp, flag); 835 disc_optim(tp, &tp->t_termios, rc); 836 rc_stop(tp, FREAD | FWRITE); 837 rc_hardclose(rc); 838 ttyclose(tp); 839 splx(s); 840 return 0; 841} 842 843static void rc_hardclose(rc) 844register struct rc_chans *rc; 845{ 846 register int s, nec = rc->rc_rcb->rcb_addr; 847 register struct tty *tp = rc->rc_tp; 848 849 s = spltty(); 850 rcout(CD180_CAR, rc->rc_chan); 851 852 /* Disable rx/tx intrs */ 853 rcout(CD180_IER, rc->rc_ier = 0); 854 if ( (tp->t_cflag & HUPCL) 855 || (!(rc->rc_flags & RC_ACTOUT) 856 && !(rc->rc_msvr & MSVR_CD) 857 && !(tp->t_cflag & CLOCAL)) 858 || !(tp->t_state & TS_ISOPEN) 859 ) { 860 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 861 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 862 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 863 if (rc->rc_dtrwait) { 864 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 865 rc->rc_flags |= RC_DTR_OFF; 866 } 867 } 868 rc->rc_flags &= ~RC_ACTOUT; 869 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 870 wakeup(TSA_CARR_ON(tp)); 871 (void) splx(s); 872} 873 874/* Reset the bastard */ 875static void rc_hwreset(unit, nec, chipid) 876 register int unit, nec; 877 unsigned int chipid; 878{ 879 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 880 DELAY(20000); 881 WAITFORCCR(unit, -1); 882 883 rcout(RC_CTOUT, 0); /* Clear timeout */ 884 rcout(CD180_GIVR, chipid); 885 rcout(CD180_GICR, 0); 886 887 /* Set Prescaler Registers (1 msec) */ 888 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 889 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 890 891 /* Initialize Priority Interrupt Level Registers */ 892 rcout(CD180_PILR1, RC_PILR_MODEM); 893 rcout(CD180_PILR2, RC_PILR_TX); 894 rcout(CD180_PILR3, RC_PILR_RX); 895 896 /* Reset DTR */ 897 rcout(RC_DTREG, ~0); 898} 899 900/* Set channel parameters */ 901static int rc_param(tp, ts) 902 register struct tty *tp; 903 struct termios *ts; 904{ 905 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 906 register int nec = rc->rc_rcb->rcb_addr; 907 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 908 909 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 910 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 911 ) 912 return (EINVAL); 913 if (ts->c_ispeed == 0) 914 ts->c_ispeed = ts->c_ospeed; 915 odivs = RC_BRD(ts->c_ospeed); 916 idivs = RC_BRD(ts->c_ispeed); 917 918 s = spltty(); 919 920 /* Select channel */ 921 rcout(CD180_CAR, rc->rc_chan); 922 923 /* If speed == 0, hangup line */ 924 if (ts->c_ospeed == 0) { 925 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 926 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 927 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 928 } 929 930 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 931 cflag = ts->c_cflag; 932 iflag = ts->c_iflag; 933 lflag = ts->c_lflag; 934 935 if (idivs > 0) { 936 rcout(CD180_RBPRL, idivs & 0xFF); 937 rcout(CD180_RBPRH, idivs >> 8); 938 } 939 if (odivs > 0) { 940 rcout(CD180_TBPRL, odivs & 0xFF); 941 rcout(CD180_TBPRH, odivs >> 8); 942 } 943 944 /* set timeout value */ 945 if (ts->c_ispeed > 0) { 946 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 947 948 if ( !(lflag & ICANON) 949 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 950 && ts->c_cc[VTIME] * 10 > itm) 951 itm = ts->c_cc[VTIME] * 10; 952 953 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 954 } 955 956 switch (cflag & CSIZE) { 957 case CS5: val = COR1_5BITS; break; 958 case CS6: val = COR1_6BITS; break; 959 case CS7: val = COR1_7BITS; break; 960 default: 961 case CS8: val = COR1_8BITS; break; 962 } 963 if (cflag & PARENB) { 964 val |= COR1_NORMPAR; 965 if (cflag & PARODD) 966 val |= COR1_ODDP; 967 if (!(cflag & INPCK)) 968 val |= COR1_Ignore; 969 } else 970 val |= COR1_Ignore; 971 if (cflag & CSTOPB) 972 val |= COR1_2SB; 973 rcout(CD180_COR1, val); 974 975 /* Set FIFO threshold */ 976 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 977 inpflow = 0; 978 if ( (iflag & IXOFF) 979 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 980 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 981 || (iflag & IXANY) 982 ) 983 ) 984 ) { 985 inpflow = 1; 986 val |= COR3_SCDE|COR3_FCT; 987 } 988 rcout(CD180_COR3, val); 989 990 /* Initialize on-chip automatic flow control */ 991 val = 0; 992 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 993 if (cflag & CCTS_OFLOW) { 994 rc->rc_flags |= RC_CTSFLOW; 995 val |= COR2_CtsAE; 996 } else 997 rc->rc_flags |= RC_SEND_RDY; 998 if (tp->t_state & TS_TTSTOP) 999 rc->rc_flags |= RC_OSUSP; 1000 else 1001 rc->rc_flags &= ~RC_OSUSP; 1002 if (cflag & CRTS_IFLOW) 1003 rc->rc_flags |= RC_RTSFLOW; 1004 else 1005 rc->rc_flags &= ~RC_RTSFLOW; 1006 1007 if (inpflow) { 1008 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1009 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1010 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1011 val |= COR2_TxIBE; 1012 if (iflag & IXANY) 1013 val |= COR2_IXM; 1014 } 1015 1016 rcout(CD180_COR2, rc->rc_cor2 = val); 1017 1018 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1019 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1020 1021 disc_optim(tp, ts, rc); 1022 1023 /* modem ctl */ 1024 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1025 if (cflag & CCTS_OFLOW) 1026 val |= MCOR1_CTSzd; 1027 rcout(CD180_MCOR1, val); 1028 1029 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1030 if (cflag & CCTS_OFLOW) 1031 val |= MCOR2_CTSod; 1032 rcout(CD180_MCOR2, val); 1033 1034 /* enable i/o and interrupts */ 1035 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1036 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1037 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1038 1039 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1040 if (cflag & CCTS_OFLOW) 1041 rc->rc_ier |= IER_CTS; 1042 if (cflag & CREAD) 1043 rc->rc_ier |= IER_RxData; 1044 if (tp->t_state & TS_BUSY) 1045 rc->rc_ier |= IER_TxRdy; 1046 if (ts->c_ospeed != 0) 1047 rc_modctl(rc, TIOCM_DTR, DMBIS); 1048 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1049 rc->rc_flags |= RC_SEND_RDY; 1050 rcout(CD180_IER, rc->rc_ier); 1051 (void) splx(s); 1052 return 0; 1053} 1054 1055/* Re-initialize board after bogus interrupts */ 1056static void rc_reinit(rcb) 1057struct rc_softc *rcb; 1058{ 1059 register struct rc_chans *rc, *rce; 1060 register int nec; 1061 1062 nec = rcb->rcb_addr; 1063 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1064 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1065 rce = rc + CD180_NCHAN; 1066 for (; rc < rce; rc++) 1067 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1068} 1069 1070static int 1071rcioctl(dev, cmd, data, flag, p) 1072dev_t dev; 1073u_long cmd; 1074int flag; 1075caddr_t data; 1076struct proc *p; 1077{ 1078 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1079 register int s, error; 1080 struct tty *tp = rc->rc_tp; 1081 1082 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1083 if (error != ENOIOCTL) 1084 return (error); 1085 error = ttioctl(tp, cmd, data, flag); 1086 disc_optim(tp, &tp->t_termios, rc); 1087 if (error != ENOIOCTL) 1088 return (error); 1089 s = spltty(); 1090 1091 switch (cmd) { 1092 case TIOCSBRK: 1093 rc->rc_pendcmd = CD180_C_SBRK; 1094 break; 1095 1096 case TIOCCBRK: 1097 rc->rc_pendcmd = CD180_C_EBRK; 1098 break; 1099 1100 case TIOCSDTR: 1101 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1102 break; 1103 1104 case TIOCCDTR: 1105 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1106 break; 1107 1108 case TIOCMGET: 1109 *(int *) data = rc_modctl(rc, 0, DMGET); 1110 break; 1111 1112 case TIOCMSET: 1113 (void) rc_modctl(rc, *(int *) data, DMSET); 1114 break; 1115 1116 case TIOCMBIC: 1117 (void) rc_modctl(rc, *(int *) data, DMBIC); 1118 break; 1119 1120 case TIOCMBIS: 1121 (void) rc_modctl(rc, *(int *) data, DMBIS); 1122 break; 1123 1124 case TIOCMSDTRWAIT: 1125 error = suser(p); 1126 if (error != 0) { 1127 splx(s); 1128 return (error); 1129 } 1130 rc->rc_dtrwait = *(int *)data * hz / 100; 1131 break; 1132 1133 case TIOCMGDTRWAIT: 1134 *(int *)data = rc->rc_dtrwait * 100 / hz; 1135 break; 1136 1137 default: 1138 (void) splx(s); 1139 return ENOTTY; 1140 } 1141 (void) splx(s); 1142 return 0; 1143} 1144 1145 1146/* Modem control routines */ 1147 1148static int rc_modctl(rc, bits, cmd) 1149register struct rc_chans *rc; 1150int bits, cmd; 1151{ 1152 register int nec = rc->rc_rcb->rcb_addr; 1153 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1154 1155 rcout(CD180_CAR, rc->rc_chan); 1156 1157 switch (cmd) { 1158 case DMSET: 1159 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1160 ~(*dtr |= 1 << rc->rc_chan) : 1161 ~(*dtr &= ~(1 << rc->rc_chan))); 1162 msvr = rcin(CD180_MSVR); 1163 if (bits & TIOCM_RTS) 1164 msvr |= MSVR_RTS; 1165 else 1166 msvr &= ~MSVR_RTS; 1167 if (bits & TIOCM_DTR) 1168 msvr |= MSVR_DTR; 1169 else 1170 msvr &= ~MSVR_DTR; 1171 rcout(CD180_MSVR, msvr); 1172 break; 1173 1174 case DMBIS: 1175 if (bits & TIOCM_DTR) 1176 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1177 msvr = rcin(CD180_MSVR); 1178 if (bits & TIOCM_RTS) 1179 msvr |= MSVR_RTS; 1180 if (bits & TIOCM_DTR) 1181 msvr |= MSVR_DTR; 1182 rcout(CD180_MSVR, msvr); 1183 break; 1184 1185 case DMGET: 1186 bits = TIOCM_LE; 1187 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1188 1189 if (msvr & MSVR_RTS) 1190 bits |= TIOCM_RTS; 1191 if (msvr & MSVR_CTS) 1192 bits |= TIOCM_CTS; 1193 if (msvr & MSVR_DSR) 1194 bits |= TIOCM_DSR; 1195 if (msvr & MSVR_DTR) 1196 bits |= TIOCM_DTR; 1197 if (msvr & MSVR_CD) 1198 bits |= TIOCM_CD; 1199 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1200 bits |= TIOCM_RI; 1201 return bits; 1202 1203 case DMBIC: 1204 if (bits & TIOCM_DTR) 1205 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1206 msvr = rcin(CD180_MSVR); 1207 if (bits & TIOCM_RTS) 1208 msvr &= ~MSVR_RTS; 1209 if (bits & TIOCM_DTR) 1210 msvr &= ~MSVR_DTR; 1211 rcout(CD180_MSVR, msvr); 1212 break; 1213 } 1214 rc->rc_msvr = rcin(CD180_MSVR); 1215 return 0; 1216} 1217 1218/* Test the board. */ 1219int rc_test(nec, unit) 1220 register int nec; 1221 int unit; 1222{ 1223 int chan = 0; 1224 int i = 0, rcnt, old_level; 1225 unsigned int iack, chipid; 1226 unsigned short divs; 1227 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1228#define CTLEN 8 1229#define ERR(s) { \ 1230 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1231 (void) splx(old_level); return 1; } 1232 1233 struct rtest { 1234 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1235 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1236 int rxptr; /* RX pointer */ 1237 int txptr; /* TX pointer */ 1238 } tchans[CD180_NCHAN]; 1239 1240 old_level = spltty(); 1241 1242 chipid = RC_FAKEID; 1243 1244 /* First, reset board to inital state */ 1245 rc_hwreset(unit, nec, chipid); 1246 1247 divs = RC_BRD(19200); 1248 1249 /* Initialize channels */ 1250 for (chan = 0; chan < CD180_NCHAN; chan++) { 1251 1252 /* Select and reset channel */ 1253 rcout(CD180_CAR, chan); 1254 CCRCMD(unit, chan, CCR_ResetChan); 1255 WAITFORCCR(unit, chan); 1256 1257 /* Set speed */ 1258 rcout(CD180_RBPRL, divs & 0xFF); 1259 rcout(CD180_RBPRH, divs >> 8); 1260 rcout(CD180_TBPRL, divs & 0xFF); 1261 rcout(CD180_TBPRH, divs >> 8); 1262 1263 /* set timeout value */ 1264 rcout(CD180_RTPR, 0); 1265 1266 /* Establish local loopback */ 1267 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1268 rcout(CD180_COR2, COR2_LLM); 1269 rcout(CD180_COR3, CD180_NFIFO); 1270 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1271 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1272 WAITFORCCR(unit, chan); 1273 rcout(CD180_MSVR, MSVR_RTS); 1274 1275 /* Fill TXBUF with test data */ 1276 for (i = 0; i < CD180_NFIFO; i++) { 1277 tchans[chan].txbuf[i] = ctest[i]; 1278 tchans[chan].rxbuf[i] = 0; 1279 } 1280 tchans[chan].txptr = tchans[chan].rxptr = 0; 1281 1282 /* Now, start transmit */ 1283 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1284 } 1285 /* Pseudo-interrupt poll stuff */ 1286 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1287 i = ~(rcin(RC_BSR)); 1288 if (i & RC_BSR_TOUT) 1289 ERR(("BSR timeout bit set\n")) 1290 else if (i & RC_BSR_TXINT) { 1291 iack = rcin(RC_PILR_TX); 1292 if (iack != (GIVR_IT_TDI | chipid)) 1293 ERR(("Bad TX intr ack (%02x != %02x)\n", 1294 iack, GIVR_IT_TDI | chipid)); 1295 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1296 /* If no more data to transmit, disable TX intr */ 1297 if (tchans[chan].txptr >= CD180_NFIFO) { 1298 iack = rcin(CD180_IER); 1299 rcout(CD180_IER, iack & ~IER_TxMpty); 1300 } else { 1301 for (iack = tchans[chan].txptr; 1302 iack < CD180_NFIFO; iack++) 1303 rcout(CD180_TDR, 1304 tchans[chan].txbuf[iack]); 1305 tchans[chan].txptr = iack; 1306 } 1307 rcout(CD180_EOIR, 0); 1308 } else if (i & RC_BSR_RXINT) { 1309 u_char ucnt; 1310 1311 iack = rcin(RC_PILR_RX); 1312 if (iack != (GIVR_IT_RGDI | chipid) && 1313 iack != (GIVR_IT_REI | chipid)) 1314 ERR(("Bad RX intr ack (%02x != %02x)\n", 1315 iack, GIVR_IT_RGDI | chipid)) 1316 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1317 ucnt = rcin(CD180_RDCR) & 0xF; 1318 while (ucnt-- > 0) { 1319 iack = rcin(CD180_RCSR); 1320 if (iack & RCSR_Timeout) 1321 break; 1322 if (iack & 0xF) 1323 ERR(("Bad char chan %d (RCSR = %02X)\n", 1324 chan, iack)) 1325 if (tchans[chan].rxptr > CD180_NFIFO) 1326 ERR(("Got extra chars chan %d\n", 1327 chan)) 1328 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1329 rcin(CD180_RDR); 1330 } 1331 rcout(CD180_EOIR, 0); 1332 } 1333 rcout(RC_CTOUT, 0); 1334 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1335 if (tchans[chan].rxptr >= CD180_NFIFO) 1336 iack++; 1337 if (iack == CD180_NCHAN) 1338 break; 1339 } 1340 for (chan = 0; chan < CD180_NCHAN; chan++) { 1341 /* Select and reset channel */ 1342 rcout(CD180_CAR, chan); 1343 CCRCMD(unit, chan, CCR_ResetChan); 1344 } 1345 1346 if (!rcnt) 1347 ERR(("looses characters during local loopback\n")) 1348 /* Now, check data */ 1349 for (chan = 0; chan < CD180_NCHAN; chan++) 1350 for (i = 0; i < CD180_NFIFO; i++) 1351 if (ctest[i] != tchans[chan].rxbuf[i]) 1352 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1353 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1354 (void) splx(old_level); 1355 return 0; 1356} 1357 1358#ifdef RCDEBUG 1359static void printrcflags(rc, comment) 1360struct rc_chans *rc; 1361char *comment; 1362{ 1363 u_short f = rc->rc_flags; 1364 register int nec = rc->rc_rcb->rcb_addr; 1365 1366 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1367 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1368 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1369 (f & RC_ACTOUT) ?"ACTOUT " :"", 1370 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1371 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1372 (f & RC_DORXFER)?"DORXFER " :"", 1373 (f & RC_DOXXFER)?"DOXXFER " :"", 1374 (f & RC_MODCHG) ?"MODCHG " :"", 1375 (f & RC_OSUSP) ?"OSUSP " :"", 1376 (f & RC_OSBUSY) ?"OSBUSY " :"", 1377 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1378 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1379 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1380 1381 rcout(CD180_CAR, rc->rc_chan); 1382 1383 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1384 rc->rc_rcb->rcb_unit, rc->rc_chan, 1385 rcin(CD180_MSVR), 1386 rcin(CD180_IER), 1387 rcin(CD180_CCSR)); 1388} 1389#endif /* RCDEBUG */ 1390 1391static void 1392rc_dtrwakeup(chan) 1393 void *chan; 1394{ 1395 struct rc_chans *rc; 1396 1397 rc = (struct rc_chans *)chan; 1398 rc->rc_flags &= ~RC_DTR_OFF; 1399 wakeup(&rc->rc_dtrwait); 1400} 1401 1402static void 1403rc_discard_output(rc) 1404 struct rc_chans *rc; 1405{ 1406 disable_intr(); 1407 if (rc->rc_flags & RC_DOXXFER) { 1408 rc_scheduled_event -= LOTS_OF_EVENTS; 1409 rc->rc_flags &= ~RC_DOXXFER; 1410 } 1411 rc->rc_optr = rc->rc_obufend; 1412 rc->rc_tp->t_state &= ~TS_BUSY; 1413 enable_intr(); 1414 ttwwakeup(rc->rc_tp); 1415} 1416 1417static void 1418rc_wakeup(chan) 1419 void *chan; 1420{ 1421 timeout(rc_wakeup, (caddr_t)NULL, 1); 1422 1423 if (rc_scheduled_event != 0) { 1424 int s; 1425 1426 s = splsofttty(); 1427 rcpoll(NULL); 1428 splx(s); 1429 } 1430} 1431 1432static void 1433disc_optim(tp, t, rc) 1434 struct tty *tp; 1435 struct termios *t; 1436 struct rc_chans *rc; 1437{ 1438 1439 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1440 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1441 && (!(t->c_iflag & PARMRK) 1442 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1443 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1444 && linesw[tp->t_line].l_rint == ttyinput) 1445 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1446 else 1447 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1448 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1449} 1450 1451static void 1452rc_wait0(nec, unit, chan, line) 1453 int nec, unit, chan, line; 1454{ 1455 int rcnt; 1456 1457 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1458 DELAY(30); 1459 if (rcnt == 0) 1460 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1461 unit, chan, line); 1462} 1463