rc.c revision 67551
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/rc/rc.c 67551 2000-10-25 05:19:40Z jhb $ 28 * 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36#include "rc.h" 37 38/*#define RCDEBUG*/ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/tty.h> 44#include <sys/proc.h> 45#include <sys/conf.h> 46#include <sys/dkstat.h> 47#include <sys/fcntl.h> 48#include <sys/bus.h> 49#include <sys/interrupt.h> 50#include <sys/ipl.h> 51 52 53#include <i386/isa/isa_device.h> 54 55#include <i386/isa/ic/cd180.h> 56#include <i386/isa/rcreg.h> 57 58/* Prototypes */ 59static int rcprobe __P((struct isa_device *)); 60static int rcattach __P((struct isa_device *)); 61 62#define rcin(port) RC_IN (nec, port) 63#define rcout(port,v) RC_OUT (nec, port, v) 64 65#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 66#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 67 68#define RC_IBUFSIZE 256 69#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 70#define RC_OBUFSIZE 512 71#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 72#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 73#define LOTS_OF_EVENTS 64 74 75#define RC_FAKEID 0x10 76 77#define RC_PROBED 1 78#define RC_ATTACHED 2 79 80#define GET_UNIT(dev) (minor(dev) & 0x3F) 81#define CALLOUT(dev) (minor(dev) & 0x80) 82 83/* For isa routines */ 84struct isa_driver rcdriver = { 85 INTR_TYPE_TTY, 86 rcprobe, 87 rcattach, 88 "rc" 89}; 90COMPAT_ISA_DRIVER(rc, rcdriver); 91 92static d_open_t rcopen; 93static d_close_t rcclose; 94static d_ioctl_t rcioctl; 95 96#define CDEV_MAJOR 63 97static struct cdevsw rc_cdevsw = { 98 /* open */ rcopen, 99 /* close */ rcclose, 100 /* read */ ttyread, 101 /* write */ ttywrite, 102 /* ioctl */ rcioctl, 103 /* poll */ ttypoll, 104 /* mmap */ nommap, 105 /* strategy */ nostrategy, 106 /* name */ "rc", 107 /* maj */ CDEV_MAJOR, 108 /* dump */ nodump, 109 /* psize */ nopsize, 110 /* flags */ D_TTY, 111 /* bmaj */ -1 112}; 113 114/* Per-board structure */ 115static struct rc_softc { 116 u_int rcb_probed; /* 1 - probed, 2 - attached */ 117 u_int rcb_addr; /* Base I/O addr */ 118 u_int rcb_unit; /* unit # */ 119 u_char rcb_dtr; /* DTR status */ 120 struct rc_chans *rcb_baserc; /* base rc ptr */ 121} rc_softc[NRC]; 122 123/* Per-channel structure */ 124static struct rc_chans { 125 struct rc_softc *rc_rcb; /* back ptr */ 126 u_short rc_flags; /* Misc. flags */ 127 int rc_chan; /* Channel # */ 128 u_char rc_ier; /* intr. enable reg */ 129 u_char rc_msvr; /* modem sig. status */ 130 u_char rc_cor2; /* options reg */ 131 u_char rc_pendcmd; /* special cmd pending */ 132 u_int rc_dtrwait; /* dtr timeout */ 133 u_int rc_dcdwaits; /* how many waits DCD in open */ 134 u_char rc_hotchar; /* end packed optimize */ 135 struct tty *rc_tp; /* tty struct */ 136 u_char *rc_iptr; /* Chars input buffer */ 137 u_char *rc_hiwat; /* hi-water mark */ 138 u_char *rc_bufend; /* end of buffer */ 139 u_char *rc_optr; /* ptr in output buf */ 140 u_char *rc_obufend; /* end of output buf */ 141 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 142 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 143} rc_chans[NRC * CD180_NCHAN]; 144 145static int rc_scheduled_event = 0; 146 147/* for pstat -t */ 148static struct tty rc_tty[NRC * CD180_NCHAN]; 149static const int nrc_tty = NRC * CD180_NCHAN; 150 151/* Flags */ 152#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 153#define RC_ACTOUT 0x0002 /* Dial-out port active */ 154#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 155#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 156#define RC_DORXFER 0x0010 /* RXFER event planned */ 157#define RC_DOXXFER 0x0020 /* XXFER event planned */ 158#define RC_MODCHG 0x0040 /* Modem status changed */ 159#define RC_OSUSP 0x0080 /* Output suspended */ 160#define RC_OSBUSY 0x0100 /* start() routine in progress */ 161#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 162#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 163#define RC_SEND_RDY 0x0800 /* ready to send */ 164 165/* Table for translation of RCSR status bits to internal form */ 166static int rc_rcsrt[16] = { 167 0, TTY_OE, TTY_FE, 168 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 169 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 170 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 171 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 172 TTY_BI|TTY_PE|TTY_FE|TTY_OE 173}; 174 175static struct intrhand *rc_ih; 176 177/* Static prototypes */ 178static ointhand2_t rcintr; 179static void rc_hwreset __P((int, int, unsigned int)); 180static int rc_test __P((int, int)); 181static void rc_discard_output __P((struct rc_chans *)); 182static void rc_hardclose __P((struct rc_chans *)); 183static int rc_modctl __P((struct rc_chans *, int, int)); 184static void rc_start __P((struct tty *)); 185static void rc_stop __P((struct tty *, int rw)); 186static int rc_param __P((struct tty *, struct termios *)); 187static swihand_t rcpoll; 188static void rc_reinit __P((struct rc_softc *)); 189#ifdef RCDEBUG 190static void printrcflags(); 191#endif 192static timeout_t rc_dtrwakeup; 193static timeout_t rc_wakeup; 194static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 195static void rc_wait0 __P((int nec, int unit, int chan, int line)); 196 197/**********************************************/ 198 199/* Quick device probing */ 200static int 201rcprobe(dvp) 202 struct isa_device *dvp; 203{ 204 int irq = ffs(dvp->id_irq) - 1; 205 register int nec = dvp->id_iobase; 206 207 if (dvp->id_unit > NRC) 208 return 0; 209 if (!RC_VALIDADDR(nec)) { 210 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec); 211 return 0; 212 } 213 if (!RC_VALIDIRQ(irq)) { 214 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq); 215 return 0; 216 } 217 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 218 rcout(CD180_PPRH, 0x11); 219 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 220 return 0; 221 /* Now, test the board more thoroughly, with diagnostic */ 222 if (rc_test(nec, dvp->id_unit)) 223 return 0; 224 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 225 226 return 0xF; 227} 228 229static int 230rcattach(dvp) 231 struct isa_device *dvp; 232{ 233 register int chan, nec = dvp->id_iobase; 234 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 235 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 236 static int rc_started = 0; 237 struct tty *tp; 238 239 dvp->id_ointr = rcintr; 240 241 /* Thorooughly test the device */ 242 if (rcb->rcb_probed != RC_PROBED) 243 return 0; 244 rcb->rcb_addr = nec; 245 rcb->rcb_dtr = 0; 246 rcb->rcb_baserc = rc; 247 rcb->rcb_unit = dvp->id_unit; 248 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 249 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit, 250 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 251 252 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 253 rc->rc_rcb = rcb; 254 rc->rc_chan = chan; 255 rc->rc_iptr = rc->rc_ibuf; 256 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 257 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 258 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 259 rc->rc_cor2 = rc->rc_pendcmd = 0; 260 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 261 rc->rc_dtrwait = 3 * hz; 262 rc->rc_dcdwaits= 0; 263 rc->rc_hotchar = 0; 264 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)]; 265 ttychars(tp); 266 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 267 tp->t_cflag = TTYDEF_CFLAG; 268 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 269 } 270 rcb->rcb_probed = RC_ATTACHED; 271 if (!rc_started) { 272 cdevsw_add(&rc_cdevsw); 273 rc_ih = sinthand_add("tty:rc", &tty_ithd, rcpoll, NULL, 274 SWI_TTY, 0); 275 rc_wakeup((void *)NULL); 276 rc_started = 1; 277 } 278 return 1; 279} 280 281/* RC interrupt handling */ 282static void 283rcintr(unit) 284 int unit; 285{ 286 register struct rc_softc *rcb = &rc_softc[unit]; 287 register struct rc_chans *rc; 288 register int nec, resid; 289 register u_char val, iack, bsr, ucnt, *optr; 290 int good_data, t_state; 291 292 if (rcb->rcb_probed != RC_ATTACHED) { 293 printf("rc%d: bogus interrupt\n", unit); 294 return; 295 } 296 nec = rcb->rcb_addr; 297 298 bsr = ~(rcin(RC_BSR)); 299 300 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 301 printf("rc%d: extra interrupt\n", unit); 302 rcout(CD180_EOIR, 0); 303 return; 304 } 305 306 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 307#ifdef RCDEBUG_DETAILED 308 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 309 (bsr & RC_BSR_TOUT)?"TOUT ":"", 310 (bsr & RC_BSR_RXINT)?"RXINT ":"", 311 (bsr & RC_BSR_TXINT)?"TXINT ":"", 312 (bsr & RC_BSR_MOINT)?"MOINT":""); 313#endif 314 if (bsr & RC_BSR_TOUT) { 315 printf("rc%d: hardware failure, reset board\n", unit); 316 rcout(RC_CTOUT, 0); 317 rc_reinit(rcb); 318 return; 319 } 320 if (bsr & RC_BSR_RXINT) { 321 iack = rcin(RC_PILR_RX); 322 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 323 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 324 printf("rc%d: fake rxint: %02x\n", unit, iack); 325 goto more_intrs; 326 } 327 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 328 t_state = rc->rc_tp->t_state; 329 /* Do RTS flow control stuff */ 330 if ( (rc->rc_flags & RC_RTSFLOW) 331 || !(t_state & TS_ISOPEN) 332 ) { 333 if ( ( !(t_state & TS_ISOPEN) 334 || (t_state & TS_TBLOCK) 335 ) 336 && (rc->rc_msvr & MSVR_RTS) 337 ) 338 rcout(CD180_MSVR, 339 rc->rc_msvr &= ~MSVR_RTS); 340 else if (!(rc->rc_msvr & MSVR_RTS)) 341 rcout(CD180_MSVR, 342 rc->rc_msvr |= MSVR_RTS); 343 } 344 ucnt = rcin(CD180_RDCR) & 0xF; 345 resid = 0; 346 347 if (t_state & TS_ISOPEN) { 348 /* check for input buffer overflow */ 349 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 350 resid = ucnt; 351 ucnt = rc->rc_bufend - rc->rc_iptr; 352 resid -= ucnt; 353 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 354 rc->rc_flags |= RC_WAS_BUFOVFL; 355 rc_scheduled_event++; 356 } 357 } 358 optr = rc->rc_iptr; 359 /* check foor good data */ 360 if (good_data) { 361 while (ucnt-- > 0) { 362 val = rcin(CD180_RDR); 363 optr[0] = val; 364 optr[INPUT_FLAGS_SHIFT] = 0; 365 optr++; 366 rc_scheduled_event++; 367 if (val != 0 && val == rc->rc_hotchar) 368 sched_swi(rc_ih, SWI_NOSWITCH); 369 } 370 } else { 371 /* Store also status data */ 372 while (ucnt-- > 0) { 373 iack = rcin(CD180_RCSR); 374 if (iack & RCSR_Timeout) 375 break; 376 if ( (iack & RCSR_OE) 377 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 378 rc->rc_flags |= RC_WAS_SILOVFL; 379 rc_scheduled_event++; 380 } 381 val = rcin(CD180_RDR); 382 /* 383 Don't store PE if IGNPAR and BREAK if IGNBRK, 384 this hack allows "raw" tty optimization 385 works even if IGN* is set. 386 */ 387 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 388 || ((!(iack & (RCSR_PE|RCSR_FE)) 389 || !(rc->rc_tp->t_iflag & IGNPAR)) 390 && (!(iack & RCSR_Break) 391 || !(rc->rc_tp->t_iflag & IGNBRK)))) { 392 if ( (iack & (RCSR_PE|RCSR_FE)) 393 && (t_state & TS_CAN_BYPASS_L_RINT) 394 && ((iack & RCSR_FE) 395 || ((iack & RCSR_PE) 396 && (rc->rc_tp->t_iflag & INPCK)))) 397 val = 0; 398 else if (val != 0 && val == rc->rc_hotchar) 399 sched_swi(rc_ih, SWI_NOSWITCH); 400 optr[0] = val; 401 optr[INPUT_FLAGS_SHIFT] = iack; 402 optr++; 403 rc_scheduled_event++; 404 } 405 } 406 } 407 rc->rc_iptr = optr; 408 rc->rc_flags |= RC_DORXFER; 409 } else 410 resid = ucnt; 411 /* Clear FIFO if necessary */ 412 while (resid-- > 0) { 413 if (!good_data) 414 iack = rcin(CD180_RCSR); 415 else 416 iack = 0; 417 if (iack & RCSR_Timeout) 418 break; 419 (void) rcin(CD180_RDR); 420 } 421 goto more_intrs; 422 } 423 if (bsr & RC_BSR_MOINT) { 424 iack = rcin(RC_PILR_MODEM); 425 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 426 printf("rc%d: fake moint: %02x\n", unit, iack); 427 goto more_intrs; 428 } 429 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 430 iack = rcin(CD180_MCR); 431 rc->rc_msvr = rcin(CD180_MSVR); 432 rcout(CD180_MCR, 0); 433#ifdef RCDEBUG 434 printrcflags(rc, "moint"); 435#endif 436 if (rc->rc_flags & RC_CTSFLOW) { 437 if (rc->rc_msvr & MSVR_CTS) 438 rc->rc_flags |= RC_SEND_RDY; 439 else 440 rc->rc_flags &= ~RC_SEND_RDY; 441 } else 442 rc->rc_flags |= RC_SEND_RDY; 443 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 444 rc_scheduled_event += LOTS_OF_EVENTS; 445 rc->rc_flags |= RC_MODCHG; 446 sched_swi(rc_ih, SWI_NOSWITCH); 447 } 448 goto more_intrs; 449 } 450 if (bsr & RC_BSR_TXINT) { 451 iack = rcin(RC_PILR_TX); 452 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 453 printf("rc%d: fake txint: %02x\n", unit, iack); 454 goto more_intrs; 455 } 456 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 457 if ( (rc->rc_flags & RC_OSUSP) 458 || !(rc->rc_flags & RC_SEND_RDY) 459 ) 460 goto more_intrs; 461 /* Handle breaks and other stuff */ 462 if (rc->rc_pendcmd) { 463 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 464 rcout(CD180_TDR, CD180_C_ESC); 465 rcout(CD180_TDR, rc->rc_pendcmd); 466 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 467 rc->rc_pendcmd = 0; 468 goto more_intrs; 469 } 470 optr = rc->rc_optr; 471 resid = rc->rc_obufend - optr; 472 if (resid > CD180_NFIFO) 473 resid = CD180_NFIFO; 474 while (resid-- > 0) 475 rcout(CD180_TDR, *optr++); 476 rc->rc_optr = optr; 477 478 /* output completed? */ 479 if (optr >= rc->rc_obufend) { 480 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 481#ifdef RCDEBUG 482 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 483#endif 484 if (!(rc->rc_flags & RC_DOXXFER)) { 485 rc_scheduled_event += LOTS_OF_EVENTS; 486 rc->rc_flags |= RC_DOXXFER; 487 sched_swi(rc_ih, SWI_NOSWITCH); 488 } 489 } 490 } 491 more_intrs: 492 rcout(CD180_EOIR, 0); /* end of interrupt */ 493 rcout(RC_CTOUT, 0); 494 bsr = ~(rcin(RC_BSR)); 495 } 496} 497 498/* Feed characters to output buffer */ 499static void rc_start(tp) 500register struct tty *tp; 501{ 502 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 503 register int nec = rc->rc_rcb->rcb_addr, s; 504 505 if (rc->rc_flags & RC_OSBUSY) 506 return; 507 s = spltty(); 508 rc->rc_flags |= RC_OSBUSY; 509 disable_intr(); 510 if (tp->t_state & TS_TTSTOP) 511 rc->rc_flags |= RC_OSUSP; 512 else 513 rc->rc_flags &= ~RC_OSUSP; 514 /* Do RTS flow control stuff */ 515 if ( (rc->rc_flags & RC_RTSFLOW) 516 && (tp->t_state & TS_TBLOCK) 517 && (rc->rc_msvr & MSVR_RTS) 518 ) { 519 rcout(CD180_CAR, rc->rc_chan); 520 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 521 } else if (!(rc->rc_msvr & MSVR_RTS)) { 522 rcout(CD180_CAR, rc->rc_chan); 523 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 524 } 525 enable_intr(); 526 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 527 goto out; 528#ifdef RCDEBUG 529 printrcflags(rc, "rcstart"); 530#endif 531 ttwwakeup(tp); 532#ifdef RCDEBUG 533 printf("rcstart: outq = %d obuf = %d\n", 534 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 535#endif 536 if (tp->t_state & TS_BUSY) 537 goto out; /* output still in progress ... */ 538 539 if (tp->t_outq.c_cc > 0) { 540 u_int ocnt; 541 542 tp->t_state |= TS_BUSY; 543 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 544 disable_intr(); 545 rc->rc_optr = rc->rc_obuf; 546 rc->rc_obufend = rc->rc_optr + ocnt; 547 enable_intr(); 548 if (!(rc->rc_ier & IER_TxRdy)) { 549#ifdef RCDEBUG 550 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 551#endif 552 rcout(CD180_CAR, rc->rc_chan); 553 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 554 } 555 } 556out: 557 rc->rc_flags &= ~RC_OSBUSY; 558 (void) splx(s); 559} 560 561/* Handle delayed events. */ 562void rcpoll() 563{ 564 register struct rc_chans *rc; 565 register struct rc_softc *rcb; 566 register u_char *tptr, *eptr; 567 register struct tty *tp; 568 register int chan, icnt, nec, unit; 569 570 if (rc_scheduled_event == 0) 571 return; 572repeat: 573 for (unit = 0; unit < NRC; unit++) { 574 rcb = &rc_softc[unit]; 575 rc = rcb->rcb_baserc; 576 nec = rc->rc_rcb->rcb_addr; 577 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 578 tp = rc->rc_tp; 579#ifdef RCDEBUG 580 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 581 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 582 printrcflags(rc, "rcevent"); 583#endif 584 if (rc->rc_flags & RC_WAS_BUFOVFL) { 585 disable_intr(); 586 rc->rc_flags &= ~RC_WAS_BUFOVFL; 587 rc_scheduled_event--; 588 enable_intr(); 589 printf("rc%d/%d: interrupt-level buffer overflow\n", 590 unit, chan); 591 } 592 if (rc->rc_flags & RC_WAS_SILOVFL) { 593 disable_intr(); 594 rc->rc_flags &= ~RC_WAS_SILOVFL; 595 rc_scheduled_event--; 596 enable_intr(); 597 printf("rc%d/%d: silo overflow\n", 598 unit, chan); 599 } 600 if (rc->rc_flags & RC_MODCHG) { 601 disable_intr(); 602 rc->rc_flags &= ~RC_MODCHG; 603 rc_scheduled_event -= LOTS_OF_EVENTS; 604 enable_intr(); 605 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 606 } 607 if (rc->rc_flags & RC_DORXFER) { 608 disable_intr(); 609 rc->rc_flags &= ~RC_DORXFER; 610 eptr = rc->rc_iptr; 611 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 612 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 613 else 614 tptr = rc->rc_ibuf; 615 icnt = eptr - tptr; 616 if (icnt > 0) { 617 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 618 rc->rc_iptr = rc->rc_ibuf; 619 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 620 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 621 } else { 622 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 623 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 624 rc->rc_hiwat = 625 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 626 } 627 if ( (rc->rc_flags & RC_RTSFLOW) 628 && (tp->t_state & TS_ISOPEN) 629 && !(tp->t_state & TS_TBLOCK) 630 && !(rc->rc_msvr & MSVR_RTS) 631 ) { 632 rcout(CD180_CAR, chan); 633 rcout(CD180_MSVR, 634 rc->rc_msvr |= MSVR_RTS); 635 } 636 rc_scheduled_event -= icnt; 637 } 638 enable_intr(); 639 640 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 641 goto done1; 642 643 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 644 && !(tp->t_state & TS_LOCAL)) { 645 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 646 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 647 && !(tp->t_state & TS_TBLOCK)) 648 ttyblock(tp); 649 tk_nin += icnt; 650 tk_rawcc += icnt; 651 tp->t_rawcc += icnt; 652 if (b_to_q(tptr, icnt, &tp->t_rawq)) 653 printf("rc%d/%d: tty-level buffer overflow\n", 654 unit, chan); 655 ttwakeup(tp); 656 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 657 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 658 tp->t_state &= ~TS_TTSTOP; 659 tp->t_lflag &= ~FLUSHO; 660 rc_start(tp); 661 } 662 } else { 663 for (; tptr < eptr; tptr++) 664 (*linesw[tp->t_line].l_rint) 665 (tptr[0] | 666 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 667 } 668done1: ; 669 } 670 if (rc->rc_flags & RC_DOXXFER) { 671 disable_intr(); 672 rc_scheduled_event -= LOTS_OF_EVENTS; 673 rc->rc_flags &= ~RC_DOXXFER; 674 rc->rc_tp->t_state &= ~TS_BUSY; 675 enable_intr(); 676 (*linesw[tp->t_line].l_start)(tp); 677 } 678 } 679 if (rc_scheduled_event == 0) 680 break; 681 } 682 if (rc_scheduled_event >= LOTS_OF_EVENTS) 683 goto repeat; 684} 685 686static void 687rc_stop(tp, rw) 688 register struct tty *tp; 689 int rw; 690{ 691 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 692 u_char *tptr, *eptr; 693 694#ifdef RCDEBUG 695 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 696 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 697#endif 698 if (rw & FWRITE) 699 rc_discard_output(rc); 700 disable_intr(); 701 if (rw & FREAD) { 702 rc->rc_flags &= ~RC_DORXFER; 703 eptr = rc->rc_iptr; 704 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 705 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 706 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 707 } else { 708 tptr = rc->rc_ibuf; 709 rc->rc_iptr = rc->rc_ibuf; 710 } 711 rc_scheduled_event -= eptr - tptr; 712 } 713 if (tp->t_state & TS_TTSTOP) 714 rc->rc_flags |= RC_OSUSP; 715 else 716 rc->rc_flags &= ~RC_OSUSP; 717 enable_intr(); 718} 719 720static int 721rcopen(dev, flag, mode, p) 722 dev_t dev; 723 int flag, mode; 724 struct proc *p; 725{ 726 register struct rc_chans *rc; 727 register struct tty *tp; 728 int unit, nec, s, error = 0; 729 730 unit = GET_UNIT(dev); 731 if (unit >= NRC * CD180_NCHAN) 732 return ENXIO; 733 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 734 return ENXIO; 735 rc = &rc_chans[unit]; 736 tp = rc->rc_tp; 737 dev->si_tty = tp; 738 nec = rc->rc_rcb->rcb_addr; 739#ifdef RCDEBUG 740 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 741#endif 742 s = spltty(); 743 744again: 745 while (rc->rc_flags & RC_DTR_OFF) { 746 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 747 if (error != 0) 748 goto out; 749 } 750 if (tp->t_state & TS_ISOPEN) { 751 if (CALLOUT(dev)) { 752 if (!(rc->rc_flags & RC_ACTOUT)) { 753 error = EBUSY; 754 goto out; 755 } 756 } else { 757 if (rc->rc_flags & RC_ACTOUT) { 758 if (flag & O_NONBLOCK) { 759 error = EBUSY; 760 goto out; 761 } 762 error = tsleep(&rc->rc_rcb, 763 TTIPRI|PCATCH, "rcbi", 0); 764 if (error) 765 goto out; 766 goto again; 767 } 768 } 769 if (tp->t_state & TS_XCLUDE && 770 suser(p)) { 771 error = EBUSY; 772 goto out; 773 } 774 } else { 775 tp->t_oproc = rc_start; 776 tp->t_param = rc_param; 777 tp->t_stop = rc_stop; 778 tp->t_dev = dev; 779 780 if (CALLOUT(dev)) 781 tp->t_cflag |= CLOCAL; 782 else 783 tp->t_cflag &= ~CLOCAL; 784 785 error = rc_param(tp, &tp->t_termios); 786 if (error) 787 goto out; 788 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 789 790 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 791 (*linesw[tp->t_line].l_modem)(tp, 1); 792 } 793 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 794 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 795 rc->rc_dcdwaits++; 796 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 797 rc->rc_dcdwaits--; 798 if (error != 0) 799 goto out; 800 goto again; 801 } 802 error = (*linesw[tp->t_line].l_open)(dev, tp); 803 disc_optim(tp, &tp->t_termios, rc); 804 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 805 rc->rc_flags |= RC_ACTOUT; 806out: 807 (void) splx(s); 808 809 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 810 rc_hardclose(rc); 811 812 return error; 813} 814 815static int 816rcclose(dev, flag, mode, p) 817 dev_t dev; 818 int flag, mode; 819 struct proc *p; 820{ 821 register struct rc_chans *rc; 822 register struct tty *tp; 823 int s, unit = GET_UNIT(dev); 824 825 if (unit >= NRC * CD180_NCHAN) 826 return ENXIO; 827 rc = &rc_chans[unit]; 828 tp = rc->rc_tp; 829#ifdef RCDEBUG 830 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 831#endif 832 s = spltty(); 833 (*linesw[tp->t_line].l_close)(tp, flag); 834 disc_optim(tp, &tp->t_termios, rc); 835 rc_stop(tp, FREAD | FWRITE); 836 rc_hardclose(rc); 837 ttyclose(tp); 838 splx(s); 839 return 0; 840} 841 842static void rc_hardclose(rc) 843register struct rc_chans *rc; 844{ 845 register int s, nec = rc->rc_rcb->rcb_addr; 846 register struct tty *tp = rc->rc_tp; 847 848 s = spltty(); 849 rcout(CD180_CAR, rc->rc_chan); 850 851 /* Disable rx/tx intrs */ 852 rcout(CD180_IER, rc->rc_ier = 0); 853 if ( (tp->t_cflag & HUPCL) 854 || (!(rc->rc_flags & RC_ACTOUT) 855 && !(rc->rc_msvr & MSVR_CD) 856 && !(tp->t_cflag & CLOCAL)) 857 || !(tp->t_state & TS_ISOPEN) 858 ) { 859 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 860 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 861 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 862 if (rc->rc_dtrwait) { 863 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 864 rc->rc_flags |= RC_DTR_OFF; 865 } 866 } 867 rc->rc_flags &= ~RC_ACTOUT; 868 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 869 wakeup(TSA_CARR_ON(tp)); 870 (void) splx(s); 871} 872 873/* Reset the bastard */ 874static void rc_hwreset(unit, nec, chipid) 875 register int unit, nec; 876 unsigned int chipid; 877{ 878 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 879 DELAY(20000); 880 WAITFORCCR(unit, -1); 881 882 rcout(RC_CTOUT, 0); /* Clear timeout */ 883 rcout(CD180_GIVR, chipid); 884 rcout(CD180_GICR, 0); 885 886 /* Set Prescaler Registers (1 msec) */ 887 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 888 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 889 890 /* Initialize Priority Interrupt Level Registers */ 891 rcout(CD180_PILR1, RC_PILR_MODEM); 892 rcout(CD180_PILR2, RC_PILR_TX); 893 rcout(CD180_PILR3, RC_PILR_RX); 894 895 /* Reset DTR */ 896 rcout(RC_DTREG, ~0); 897} 898 899/* Set channel parameters */ 900static int rc_param(tp, ts) 901 register struct tty *tp; 902 struct termios *ts; 903{ 904 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 905 register int nec = rc->rc_rcb->rcb_addr; 906 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 907 908 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 909 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 910 ) 911 return (EINVAL); 912 if (ts->c_ispeed == 0) 913 ts->c_ispeed = ts->c_ospeed; 914 odivs = RC_BRD(ts->c_ospeed); 915 idivs = RC_BRD(ts->c_ispeed); 916 917 s = spltty(); 918 919 /* Select channel */ 920 rcout(CD180_CAR, rc->rc_chan); 921 922 /* If speed == 0, hangup line */ 923 if (ts->c_ospeed == 0) { 924 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 925 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 926 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 927 } 928 929 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 930 cflag = ts->c_cflag; 931 iflag = ts->c_iflag; 932 lflag = ts->c_lflag; 933 934 if (idivs > 0) { 935 rcout(CD180_RBPRL, idivs & 0xFF); 936 rcout(CD180_RBPRH, idivs >> 8); 937 } 938 if (odivs > 0) { 939 rcout(CD180_TBPRL, odivs & 0xFF); 940 rcout(CD180_TBPRH, odivs >> 8); 941 } 942 943 /* set timeout value */ 944 if (ts->c_ispeed > 0) { 945 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 946 947 if ( !(lflag & ICANON) 948 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 949 && ts->c_cc[VTIME] * 10 > itm) 950 itm = ts->c_cc[VTIME] * 10; 951 952 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 953 } 954 955 switch (cflag & CSIZE) { 956 case CS5: val = COR1_5BITS; break; 957 case CS6: val = COR1_6BITS; break; 958 case CS7: val = COR1_7BITS; break; 959 default: 960 case CS8: val = COR1_8BITS; break; 961 } 962 if (cflag & PARENB) { 963 val |= COR1_NORMPAR; 964 if (cflag & PARODD) 965 val |= COR1_ODDP; 966 if (!(cflag & INPCK)) 967 val |= COR1_Ignore; 968 } else 969 val |= COR1_Ignore; 970 if (cflag & CSTOPB) 971 val |= COR1_2SB; 972 rcout(CD180_COR1, val); 973 974 /* Set FIFO threshold */ 975 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 976 inpflow = 0; 977 if ( (iflag & IXOFF) 978 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 979 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 980 || (iflag & IXANY) 981 ) 982 ) 983 ) { 984 inpflow = 1; 985 val |= COR3_SCDE|COR3_FCT; 986 } 987 rcout(CD180_COR3, val); 988 989 /* Initialize on-chip automatic flow control */ 990 val = 0; 991 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 992 if (cflag & CCTS_OFLOW) { 993 rc->rc_flags |= RC_CTSFLOW; 994 val |= COR2_CtsAE; 995 } else 996 rc->rc_flags |= RC_SEND_RDY; 997 if (tp->t_state & TS_TTSTOP) 998 rc->rc_flags |= RC_OSUSP; 999 else 1000 rc->rc_flags &= ~RC_OSUSP; 1001 if (cflag & CRTS_IFLOW) 1002 rc->rc_flags |= RC_RTSFLOW; 1003 else 1004 rc->rc_flags &= ~RC_RTSFLOW; 1005 1006 if (inpflow) { 1007 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1008 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1009 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1010 val |= COR2_TxIBE; 1011 if (iflag & IXANY) 1012 val |= COR2_IXM; 1013 } 1014 1015 rcout(CD180_COR2, rc->rc_cor2 = val); 1016 1017 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1018 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1019 1020 disc_optim(tp, ts, rc); 1021 1022 /* modem ctl */ 1023 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1024 if (cflag & CCTS_OFLOW) 1025 val |= MCOR1_CTSzd; 1026 rcout(CD180_MCOR1, val); 1027 1028 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1029 if (cflag & CCTS_OFLOW) 1030 val |= MCOR2_CTSod; 1031 rcout(CD180_MCOR2, val); 1032 1033 /* enable i/o and interrupts */ 1034 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1035 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1036 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1037 1038 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1039 if (cflag & CCTS_OFLOW) 1040 rc->rc_ier |= IER_CTS; 1041 if (cflag & CREAD) 1042 rc->rc_ier |= IER_RxData; 1043 if (tp->t_state & TS_BUSY) 1044 rc->rc_ier |= IER_TxRdy; 1045 if (ts->c_ospeed != 0) 1046 rc_modctl(rc, TIOCM_DTR, DMBIS); 1047 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1048 rc->rc_flags |= RC_SEND_RDY; 1049 rcout(CD180_IER, rc->rc_ier); 1050 (void) splx(s); 1051 return 0; 1052} 1053 1054/* Re-initialize board after bogus interrupts */ 1055static void rc_reinit(rcb) 1056struct rc_softc *rcb; 1057{ 1058 register struct rc_chans *rc, *rce; 1059 register int nec; 1060 1061 nec = rcb->rcb_addr; 1062 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1063 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1064 rce = rc + CD180_NCHAN; 1065 for (; rc < rce; rc++) 1066 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1067} 1068 1069static int 1070rcioctl(dev, cmd, data, flag, p) 1071dev_t dev; 1072u_long cmd; 1073int flag; 1074caddr_t data; 1075struct proc *p; 1076{ 1077 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1078 register int s, error; 1079 struct tty *tp = rc->rc_tp; 1080 1081 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1082 if (error != ENOIOCTL) 1083 return (error); 1084 error = ttioctl(tp, cmd, data, flag); 1085 disc_optim(tp, &tp->t_termios, rc); 1086 if (error != ENOIOCTL) 1087 return (error); 1088 s = spltty(); 1089 1090 switch (cmd) { 1091 case TIOCSBRK: 1092 rc->rc_pendcmd = CD180_C_SBRK; 1093 break; 1094 1095 case TIOCCBRK: 1096 rc->rc_pendcmd = CD180_C_EBRK; 1097 break; 1098 1099 case TIOCSDTR: 1100 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1101 break; 1102 1103 case TIOCCDTR: 1104 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1105 break; 1106 1107 case TIOCMGET: 1108 *(int *) data = rc_modctl(rc, 0, DMGET); 1109 break; 1110 1111 case TIOCMSET: 1112 (void) rc_modctl(rc, *(int *) data, DMSET); 1113 break; 1114 1115 case TIOCMBIC: 1116 (void) rc_modctl(rc, *(int *) data, DMBIC); 1117 break; 1118 1119 case TIOCMBIS: 1120 (void) rc_modctl(rc, *(int *) data, DMBIS); 1121 break; 1122 1123 case TIOCMSDTRWAIT: 1124 error = suser(p); 1125 if (error != 0) { 1126 splx(s); 1127 return (error); 1128 } 1129 rc->rc_dtrwait = *(int *)data * hz / 100; 1130 break; 1131 1132 case TIOCMGDTRWAIT: 1133 *(int *)data = rc->rc_dtrwait * 100 / hz; 1134 break; 1135 1136 default: 1137 (void) splx(s); 1138 return ENOTTY; 1139 } 1140 (void) splx(s); 1141 return 0; 1142} 1143 1144 1145/* Modem control routines */ 1146 1147static int rc_modctl(rc, bits, cmd) 1148register struct rc_chans *rc; 1149int bits, cmd; 1150{ 1151 register int nec = rc->rc_rcb->rcb_addr; 1152 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1153 1154 rcout(CD180_CAR, rc->rc_chan); 1155 1156 switch (cmd) { 1157 case DMSET: 1158 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1159 ~(*dtr |= 1 << rc->rc_chan) : 1160 ~(*dtr &= ~(1 << rc->rc_chan))); 1161 msvr = rcin(CD180_MSVR); 1162 if (bits & TIOCM_RTS) 1163 msvr |= MSVR_RTS; 1164 else 1165 msvr &= ~MSVR_RTS; 1166 if (bits & TIOCM_DTR) 1167 msvr |= MSVR_DTR; 1168 else 1169 msvr &= ~MSVR_DTR; 1170 rcout(CD180_MSVR, msvr); 1171 break; 1172 1173 case DMBIS: 1174 if (bits & TIOCM_DTR) 1175 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1176 msvr = rcin(CD180_MSVR); 1177 if (bits & TIOCM_RTS) 1178 msvr |= MSVR_RTS; 1179 if (bits & TIOCM_DTR) 1180 msvr |= MSVR_DTR; 1181 rcout(CD180_MSVR, msvr); 1182 break; 1183 1184 case DMGET: 1185 bits = TIOCM_LE; 1186 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1187 1188 if (msvr & MSVR_RTS) 1189 bits |= TIOCM_RTS; 1190 if (msvr & MSVR_CTS) 1191 bits |= TIOCM_CTS; 1192 if (msvr & MSVR_DSR) 1193 bits |= TIOCM_DSR; 1194 if (msvr & MSVR_DTR) 1195 bits |= TIOCM_DTR; 1196 if (msvr & MSVR_CD) 1197 bits |= TIOCM_CD; 1198 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1199 bits |= TIOCM_RI; 1200 return bits; 1201 1202 case DMBIC: 1203 if (bits & TIOCM_DTR) 1204 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1205 msvr = rcin(CD180_MSVR); 1206 if (bits & TIOCM_RTS) 1207 msvr &= ~MSVR_RTS; 1208 if (bits & TIOCM_DTR) 1209 msvr &= ~MSVR_DTR; 1210 rcout(CD180_MSVR, msvr); 1211 break; 1212 } 1213 rc->rc_msvr = rcin(CD180_MSVR); 1214 return 0; 1215} 1216 1217/* Test the board. */ 1218int rc_test(nec, unit) 1219 register int nec; 1220 int unit; 1221{ 1222 int chan = 0; 1223 int i = 0, rcnt, old_level; 1224 unsigned int iack, chipid; 1225 unsigned short divs; 1226 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1227#define CTLEN 8 1228#define ERR(s) { \ 1229 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1230 (void) splx(old_level); return 1; } 1231 1232 struct rtest { 1233 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1234 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1235 int rxptr; /* RX pointer */ 1236 int txptr; /* TX pointer */ 1237 } tchans[CD180_NCHAN]; 1238 1239 old_level = spltty(); 1240 1241 chipid = RC_FAKEID; 1242 1243 /* First, reset board to inital state */ 1244 rc_hwreset(unit, nec, chipid); 1245 1246 divs = RC_BRD(19200); 1247 1248 /* Initialize channels */ 1249 for (chan = 0; chan < CD180_NCHAN; chan++) { 1250 1251 /* Select and reset channel */ 1252 rcout(CD180_CAR, chan); 1253 CCRCMD(unit, chan, CCR_ResetChan); 1254 WAITFORCCR(unit, chan); 1255 1256 /* Set speed */ 1257 rcout(CD180_RBPRL, divs & 0xFF); 1258 rcout(CD180_RBPRH, divs >> 8); 1259 rcout(CD180_TBPRL, divs & 0xFF); 1260 rcout(CD180_TBPRH, divs >> 8); 1261 1262 /* set timeout value */ 1263 rcout(CD180_RTPR, 0); 1264 1265 /* Establish local loopback */ 1266 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1267 rcout(CD180_COR2, COR2_LLM); 1268 rcout(CD180_COR3, CD180_NFIFO); 1269 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1270 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1271 WAITFORCCR(unit, chan); 1272 rcout(CD180_MSVR, MSVR_RTS); 1273 1274 /* Fill TXBUF with test data */ 1275 for (i = 0; i < CD180_NFIFO; i++) { 1276 tchans[chan].txbuf[i] = ctest[i]; 1277 tchans[chan].rxbuf[i] = 0; 1278 } 1279 tchans[chan].txptr = tchans[chan].rxptr = 0; 1280 1281 /* Now, start transmit */ 1282 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1283 } 1284 /* Pseudo-interrupt poll stuff */ 1285 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1286 i = ~(rcin(RC_BSR)); 1287 if (i & RC_BSR_TOUT) 1288 ERR(("BSR timeout bit set\n")) 1289 else if (i & RC_BSR_TXINT) { 1290 iack = rcin(RC_PILR_TX); 1291 if (iack != (GIVR_IT_TDI | chipid)) 1292 ERR(("Bad TX intr ack (%02x != %02x)\n", 1293 iack, GIVR_IT_TDI | chipid)); 1294 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1295 /* If no more data to transmit, disable TX intr */ 1296 if (tchans[chan].txptr >= CD180_NFIFO) { 1297 iack = rcin(CD180_IER); 1298 rcout(CD180_IER, iack & ~IER_TxMpty); 1299 } else { 1300 for (iack = tchans[chan].txptr; 1301 iack < CD180_NFIFO; iack++) 1302 rcout(CD180_TDR, 1303 tchans[chan].txbuf[iack]); 1304 tchans[chan].txptr = iack; 1305 } 1306 rcout(CD180_EOIR, 0); 1307 } else if (i & RC_BSR_RXINT) { 1308 u_char ucnt; 1309 1310 iack = rcin(RC_PILR_RX); 1311 if (iack != (GIVR_IT_RGDI | chipid) && 1312 iack != (GIVR_IT_REI | chipid)) 1313 ERR(("Bad RX intr ack (%02x != %02x)\n", 1314 iack, GIVR_IT_RGDI | chipid)) 1315 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1316 ucnt = rcin(CD180_RDCR) & 0xF; 1317 while (ucnt-- > 0) { 1318 iack = rcin(CD180_RCSR); 1319 if (iack & RCSR_Timeout) 1320 break; 1321 if (iack & 0xF) 1322 ERR(("Bad char chan %d (RCSR = %02X)\n", 1323 chan, iack)) 1324 if (tchans[chan].rxptr > CD180_NFIFO) 1325 ERR(("Got extra chars chan %d\n", 1326 chan)) 1327 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1328 rcin(CD180_RDR); 1329 } 1330 rcout(CD180_EOIR, 0); 1331 } 1332 rcout(RC_CTOUT, 0); 1333 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1334 if (tchans[chan].rxptr >= CD180_NFIFO) 1335 iack++; 1336 if (iack == CD180_NCHAN) 1337 break; 1338 } 1339 for (chan = 0; chan < CD180_NCHAN; chan++) { 1340 /* Select and reset channel */ 1341 rcout(CD180_CAR, chan); 1342 CCRCMD(unit, chan, CCR_ResetChan); 1343 } 1344 1345 if (!rcnt) 1346 ERR(("looses characters during local loopback\n")) 1347 /* Now, check data */ 1348 for (chan = 0; chan < CD180_NCHAN; chan++) 1349 for (i = 0; i < CD180_NFIFO; i++) 1350 if (ctest[i] != tchans[chan].rxbuf[i]) 1351 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1352 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1353 (void) splx(old_level); 1354 return 0; 1355} 1356 1357#ifdef RCDEBUG 1358static void printrcflags(rc, comment) 1359struct rc_chans *rc; 1360char *comment; 1361{ 1362 u_short f = rc->rc_flags; 1363 register int nec = rc->rc_rcb->rcb_addr; 1364 1365 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1366 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1367 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1368 (f & RC_ACTOUT) ?"ACTOUT " :"", 1369 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1370 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1371 (f & RC_DORXFER)?"DORXFER " :"", 1372 (f & RC_DOXXFER)?"DOXXFER " :"", 1373 (f & RC_MODCHG) ?"MODCHG " :"", 1374 (f & RC_OSUSP) ?"OSUSP " :"", 1375 (f & RC_OSBUSY) ?"OSBUSY " :"", 1376 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1377 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1378 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1379 1380 rcout(CD180_CAR, rc->rc_chan); 1381 1382 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1383 rc->rc_rcb->rcb_unit, rc->rc_chan, 1384 rcin(CD180_MSVR), 1385 rcin(CD180_IER), 1386 rcin(CD180_CCSR)); 1387} 1388#endif /* RCDEBUG */ 1389 1390static void 1391rc_dtrwakeup(chan) 1392 void *chan; 1393{ 1394 struct rc_chans *rc; 1395 1396 rc = (struct rc_chans *)chan; 1397 rc->rc_flags &= ~RC_DTR_OFF; 1398 wakeup(&rc->rc_dtrwait); 1399} 1400 1401static void 1402rc_discard_output(rc) 1403 struct rc_chans *rc; 1404{ 1405 disable_intr(); 1406 if (rc->rc_flags & RC_DOXXFER) { 1407 rc_scheduled_event -= LOTS_OF_EVENTS; 1408 rc->rc_flags &= ~RC_DOXXFER; 1409 } 1410 rc->rc_optr = rc->rc_obufend; 1411 rc->rc_tp->t_state &= ~TS_BUSY; 1412 enable_intr(); 1413 ttwwakeup(rc->rc_tp); 1414} 1415 1416static void 1417rc_wakeup(chan) 1418 void *chan; 1419{ 1420 timeout(rc_wakeup, (caddr_t)NULL, 1); 1421 1422 if (rc_scheduled_event != 0) { 1423 int s; 1424 1425 s = splsofttty(); 1426 rcpoll(); 1427 splx(s); 1428 } 1429} 1430 1431static void 1432disc_optim(tp, t, rc) 1433 struct tty *tp; 1434 struct termios *t; 1435 struct rc_chans *rc; 1436{ 1437 1438 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1439 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1440 && (!(t->c_iflag & PARMRK) 1441 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1442 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1443 && linesw[tp->t_line].l_rint == ttyinput) 1444 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1445 else 1446 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1447 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1448} 1449 1450static void 1451rc_wait0(nec, unit, chan, line) 1452 int nec, unit, chan, line; 1453{ 1454 int rcnt; 1455 1456 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1457 DELAY(30); 1458 if (rcnt == 0) 1459 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1460 unit, chan, line); 1461} 1462