rc.c revision 66824
1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/rc/rc.c 66824 2000-10-08 14:41:13Z bde $
28 *
29 */
30
31/*
32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
33 *
34 */
35
36#include "rc.h"
37
38/*#define RCDEBUG*/
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/tty.h>
44#include <sys/proc.h>
45#include <sys/conf.h>
46#include <sys/dkstat.h>
47#include <sys/fcntl.h>
48#include <sys/bus.h>
49#include <sys/interrupt.h>
50#include <sys/ipl.h>
51
52#include <machine/clock.h>
53
54#include <i386/isa/isa_device.h>
55
56#include <i386/isa/ic/cd180.h>
57#include <i386/isa/rcreg.h>
58
59/* Prototypes */
60static int     rcprobe         __P((struct isa_device *));
61static int     rcattach        __P((struct isa_device *));
62
63#define rcin(port)      RC_IN  (nec, port)
64#define rcout(port,v)   RC_OUT (nec, port, v)
65
66#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
67#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
68
69#define RC_IBUFSIZE     256
70#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
71#define RC_OBUFSIZE     512
72#define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
73#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
74#define LOTS_OF_EVENTS  64
75
76#define RC_FAKEID       0x10
77
78#define RC_PROBED 1
79#define RC_ATTACHED 2
80
81#define GET_UNIT(dev)   (minor(dev) & 0x3F)
82#define CALLOUT(dev)    (minor(dev) & 0x80)
83
84/* For isa routines */
85struct isa_driver rcdriver = {
86	INTR_TYPE_TTY,
87	rcprobe,
88	rcattach,
89	"rc"
90};
91COMPAT_ISA_DRIVER(rc, rcdriver);
92
93static	d_open_t	rcopen;
94static	d_close_t	rcclose;
95static	d_ioctl_t	rcioctl;
96
97#define	CDEV_MAJOR	63
98static struct cdevsw rc_cdevsw = {
99	/* open */	rcopen,
100	/* close */	rcclose,
101	/* read */	ttyread,
102	/* write */	ttywrite,
103	/* ioctl */	rcioctl,
104	/* poll */	ttypoll,
105	/* mmap */	nommap,
106	/* strategy */	nostrategy,
107	/* name */	"rc",
108	/* maj */	CDEV_MAJOR,
109	/* dump */	nodump,
110	/* psize */	nopsize,
111	/* flags */	D_TTY,
112	/* bmaj */	-1
113};
114
115/* Per-board structure */
116static struct rc_softc {
117	u_int           rcb_probed;     /* 1 - probed, 2 - attached */
118	u_int           rcb_addr;       /* Base I/O addr        */
119	u_int           rcb_unit;       /* unit #               */
120	u_char          rcb_dtr;        /* DTR status           */
121	struct rc_chans *rcb_baserc;    /* base rc ptr          */
122} rc_softc[NRC];
123
124/* Per-channel structure */
125static struct rc_chans  {
126	struct rc_softc *rc_rcb;                /* back ptr             */
127	u_short          rc_flags;              /* Misc. flags          */
128	int              rc_chan;               /* Channel #            */
129	u_char           rc_ier;                /* intr. enable reg     */
130	u_char           rc_msvr;               /* modem sig. status    */
131	u_char           rc_cor2;               /* options reg          */
132	u_char           rc_pendcmd;            /* special cmd pending  */
133	u_int            rc_dtrwait;            /* dtr timeout          */
134	u_int            rc_dcdwaits;           /* how many waits DCD in open */
135	u_char		 rc_hotchar;		/* end packed optimize */
136	struct tty      *rc_tp;                 /* tty struct           */
137	u_char          *rc_iptr;               /* Chars input buffer         */
138	u_char          *rc_hiwat;              /* hi-water mark        */
139	u_char          *rc_bufend;             /* end of buffer        */
140	u_char          *rc_optr;               /* ptr in output buf    */
141	u_char          *rc_obufend;            /* end of output buf    */
142	u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
143	u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
144} rc_chans[NRC * CD180_NCHAN];
145
146static int rc_scheduled_event = 0;
147
148/* for pstat -t */
149static struct tty rc_tty[NRC * CD180_NCHAN];
150static const int  nrc_tty = NRC * CD180_NCHAN;
151
152/* Flags */
153#define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
154#define RC_ACTOUT       0x0002          /* Dial-out port active         */
155#define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
156#define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
157#define RC_DORXFER      0x0010          /* RXFER event planned          */
158#define RC_DOXXFER      0x0020          /* XXFER event planned          */
159#define RC_MODCHG       0x0040          /* Modem status changed         */
160#define RC_OSUSP        0x0080          /* Output suspended             */
161#define RC_OSBUSY       0x0100          /* start() routine in progress  */
162#define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
163#define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
164#define RC_SEND_RDY     0x0800          /* ready to send */
165
166/* Table for translation of RCSR status bits to internal form */
167static int rc_rcsrt[16] = {
168	0,             TTY_OE,               TTY_FE,
169	TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
170	TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
171	TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
172	TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
173	TTY_BI|TTY_PE|TTY_FE|TTY_OE
174};
175
176/* Static prototypes */
177static ointhand2_t rcintr;
178static void rc_hwreset          __P((int, int, unsigned int));
179static int  rc_test             __P((int, int));
180static void rc_discard_output   __P((struct rc_chans *));
181static void rc_hardclose        __P((struct rc_chans *));
182static int  rc_modctl           __P((struct rc_chans *, int, int));
183static void rc_start            __P((struct tty *));
184static void rc_stop              __P((struct tty *, int rw));
185static int  rc_param            __P((struct tty *, struct termios *));
186static swihand_t rcpoll;
187static void rc_reinit           __P((struct rc_softc *));
188#ifdef RCDEBUG
189static void printrcflags();
190#endif
191static timeout_t rc_dtrwakeup;
192static timeout_t rc_wakeup;
193static void disc_optim		__P((struct tty	*tp, struct termios *t,	struct rc_chans	*));
194static void rc_wait0            __P((int nec, int unit, int chan, int line));
195
196/**********************************************/
197
198/* Quick device probing */
199static int
200rcprobe(dvp)
201	struct  isa_device      *dvp;
202{
203	int             irq = ffs(dvp->id_irq) - 1;
204	register int    nec = dvp->id_iobase;
205
206	if (dvp->id_unit > NRC)
207		return 0;
208	if (!RC_VALIDADDR(nec)) {
209		printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
210		return 0;
211	}
212	if (!RC_VALIDIRQ(irq)) {
213		printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
214		return 0;
215	}
216	rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
217	rcout(CD180_PPRH, 0x11);
218	if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
219		return 0;
220	/* Now, test the board more thoroughly, with diagnostic */
221	if (rc_test(nec, dvp->id_unit))
222		return 0;
223	rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
224
225	return 0xF;
226}
227
228static int
229rcattach(dvp)
230	struct  isa_device      *dvp;
231{
232	register int            chan, nec = dvp->id_iobase;
233	struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
234	struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
235	static int              rc_started = 0;
236	struct tty              *tp;
237
238	dvp->id_ointr = rcintr;
239
240	/* Thorooughly test the device */
241	if (rcb->rcb_probed != RC_PROBED)
242		return 0;
243	rcb->rcb_addr   = nec;
244	rcb->rcb_dtr    = 0;
245	rcb->rcb_baserc = rc;
246	rcb->rcb_unit	= dvp->id_unit;
247	/*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
248	printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
249		CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
250
251	for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
252		rc->rc_rcb     = rcb;
253		rc->rc_chan    = chan;
254		rc->rc_iptr    = rc->rc_ibuf;
255		rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
256		rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
257		rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
258		rc->rc_cor2    = rc->rc_pendcmd = 0;
259		rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
260		rc->rc_dtrwait = 3 * hz;
261		rc->rc_dcdwaits= 0;
262		rc->rc_hotchar = 0;
263		tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
264		ttychars(tp);
265		tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
266		tp->t_cflag = TTYDEF_CFLAG;
267		tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
268	}
269	rcb->rcb_probed = RC_ATTACHED;
270	if (!rc_started) {
271		cdevsw_add(&rc_cdevsw);
272		register_swi(SWI_TTY, rcpoll);
273		rc_wakeup((void *)NULL);
274		rc_started = 1;
275	}
276	return 1;
277}
278
279/* RC interrupt handling */
280static void
281rcintr(unit)
282	int             unit;
283{
284	register struct rc_softc        *rcb = &rc_softc[unit];
285	register struct rc_chans        *rc;
286	register int                    nec, resid;
287	register u_char                 val, iack, bsr, ucnt, *optr;
288	int                             good_data, t_state;
289
290	if (rcb->rcb_probed != RC_ATTACHED) {
291		printf("rc%d: bogus interrupt\n", unit);
292		return;
293	}
294	nec = rcb->rcb_addr;
295
296	bsr = ~(rcin(RC_BSR));
297
298	if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
299		printf("rc%d: extra interrupt\n", unit);
300		rcout(CD180_EOIR, 0);
301		return;
302	}
303
304	while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
305#ifdef RCDEBUG_DETAILED
306		printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
307			(bsr & RC_BSR_TOUT)?"TOUT ":"",
308			(bsr & RC_BSR_RXINT)?"RXINT ":"",
309			(bsr & RC_BSR_TXINT)?"TXINT ":"",
310			(bsr & RC_BSR_MOINT)?"MOINT":"");
311#endif
312		if (bsr & RC_BSR_TOUT) {
313			printf("rc%d: hardware failure, reset board\n", unit);
314			rcout(RC_CTOUT, 0);
315			rc_reinit(rcb);
316			return;
317		}
318		if (bsr & RC_BSR_RXINT) {
319			iack = rcin(RC_PILR_RX);
320			good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
321			if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
322				printf("rc%d: fake rxint: %02x\n", unit, iack);
323				goto more_intrs;
324			}
325			rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
326			t_state = rc->rc_tp->t_state;
327			/* Do RTS flow control stuff */
328			if (  (rc->rc_flags & RC_RTSFLOW)
329			    || !(t_state & TS_ISOPEN)
330			   ) {
331				if (  (   !(t_state & TS_ISOPEN)
332				       || (t_state & TS_TBLOCK)
333				      )
334				    && (rc->rc_msvr & MSVR_RTS)
335				   )
336					rcout(CD180_MSVR,
337						rc->rc_msvr &= ~MSVR_RTS);
338				else if (!(rc->rc_msvr & MSVR_RTS))
339					rcout(CD180_MSVR,
340						rc->rc_msvr |= MSVR_RTS);
341			}
342			ucnt  = rcin(CD180_RDCR) & 0xF;
343			resid = 0;
344
345			if (t_state & TS_ISOPEN) {
346				/* check for input buffer overflow */
347				if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
348					resid  = ucnt;
349					ucnt   = rc->rc_bufend - rc->rc_iptr;
350					resid -= ucnt;
351					if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
352						rc->rc_flags |= RC_WAS_BUFOVFL;
353						rc_scheduled_event++;
354					}
355				}
356				optr = rc->rc_iptr;
357				/* check foor good data */
358				if (good_data) {
359					while (ucnt-- > 0) {
360						val = rcin(CD180_RDR);
361						optr[0] = val;
362						optr[INPUT_FLAGS_SHIFT] = 0;
363						optr++;
364						rc_scheduled_event++;
365						if (val != 0 && val == rc->rc_hotchar)
366							setsofttty();
367					}
368				} else {
369					/* Store also status data */
370					while (ucnt-- > 0) {
371						iack = rcin(CD180_RCSR);
372						if (iack & RCSR_Timeout)
373							break;
374						if (   (iack & RCSR_OE)
375						    && !(rc->rc_flags & RC_WAS_SILOVFL)) {
376							rc->rc_flags |= RC_WAS_SILOVFL;
377							rc_scheduled_event++;
378						}
379						val = rcin(CD180_RDR);
380						/*
381						  Don't store PE if IGNPAR and BREAK if IGNBRK,
382						  this hack allows "raw" tty optimization
383						  works even if IGN* is set.
384						*/
385						if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
386						    || ((!(iack & (RCSR_PE|RCSR_FE))
387						    ||  !(rc->rc_tp->t_iflag & IGNPAR))
388						    && (!(iack & RCSR_Break)
389						    ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
390							if (   (iack & (RCSR_PE|RCSR_FE))
391							    && (t_state & TS_CAN_BYPASS_L_RINT)
392							    && ((iack & RCSR_FE)
393							    ||  ((iack & RCSR_PE)
394							    &&  (rc->rc_tp->t_iflag & INPCK))))
395								val = 0;
396							else if (val != 0 && val == rc->rc_hotchar)
397								setsofttty();
398							optr[0] = val;
399							optr[INPUT_FLAGS_SHIFT] = iack;
400							optr++;
401							rc_scheduled_event++;
402						}
403					}
404				}
405				rc->rc_iptr = optr;
406				rc->rc_flags |= RC_DORXFER;
407			} else
408				resid = ucnt;
409			/* Clear FIFO if necessary */
410			while (resid-- > 0) {
411				if (!good_data)
412					iack = rcin(CD180_RCSR);
413				else
414					iack = 0;
415				if (iack & RCSR_Timeout)
416					break;
417				(void) rcin(CD180_RDR);
418			}
419			goto more_intrs;
420		}
421		if (bsr & RC_BSR_MOINT) {
422			iack = rcin(RC_PILR_MODEM);
423			if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
424				printf("rc%d: fake moint: %02x\n", unit, iack);
425				goto more_intrs;
426			}
427			rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
428			iack = rcin(CD180_MCR);
429			rc->rc_msvr = rcin(CD180_MSVR);
430			rcout(CD180_MCR, 0);
431#ifdef RCDEBUG
432			printrcflags(rc, "moint");
433#endif
434			if (rc->rc_flags & RC_CTSFLOW) {
435				if (rc->rc_msvr & MSVR_CTS)
436					rc->rc_flags |= RC_SEND_RDY;
437				else
438					rc->rc_flags &= ~RC_SEND_RDY;
439			} else
440				rc->rc_flags |= RC_SEND_RDY;
441			if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
442				rc_scheduled_event += LOTS_OF_EVENTS;
443				rc->rc_flags |= RC_MODCHG;
444				setsofttty();
445			}
446			goto more_intrs;
447		}
448		if (bsr & RC_BSR_TXINT) {
449			iack = rcin(RC_PILR_TX);
450			if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
451				printf("rc%d: fake txint: %02x\n", unit, iack);
452				goto more_intrs;
453			}
454			rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
455			if (    (rc->rc_flags & RC_OSUSP)
456			    || !(rc->rc_flags & RC_SEND_RDY)
457			   )
458				goto more_intrs;
459			/* Handle breaks and other stuff */
460			if (rc->rc_pendcmd) {
461				rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
462				rcout(CD180_TDR,  CD180_C_ESC);
463				rcout(CD180_TDR,  rc->rc_pendcmd);
464				rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
465				rc->rc_pendcmd = 0;
466				goto more_intrs;
467			}
468			optr = rc->rc_optr;
469			resid = rc->rc_obufend - optr;
470			if (resid > CD180_NFIFO)
471				resid = CD180_NFIFO;
472			while (resid-- > 0)
473				rcout(CD180_TDR, *optr++);
474			rc->rc_optr = optr;
475
476			/* output completed? */
477			if (optr >= rc->rc_obufend) {
478				rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
479#ifdef RCDEBUG
480				printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
481#endif
482				if (!(rc->rc_flags & RC_DOXXFER)) {
483					rc_scheduled_event += LOTS_OF_EVENTS;
484					rc->rc_flags |= RC_DOXXFER;
485					setsofttty();
486				}
487			}
488		}
489	more_intrs:
490		rcout(CD180_EOIR, 0);   /* end of interrupt */
491		rcout(RC_CTOUT, 0);
492		bsr = ~(rcin(RC_BSR));
493	}
494}
495
496/* Feed characters to output buffer */
497static void rc_start(tp)
498register struct tty *tp;
499{
500	register struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
501	register int                    nec = rc->rc_rcb->rcb_addr, s;
502
503	if (rc->rc_flags & RC_OSBUSY)
504		return;
505	s = spltty();
506	rc->rc_flags |= RC_OSBUSY;
507	disable_intr();
508	if (tp->t_state & TS_TTSTOP)
509		rc->rc_flags |= RC_OSUSP;
510	else
511		rc->rc_flags &= ~RC_OSUSP;
512	/* Do RTS flow control stuff */
513	if (   (rc->rc_flags & RC_RTSFLOW)
514	    && (tp->t_state & TS_TBLOCK)
515	    && (rc->rc_msvr & MSVR_RTS)
516	   ) {
517		rcout(CD180_CAR, rc->rc_chan);
518		rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
519	} else if (!(rc->rc_msvr & MSVR_RTS)) {
520		rcout(CD180_CAR, rc->rc_chan);
521		rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
522	}
523	enable_intr();
524	if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
525		goto out;
526#ifdef RCDEBUG
527	printrcflags(rc, "rcstart");
528#endif
529	ttwwakeup(tp);
530#ifdef RCDEBUG
531	printf("rcstart: outq = %d obuf = %d\n",
532		tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
533#endif
534	if (tp->t_state & TS_BUSY)
535		goto    out;    /* output still in progress ... */
536
537	if (tp->t_outq.c_cc > 0) {
538		u_int   ocnt;
539
540		tp->t_state |= TS_BUSY;
541		ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
542		disable_intr();
543		rc->rc_optr = rc->rc_obuf;
544		rc->rc_obufend = rc->rc_optr + ocnt;
545		enable_intr();
546		if (!(rc->rc_ier & IER_TxRdy)) {
547#ifdef RCDEBUG
548			printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
549#endif
550			rcout(CD180_CAR, rc->rc_chan);
551			rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
552		}
553	}
554out:
555	rc->rc_flags &= ~RC_OSBUSY;
556	(void) splx(s);
557}
558
559/* Handle delayed events. */
560void rcpoll()
561{
562	register struct rc_chans *rc;
563	register struct rc_softc *rcb;
564	register u_char        *tptr, *eptr;
565	register struct tty    *tp;
566	register int            chan, icnt, nec, unit;
567
568	if (rc_scheduled_event == 0)
569		return;
570repeat:
571	for (unit = 0; unit < NRC; unit++) {
572		rcb = &rc_softc[unit];
573		rc = rcb->rcb_baserc;
574		nec = rc->rc_rcb->rcb_addr;
575		for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
576			tp = rc->rc_tp;
577#ifdef RCDEBUG
578			if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
579			    RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
580				printrcflags(rc, "rcevent");
581#endif
582			if (rc->rc_flags & RC_WAS_BUFOVFL) {
583				disable_intr();
584				rc->rc_flags &= ~RC_WAS_BUFOVFL;
585				rc_scheduled_event--;
586				enable_intr();
587				printf("rc%d/%d: interrupt-level buffer overflow\n",
588					unit, chan);
589			}
590			if (rc->rc_flags & RC_WAS_SILOVFL) {
591				disable_intr();
592				rc->rc_flags &= ~RC_WAS_SILOVFL;
593				rc_scheduled_event--;
594				enable_intr();
595				printf("rc%d/%d: silo overflow\n",
596					unit, chan);
597			}
598			if (rc->rc_flags & RC_MODCHG) {
599				disable_intr();
600				rc->rc_flags &= ~RC_MODCHG;
601				rc_scheduled_event -= LOTS_OF_EVENTS;
602				enable_intr();
603				(*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
604			}
605			if (rc->rc_flags & RC_DORXFER) {
606				disable_intr();
607				rc->rc_flags &= ~RC_DORXFER;
608				eptr = rc->rc_iptr;
609				if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
610					tptr = &rc->rc_ibuf[RC_IBUFSIZE];
611				else
612					tptr = rc->rc_ibuf;
613				icnt = eptr - tptr;
614				if (icnt > 0) {
615					if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
616						rc->rc_iptr   = rc->rc_ibuf;
617						rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
618						rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
619					} else {
620						rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
621						rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
622						rc->rc_hiwat  =
623							&rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
624					}
625					if (   (rc->rc_flags & RC_RTSFLOW)
626					    && (tp->t_state & TS_ISOPEN)
627					    && !(tp->t_state & TS_TBLOCK)
628					    && !(rc->rc_msvr & MSVR_RTS)
629					    ) {
630						rcout(CD180_CAR, chan);
631						rcout(CD180_MSVR,
632							rc->rc_msvr |= MSVR_RTS);
633					}
634					rc_scheduled_event -= icnt;
635				}
636				enable_intr();
637
638				if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
639					goto done1;
640
641				if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
642				    && !(tp->t_state & TS_LOCAL)) {
643					if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
644					    && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
645					    && !(tp->t_state & TS_TBLOCK))
646						ttyblock(tp);
647					tk_nin += icnt;
648					tk_rawcc += icnt;
649					tp->t_rawcc += icnt;
650					if (b_to_q(tptr, icnt, &tp->t_rawq))
651						printf("rc%d/%d: tty-level buffer overflow\n",
652							unit, chan);
653					ttwakeup(tp);
654					if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
655					    || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
656						tp->t_state &= ~TS_TTSTOP;
657						tp->t_lflag &= ~FLUSHO;
658						rc_start(tp);
659					}
660				} else {
661					for (; tptr < eptr; tptr++)
662						(*linesw[tp->t_line].l_rint)
663						    (tptr[0] |
664						    rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
665				}
666done1: ;
667			}
668			if (rc->rc_flags & RC_DOXXFER) {
669				disable_intr();
670				rc_scheduled_event -= LOTS_OF_EVENTS;
671				rc->rc_flags &= ~RC_DOXXFER;
672				rc->rc_tp->t_state &= ~TS_BUSY;
673				enable_intr();
674				(*linesw[tp->t_line].l_start)(tp);
675			}
676		}
677		if (rc_scheduled_event == 0)
678			break;
679	}
680	if (rc_scheduled_event >= LOTS_OF_EVENTS)
681		goto repeat;
682}
683
684static	void
685rc_stop(tp, rw)
686	register struct tty     *tp;
687	int                     rw;
688{
689	register struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
690	u_char *tptr, *eptr;
691
692#ifdef RCDEBUG
693	printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
694		(rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
695#endif
696	if (rw & FWRITE)
697		rc_discard_output(rc);
698	disable_intr();
699	if (rw & FREAD) {
700		rc->rc_flags &= ~RC_DORXFER;
701		eptr = rc->rc_iptr;
702		if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
703			tptr = &rc->rc_ibuf[RC_IBUFSIZE];
704			rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
705		} else {
706			tptr = rc->rc_ibuf;
707			rc->rc_iptr = rc->rc_ibuf;
708		}
709		rc_scheduled_event -= eptr - tptr;
710	}
711	if (tp->t_state & TS_TTSTOP)
712		rc->rc_flags |= RC_OSUSP;
713	else
714		rc->rc_flags &= ~RC_OSUSP;
715	enable_intr();
716}
717
718static	int
719rcopen(dev, flag, mode, p)
720	dev_t           dev;
721	int             flag, mode;
722	struct proc    *p;
723{
724	register struct rc_chans *rc;
725	register struct tty      *tp;
726	int             unit, nec, s, error = 0;
727
728	unit = GET_UNIT(dev);
729	if (unit >= NRC * CD180_NCHAN)
730		return ENXIO;
731	if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
732		return ENXIO;
733	rc  = &rc_chans[unit];
734	tp  = rc->rc_tp;
735	dev->si_tty = tp;
736	nec = rc->rc_rcb->rcb_addr;
737#ifdef RCDEBUG
738	printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
739#endif
740	s = spltty();
741
742again:
743	while (rc->rc_flags & RC_DTR_OFF) {
744		error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
745		if (error != 0)
746			goto out;
747	}
748	if (tp->t_state & TS_ISOPEN) {
749		if (CALLOUT(dev)) {
750			if (!(rc->rc_flags & RC_ACTOUT)) {
751				error = EBUSY;
752				goto out;
753			}
754		} else {
755			if (rc->rc_flags & RC_ACTOUT) {
756				if (flag & O_NONBLOCK) {
757					error = EBUSY;
758					goto out;
759				}
760				error = tsleep(&rc->rc_rcb,
761				     TTIPRI|PCATCH, "rcbi", 0);
762				if (error)
763					goto out;
764				goto again;
765			}
766		}
767		if (tp->t_state & TS_XCLUDE &&
768		    suser(p)) {
769			error = EBUSY;
770			goto out;
771		}
772	} else {
773		tp->t_oproc   = rc_start;
774		tp->t_param   = rc_param;
775		tp->t_stop    = rc_stop;
776		tp->t_dev     = dev;
777
778		if (CALLOUT(dev))
779			tp->t_cflag |= CLOCAL;
780		else
781			tp->t_cflag &= ~CLOCAL;
782
783		error = rc_param(tp, &tp->t_termios);
784		if (error)
785			goto out;
786		(void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
787
788		if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
789			(*linesw[tp->t_line].l_modem)(tp, 1);
790	}
791	if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
792	    && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
793		rc->rc_dcdwaits++;
794		error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0);
795		rc->rc_dcdwaits--;
796		if (error != 0)
797			goto out;
798		goto again;
799	}
800	error = (*linesw[tp->t_line].l_open)(dev, tp);
801	disc_optim(tp, &tp->t_termios, rc);
802	if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
803		rc->rc_flags |= RC_ACTOUT;
804out:
805	(void) splx(s);
806
807	if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
808		rc_hardclose(rc);
809
810	return error;
811}
812
813static	int
814rcclose(dev, flag, mode, p)
815	dev_t           dev;
816	int             flag, mode;
817	struct proc    *p;
818{
819	register struct rc_chans *rc;
820	register struct tty      *tp;
821	int  s, unit = GET_UNIT(dev);
822
823	if (unit >= NRC * CD180_NCHAN)
824		return ENXIO;
825	rc  = &rc_chans[unit];
826	tp  = rc->rc_tp;
827#ifdef RCDEBUG
828	printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
829#endif
830	s = spltty();
831	(*linesw[tp->t_line].l_close)(tp, flag);
832	disc_optim(tp, &tp->t_termios, rc);
833	rc_stop(tp, FREAD | FWRITE);
834	rc_hardclose(rc);
835	ttyclose(tp);
836	splx(s);
837	return 0;
838}
839
840static void rc_hardclose(rc)
841register struct rc_chans *rc;
842{
843	register int s, nec = rc->rc_rcb->rcb_addr;
844	register struct tty *tp = rc->rc_tp;
845
846	s = spltty();
847	rcout(CD180_CAR, rc->rc_chan);
848
849	/* Disable rx/tx intrs */
850	rcout(CD180_IER, rc->rc_ier = 0);
851	if (   (tp->t_cflag & HUPCL)
852	    || (!(rc->rc_flags & RC_ACTOUT)
853	       && !(rc->rc_msvr & MSVR_CD)
854	       && !(tp->t_cflag & CLOCAL))
855	    || !(tp->t_state & TS_ISOPEN)
856	   ) {
857		CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
858		WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
859		(void) rc_modctl(rc, TIOCM_RTS, DMSET);
860		if (rc->rc_dtrwait) {
861			timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
862			rc->rc_flags |= RC_DTR_OFF;
863		}
864	}
865	rc->rc_flags &= ~RC_ACTOUT;
866	wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
867	wakeup(TSA_CARR_ON(tp));
868	(void) splx(s);
869}
870
871/* Reset the bastard */
872static void rc_hwreset(unit, nec, chipid)
873	register int    unit, nec;
874	unsigned int    chipid;
875{
876	CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
877	DELAY(20000);
878	WAITFORCCR(unit, -1);
879
880	rcout(RC_CTOUT, 0);             /* Clear timeout  */
881	rcout(CD180_GIVR,  chipid);
882	rcout(CD180_GICR,  0);
883
884	/* Set Prescaler Registers (1 msec) */
885	rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
886	rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
887
888	/* Initialize Priority Interrupt Level Registers */
889	rcout(CD180_PILR1, RC_PILR_MODEM);
890	rcout(CD180_PILR2, RC_PILR_TX);
891	rcout(CD180_PILR3, RC_PILR_RX);
892
893	/* Reset DTR */
894	rcout(RC_DTREG, ~0);
895}
896
897/* Set channel parameters */
898static int rc_param(tp, ts)
899	register struct  tty    *tp;
900	struct termios          *ts;
901{
902	register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
903	register int    nec = rc->rc_rcb->rcb_addr;
904	int      idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
905
906	if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
907	    || ts->c_ispeed < 0 || ts->c_ispeed > 76800
908	   )
909		return (EINVAL);
910	if (ts->c_ispeed == 0)
911		ts->c_ispeed = ts->c_ospeed;
912	odivs = RC_BRD(ts->c_ospeed);
913	idivs = RC_BRD(ts->c_ispeed);
914
915	s = spltty();
916
917	/* Select channel */
918	rcout(CD180_CAR, rc->rc_chan);
919
920	/* If speed == 0, hangup line */
921	if (ts->c_ospeed == 0) {
922		CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
923		WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
924		(void) rc_modctl(rc, TIOCM_DTR, DMBIC);
925	}
926
927	tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
928	cflag = ts->c_cflag;
929	iflag = ts->c_iflag;
930	lflag = ts->c_lflag;
931
932	if (idivs > 0) {
933		rcout(CD180_RBPRL, idivs & 0xFF);
934		rcout(CD180_RBPRH, idivs >> 8);
935	}
936	if (odivs > 0) {
937		rcout(CD180_TBPRL, odivs & 0xFF);
938		rcout(CD180_TBPRH, odivs >> 8);
939	}
940
941	/* set timeout value */
942	if (ts->c_ispeed > 0) {
943		int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
944
945		if (   !(lflag & ICANON)
946		    && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
947		    && ts->c_cc[VTIME] * 10 > itm)
948			itm = ts->c_cc[VTIME] * 10;
949
950		rcout(CD180_RTPR, itm <= 255 ? itm : 255);
951	}
952
953	switch (cflag & CSIZE) {
954		case CS5:       val = COR1_5BITS;      break;
955		case CS6:       val = COR1_6BITS;      break;
956		case CS7:       val = COR1_7BITS;      break;
957		default:
958		case CS8:       val = COR1_8BITS;      break;
959	}
960	if (cflag & PARENB) {
961		val |= COR1_NORMPAR;
962		if (cflag & PARODD)
963			val |= COR1_ODDP;
964		if (!(cflag & INPCK))
965			val |= COR1_Ignore;
966	} else
967		val |= COR1_Ignore;
968	if (cflag & CSTOPB)
969		val |= COR1_2SB;
970	rcout(CD180_COR1, val);
971
972	/* Set FIFO threshold */
973	val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
974	inpflow = 0;
975	if (   (iflag & IXOFF)
976	    && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
977		&& (   ts->c_cc[VSTART] != _POSIX_VDISABLE
978		    || (iflag & IXANY)
979		   )
980	       )
981	   ) {
982		inpflow = 1;
983		val |= COR3_SCDE|COR3_FCT;
984	}
985	rcout(CD180_COR3, val);
986
987	/* Initialize on-chip automatic flow control */
988	val = 0;
989	rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
990	if (cflag & CCTS_OFLOW) {
991		rc->rc_flags |= RC_CTSFLOW;
992		val |= COR2_CtsAE;
993	} else
994		rc->rc_flags |= RC_SEND_RDY;
995	if (tp->t_state & TS_TTSTOP)
996		rc->rc_flags |= RC_OSUSP;
997	else
998		rc->rc_flags &= ~RC_OSUSP;
999	if (cflag & CRTS_IFLOW)
1000		rc->rc_flags |= RC_RTSFLOW;
1001	else
1002		rc->rc_flags &= ~RC_RTSFLOW;
1003
1004	if (inpflow) {
1005		if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1006			rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1007		rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1008		val |= COR2_TxIBE;
1009		if (iflag & IXANY)
1010			val |= COR2_IXM;
1011	}
1012
1013	rcout(CD180_COR2, rc->rc_cor2 = val);
1014
1015	CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1016		CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1017
1018	disc_optim(tp, ts, rc);
1019
1020	/* modem ctl */
1021	val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1022	if (cflag & CCTS_OFLOW)
1023		val |= MCOR1_CTSzd;
1024	rcout(CD180_MCOR1, val);
1025
1026	val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1027	if (cflag & CCTS_OFLOW)
1028		val |= MCOR2_CTSod;
1029	rcout(CD180_MCOR2, val);
1030
1031	/* enable i/o and interrupts */
1032	CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1033		CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1034	WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1035
1036	rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1037	if (cflag & CCTS_OFLOW)
1038		rc->rc_ier |= IER_CTS;
1039	if (cflag & CREAD)
1040		rc->rc_ier |= IER_RxData;
1041	if (tp->t_state & TS_BUSY)
1042		rc->rc_ier |= IER_TxRdy;
1043	if (ts->c_ospeed != 0)
1044		rc_modctl(rc, TIOCM_DTR, DMBIS);
1045	if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1046		rc->rc_flags |= RC_SEND_RDY;
1047	rcout(CD180_IER, rc->rc_ier);
1048	(void) splx(s);
1049	return 0;
1050}
1051
1052/* Re-initialize board after bogus interrupts */
1053static void rc_reinit(rcb)
1054struct rc_softc         *rcb;
1055{
1056	register struct rc_chans       *rc, *rce;
1057	register int                    nec;
1058
1059	nec = rcb->rcb_addr;
1060	rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1061	rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1062	rce = rc + CD180_NCHAN;
1063	for (; rc < rce; rc++)
1064		(void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1065}
1066
1067static	int
1068rcioctl(dev, cmd, data, flag, p)
1069dev_t           dev;
1070u_long          cmd;
1071int		flag;
1072caddr_t         data;
1073struct proc     *p;
1074{
1075	register struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1076	register int                    s, error;
1077	struct tty                     *tp = rc->rc_tp;
1078
1079	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1080	if (error != ENOIOCTL)
1081		return (error);
1082	error = ttioctl(tp, cmd, data, flag);
1083	disc_optim(tp, &tp->t_termios, rc);
1084	if (error != ENOIOCTL)
1085		return (error);
1086	s = spltty();
1087
1088	switch (cmd) {
1089	    case TIOCSBRK:
1090		rc->rc_pendcmd = CD180_C_SBRK;
1091		break;
1092
1093	    case TIOCCBRK:
1094		rc->rc_pendcmd = CD180_C_EBRK;
1095		break;
1096
1097	    case TIOCSDTR:
1098		(void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1099		break;
1100
1101	    case TIOCCDTR:
1102		(void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1103		break;
1104
1105	    case TIOCMGET:
1106		*(int *) data = rc_modctl(rc, 0, DMGET);
1107		break;
1108
1109	    case TIOCMSET:
1110		(void) rc_modctl(rc, *(int *) data, DMSET);
1111		break;
1112
1113	    case TIOCMBIC:
1114		(void) rc_modctl(rc, *(int *) data, DMBIC);
1115		break;
1116
1117	    case TIOCMBIS:
1118		(void) rc_modctl(rc, *(int *) data, DMBIS);
1119		break;
1120
1121	    case TIOCMSDTRWAIT:
1122		error = suser(p);
1123		if (error != 0) {
1124			splx(s);
1125			return (error);
1126		}
1127		rc->rc_dtrwait = *(int *)data * hz / 100;
1128		break;
1129
1130	    case TIOCMGDTRWAIT:
1131		*(int *)data = rc->rc_dtrwait * 100 / hz;
1132		break;
1133
1134	    default:
1135		(void) splx(s);
1136		return ENOTTY;
1137	}
1138	(void) splx(s);
1139	return 0;
1140}
1141
1142
1143/* Modem control routines */
1144
1145static int rc_modctl(rc, bits, cmd)
1146register struct rc_chans       *rc;
1147int                             bits, cmd;
1148{
1149	register int    nec = rc->rc_rcb->rcb_addr;
1150	u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1151
1152	rcout(CD180_CAR, rc->rc_chan);
1153
1154	switch (cmd) {
1155	    case DMSET:
1156		rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1157				~(*dtr |= 1 << rc->rc_chan) :
1158				~(*dtr &= ~(1 << rc->rc_chan)));
1159		msvr = rcin(CD180_MSVR);
1160		if (bits & TIOCM_RTS)
1161			msvr |= MSVR_RTS;
1162		else
1163			msvr &= ~MSVR_RTS;
1164		if (bits & TIOCM_DTR)
1165			msvr |= MSVR_DTR;
1166		else
1167			msvr &= ~MSVR_DTR;
1168		rcout(CD180_MSVR, msvr);
1169		break;
1170
1171	    case DMBIS:
1172		if (bits & TIOCM_DTR)
1173			rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1174		msvr = rcin(CD180_MSVR);
1175		if (bits & TIOCM_RTS)
1176			msvr |= MSVR_RTS;
1177		if (bits & TIOCM_DTR)
1178			msvr |= MSVR_DTR;
1179		rcout(CD180_MSVR, msvr);
1180		break;
1181
1182	    case DMGET:
1183		bits = TIOCM_LE;
1184		msvr = rc->rc_msvr = rcin(CD180_MSVR);
1185
1186		if (msvr & MSVR_RTS)
1187			bits |= TIOCM_RTS;
1188		if (msvr & MSVR_CTS)
1189			bits |= TIOCM_CTS;
1190		if (msvr & MSVR_DSR)
1191			bits |= TIOCM_DSR;
1192		if (msvr & MSVR_DTR)
1193			bits |= TIOCM_DTR;
1194		if (msvr & MSVR_CD)
1195			bits |= TIOCM_CD;
1196		if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1197			bits |= TIOCM_RI;
1198		return bits;
1199
1200	    case DMBIC:
1201		if (bits & TIOCM_DTR)
1202			rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1203		msvr = rcin(CD180_MSVR);
1204		if (bits & TIOCM_RTS)
1205			msvr &= ~MSVR_RTS;
1206		if (bits & TIOCM_DTR)
1207			msvr &= ~MSVR_DTR;
1208		rcout(CD180_MSVR, msvr);
1209		break;
1210	}
1211	rc->rc_msvr = rcin(CD180_MSVR);
1212	return 0;
1213}
1214
1215/* Test the board. */
1216int rc_test(nec, unit)
1217	register int    nec;
1218	int             unit;
1219{
1220	int     chan = 0;
1221	int     i = 0, rcnt, old_level;
1222	unsigned int    iack, chipid;
1223	unsigned short  divs;
1224	static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1225#define CTLEN   8
1226#define ERR(s)  { \
1227		printf("rc%d: ", unit); printf s ; printf("\n"); \
1228		(void) splx(old_level); return 1; }
1229
1230	struct rtest {
1231		u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1232		u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1233		int     rxptr;                  /* RX pointer */
1234		int     txptr;                  /* TX pointer */
1235	} tchans[CD180_NCHAN];
1236
1237	old_level = spltty();
1238
1239	chipid = RC_FAKEID;
1240
1241	/* First, reset board to inital state */
1242	rc_hwreset(unit, nec, chipid);
1243
1244	divs = RC_BRD(19200);
1245
1246	/* Initialize channels */
1247	for (chan = 0; chan < CD180_NCHAN; chan++) {
1248
1249		/* Select and reset channel */
1250		rcout(CD180_CAR, chan);
1251		CCRCMD(unit, chan, CCR_ResetChan);
1252		WAITFORCCR(unit, chan);
1253
1254		/* Set speed */
1255		rcout(CD180_RBPRL, divs & 0xFF);
1256		rcout(CD180_RBPRH, divs >> 8);
1257		rcout(CD180_TBPRL, divs & 0xFF);
1258		rcout(CD180_TBPRH, divs >> 8);
1259
1260		/* set timeout value */
1261		rcout(CD180_RTPR,  0);
1262
1263		/* Establish local loopback */
1264		rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1265		rcout(CD180_COR2, COR2_LLM);
1266		rcout(CD180_COR3, CD180_NFIFO);
1267		CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1268		CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1269		WAITFORCCR(unit, chan);
1270		rcout(CD180_MSVR, MSVR_RTS);
1271
1272		/* Fill TXBUF with test data */
1273		for (i = 0; i < CD180_NFIFO; i++) {
1274			tchans[chan].txbuf[i] = ctest[i];
1275			tchans[chan].rxbuf[i] = 0;
1276		}
1277		tchans[chan].txptr = tchans[chan].rxptr = 0;
1278
1279		/* Now, start transmit */
1280		rcout(CD180_IER, IER_TxMpty|IER_RxData);
1281	}
1282	/* Pseudo-interrupt poll stuff */
1283	for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1284		i = ~(rcin(RC_BSR));
1285		if (i & RC_BSR_TOUT)
1286			ERR(("BSR timeout bit set\n"))
1287		else if (i & RC_BSR_TXINT) {
1288			iack = rcin(RC_PILR_TX);
1289			if (iack != (GIVR_IT_TDI | chipid))
1290				ERR(("Bad TX intr ack (%02x != %02x)\n",
1291					iack, GIVR_IT_TDI | chipid));
1292			chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1293			/* If no more data to transmit, disable TX intr */
1294			if (tchans[chan].txptr >= CD180_NFIFO) {
1295				iack = rcin(CD180_IER);
1296				rcout(CD180_IER, iack & ~IER_TxMpty);
1297			} else {
1298				for (iack = tchans[chan].txptr;
1299				    iack < CD180_NFIFO; iack++)
1300					rcout(CD180_TDR,
1301					    tchans[chan].txbuf[iack]);
1302				tchans[chan].txptr = iack;
1303			}
1304			rcout(CD180_EOIR, 0);
1305		} else if (i & RC_BSR_RXINT) {
1306			u_char ucnt;
1307
1308			iack = rcin(RC_PILR_RX);
1309			if (iack != (GIVR_IT_RGDI | chipid) &&
1310			    iack != (GIVR_IT_REI  | chipid))
1311				ERR(("Bad RX intr ack (%02x != %02x)\n",
1312					iack, GIVR_IT_RGDI | chipid))
1313			chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1314			ucnt = rcin(CD180_RDCR) & 0xF;
1315			while (ucnt-- > 0) {
1316				iack = rcin(CD180_RCSR);
1317				if (iack & RCSR_Timeout)
1318					break;
1319				if (iack & 0xF)
1320					ERR(("Bad char chan %d (RCSR = %02X)\n",
1321					    chan, iack))
1322				if (tchans[chan].rxptr > CD180_NFIFO)
1323					ERR(("Got extra chars chan %d\n",
1324					    chan))
1325				tchans[chan].rxbuf[tchans[chan].rxptr++] =
1326					rcin(CD180_RDR);
1327			}
1328			rcout(CD180_EOIR, 0);
1329		}
1330		rcout(RC_CTOUT, 0);
1331		for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1332			if (tchans[chan].rxptr >= CD180_NFIFO)
1333				iack++;
1334		if (iack == CD180_NCHAN)
1335			break;
1336	}
1337	for (chan = 0; chan < CD180_NCHAN; chan++) {
1338		/* Select and reset channel */
1339		rcout(CD180_CAR, chan);
1340		CCRCMD(unit, chan, CCR_ResetChan);
1341	}
1342
1343	if (!rcnt)
1344		ERR(("looses characters during local loopback\n"))
1345	/* Now, check data */
1346	for (chan = 0; chan < CD180_NCHAN; chan++)
1347		for (i = 0; i < CD180_NFIFO; i++)
1348			if (ctest[i] != tchans[chan].rxbuf[i])
1349				ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1350				    chan, i, ctest[i], tchans[chan].rxbuf[i]))
1351	(void) splx(old_level);
1352	return 0;
1353}
1354
1355#ifdef RCDEBUG
1356static void printrcflags(rc, comment)
1357struct rc_chans  *rc;
1358char             *comment;
1359{
1360	u_short f = rc->rc_flags;
1361	register int    nec = rc->rc_rcb->rcb_addr;
1362
1363	printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1364		rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1365		(f & RC_DTR_OFF)?"DTR_OFF " :"",
1366		(f & RC_ACTOUT) ?"ACTOUT " :"",
1367		(f & RC_RTSFLOW)?"RTSFLOW " :"",
1368		(f & RC_CTSFLOW)?"CTSFLOW " :"",
1369		(f & RC_DORXFER)?"DORXFER " :"",
1370		(f & RC_DOXXFER)?"DOXXFER " :"",
1371		(f & RC_MODCHG) ?"MODCHG "  :"",
1372		(f & RC_OSUSP)  ?"OSUSP " :"",
1373		(f & RC_OSBUSY) ?"OSBUSY " :"",
1374		(f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1375		(f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1376		(f & RC_SEND_RDY) ?"SEND_RDY":"");
1377
1378	rcout(CD180_CAR, rc->rc_chan);
1379
1380	printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1381		rc->rc_rcb->rcb_unit, rc->rc_chan,
1382		rcin(CD180_MSVR),
1383		rcin(CD180_IER),
1384		rcin(CD180_CCSR));
1385}
1386#endif /* RCDEBUG */
1387
1388static void
1389rc_dtrwakeup(chan)
1390	void	*chan;
1391{
1392	struct rc_chans  *rc;
1393
1394	rc = (struct rc_chans *)chan;
1395	rc->rc_flags &= ~RC_DTR_OFF;
1396	wakeup(&rc->rc_dtrwait);
1397}
1398
1399static void
1400rc_discard_output(rc)
1401	struct rc_chans  *rc;
1402{
1403	disable_intr();
1404	if (rc->rc_flags & RC_DOXXFER) {
1405		rc_scheduled_event -= LOTS_OF_EVENTS;
1406		rc->rc_flags &= ~RC_DOXXFER;
1407	}
1408	rc->rc_optr = rc->rc_obufend;
1409	rc->rc_tp->t_state &= ~TS_BUSY;
1410	enable_intr();
1411	ttwwakeup(rc->rc_tp);
1412}
1413
1414static void
1415rc_wakeup(chan)
1416	void	*chan;
1417{
1418	timeout(rc_wakeup, (caddr_t)NULL, 1);
1419
1420	if (rc_scheduled_event != 0) {
1421		int	s;
1422
1423		s = splsofttty();
1424		rcpoll();
1425		splx(s);
1426	}
1427}
1428
1429static void
1430disc_optim(tp, t, rc)
1431	struct tty	*tp;
1432	struct termios	*t;
1433	struct rc_chans	*rc;
1434{
1435
1436	if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1437	    && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1438	    && (!(t->c_iflag & PARMRK)
1439		|| (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1440	    && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1441	    && linesw[tp->t_line].l_rint == ttyinput)
1442		tp->t_state |= TS_CAN_BYPASS_L_RINT;
1443	else
1444		tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1445	rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1446}
1447
1448static void
1449rc_wait0(nec, unit, chan, line)
1450	int     nec, unit, chan, line;
1451{
1452	int rcnt;
1453
1454	for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1455		DELAY(30);
1456	if (rcnt == 0)
1457		printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1458		      unit, chan, line);
1459}
1460