rc.c revision 46704
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34 35#if NRC > 0 36 37#include "opt_devfs.h" 38 39/*#define RCDEBUG*/ 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/tty.h> 44#include <sys/proc.h> 45#include <sys/conf.h> 46#include <sys/dkstat.h> 47#include <sys/fcntl.h> 48#include <sys/interrupt.h> 49#include <sys/kernel.h> 50#ifdef DEVFS 51#include <sys/devfsext.h> 52#endif /*DEVFS*/ 53 54#include <machine/clock.h> 55#include <machine/ipl.h> 56 57#include <i386/isa/isa_device.h> 58 59#include <i386/isa/ic/cd180.h> 60#include <i386/isa/rcreg.h> 61 62 63/* Prototypes */ 64static int rcprobe __P((struct isa_device *)); 65static int rcattach __P((struct isa_device *)); 66 67#define rcin(port) RC_IN (nec, port) 68#define rcout(port,v) RC_OUT (nec, port, v) 69 70#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 71#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 72 73#define RC_IBUFSIZE 256 74#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 75#define RC_OBUFSIZE 512 76#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 77#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 78#define LOTS_OF_EVENTS 64 79 80#define RC_FAKEID 0x10 81 82#define RC_PROBED 1 83#define RC_ATTACHED 2 84 85#define GET_UNIT(dev) (minor(dev) & 0x3F) 86#define CALLOUT(dev) (minor(dev) & 0x80) 87 88/* For isa routines */ 89struct isa_driver rcdriver = { 90 rcprobe, rcattach, "rc" 91}; 92 93static d_open_t rcopen; 94static d_close_t rcclose; 95static d_read_t rcread; 96static d_write_t rcwrite; 97static d_ioctl_t rcioctl; 98static d_stop_t rcstop; 99static d_devtotty_t rcdevtotty; 100 101#define CDEV_MAJOR 63 102static struct cdevsw rc_cdevsw = { 103 rcopen, rcclose, rcread, rcwrite, 104 rcioctl, rcstop, noreset, rcdevtotty, 105 ttpoll, nommap, NULL, "rc", 106 NULL, -1, nodump, nopsize, 107 D_TTY, 108}; 109 110/* Per-board structure */ 111static struct rc_softc { 112 u_int rcb_probed; /* 1 - probed, 2 - attached */ 113 u_int rcb_addr; /* Base I/O addr */ 114 u_int rcb_unit; /* unit # */ 115 u_char rcb_dtr; /* DTR status */ 116 struct rc_chans *rcb_baserc; /* base rc ptr */ 117} rc_softc[NRC]; 118 119/* Per-channel structure */ 120static struct rc_chans { 121 struct rc_softc *rc_rcb; /* back ptr */ 122 u_short rc_flags; /* Misc. flags */ 123 int rc_chan; /* Channel # */ 124 u_char rc_ier; /* intr. enable reg */ 125 u_char rc_msvr; /* modem sig. status */ 126 u_char rc_cor2; /* options reg */ 127 u_char rc_pendcmd; /* special cmd pending */ 128 u_int rc_dtrwait; /* dtr timeout */ 129 u_int rc_dcdwaits; /* how many waits DCD in open */ 130 u_char rc_hotchar; /* end packed optimize */ 131 struct tty *rc_tp; /* tty struct */ 132 u_char *rc_iptr; /* Chars input buffer */ 133 u_char *rc_hiwat; /* hi-water mark */ 134 u_char *rc_bufend; /* end of buffer */ 135 u_char *rc_optr; /* ptr in output buf */ 136 u_char *rc_obufend; /* end of output buf */ 137 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 138 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 139#ifdef DEVFS 140 void *devfs_token; 141#endif 142} rc_chans[NRC * CD180_NCHAN]; 143 144static int rc_scheduled_event = 0; 145 146/* for pstat -t */ 147static struct tty rc_tty[NRC * CD180_NCHAN]; 148static const int nrc_tty = NRC * CD180_NCHAN; 149 150/* Flags */ 151#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 152#define RC_ACTOUT 0x0002 /* Dial-out port active */ 153#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 154#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 155#define RC_DORXFER 0x0010 /* RXFER event planned */ 156#define RC_DOXXFER 0x0020 /* XXFER event planned */ 157#define RC_MODCHG 0x0040 /* Modem status changed */ 158#define RC_OSUSP 0x0080 /* Output suspended */ 159#define RC_OSBUSY 0x0100 /* start() routine in progress */ 160#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 161#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 162#define RC_SEND_RDY 0x0800 /* ready to send */ 163 164/* Table for translation of RCSR status bits to internal form */ 165static int rc_rcsrt[16] = { 166 0, TTY_OE, TTY_FE, 167 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 168 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 169 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 170 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 171 TTY_BI|TTY_PE|TTY_FE|TTY_OE 172}; 173 174/* Static prototypes */ 175static ointhand2_t rcintr; 176static void rc_hwreset __P((int, int, unsigned int)); 177static int rc_test __P((int, int)); 178static void rc_discard_output __P((struct rc_chans *)); 179static void rc_hardclose __P((struct rc_chans *)); 180static int rc_modctl __P((struct rc_chans *, int, int)); 181static void rc_start __P((struct tty *)); 182static int rc_param __P((struct tty *, struct termios *)); 183static swihand_t rcpoll; 184static void rc_reinit __P((struct rc_softc *)); 185#ifdef RCDEBUG 186static void printrcflags(); 187#endif 188static timeout_t rc_dtrwakeup; 189static timeout_t rc_wakeup; 190static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 191static void rc_wait0 __P((int nec, int unit, int chan, int line)); 192 193/**********************************************/ 194 195/* Quick device probing */ 196static int 197rcprobe(dvp) 198 struct isa_device *dvp; 199{ 200 int irq = ffs(dvp->id_irq) - 1; 201 register int nec = dvp->id_iobase; 202 203 if (dvp->id_unit > NRC) 204 return 0; 205 if (!RC_VALIDADDR(nec)) { 206 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec); 207 return 0; 208 } 209 if (!RC_VALIDIRQ(irq)) { 210 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq); 211 return 0; 212 } 213 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 214 rcout(CD180_PPRH, 0x11); 215 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 216 return 0; 217 /* Now, test the board more thoroughly, with diagnostic */ 218 if (rc_test(nec, dvp->id_unit)) 219 return 0; 220 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 221 222 return 0xF; 223} 224 225static int 226rcattach(dvp) 227 struct isa_device *dvp; 228{ 229 register int chan, nec = dvp->id_iobase; 230 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 231 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 232 static int rc_started = 0; 233 struct tty *tp; 234 235 dvp->id_ointr = rcintr; 236 237 /* Thorooughly test the device */ 238 if (rcb->rcb_probed != RC_PROBED) 239 return 0; 240 rcb->rcb_addr = nec; 241 rcb->rcb_dtr = 0; 242 rcb->rcb_baserc = rc; 243 rcb->rcb_unit = dvp->id_unit; 244 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 245 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit, 246 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 247 248 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 249 rc->rc_rcb = rcb; 250 rc->rc_chan = chan; 251 rc->rc_iptr = rc->rc_ibuf; 252 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 253 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 254 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 255 rc->rc_cor2 = rc->rc_pendcmd = 0; 256 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 257 rc->rc_dtrwait = 3 * hz; 258 rc->rc_dcdwaits= 0; 259 rc->rc_hotchar = 0; 260 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)]; 261 ttychars(tp); 262 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 263 tp->t_cflag = TTYDEF_CFLAG; 264 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 265#ifdef DEVFS 266/* FIX THIS to reflect real devices */ 267 rc->devfs_token = 268 devfs_add_devswf(&rc_cdevsw, 269 (dvp->id_unit * CD180_NCHAN) + chan, 270 DV_CHR, 0, 0, 0600, "rc%d.%d", 271 dvp->id_unit, chan); 272#endif 273 } 274 rcb->rcb_probed = RC_ATTACHED; 275 if (!rc_started) { 276 register_swi(SWI_TTY, rcpoll); 277 rc_wakeup((void *)NULL); 278 rc_started = 0; 279 } 280 return 1; 281} 282 283/* RC interrupt handling */ 284static void 285rcintr(unit) 286 int unit; 287{ 288 register struct rc_softc *rcb = &rc_softc[unit]; 289 register struct rc_chans *rc; 290 register int nec, resid; 291 register u_char val, iack, bsr, ucnt, *optr; 292 int good_data, t_state; 293 294 if (rcb->rcb_probed != RC_ATTACHED) { 295 printf("rc%d: bogus interrupt\n", unit); 296 return; 297 } 298 nec = rcb->rcb_addr; 299 300 bsr = ~(rcin(RC_BSR)); 301 302 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 303 printf("rc%d: extra interrupt\n", unit); 304 rcout(CD180_EOIR, 0); 305 return; 306 } 307 308 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 309#ifdef RCDEBUG_DETAILED 310 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 311 (bsr & RC_BSR_TOUT)?"TOUT ":"", 312 (bsr & RC_BSR_RXINT)?"RXINT ":"", 313 (bsr & RC_BSR_TXINT)?"TXINT ":"", 314 (bsr & RC_BSR_MOINT)?"MOINT":""); 315#endif 316 if (bsr & RC_BSR_TOUT) { 317 printf("rc%d: hardware failure, reset board\n", unit); 318 rcout(RC_CTOUT, 0); 319 rc_reinit(rcb); 320 return; 321 } 322 if (bsr & RC_BSR_RXINT) { 323 iack = rcin(RC_PILR_RX); 324 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 325 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 326 printf("rc%d: fake rxint: %02x\n", unit, iack); 327 goto more_intrs; 328 } 329 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 330 t_state = rc->rc_tp->t_state; 331 /* Do RTS flow control stuff */ 332 if ( (rc->rc_flags & RC_RTSFLOW) 333 || !(t_state & TS_ISOPEN) 334 ) { 335 if ( ( !(t_state & TS_ISOPEN) 336 || (t_state & TS_TBLOCK) 337 ) 338 && (rc->rc_msvr & MSVR_RTS) 339 ) 340 rcout(CD180_MSVR, 341 rc->rc_msvr &= ~MSVR_RTS); 342 else if (!(rc->rc_msvr & MSVR_RTS)) 343 rcout(CD180_MSVR, 344 rc->rc_msvr |= MSVR_RTS); 345 } 346 ucnt = rcin(CD180_RDCR) & 0xF; 347 resid = 0; 348 349 if (t_state & TS_ISOPEN) { 350 /* check for input buffer overflow */ 351 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 352 resid = ucnt; 353 ucnt = rc->rc_bufend - rc->rc_iptr; 354 resid -= ucnt; 355 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 356 rc->rc_flags |= RC_WAS_BUFOVFL; 357 rc_scheduled_event++; 358 } 359 } 360 optr = rc->rc_iptr; 361 /* check foor good data */ 362 if (good_data) { 363 while (ucnt-- > 0) { 364 val = rcin(CD180_RDR); 365 optr[0] = val; 366 optr[INPUT_FLAGS_SHIFT] = 0; 367 optr++; 368 rc_scheduled_event++; 369 if (val != 0 && val == rc->rc_hotchar) 370 setsofttty(); 371 } 372 } else { 373 /* Store also status data */ 374 while (ucnt-- > 0) { 375 iack = rcin(CD180_RCSR); 376 if (iack & RCSR_Timeout) 377 break; 378 if ( (iack & RCSR_OE) 379 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 380 rc->rc_flags |= RC_WAS_SILOVFL; 381 rc_scheduled_event++; 382 } 383 val = rcin(CD180_RDR); 384 /* 385 Don't store PE if IGNPAR and BREAK if IGNBRK, 386 this hack allows "raw" tty optimization 387 works even if IGN* is set. 388 */ 389 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 390 || ((!(iack & (RCSR_PE|RCSR_FE)) 391 || !(rc->rc_tp->t_iflag & IGNPAR)) 392 && (!(iack & RCSR_Break) 393 || !(rc->rc_tp->t_iflag & IGNBRK)))) { 394 if ( (iack & (RCSR_PE|RCSR_FE)) 395 && (t_state & TS_CAN_BYPASS_L_RINT) 396 && ((iack & RCSR_FE) 397 || ((iack & RCSR_PE) 398 && (rc->rc_tp->t_iflag & INPCK)))) 399 val = 0; 400 else if (val != 0 && val == rc->rc_hotchar) 401 setsofttty(); 402 optr[0] = val; 403 optr[INPUT_FLAGS_SHIFT] = iack; 404 optr++; 405 rc_scheduled_event++; 406 } 407 } 408 } 409 rc->rc_iptr = optr; 410 rc->rc_flags |= RC_DORXFER; 411 } else 412 resid = ucnt; 413 /* Clear FIFO if necessary */ 414 while (resid-- > 0) { 415 if (!good_data) 416 iack = rcin(CD180_RCSR); 417 else 418 iack = 0; 419 if (iack & RCSR_Timeout) 420 break; 421 (void) rcin(CD180_RDR); 422 } 423 goto more_intrs; 424 } 425 if (bsr & RC_BSR_MOINT) { 426 iack = rcin(RC_PILR_MODEM); 427 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 428 printf("rc%d: fake moint: %02x\n", unit, iack); 429 goto more_intrs; 430 } 431 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 432 iack = rcin(CD180_MCR); 433 rc->rc_msvr = rcin(CD180_MSVR); 434 rcout(CD180_MCR, 0); 435#ifdef RCDEBUG 436 printrcflags(rc, "moint"); 437#endif 438 if (rc->rc_flags & RC_CTSFLOW) { 439 if (rc->rc_msvr & MSVR_CTS) 440 rc->rc_flags |= RC_SEND_RDY; 441 else 442 rc->rc_flags &= ~RC_SEND_RDY; 443 } else 444 rc->rc_flags |= RC_SEND_RDY; 445 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 446 rc_scheduled_event += LOTS_OF_EVENTS; 447 rc->rc_flags |= RC_MODCHG; 448 setsofttty(); 449 } 450 goto more_intrs; 451 } 452 if (bsr & RC_BSR_TXINT) { 453 iack = rcin(RC_PILR_TX); 454 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 455 printf("rc%d: fake txint: %02x\n", unit, iack); 456 goto more_intrs; 457 } 458 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 459 if ( (rc->rc_flags & RC_OSUSP) 460 || !(rc->rc_flags & RC_SEND_RDY) 461 ) 462 goto more_intrs; 463 /* Handle breaks and other stuff */ 464 if (rc->rc_pendcmd) { 465 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 466 rcout(CD180_TDR, CD180_C_ESC); 467 rcout(CD180_TDR, rc->rc_pendcmd); 468 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 469 rc->rc_pendcmd = 0; 470 goto more_intrs; 471 } 472 optr = rc->rc_optr; 473 resid = rc->rc_obufend - optr; 474 if (resid > CD180_NFIFO) 475 resid = CD180_NFIFO; 476 while (resid-- > 0) 477 rcout(CD180_TDR, *optr++); 478 rc->rc_optr = optr; 479 480 /* output completed? */ 481 if (optr >= rc->rc_obufend) { 482 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 483#ifdef RCDEBUG 484 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 485#endif 486 if (!(rc->rc_flags & RC_DOXXFER)) { 487 rc_scheduled_event += LOTS_OF_EVENTS; 488 rc->rc_flags |= RC_DOXXFER; 489 setsofttty(); 490 } 491 } 492 } 493 more_intrs: 494 rcout(CD180_EOIR, 0); /* end of interrupt */ 495 rcout(RC_CTOUT, 0); 496 bsr = ~(rcin(RC_BSR)); 497 } 498} 499 500/* Feed characters to output buffer */ 501static void rc_start(tp) 502register struct tty *tp; 503{ 504 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 505 register int nec = rc->rc_rcb->rcb_addr, s; 506 507 if (rc->rc_flags & RC_OSBUSY) 508 return; 509 s = spltty(); 510 rc->rc_flags |= RC_OSBUSY; 511 disable_intr(); 512 if (tp->t_state & TS_TTSTOP) 513 rc->rc_flags |= RC_OSUSP; 514 else 515 rc->rc_flags &= ~RC_OSUSP; 516 /* Do RTS flow control stuff */ 517 if ( (rc->rc_flags & RC_RTSFLOW) 518 && (tp->t_state & TS_TBLOCK) 519 && (rc->rc_msvr & MSVR_RTS) 520 ) { 521 rcout(CD180_CAR, rc->rc_chan); 522 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 523 } else if (!(rc->rc_msvr & MSVR_RTS)) { 524 rcout(CD180_CAR, rc->rc_chan); 525 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 526 } 527 enable_intr(); 528 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 529 goto out; 530#ifdef RCDEBUG 531 printrcflags(rc, "rcstart"); 532#endif 533 ttwwakeup(tp); 534#ifdef RCDEBUG 535 printf("rcstart: outq = %d obuf = %d\n", 536 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 537#endif 538 if (tp->t_state & TS_BUSY) 539 goto out; /* output still in progress ... */ 540 541 if (tp->t_outq.c_cc > 0) { 542 u_int ocnt; 543 544 tp->t_state |= TS_BUSY; 545 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 546 disable_intr(); 547 rc->rc_optr = rc->rc_obuf; 548 rc->rc_obufend = rc->rc_optr + ocnt; 549 enable_intr(); 550 if (!(rc->rc_ier & IER_TxRdy)) { 551#ifdef RCDEBUG 552 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 553#endif 554 rcout(CD180_CAR, rc->rc_chan); 555 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 556 } 557 } 558out: 559 rc->rc_flags &= ~RC_OSBUSY; 560 (void) splx(s); 561} 562 563/* Handle delayed events. */ 564void rcpoll() 565{ 566 register struct rc_chans *rc; 567 register struct rc_softc *rcb; 568 register u_char *tptr, *eptr; 569 register struct tty *tp; 570 register int chan, icnt, nec, unit; 571 572 if (rc_scheduled_event == 0) 573 return; 574repeat: 575 for (unit = 0; unit < NRC; unit++) { 576 rcb = &rc_softc[unit]; 577 rc = rcb->rcb_baserc; 578 nec = rc->rc_rcb->rcb_addr; 579 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 580 tp = rc->rc_tp; 581#ifdef RCDEBUG 582 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 583 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 584 printrcflags(rc, "rcevent"); 585#endif 586 if (rc->rc_flags & RC_WAS_BUFOVFL) { 587 disable_intr(); 588 rc->rc_flags &= ~RC_WAS_BUFOVFL; 589 rc_scheduled_event--; 590 enable_intr(); 591 printf("rc%d/%d: interrupt-level buffer overflow\n", 592 unit, chan); 593 } 594 if (rc->rc_flags & RC_WAS_SILOVFL) { 595 disable_intr(); 596 rc->rc_flags &= ~RC_WAS_SILOVFL; 597 rc_scheduled_event--; 598 enable_intr(); 599 printf("rc%d/%d: silo overflow\n", 600 unit, chan); 601 } 602 if (rc->rc_flags & RC_MODCHG) { 603 disable_intr(); 604 rc->rc_flags &= ~RC_MODCHG; 605 rc_scheduled_event -= LOTS_OF_EVENTS; 606 enable_intr(); 607 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 608 } 609 if (rc->rc_flags & RC_DORXFER) { 610 disable_intr(); 611 rc->rc_flags &= ~RC_DORXFER; 612 eptr = rc->rc_iptr; 613 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 614 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 615 else 616 tptr = rc->rc_ibuf; 617 icnt = eptr - tptr; 618 if (icnt > 0) { 619 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 620 rc->rc_iptr = rc->rc_ibuf; 621 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 622 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 623 } else { 624 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 625 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 626 rc->rc_hiwat = 627 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 628 } 629 if ( (rc->rc_flags & RC_RTSFLOW) 630 && (tp->t_state & TS_ISOPEN) 631 && !(tp->t_state & TS_TBLOCK) 632 && !(rc->rc_msvr & MSVR_RTS) 633 ) { 634 rcout(CD180_CAR, chan); 635 rcout(CD180_MSVR, 636 rc->rc_msvr |= MSVR_RTS); 637 } 638 rc_scheduled_event -= icnt; 639 } 640 enable_intr(); 641 642 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 643 goto done1; 644 645 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 646 && !(tp->t_state & TS_LOCAL)) { 647 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 648 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 649 && !(tp->t_state & TS_TBLOCK)) 650 ttyblock(tp); 651 tk_nin += icnt; 652 tk_rawcc += icnt; 653 tp->t_rawcc += icnt; 654 if (b_to_q(tptr, icnt, &tp->t_rawq)) 655 printf("rc%d/%d: tty-level buffer overflow\n", 656 unit, chan); 657 ttwakeup(tp); 658 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 659 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 660 tp->t_state &= ~TS_TTSTOP; 661 tp->t_lflag &= ~FLUSHO; 662 rc_start(tp); 663 } 664 } else { 665 for (; tptr < eptr; tptr++) 666 (*linesw[tp->t_line].l_rint) 667 (tptr[0] | 668 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 669 } 670done1: ; 671 } 672 if (rc->rc_flags & RC_DOXXFER) { 673 disable_intr(); 674 rc_scheduled_event -= LOTS_OF_EVENTS; 675 rc->rc_flags &= ~RC_DOXXFER; 676 rc->rc_tp->t_state &= ~TS_BUSY; 677 enable_intr(); 678 (*linesw[tp->t_line].l_start)(tp); 679 } 680 } 681 if (rc_scheduled_event == 0) 682 break; 683 } 684 if (rc_scheduled_event >= LOTS_OF_EVENTS) 685 goto repeat; 686} 687 688static void 689rcstop(tp, rw) 690 register struct tty *tp; 691 int rw; 692{ 693 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 694 u_char *tptr, *eptr; 695 696#ifdef RCDEBUG 697 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 698 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 699#endif 700 if (rw & FWRITE) 701 rc_discard_output(rc); 702 disable_intr(); 703 if (rw & FREAD) { 704 rc->rc_flags &= ~RC_DORXFER; 705 eptr = rc->rc_iptr; 706 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 707 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 708 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 709 } else { 710 tptr = rc->rc_ibuf; 711 rc->rc_iptr = rc->rc_ibuf; 712 } 713 rc_scheduled_event -= eptr - tptr; 714 } 715 if (tp->t_state & TS_TTSTOP) 716 rc->rc_flags |= RC_OSUSP; 717 else 718 rc->rc_flags &= ~RC_OSUSP; 719 enable_intr(); 720} 721 722static int 723rcopen(dev, flag, mode, p) 724 dev_t dev; 725 int flag, mode; 726 struct proc *p; 727{ 728 register struct rc_chans *rc; 729 register struct tty *tp; 730 int unit, nec, s, error = 0; 731 732 unit = GET_UNIT(dev); 733 if (unit >= NRC * CD180_NCHAN) 734 return ENXIO; 735 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 736 return ENXIO; 737 rc = &rc_chans[unit]; 738 tp = rc->rc_tp; 739 nec = rc->rc_rcb->rcb_addr; 740#ifdef RCDEBUG 741 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 742#endif 743 s = spltty(); 744 745again: 746 while (rc->rc_flags & RC_DTR_OFF) { 747 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 748 if (error != 0) 749 goto out; 750 } 751 if (tp->t_state & TS_ISOPEN) { 752 if (CALLOUT(dev)) { 753 if (!(rc->rc_flags & RC_ACTOUT)) { 754 error = EBUSY; 755 goto out; 756 } 757 } else { 758 if (rc->rc_flags & RC_ACTOUT) { 759 if (flag & O_NONBLOCK) { 760 error = EBUSY; 761 goto out; 762 } 763 error = tsleep(&rc->rc_rcb, 764 TTIPRI|PCATCH, "rcbi", 0); 765 if (error) 766 goto out; 767 goto again; 768 } 769 } 770 if (tp->t_state & TS_XCLUDE && 771 suser(p)) { 772 error = EBUSY; 773 goto out; 774 } 775 } else { 776 tp->t_oproc = rc_start; 777 tp->t_param = rc_param; 778 tp->t_dev = dev; 779 780 if (CALLOUT(dev)) 781 tp->t_cflag |= CLOCAL; 782 else 783 tp->t_cflag &= ~CLOCAL; 784 785 error = rc_param(tp, &tp->t_termios); 786 if (error) 787 goto out; 788 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 789 790 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 791 (*linesw[tp->t_line].l_modem)(tp, 1); 792 } 793 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 794 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 795 rc->rc_dcdwaits++; 796 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 797 rc->rc_dcdwaits--; 798 if (error != 0) 799 goto out; 800 goto again; 801 } 802 error = (*linesw[tp->t_line].l_open)(dev, tp); 803 disc_optim(tp, &tp->t_termios, rc); 804 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 805 rc->rc_flags |= RC_ACTOUT; 806out: 807 (void) splx(s); 808 809 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 810 rc_hardclose(rc); 811 812 return error; 813} 814 815static int 816rcclose(dev, flag, mode, p) 817 dev_t dev; 818 int flag, mode; 819 struct proc *p; 820{ 821 register struct rc_chans *rc; 822 register struct tty *tp; 823 int s, unit = GET_UNIT(dev); 824 825 if (unit >= NRC * CD180_NCHAN) 826 return ENXIO; 827 rc = &rc_chans[unit]; 828 tp = rc->rc_tp; 829#ifdef RCDEBUG 830 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 831#endif 832 s = spltty(); 833 (*linesw[tp->t_line].l_close)(tp, flag); 834 disc_optim(tp, &tp->t_termios, rc); 835 rcstop(tp, FREAD | FWRITE); 836 rc_hardclose(rc); 837 ttyclose(tp); 838 splx(s); 839 return 0; 840} 841 842static void rc_hardclose(rc) 843register struct rc_chans *rc; 844{ 845 register int s, nec = rc->rc_rcb->rcb_addr; 846 register struct tty *tp = rc->rc_tp; 847 848 s = spltty(); 849 rcout(CD180_CAR, rc->rc_chan); 850 851 /* Disable rx/tx intrs */ 852 rcout(CD180_IER, rc->rc_ier = 0); 853 if ( (tp->t_cflag & HUPCL) 854 || (!(rc->rc_flags & RC_ACTOUT) 855 && !(rc->rc_msvr & MSVR_CD) 856 && !(tp->t_cflag & CLOCAL)) 857 || !(tp->t_state & TS_ISOPEN) 858 ) { 859 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 860 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 861 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 862 if (rc->rc_dtrwait) { 863 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 864 rc->rc_flags |= RC_DTR_OFF; 865 } 866 } 867 rc->rc_flags &= ~RC_ACTOUT; 868 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 869 wakeup(TSA_CARR_ON(tp)); 870 (void) splx(s); 871} 872 873/* Read from line */ 874static int 875rcread(dev, uio, flag) 876 dev_t dev; 877 struct uio *uio; 878 int flag; 879{ 880 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 881 882 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 883} 884 885/* Write to line */ 886static int 887rcwrite(dev, uio, flag) 888 dev_t dev; 889 struct uio *uio; 890 int flag; 891{ 892 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 893 894 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 895} 896 897/* Reset the bastard */ 898static void rc_hwreset(unit, nec, chipid) 899 register int unit, nec; 900 unsigned int chipid; 901{ 902 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 903 DELAY(20000); 904 WAITFORCCR(unit, -1); 905 906 rcout(RC_CTOUT, 0); /* Clear timeout */ 907 rcout(CD180_GIVR, chipid); 908 rcout(CD180_GICR, 0); 909 910 /* Set Prescaler Registers (1 msec) */ 911 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 912 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 913 914 /* Initialize Priority Interrupt Level Registers */ 915 rcout(CD180_PILR1, RC_PILR_MODEM); 916 rcout(CD180_PILR2, RC_PILR_TX); 917 rcout(CD180_PILR3, RC_PILR_RX); 918 919 /* Reset DTR */ 920 rcout(RC_DTREG, ~0); 921} 922 923/* Set channel parameters */ 924static int rc_param(tp, ts) 925 register struct tty *tp; 926 struct termios *ts; 927{ 928 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 929 register int nec = rc->rc_rcb->rcb_addr; 930 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 931 932 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 933 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 934 ) 935 return (EINVAL); 936 if (ts->c_ispeed == 0) 937 ts->c_ispeed = ts->c_ospeed; 938 odivs = RC_BRD(ts->c_ospeed); 939 idivs = RC_BRD(ts->c_ispeed); 940 941 s = spltty(); 942 943 /* Select channel */ 944 rcout(CD180_CAR, rc->rc_chan); 945 946 /* If speed == 0, hangup line */ 947 if (ts->c_ospeed == 0) { 948 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 949 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 950 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 951 } 952 953 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 954 cflag = ts->c_cflag; 955 iflag = ts->c_iflag; 956 lflag = ts->c_lflag; 957 958 if (idivs > 0) { 959 rcout(CD180_RBPRL, idivs & 0xFF); 960 rcout(CD180_RBPRH, idivs >> 8); 961 } 962 if (odivs > 0) { 963 rcout(CD180_TBPRL, odivs & 0xFF); 964 rcout(CD180_TBPRH, odivs >> 8); 965 } 966 967 /* set timeout value */ 968 if (ts->c_ispeed > 0) { 969 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 970 971 if ( !(lflag & ICANON) 972 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 973 && ts->c_cc[VTIME] * 10 > itm) 974 itm = ts->c_cc[VTIME] * 10; 975 976 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 977 } 978 979 switch (cflag & CSIZE) { 980 case CS5: val = COR1_5BITS; break; 981 case CS6: val = COR1_6BITS; break; 982 case CS7: val = COR1_7BITS; break; 983 default: 984 case CS8: val = COR1_8BITS; break; 985 } 986 if (cflag & PARENB) { 987 val |= COR1_NORMPAR; 988 if (cflag & PARODD) 989 val |= COR1_ODDP; 990 if (!(cflag & INPCK)) 991 val |= COR1_Ignore; 992 } else 993 val |= COR1_Ignore; 994 if (cflag & CSTOPB) 995 val |= COR1_2SB; 996 rcout(CD180_COR1, val); 997 998 /* Set FIFO threshold */ 999 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1000 inpflow = 0; 1001 if ( (iflag & IXOFF) 1002 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1003 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1004 || (iflag & IXANY) 1005 ) 1006 ) 1007 ) { 1008 inpflow = 1; 1009 val |= COR3_SCDE|COR3_FCT; 1010 } 1011 rcout(CD180_COR3, val); 1012 1013 /* Initialize on-chip automatic flow control */ 1014 val = 0; 1015 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1016 if (cflag & CCTS_OFLOW) { 1017 rc->rc_flags |= RC_CTSFLOW; 1018 val |= COR2_CtsAE; 1019 } else 1020 rc->rc_flags |= RC_SEND_RDY; 1021 if (tp->t_state & TS_TTSTOP) 1022 rc->rc_flags |= RC_OSUSP; 1023 else 1024 rc->rc_flags &= ~RC_OSUSP; 1025 if (cflag & CRTS_IFLOW) 1026 rc->rc_flags |= RC_RTSFLOW; 1027 else 1028 rc->rc_flags &= ~RC_RTSFLOW; 1029 1030 if (inpflow) { 1031 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1032 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1033 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1034 val |= COR2_TxIBE; 1035 if (iflag & IXANY) 1036 val |= COR2_IXM; 1037 } 1038 1039 rcout(CD180_COR2, rc->rc_cor2 = val); 1040 1041 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1042 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1043 1044 disc_optim(tp, ts, rc); 1045 1046 /* modem ctl */ 1047 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1048 if (cflag & CCTS_OFLOW) 1049 val |= MCOR1_CTSzd; 1050 rcout(CD180_MCOR1, val); 1051 1052 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1053 if (cflag & CCTS_OFLOW) 1054 val |= MCOR2_CTSod; 1055 rcout(CD180_MCOR2, val); 1056 1057 /* enable i/o and interrupts */ 1058 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1059 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1060 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1061 1062 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1063 if (cflag & CCTS_OFLOW) 1064 rc->rc_ier |= IER_CTS; 1065 if (cflag & CREAD) 1066 rc->rc_ier |= IER_RxData; 1067 if (tp->t_state & TS_BUSY) 1068 rc->rc_ier |= IER_TxRdy; 1069 if (ts->c_ospeed != 0) 1070 rc_modctl(rc, TIOCM_DTR, DMBIS); 1071 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1072 rc->rc_flags |= RC_SEND_RDY; 1073 rcout(CD180_IER, rc->rc_ier); 1074 (void) splx(s); 1075 return 0; 1076} 1077 1078/* Re-initialize board after bogus interrupts */ 1079static void rc_reinit(rcb) 1080struct rc_softc *rcb; 1081{ 1082 register struct rc_chans *rc, *rce; 1083 register int nec; 1084 1085 nec = rcb->rcb_addr; 1086 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1087 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1088 rce = rc + CD180_NCHAN; 1089 for (; rc < rce; rc++) 1090 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1091} 1092 1093static int 1094rcioctl(dev, cmd, data, flag, p) 1095dev_t dev; 1096u_long cmd; 1097int flag; 1098caddr_t data; 1099struct proc *p; 1100{ 1101 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1102 register int s, error; 1103 struct tty *tp = rc->rc_tp; 1104 1105 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1106 if (error != ENOIOCTL) 1107 return (error); 1108 error = ttioctl(tp, cmd, data, flag); 1109 disc_optim(tp, &tp->t_termios, rc); 1110 if (error != ENOIOCTL) 1111 return (error); 1112 s = spltty(); 1113 1114 switch (cmd) { 1115 case TIOCSBRK: 1116 rc->rc_pendcmd = CD180_C_SBRK; 1117 break; 1118 1119 case TIOCCBRK: 1120 rc->rc_pendcmd = CD180_C_EBRK; 1121 break; 1122 1123 case TIOCSDTR: 1124 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1125 break; 1126 1127 case TIOCCDTR: 1128 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1129 break; 1130 1131 case TIOCMGET: 1132 *(int *) data = rc_modctl(rc, 0, DMGET); 1133 break; 1134 1135 case TIOCMSET: 1136 (void) rc_modctl(rc, *(int *) data, DMSET); 1137 break; 1138 1139 case TIOCMBIC: 1140 (void) rc_modctl(rc, *(int *) data, DMBIC); 1141 break; 1142 1143 case TIOCMBIS: 1144 (void) rc_modctl(rc, *(int *) data, DMBIS); 1145 break; 1146 1147 case TIOCMSDTRWAIT: 1148 error = suser(p); 1149 if (error != 0) { 1150 splx(s); 1151 return (error); 1152 } 1153 rc->rc_dtrwait = *(int *)data * hz / 100; 1154 break; 1155 1156 case TIOCMGDTRWAIT: 1157 *(int *)data = rc->rc_dtrwait * 100 / hz; 1158 break; 1159 1160 default: 1161 (void) splx(s); 1162 return ENOTTY; 1163 } 1164 (void) splx(s); 1165 return 0; 1166} 1167 1168 1169/* Modem control routines */ 1170 1171static int rc_modctl(rc, bits, cmd) 1172register struct rc_chans *rc; 1173int bits, cmd; 1174{ 1175 register int nec = rc->rc_rcb->rcb_addr; 1176 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1177 1178 rcout(CD180_CAR, rc->rc_chan); 1179 1180 switch (cmd) { 1181 case DMSET: 1182 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1183 ~(*dtr |= 1 << rc->rc_chan) : 1184 ~(*dtr &= ~(1 << rc->rc_chan))); 1185 msvr = rcin(CD180_MSVR); 1186 if (bits & TIOCM_RTS) 1187 msvr |= MSVR_RTS; 1188 else 1189 msvr &= ~MSVR_RTS; 1190 if (bits & TIOCM_DTR) 1191 msvr |= MSVR_DTR; 1192 else 1193 msvr &= ~MSVR_DTR; 1194 rcout(CD180_MSVR, msvr); 1195 break; 1196 1197 case DMBIS: 1198 if (bits & TIOCM_DTR) 1199 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1200 msvr = rcin(CD180_MSVR); 1201 if (bits & TIOCM_RTS) 1202 msvr |= MSVR_RTS; 1203 if (bits & TIOCM_DTR) 1204 msvr |= MSVR_DTR; 1205 rcout(CD180_MSVR, msvr); 1206 break; 1207 1208 case DMGET: 1209 bits = TIOCM_LE; 1210 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1211 1212 if (msvr & MSVR_RTS) 1213 bits |= TIOCM_RTS; 1214 if (msvr & MSVR_CTS) 1215 bits |= TIOCM_CTS; 1216 if (msvr & MSVR_DSR) 1217 bits |= TIOCM_DSR; 1218 if (msvr & MSVR_DTR) 1219 bits |= TIOCM_DTR; 1220 if (msvr & MSVR_CD) 1221 bits |= TIOCM_CD; 1222 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1223 bits |= TIOCM_RI; 1224 return bits; 1225 1226 case DMBIC: 1227 if (bits & TIOCM_DTR) 1228 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1229 msvr = rcin(CD180_MSVR); 1230 if (bits & TIOCM_RTS) 1231 msvr &= ~MSVR_RTS; 1232 if (bits & TIOCM_DTR) 1233 msvr &= ~MSVR_DTR; 1234 rcout(CD180_MSVR, msvr); 1235 break; 1236 } 1237 rc->rc_msvr = rcin(CD180_MSVR); 1238 return 0; 1239} 1240 1241/* Test the board. */ 1242int rc_test(nec, unit) 1243 register int nec; 1244 int unit; 1245{ 1246 int chan = 0; 1247 int i = 0, rcnt, old_level; 1248 unsigned int iack, chipid; 1249 unsigned short divs; 1250 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1251#define CTLEN 8 1252#define ERR(s) { \ 1253 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1254 (void) splx(old_level); return 1; } 1255 1256 struct rtest { 1257 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1258 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1259 int rxptr; /* RX pointer */ 1260 int txptr; /* TX pointer */ 1261 } tchans[CD180_NCHAN]; 1262 1263 old_level = spltty(); 1264 1265 chipid = RC_FAKEID; 1266 1267 /* First, reset board to inital state */ 1268 rc_hwreset(unit, nec, chipid); 1269 1270 divs = RC_BRD(19200); 1271 1272 /* Initialize channels */ 1273 for (chan = 0; chan < CD180_NCHAN; chan++) { 1274 1275 /* Select and reset channel */ 1276 rcout(CD180_CAR, chan); 1277 CCRCMD(unit, chan, CCR_ResetChan); 1278 WAITFORCCR(unit, chan); 1279 1280 /* Set speed */ 1281 rcout(CD180_RBPRL, divs & 0xFF); 1282 rcout(CD180_RBPRH, divs >> 8); 1283 rcout(CD180_TBPRL, divs & 0xFF); 1284 rcout(CD180_TBPRH, divs >> 8); 1285 1286 /* set timeout value */ 1287 rcout(CD180_RTPR, 0); 1288 1289 /* Establish local loopback */ 1290 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1291 rcout(CD180_COR2, COR2_LLM); 1292 rcout(CD180_COR3, CD180_NFIFO); 1293 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1294 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1295 WAITFORCCR(unit, chan); 1296 rcout(CD180_MSVR, MSVR_RTS); 1297 1298 /* Fill TXBUF with test data */ 1299 for (i = 0; i < CD180_NFIFO; i++) { 1300 tchans[chan].txbuf[i] = ctest[i]; 1301 tchans[chan].rxbuf[i] = 0; 1302 } 1303 tchans[chan].txptr = tchans[chan].rxptr = 0; 1304 1305 /* Now, start transmit */ 1306 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1307 } 1308 /* Pseudo-interrupt poll stuff */ 1309 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1310 i = ~(rcin(RC_BSR)); 1311 if (i & RC_BSR_TOUT) 1312 ERR(("BSR timeout bit set\n")) 1313 else if (i & RC_BSR_TXINT) { 1314 iack = rcin(RC_PILR_TX); 1315 if (iack != (GIVR_IT_TDI | chipid)) 1316 ERR(("Bad TX intr ack (%02x != %02x)\n", 1317 iack, GIVR_IT_TDI | chipid)); 1318 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1319 /* If no more data to transmit, disable TX intr */ 1320 if (tchans[chan].txptr >= CD180_NFIFO) { 1321 iack = rcin(CD180_IER); 1322 rcout(CD180_IER, iack & ~IER_TxMpty); 1323 } else { 1324 for (iack = tchans[chan].txptr; 1325 iack < CD180_NFIFO; iack++) 1326 rcout(CD180_TDR, 1327 tchans[chan].txbuf[iack]); 1328 tchans[chan].txptr = iack; 1329 } 1330 rcout(CD180_EOIR, 0); 1331 } else if (i & RC_BSR_RXINT) { 1332 u_char ucnt; 1333 1334 iack = rcin(RC_PILR_RX); 1335 if (iack != (GIVR_IT_RGDI | chipid) && 1336 iack != (GIVR_IT_REI | chipid)) 1337 ERR(("Bad RX intr ack (%02x != %02x)\n", 1338 iack, GIVR_IT_RGDI | chipid)) 1339 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1340 ucnt = rcin(CD180_RDCR) & 0xF; 1341 while (ucnt-- > 0) { 1342 iack = rcin(CD180_RCSR); 1343 if (iack & RCSR_Timeout) 1344 break; 1345 if (iack & 0xF) 1346 ERR(("Bad char chan %d (RCSR = %02X)\n", 1347 chan, iack)) 1348 if (tchans[chan].rxptr > CD180_NFIFO) 1349 ERR(("Got extra chars chan %d\n", 1350 chan)) 1351 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1352 rcin(CD180_RDR); 1353 } 1354 rcout(CD180_EOIR, 0); 1355 } 1356 rcout(RC_CTOUT, 0); 1357 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1358 if (tchans[chan].rxptr >= CD180_NFIFO) 1359 iack++; 1360 if (iack == CD180_NCHAN) 1361 break; 1362 } 1363 for (chan = 0; chan < CD180_NCHAN; chan++) { 1364 /* Select and reset channel */ 1365 rcout(CD180_CAR, chan); 1366 CCRCMD(unit, chan, CCR_ResetChan); 1367 } 1368 1369 if (!rcnt) 1370 ERR(("looses characters during local loopback\n")) 1371 /* Now, check data */ 1372 for (chan = 0; chan < CD180_NCHAN; chan++) 1373 for (i = 0; i < CD180_NFIFO; i++) 1374 if (ctest[i] != tchans[chan].rxbuf[i]) 1375 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1376 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1377 (void) splx(old_level); 1378 return 0; 1379} 1380 1381#ifdef RCDEBUG 1382static void printrcflags(rc, comment) 1383struct rc_chans *rc; 1384char *comment; 1385{ 1386 u_short f = rc->rc_flags; 1387 register int nec = rc->rc_rcb->rcb_addr; 1388 1389 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1390 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1391 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1392 (f & RC_ACTOUT) ?"ACTOUT " :"", 1393 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1394 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1395 (f & RC_DORXFER)?"DORXFER " :"", 1396 (f & RC_DOXXFER)?"DOXXFER " :"", 1397 (f & RC_MODCHG) ?"MODCHG " :"", 1398 (f & RC_OSUSP) ?"OSUSP " :"", 1399 (f & RC_OSBUSY) ?"OSBUSY " :"", 1400 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1401 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1402 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1403 1404 rcout(CD180_CAR, rc->rc_chan); 1405 1406 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1407 rc->rc_rcb->rcb_unit, rc->rc_chan, 1408 rcin(CD180_MSVR), 1409 rcin(CD180_IER), 1410 rcin(CD180_CCSR)); 1411} 1412#endif /* RCDEBUG */ 1413 1414static struct tty * 1415rcdevtotty(dev) 1416 dev_t dev; 1417{ 1418 int unit; 1419 1420 unit = GET_UNIT(dev); 1421 if (unit >= NRC * CD180_NCHAN) 1422 return NULL; 1423 return (&rc_tty[unit]); 1424} 1425 1426static void 1427rc_dtrwakeup(chan) 1428 void *chan; 1429{ 1430 struct rc_chans *rc; 1431 1432 rc = (struct rc_chans *)chan; 1433 rc->rc_flags &= ~RC_DTR_OFF; 1434 wakeup(&rc->rc_dtrwait); 1435} 1436 1437static void 1438rc_discard_output(rc) 1439 struct rc_chans *rc; 1440{ 1441 disable_intr(); 1442 if (rc->rc_flags & RC_DOXXFER) { 1443 rc_scheduled_event -= LOTS_OF_EVENTS; 1444 rc->rc_flags &= ~RC_DOXXFER; 1445 } 1446 rc->rc_optr = rc->rc_obufend; 1447 rc->rc_tp->t_state &= ~TS_BUSY; 1448 enable_intr(); 1449 ttwwakeup(rc->rc_tp); 1450} 1451 1452static void 1453rc_wakeup(chan) 1454 void *chan; 1455{ 1456 timeout(rc_wakeup, (caddr_t)NULL, 1); 1457 1458 if (rc_scheduled_event != 0) { 1459 int s; 1460 1461 s = splsofttty(); 1462 rcpoll(); 1463 splx(s); 1464 } 1465} 1466 1467static void 1468disc_optim(tp, t, rc) 1469 struct tty *tp; 1470 struct termios *t; 1471 struct rc_chans *rc; 1472{ 1473 1474 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1475 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1476 && (!(t->c_iflag & PARMRK) 1477 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1478 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1479 && linesw[tp->t_line].l_rint == ttyinput) 1480 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1481 else 1482 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1483 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1484} 1485 1486static void 1487rc_wait0(nec, unit, chan, line) 1488 int nec, unit, chan, line; 1489{ 1490 int rcnt; 1491 1492 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1493 DELAY(30); 1494 if (rcnt == 0) 1495 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1496 unit, chan, line); 1497} 1498 1499static int rc_devsw_installed; 1500 1501static void rc_drvinit(void *unused) 1502{ 1503 dev_t dev; 1504 1505 if( ! rc_devsw_installed ) { 1506 dev = makedev(CDEV_MAJOR, 0); 1507 cdevsw_add(&dev,&rc_cdevsw, NULL); 1508 rc_devsw_installed = 1; 1509 } 1510} 1511 1512SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1513 1514 1515#endif /* NRC */ 1516