rc.c revision 33322
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34 35#if NRC > 0 36 37#include "opt_devfs.h" 38 39/*#define RCDEBUG*/ 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/tty.h> 44#include <sys/proc.h> 45#include <sys/conf.h> 46#include <sys/dkstat.h> 47#include <sys/fcntl.h> 48#include <sys/kernel.h> 49#ifdef DEVFS 50#include <sys/devfsext.h> 51#endif /*DEVFS*/ 52 53#include <machine/clock.h> 54 55#include <i386/isa/isa_device.h> 56 57#include <i386/isa/ic/cd180.h> 58#include <i386/isa/rcreg.h> 59 60 61/* Prototypes */ 62static int rcprobe __P((struct isa_device *)); 63static int rcattach __P((struct isa_device *)); 64 65/*- 66 * This space intentionally left blank to stop __LINE__ from screwing up 67 * regression tests :-(. 68 * 69 * 70 * 71 */ 72void rcpoll __P((void)); 73 74#define rcin(port) RC_IN (nec, port) 75#define rcout(port,v) RC_OUT (nec, port, v) 76 77#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 78#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 79 80#define RC_IBUFSIZE 256 81#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 82#define RC_OBUFSIZE 512 83#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 84#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 85#define LOTS_OF_EVENTS 64 86 87#define RC_FAKEID 0x10 88 89#define RC_PROBED 1 90#define RC_ATTACHED 2 91 92#define GET_UNIT(dev) (minor(dev) & 0x3F) 93#define CALLOUT(dev) (minor(dev) & 0x80) 94 95/* For isa routines */ 96struct isa_driver rcdriver = { 97 rcprobe, rcattach, "rc" 98}; 99 100static d_open_t rcopen; 101static d_close_t rcclose; 102static d_read_t rcread; 103static d_write_t rcwrite; 104static d_ioctl_t rcioctl; 105static d_stop_t rcstop; 106static d_devtotty_t rcdevtotty; 107 108#define CDEV_MAJOR 63 109static struct cdevsw rc_cdevsw = 110 { rcopen, rcclose, rcread, rcwrite, /*63*/ 111 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 112 ttpoll, nommap, NULL, "rc", NULL, -1 }; 113 114/* Per-board structure */ 115static struct rc_softc { 116 u_int rcb_probed; /* 1 - probed, 2 - attached */ 117 u_int rcb_addr; /* Base I/O addr */ 118 u_int rcb_unit; /* unit # */ 119 u_char rcb_dtr; /* DTR status */ 120 struct rc_chans *rcb_baserc; /* base rc ptr */ 121} rc_softc[NRC]; 122 123/* Per-channel structure */ 124static struct rc_chans { 125 struct rc_softc *rc_rcb; /* back ptr */ 126 u_short rc_flags; /* Misc. flags */ 127 int rc_chan; /* Channel # */ 128 u_char rc_ier; /* intr. enable reg */ 129 u_char rc_msvr; /* modem sig. status */ 130 u_char rc_cor2; /* options reg */ 131 u_char rc_pendcmd; /* special cmd pending */ 132 u_int rc_dtrwait; /* dtr timeout */ 133 u_int rc_dcdwaits; /* how many waits DCD in open */ 134 u_char rc_hotchar; /* end packed optimize */ 135 struct tty *rc_tp; /* tty struct */ 136 u_char *rc_iptr; /* Chars input buffer */ 137 u_char *rc_hiwat; /* hi-water mark */ 138 u_char *rc_bufend; /* end of buffer */ 139 u_char *rc_optr; /* ptr in output buf */ 140 u_char *rc_obufend; /* end of output buf */ 141 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 142 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 143#ifdef DEVFS 144 void *devfs_token; 145#endif 146} rc_chans[NRC * CD180_NCHAN]; 147 148static int rc_scheduled_event = 0; 149 150/* for pstat -t */ 151static struct tty rc_tty[NRC * CD180_NCHAN]; 152static const int nrc_tty = NRC * CD180_NCHAN; 153 154/* Flags */ 155#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 156#define RC_ACTOUT 0x0002 /* Dial-out port active */ 157#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 158#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 159#define RC_DORXFER 0x0010 /* RXFER event planned */ 160#define RC_DOXXFER 0x0020 /* XXFER event planned */ 161#define RC_MODCHG 0x0040 /* Modem status changed */ 162#define RC_OSUSP 0x0080 /* Output suspended */ 163#define RC_OSBUSY 0x0100 /* start() routine in progress */ 164#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 165#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 166#define RC_SEND_RDY 0x0800 /* ready to send */ 167 168/* Table for translation of RCSR status bits to internal form */ 169static int rc_rcsrt[16] = { 170 0, TTY_OE, TTY_FE, 171 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 172 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 173 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 174 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 175 TTY_BI|TTY_PE|TTY_FE|TTY_OE 176}; 177 178/* Static prototypes */ 179static void rc_hwreset __P((int, int, unsigned int)); 180static int rc_test __P((int, int)); 181static void rc_discard_output __P((struct rc_chans *)); 182static void rc_hardclose __P((struct rc_chans *)); 183static int rc_modctl __P((struct rc_chans *, int, int)); 184static void rc_start __P((struct tty *)); 185static int rc_param __P((struct tty *, struct termios *)); 186static void rc_reinit __P((struct rc_softc *)); 187#ifdef RCDEBUG 188static void printrcflags(); 189#endif 190static timeout_t rc_dtrwakeup; 191static timeout_t rc_wakeup; 192static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 193static void rc_wait0 __P((int nec, int unit, int chan, int line)); 194 195/**********************************************/ 196 197/* Quick device probing */ 198static int 199rcprobe(dvp) 200 struct isa_device *dvp; 201{ 202 int irq = ffs(dvp->id_irq) - 1; 203 register int nec = dvp->id_iobase; 204 205 if (dvp->id_unit > NRC) 206 return 0; 207 if (!RC_VALIDADDR(nec)) { 208 printf("rc%d: illegal base address %x\n", nec); 209 return 0; 210 } 211 if (!RC_VALIDIRQ(irq)) { 212 printf("rc%d: illegal IRQ value %d\n", irq); 213 return 0; 214 } 215 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 216 rcout(CD180_PPRH, 0x11); 217 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 218 return 0; 219 /* Now, test the board more thoroughly, with diagnostic */ 220 if (rc_test(nec, dvp->id_unit)) 221 return 0; 222 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 223 224 return 0xF; 225} 226 227static int 228rcattach(dvp) 229 struct isa_device *dvp; 230{ 231 register int chan, nec = dvp->id_iobase; 232 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 233 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 234 static int rc_wakeup_started = 0; 235 struct tty *tp; 236 237 /* Thorooughly test the device */ 238 if (rcb->rcb_probed != RC_PROBED) 239 return 0; 240 rcb->rcb_addr = nec; 241 rcb->rcb_dtr = 0; 242 rcb->rcb_baserc = rc; 243 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 244 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 245 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 246 247 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 248 rc->rc_rcb = rcb; 249 rc->rc_chan = chan; 250 rc->rc_iptr = rc->rc_ibuf; 251 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 252 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 253 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 254 rc->rc_cor2 = rc->rc_pendcmd = 0; 255 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 256 rc->rc_dtrwait = 3 * hz; 257 rc->rc_dcdwaits= 0; 258 rc->rc_hotchar = 0; 259 tp = rc->rc_tp = &rc_tty[chan]; 260 ttychars(tp); 261 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 262 tp->t_cflag = TTYDEF_CFLAG; 263 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 264#ifdef DEVFS 265/* FIX THIS to reflect real devices */ 266 rc->devfs_token = 267 devfs_add_devswf(&rc_cdevsw, 268 (dvp->id_unit * CD180_NCHAN) + chan, 269 DV_CHR, 0, 0, 0600, "rc%d.%d", 270 dvp->id_unit, chan); 271#endif 272 } 273 rcb->rcb_probed = RC_ATTACHED; 274 if (!rc_wakeup_started) { 275 rc_wakeup((void *)NULL); 276 rc_wakeup_started = 0; 277 } 278 return 1; 279} 280 281/* RC interrupt handling */ 282void rcintr(unit) 283 int unit; 284{ 285 register struct rc_softc *rcb = &rc_softc[unit]; 286 register struct rc_chans *rc; 287 register int nec, resid; 288 register u_char val, iack, bsr, ucnt, *optr; 289 int good_data, t_state; 290 291 if (rcb->rcb_probed != RC_ATTACHED) { 292 printf("rc%d: bogus interrupt\n", unit); 293 return; 294 } 295 nec = rcb->rcb_addr; 296 297 bsr = ~(rcin(RC_BSR)); 298 299 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 300 printf("rc%d: extra interrupt\n", unit); 301 rcout(CD180_EOIR, 0); 302 return; 303 } 304 305 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 306#ifdef RCDEBUG_DETAILED 307 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 308 (bsr & RC_BSR_TOUT)?"TOUT ":"", 309 (bsr & RC_BSR_RXINT)?"RXINT ":"", 310 (bsr & RC_BSR_TXINT)?"TXINT ":"", 311 (bsr & RC_BSR_MOINT)?"MOINT":""); 312#endif 313 if (bsr & RC_BSR_TOUT) { 314 printf("rc%d: hardware failure, reset board\n", unit); 315 rcout(RC_CTOUT, 0); 316 rc_reinit(rcb); 317 return; 318 } 319 if (bsr & RC_BSR_RXINT) { 320 iack = rcin(RC_PILR_RX); 321 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 322 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 323 printf("rc%d: fake rxint: %02x\n", unit, iack); 324 goto more_intrs; 325 } 326 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 327 t_state = rc->rc_tp->t_state; 328 /* Do RTS flow control stuff */ 329 if ( (rc->rc_flags & RC_RTSFLOW) 330 || !(t_state & TS_ISOPEN) 331 ) { 332 if ( ( !(t_state & TS_ISOPEN) 333 || (t_state & TS_TBLOCK) 334 ) 335 && (rc->rc_msvr & MSVR_RTS) 336 ) 337 rcout(CD180_MSVR, 338 rc->rc_msvr &= ~MSVR_RTS); 339 else if (!(rc->rc_msvr & MSVR_RTS)) 340 rcout(CD180_MSVR, 341 rc->rc_msvr |= MSVR_RTS); 342 } 343 ucnt = rcin(CD180_RDCR) & 0xF; 344 resid = 0; 345 346 if (t_state & TS_ISOPEN) { 347 /* check for input buffer overflow */ 348 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 349 resid = ucnt; 350 ucnt = rc->rc_bufend - rc->rc_iptr; 351 resid -= ucnt; 352 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 353 rc->rc_flags |= RC_WAS_BUFOVFL; 354 rc_scheduled_event++; 355 } 356 } 357 optr = rc->rc_iptr; 358 /* check foor good data */ 359 if (good_data) { 360 while (ucnt-- > 0) { 361 val = rcin(CD180_RDR); 362 optr[0] = val; 363 optr[INPUT_FLAGS_SHIFT] = 0; 364 optr++; 365 rc_scheduled_event++; 366 if (val != 0 && val == rc->rc_hotchar) 367 setsofttty(); 368 } 369 } else { 370 /* Store also status data */ 371 while (ucnt-- > 0) { 372 iack = rcin(CD180_RCSR); 373 if (iack & RCSR_Timeout) 374 break; 375 if ( (iack & RCSR_OE) 376 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 377 rc->rc_flags |= RC_WAS_SILOVFL; 378 rc_scheduled_event++; 379 } 380 val = rcin(CD180_RDR); 381 /* 382 Don't store PE if IGNPAR and BREAK if IGNBRK, 383 this hack allows "raw" tty optimization 384 works even if IGN* is set. 385 */ 386 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 387 || (!(iack & (RCSR_PE|RCSR_FE)) 388 || !(rc->rc_tp->t_iflag & IGNPAR)) 389 && (!(iack & RCSR_Break) 390 || !(rc->rc_tp->t_iflag & IGNBRK))) { 391 if ( (iack & (RCSR_PE|RCSR_FE)) 392 && (t_state & TS_CAN_BYPASS_L_RINT) 393 && ((iack & RCSR_FE) 394 || (iack & RCSR_PE) 395 && (rc->rc_tp->t_iflag & INPCK))) 396 val = 0; 397 else if (val != 0 && val == rc->rc_hotchar) 398 setsofttty(); 399 optr[0] = val; 400 optr[INPUT_FLAGS_SHIFT] = iack; 401 optr++; 402 rc_scheduled_event++; 403 } 404 } 405 } 406 rc->rc_iptr = optr; 407 rc->rc_flags |= RC_DORXFER; 408 } else 409 resid = ucnt; 410 /* Clear FIFO if necessary */ 411 while (resid-- > 0) { 412 if (!good_data) 413 iack = rcin(CD180_RCSR); 414 else 415 iack = 0; 416 if (iack & RCSR_Timeout) 417 break; 418 (void) rcin(CD180_RDR); 419 } 420 goto more_intrs; 421 } 422 if (bsr & RC_BSR_MOINT) { 423 iack = rcin(RC_PILR_MODEM); 424 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 425 printf("rc%d: fake moint: %02x\n", unit, iack); 426 goto more_intrs; 427 } 428 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 429 iack = rcin(CD180_MCR); 430 rc->rc_msvr = rcin(CD180_MSVR); 431 rcout(CD180_MCR, 0); 432#ifdef RCDEBUG 433 printrcflags(rc, "moint"); 434#endif 435 if (rc->rc_flags & RC_CTSFLOW) { 436 if (rc->rc_msvr & MSVR_CTS) 437 rc->rc_flags |= RC_SEND_RDY; 438 else 439 rc->rc_flags &= ~RC_SEND_RDY; 440 } else 441 rc->rc_flags |= RC_SEND_RDY; 442 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 443 rc_scheduled_event += LOTS_OF_EVENTS; 444 rc->rc_flags |= RC_MODCHG; 445 setsofttty(); 446 } 447 goto more_intrs; 448 } 449 if (bsr & RC_BSR_TXINT) { 450 iack = rcin(RC_PILR_TX); 451 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 452 printf("rc%d: fake txint: %02x\n", unit, iack); 453 goto more_intrs; 454 } 455 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 456 if ( (rc->rc_flags & RC_OSUSP) 457 || !(rc->rc_flags & RC_SEND_RDY) 458 ) 459 goto more_intrs; 460 /* Handle breaks and other stuff */ 461 if (rc->rc_pendcmd) { 462 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 463 rcout(CD180_TDR, CD180_C_ESC); 464 rcout(CD180_TDR, rc->rc_pendcmd); 465 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 466 rc->rc_pendcmd = 0; 467 goto more_intrs; 468 } 469 optr = rc->rc_optr; 470 resid = rc->rc_obufend - optr; 471 if (resid > CD180_NFIFO) 472 resid = CD180_NFIFO; 473 while (resid-- > 0) 474 rcout(CD180_TDR, *optr++); 475 rc->rc_optr = optr; 476 477 /* output completed? */ 478 if (optr >= rc->rc_obufend) { 479 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 480#ifdef RCDEBUG 481 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 482#endif 483 if (!(rc->rc_flags & RC_DOXXFER)) { 484 rc_scheduled_event += LOTS_OF_EVENTS; 485 rc->rc_flags |= RC_DOXXFER; 486 setsofttty(); 487 } 488 } 489 } 490 more_intrs: 491 rcout(CD180_EOIR, 0); /* end of interrupt */ 492 rcout(RC_CTOUT, 0); 493 bsr = ~(rcin(RC_BSR)); 494 } 495} 496 497/* Feed characters to output buffer */ 498static void rc_start(tp) 499register struct tty *tp; 500{ 501 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 502 register int nec = rc->rc_rcb->rcb_addr, s; 503 504 if (rc->rc_flags & RC_OSBUSY) 505 return; 506 s = spltty(); 507 rc->rc_flags |= RC_OSBUSY; 508 disable_intr(); 509 if (tp->t_state & TS_TTSTOP) 510 rc->rc_flags |= RC_OSUSP; 511 else 512 rc->rc_flags &= ~RC_OSUSP; 513 /* Do RTS flow control stuff */ 514 if ( (rc->rc_flags & RC_RTSFLOW) 515 && (tp->t_state & TS_TBLOCK) 516 && (rc->rc_msvr & MSVR_RTS) 517 ) { 518 rcout(CD180_CAR, rc->rc_chan); 519 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 520 } else if (!(rc->rc_msvr & MSVR_RTS)) { 521 rcout(CD180_CAR, rc->rc_chan); 522 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 523 } 524 enable_intr(); 525 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 526 goto out; 527#ifdef RCDEBUG 528 printrcflags(rc, "rcstart"); 529#endif 530 ttwwakeup(tp); 531#ifdef RCDEBUG 532 printf("rcstart: outq = %d obuf = %d\n", 533 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 534#endif 535 if (tp->t_state & TS_BUSY) 536 goto out; /* output still in progress ... */ 537 538 if (tp->t_outq.c_cc > 0) { 539 u_int ocnt; 540 541 tp->t_state |= TS_BUSY; 542 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 543 disable_intr(); 544 rc->rc_optr = rc->rc_obuf; 545 rc->rc_obufend = rc->rc_optr + ocnt; 546 enable_intr(); 547 if (!(rc->rc_ier & IER_TxRdy)) { 548#ifdef RCDEBUG 549 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 550#endif 551 rcout(CD180_CAR, rc->rc_chan); 552 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 553 } 554 } 555out: 556 rc->rc_flags &= ~RC_OSBUSY; 557 (void) splx(s); 558} 559 560/* Handle delayed events. */ 561void rcpoll() 562{ 563 register struct rc_chans *rc; 564 register struct rc_softc *rcb; 565 register u_char *tptr, *eptr; 566 register struct tty *tp; 567 register int chan, icnt, nec, unit; 568 569 if (rc_scheduled_event == 0) 570 return; 571repeat: 572 for (unit = 0; unit < NRC; unit++) { 573 rcb = &rc_softc[unit]; 574 rc = rcb->rcb_baserc; 575 nec = rc->rc_rcb->rcb_addr; 576 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 577 tp = rc->rc_tp; 578#ifdef RCDEBUG 579 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 580 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 581 printrcflags(rc, "rcevent"); 582#endif 583 if (rc->rc_flags & RC_WAS_BUFOVFL) { 584 disable_intr(); 585 rc->rc_flags &= ~RC_WAS_BUFOVFL; 586 rc_scheduled_event--; 587 enable_intr(); 588 printf("rc%d/%d: interrupt-level buffer overflow\n", 589 unit, chan); 590 } 591 if (rc->rc_flags & RC_WAS_SILOVFL) { 592 disable_intr(); 593 rc->rc_flags &= ~RC_WAS_SILOVFL; 594 rc_scheduled_event--; 595 enable_intr(); 596 printf("rc%d/%d: silo overflow\n", 597 unit, chan); 598 } 599 if (rc->rc_flags & RC_MODCHG) { 600 disable_intr(); 601 rc->rc_flags &= ~RC_MODCHG; 602 rc_scheduled_event -= LOTS_OF_EVENTS; 603 enable_intr(); 604 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 605 } 606 if (rc->rc_flags & RC_DORXFER) { 607 disable_intr(); 608 rc->rc_flags &= ~RC_DORXFER; 609 eptr = rc->rc_iptr; 610 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 611 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 612 else 613 tptr = rc->rc_ibuf; 614 icnt = eptr - tptr; 615 if (icnt > 0) { 616 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 617 rc->rc_iptr = rc->rc_ibuf; 618 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 619 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 620 } else { 621 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 622 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 623 rc->rc_hiwat = 624 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 625 } 626 if ( (rc->rc_flags & RC_RTSFLOW) 627 && (tp->t_state & TS_ISOPEN) 628 && !(tp->t_state & TS_TBLOCK) 629 && !(rc->rc_msvr & MSVR_RTS) 630 ) { 631 rcout(CD180_CAR, chan); 632 rcout(CD180_MSVR, 633 rc->rc_msvr |= MSVR_RTS); 634 } 635 rc_scheduled_event -= icnt; 636 } 637 enable_intr(); 638 639 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 640 goto done1; 641 642 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 643 && !(tp->t_state & TS_LOCAL)) { 644 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 645 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 646 && !(tp->t_state & TS_TBLOCK)) 647 ttyblock(tp); 648 tk_nin += icnt; 649 tk_rawcc += icnt; 650 tp->t_rawcc += icnt; 651 if (b_to_q(tptr, icnt, &tp->t_rawq)) 652 printf("rc%d/%d: tty-level buffer overflow\n", 653 unit, chan); 654 ttwakeup(tp); 655 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 656 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 657 tp->t_state &= ~TS_TTSTOP; 658 tp->t_lflag &= ~FLUSHO; 659 rc_start(tp); 660 } 661 } else { 662 for (; tptr < eptr; tptr++) 663 (*linesw[tp->t_line].l_rint) 664 (tptr[0] | 665 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 666 } 667done1: ; 668 } 669 if (rc->rc_flags & RC_DOXXFER) { 670 disable_intr(); 671 rc_scheduled_event -= LOTS_OF_EVENTS; 672 rc->rc_flags &= ~RC_DOXXFER; 673 rc->rc_tp->t_state &= ~TS_BUSY; 674 enable_intr(); 675 (*linesw[tp->t_line].l_start)(tp); 676 } 677 } 678 if (rc_scheduled_event == 0) 679 break; 680 } 681 if (rc_scheduled_event >= LOTS_OF_EVENTS) 682 goto repeat; 683} 684 685static void 686rcstop(tp, rw) 687 register struct tty *tp; 688 int rw; 689{ 690 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 691 u_char *tptr, *eptr; 692 693#ifdef RCDEBUG 694 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 695 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 696#endif 697 if (rw & FWRITE) 698 rc_discard_output(rc); 699 disable_intr(); 700 if (rw & FREAD) { 701 rc->rc_flags &= ~RC_DORXFER; 702 eptr = rc->rc_iptr; 703 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 704 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 705 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 706 } else { 707 tptr = rc->rc_ibuf; 708 rc->rc_iptr = rc->rc_ibuf; 709 } 710 rc_scheduled_event -= eptr - tptr; 711 } 712 if (tp->t_state & TS_TTSTOP) 713 rc->rc_flags |= RC_OSUSP; 714 else 715 rc->rc_flags &= ~RC_OSUSP; 716 enable_intr(); 717} 718 719static int 720rcopen(dev, flag, mode, p) 721 dev_t dev; 722 int flag, mode; 723 struct proc *p; 724{ 725 register struct rc_chans *rc; 726 register struct tty *tp; 727 int unit, nec, s, error = 0; 728 729 unit = GET_UNIT(dev); 730 if (unit >= NRC * CD180_NCHAN) 731 return ENXIO; 732 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 733 return ENXIO; 734 rc = &rc_chans[unit]; 735 tp = rc->rc_tp; 736 nec = rc->rc_rcb->rcb_addr; 737#ifdef RCDEBUG 738 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 739#endif 740 s = spltty(); 741 742again: 743 while (rc->rc_flags & RC_DTR_OFF) { 744 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 745 if (error != 0) 746 goto out; 747 } 748 if (tp->t_state & TS_ISOPEN) { 749 if (CALLOUT(dev)) { 750 if (!(rc->rc_flags & RC_ACTOUT)) { 751 error = EBUSY; 752 goto out; 753 } 754 } else { 755 if (rc->rc_flags & RC_ACTOUT) { 756 if (flag & O_NONBLOCK) { 757 error = EBUSY; 758 goto out; 759 } 760 if (error = tsleep(&rc->rc_rcb, 761 TTIPRI|PCATCH, "rcbi", 0)) 762 goto out; 763 goto again; 764 } 765 } 766 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 767 error = EBUSY; 768 goto out; 769 } 770 } else { 771 tp->t_oproc = rc_start; 772 tp->t_param = rc_param; 773 tp->t_dev = dev; 774 775 if (CALLOUT(dev)) 776 tp->t_cflag |= CLOCAL; 777 else 778 tp->t_cflag &= ~CLOCAL; 779 780 error = rc_param(tp, &tp->t_termios); 781 if (error) 782 goto out; 783 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 784 785 ttsetwater(tp); 786 787 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 788 (*linesw[tp->t_line].l_modem)(tp, 1); 789 } 790 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 791 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 792 rc->rc_dcdwaits++; 793 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 794 rc->rc_dcdwaits--; 795 if (error != 0) 796 goto out; 797 goto again; 798 } 799 error = (*linesw[tp->t_line].l_open)(dev, tp); 800 disc_optim(tp, &tp->t_termios, rc); 801 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 802 rc->rc_flags |= RC_ACTOUT; 803out: 804 (void) splx(s); 805 806 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 807 rc_hardclose(rc); 808 809 return error; 810} 811 812static int 813rcclose(dev, flag, mode, p) 814 dev_t dev; 815 int flag, mode; 816 struct proc *p; 817{ 818 register struct rc_chans *rc; 819 register struct tty *tp; 820 int s, unit = GET_UNIT(dev); 821 822 if (unit >= NRC * CD180_NCHAN) 823 return ENXIO; 824 rc = &rc_chans[unit]; 825 tp = rc->rc_tp; 826#ifdef RCDEBUG 827 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 828#endif 829 s = spltty(); 830 (*linesw[tp->t_line].l_close)(tp, flag); 831 disc_optim(tp, &tp->t_termios, rc); 832 rcstop(tp, FREAD | FWRITE); 833 rc_hardclose(rc); 834 ttyclose(tp); 835 splx(s); 836 return 0; 837} 838 839static void rc_hardclose(rc) 840register struct rc_chans *rc; 841{ 842 register int s, nec = rc->rc_rcb->rcb_addr; 843 register struct tty *tp = rc->rc_tp; 844 845 s = spltty(); 846 rcout(CD180_CAR, rc->rc_chan); 847 848 /* Disable rx/tx intrs */ 849 rcout(CD180_IER, rc->rc_ier = 0); 850 if ( (tp->t_cflag & HUPCL) 851 || !(rc->rc_flags & RC_ACTOUT) 852 && !(rc->rc_msvr & MSVR_CD) 853 && !(tp->t_cflag & CLOCAL) 854 || !(tp->t_state & TS_ISOPEN) 855 ) { 856 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 857 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 858 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 859 if (rc->rc_dtrwait) { 860 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 861 rc->rc_flags |= RC_DTR_OFF; 862 } 863 } 864 rc->rc_flags &= ~RC_ACTOUT; 865 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 866 wakeup(TSA_CARR_ON(tp)); 867 (void) splx(s); 868} 869 870/* Read from line */ 871static int 872rcread(dev, uio, flag) 873 dev_t dev; 874 struct uio *uio; 875 int flag; 876{ 877 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 878 879 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 880} 881 882/* Write to line */ 883static int 884rcwrite(dev, uio, flag) 885 dev_t dev; 886 struct uio *uio; 887 int flag; 888{ 889 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 890 891 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 892} 893 894/* Reset the bastard */ 895static void rc_hwreset(unit, nec, chipid) 896 register int unit, nec; 897 unsigned int chipid; 898{ 899 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 900 DELAY(20000); 901 WAITFORCCR(unit, -1); 902 903 rcout(RC_CTOUT, 0); /* Clear timeout */ 904 rcout(CD180_GIVR, chipid); 905 rcout(CD180_GICR, 0); 906 907 /* Set Prescaler Registers (1 msec) */ 908 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 909 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 910 911 /* Initialize Priority Interrupt Level Registers */ 912 rcout(CD180_PILR1, RC_PILR_MODEM); 913 rcout(CD180_PILR2, RC_PILR_TX); 914 rcout(CD180_PILR3, RC_PILR_RX); 915 916 /* Reset DTR */ 917 rcout(RC_DTREG, ~0); 918} 919 920/* Set channel parameters */ 921static int rc_param(tp, ts) 922 register struct tty *tp; 923 struct termios *ts; 924{ 925 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 926 register int nec = rc->rc_rcb->rcb_addr; 927 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 928 929 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 930 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 931 ) 932 return (EINVAL); 933 if (ts->c_ispeed == 0) 934 ts->c_ispeed = ts->c_ospeed; 935 odivs = RC_BRD(ts->c_ospeed); 936 idivs = RC_BRD(ts->c_ispeed); 937 938 s = spltty(); 939 940 /* Select channel */ 941 rcout(CD180_CAR, rc->rc_chan); 942 943 /* If speed == 0, hangup line */ 944 if (ts->c_ospeed == 0) { 945 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 946 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 947 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 948 } 949 950 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 951 cflag = ts->c_cflag; 952 iflag = ts->c_iflag; 953 lflag = ts->c_lflag; 954 955 if (idivs > 0) { 956 rcout(CD180_RBPRL, idivs & 0xFF); 957 rcout(CD180_RBPRH, idivs >> 8); 958 } 959 if (odivs > 0) { 960 rcout(CD180_TBPRL, odivs & 0xFF); 961 rcout(CD180_TBPRH, odivs >> 8); 962 } 963 964 /* set timeout value */ 965 if (ts->c_ispeed > 0) { 966 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 967 968 if ( !(lflag & ICANON) 969 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 970 && ts->c_cc[VTIME] * 10 > itm) 971 itm = ts->c_cc[VTIME] * 10; 972 973 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 974 } 975 976 switch (cflag & CSIZE) { 977 case CS5: val = COR1_5BITS; break; 978 case CS6: val = COR1_6BITS; break; 979 case CS7: val = COR1_7BITS; break; 980 default: 981 case CS8: val = COR1_8BITS; break; 982 } 983 if (cflag & PARENB) { 984 val |= COR1_NORMPAR; 985 if (cflag & PARODD) 986 val |= COR1_ODDP; 987 if (!(cflag & INPCK)) 988 val |= COR1_Ignore; 989 } else 990 val |= COR1_Ignore; 991 if (cflag & CSTOPB) 992 val |= COR1_2SB; 993 rcout(CD180_COR1, val); 994 995 /* Set FIFO threshold */ 996 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 997 inpflow = 0; 998 if ( (iflag & IXOFF) 999 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1000 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1001 || (iflag & IXANY) 1002 ) 1003 ) 1004 ) { 1005 inpflow = 1; 1006 val |= COR3_SCDE|COR3_FCT; 1007 } 1008 rcout(CD180_COR3, val); 1009 1010 /* Initialize on-chip automatic flow control */ 1011 val = 0; 1012 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1013 if (cflag & CCTS_OFLOW) { 1014 rc->rc_flags |= RC_CTSFLOW; 1015 val |= COR2_CtsAE; 1016 } else 1017 rc->rc_flags |= RC_SEND_RDY; 1018 if (tp->t_state & TS_TTSTOP) 1019 rc->rc_flags |= RC_OSUSP; 1020 else 1021 rc->rc_flags &= ~RC_OSUSP; 1022 if (cflag & CRTS_IFLOW) 1023 rc->rc_flags |= RC_RTSFLOW; 1024 else 1025 rc->rc_flags &= ~RC_RTSFLOW; 1026 1027 if (inpflow) { 1028 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1029 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1030 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1031 val |= COR2_TxIBE; 1032 if (iflag & IXANY) 1033 val |= COR2_IXM; 1034 } 1035 1036 rcout(CD180_COR2, rc->rc_cor2 = val); 1037 1038 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1039 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1040 1041 disc_optim(tp, ts, rc); 1042 1043 /* modem ctl */ 1044 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1045 if (cflag & CCTS_OFLOW) 1046 val |= MCOR1_CTSzd; 1047 rcout(CD180_MCOR1, val); 1048 1049 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1050 if (cflag & CCTS_OFLOW) 1051 val |= MCOR2_CTSod; 1052 rcout(CD180_MCOR2, val); 1053 1054 /* enable i/o and interrupts */ 1055 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1056 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1057 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1058 1059 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1060 if (cflag & CCTS_OFLOW) 1061 rc->rc_ier |= IER_CTS; 1062 if (cflag & CREAD) 1063 rc->rc_ier |= IER_RxData; 1064 if (tp->t_state & TS_BUSY) 1065 rc->rc_ier |= IER_TxRdy; 1066 if (ts->c_ospeed != 0) 1067 rc_modctl(rc, TIOCM_DTR, DMBIS); 1068 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1069 rc->rc_flags |= RC_SEND_RDY; 1070 rcout(CD180_IER, rc->rc_ier); 1071 (void) splx(s); 1072 return 0; 1073} 1074 1075/* Re-initialize board after bogus interrupts */ 1076static void rc_reinit(rcb) 1077struct rc_softc *rcb; 1078{ 1079 register struct rc_chans *rc, *rce; 1080 register int nec; 1081 1082 nec = rcb->rcb_addr; 1083 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1084 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1085 rce = rc + CD180_NCHAN; 1086 for (; rc < rce; rc++) 1087 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1088} 1089 1090static int 1091rcioctl(dev, cmd, data, flag, p) 1092dev_t dev; 1093int cmd, flag; 1094caddr_t data; 1095struct proc *p; 1096{ 1097 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1098 register int s, error; 1099 struct tty *tp = rc->rc_tp; 1100 1101 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1102 if (error != ENOIOCTL) 1103 return (error); 1104 error = ttioctl(tp, cmd, data, flag); 1105 disc_optim(tp, &tp->t_termios, rc); 1106 if (error != ENOIOCTL) 1107 return (error); 1108 s = spltty(); 1109 1110 switch (cmd) { 1111 case TIOCSBRK: 1112 rc->rc_pendcmd = CD180_C_SBRK; 1113 break; 1114 1115 case TIOCCBRK: 1116 rc->rc_pendcmd = CD180_C_EBRK; 1117 break; 1118 1119 case TIOCSDTR: 1120 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1121 break; 1122 1123 case TIOCCDTR: 1124 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1125 break; 1126 1127 case TIOCMGET: 1128 *(int *) data = rc_modctl(rc, 0, DMGET); 1129 break; 1130 1131 case TIOCMSET: 1132 (void) rc_modctl(rc, *(int *) data, DMSET); 1133 break; 1134 1135 case TIOCMBIC: 1136 (void) rc_modctl(rc, *(int *) data, DMBIC); 1137 break; 1138 1139 case TIOCMBIS: 1140 (void) rc_modctl(rc, *(int *) data, DMBIS); 1141 break; 1142 1143 case TIOCMSDTRWAIT: 1144 error = suser(p->p_ucred, &p->p_acflag); 1145 if (error != 0) { 1146 splx(s); 1147 return (error); 1148 } 1149 rc->rc_dtrwait = *(int *)data * hz / 100; 1150 break; 1151 1152 case TIOCMGDTRWAIT: 1153 *(int *)data = rc->rc_dtrwait * 100 / hz; 1154 break; 1155 1156 default: 1157 (void) splx(s); 1158 return ENOTTY; 1159 } 1160 (void) splx(s); 1161 return 0; 1162} 1163 1164 1165/* Modem control routines */ 1166 1167static int rc_modctl(rc, bits, cmd) 1168register struct rc_chans *rc; 1169int bits, cmd; 1170{ 1171 register int nec = rc->rc_rcb->rcb_addr; 1172 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1173 1174 rcout(CD180_CAR, rc->rc_chan); 1175 1176 switch (cmd) { 1177 case DMSET: 1178 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1179 ~(*dtr |= 1 << rc->rc_chan) : 1180 ~(*dtr &= ~(1 << rc->rc_chan))); 1181 msvr = rcin(CD180_MSVR); 1182 if (bits & TIOCM_RTS) 1183 msvr |= MSVR_RTS; 1184 else 1185 msvr &= ~MSVR_RTS; 1186 if (bits & TIOCM_DTR) 1187 msvr |= MSVR_DTR; 1188 else 1189 msvr &= ~MSVR_DTR; 1190 rcout(CD180_MSVR, msvr); 1191 break; 1192 1193 case DMBIS: 1194 if (bits & TIOCM_DTR) 1195 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1196 msvr = rcin(CD180_MSVR); 1197 if (bits & TIOCM_RTS) 1198 msvr |= MSVR_RTS; 1199 if (bits & TIOCM_DTR) 1200 msvr |= MSVR_DTR; 1201 rcout(CD180_MSVR, msvr); 1202 break; 1203 1204 case DMGET: 1205 bits = TIOCM_LE; 1206 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1207 1208 if (msvr & MSVR_RTS) 1209 bits |= TIOCM_RTS; 1210 if (msvr & MSVR_CTS) 1211 bits |= TIOCM_CTS; 1212 if (msvr & MSVR_DSR) 1213 bits |= TIOCM_DSR; 1214 if (msvr & MSVR_DTR) 1215 bits |= TIOCM_DTR; 1216 if (msvr & MSVR_CD) 1217 bits |= TIOCM_CD; 1218 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1219 bits |= TIOCM_RI; 1220 return bits; 1221 1222 case DMBIC: 1223 if (bits & TIOCM_DTR) 1224 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1225 msvr = rcin(CD180_MSVR); 1226 if (bits & TIOCM_RTS) 1227 msvr &= ~MSVR_RTS; 1228 if (bits & TIOCM_DTR) 1229 msvr &= ~MSVR_DTR; 1230 rcout(CD180_MSVR, msvr); 1231 break; 1232 } 1233 rc->rc_msvr = rcin(CD180_MSVR); 1234 return 0; 1235} 1236 1237/* Test the board. */ 1238int rc_test(nec, unit) 1239 register int nec; 1240 int unit; 1241{ 1242 int chan = 0; 1243 int i = 0, rcnt, old_level; 1244 unsigned int iack, chipid; 1245 unsigned short divs; 1246 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1247#define CTLEN 8 1248#define ERR(s) { \ 1249 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1250 (void) splx(old_level); return 1; } 1251 1252 struct rtest { 1253 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1254 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1255 int rxptr; /* RX pointer */ 1256 int txptr; /* TX pointer */ 1257 } tchans[CD180_NCHAN]; 1258 1259 old_level = spltty(); 1260 1261 chipid = RC_FAKEID; 1262 1263 /* First, reset board to inital state */ 1264 rc_hwreset(unit, nec, chipid); 1265 1266 divs = RC_BRD(19200); 1267 1268 /* Initialize channels */ 1269 for (chan = 0; chan < CD180_NCHAN; chan++) { 1270 1271 /* Select and reset channel */ 1272 rcout(CD180_CAR, chan); 1273 CCRCMD(unit, chan, CCR_ResetChan); 1274 WAITFORCCR(unit, chan); 1275 1276 /* Set speed */ 1277 rcout(CD180_RBPRL, divs & 0xFF); 1278 rcout(CD180_RBPRH, divs >> 8); 1279 rcout(CD180_TBPRL, divs & 0xFF); 1280 rcout(CD180_TBPRH, divs >> 8); 1281 1282 /* set timeout value */ 1283 rcout(CD180_RTPR, 0); 1284 1285 /* Establish local loopback */ 1286 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1287 rcout(CD180_COR2, COR2_LLM); 1288 rcout(CD180_COR3, CD180_NFIFO); 1289 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1290 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1291 WAITFORCCR(unit, chan); 1292 rcout(CD180_MSVR, MSVR_RTS); 1293 1294 /* Fill TXBUF with test data */ 1295 for (i = 0; i < CD180_NFIFO; i++) { 1296 tchans[chan].txbuf[i] = ctest[i]; 1297 tchans[chan].rxbuf[i] = 0; 1298 } 1299 tchans[chan].txptr = tchans[chan].rxptr = 0; 1300 1301 /* Now, start transmit */ 1302 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1303 } 1304 /* Pseudo-interrupt poll stuff */ 1305 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1306 i = ~(rcin(RC_BSR)); 1307 if (i & RC_BSR_TOUT) 1308 ERR(("BSR timeout bit set\n")) 1309 else if (i & RC_BSR_TXINT) { 1310 iack = rcin(RC_PILR_TX); 1311 if (iack != (GIVR_IT_TDI | chipid)) 1312 ERR(("Bad TX intr ack (%02x != %02x)\n", 1313 iack, GIVR_IT_TDI | chipid)); 1314 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1315 /* If no more data to transmit, disable TX intr */ 1316 if (tchans[chan].txptr >= CD180_NFIFO) { 1317 iack = rcin(CD180_IER); 1318 rcout(CD180_IER, iack & ~IER_TxMpty); 1319 } else { 1320 for (iack = tchans[chan].txptr; 1321 iack < CD180_NFIFO; iack++) 1322 rcout(CD180_TDR, 1323 tchans[chan].txbuf[iack]); 1324 tchans[chan].txptr = iack; 1325 } 1326 rcout(CD180_EOIR, 0); 1327 } else if (i & RC_BSR_RXINT) { 1328 u_char ucnt; 1329 1330 iack = rcin(RC_PILR_RX); 1331 if (iack != (GIVR_IT_RGDI | chipid) && 1332 iack != (GIVR_IT_REI | chipid)) 1333 ERR(("Bad RX intr ack (%02x != %02x)\n", 1334 iack, GIVR_IT_RGDI | chipid)) 1335 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1336 ucnt = rcin(CD180_RDCR) & 0xF; 1337 while (ucnt-- > 0) { 1338 iack = rcin(CD180_RCSR); 1339 if (iack & RCSR_Timeout) 1340 break; 1341 if (iack & 0xF) 1342 ERR(("Bad char chan %d (RCSR = %02X)\n", 1343 chan, iack)) 1344 if (tchans[chan].rxptr > CD180_NFIFO) 1345 ERR(("Got extra chars chan %d\n", 1346 chan)) 1347 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1348 rcin(CD180_RDR); 1349 } 1350 rcout(CD180_EOIR, 0); 1351 } 1352 rcout(RC_CTOUT, 0); 1353 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1354 if (tchans[chan].rxptr >= CD180_NFIFO) 1355 iack++; 1356 if (iack == CD180_NCHAN) 1357 break; 1358 } 1359 for (chan = 0; chan < CD180_NCHAN; chan++) { 1360 /* Select and reset channel */ 1361 rcout(CD180_CAR, chan); 1362 CCRCMD(unit, chan, CCR_ResetChan); 1363 } 1364 1365 if (!rcnt) 1366 ERR(("looses characters during local loopback\n")) 1367 /* Now, check data */ 1368 for (chan = 0; chan < CD180_NCHAN; chan++) 1369 for (i = 0; i < CD180_NFIFO; i++) 1370 if (ctest[i] != tchans[chan].rxbuf[i]) 1371 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1372 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1373 (void) splx(old_level); 1374 return 0; 1375} 1376 1377#ifdef RCDEBUG 1378static void printrcflags(rc, comment) 1379struct rc_chans *rc; 1380char *comment; 1381{ 1382 u_short f = rc->rc_flags; 1383 register int nec = rc->rc_rcb->rcb_addr; 1384 1385 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1386 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1387 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1388 (f & RC_ACTOUT) ?"ACTOUT " :"", 1389 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1390 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1391 (f & RC_DORXFER)?"DORXFER " :"", 1392 (f & RC_DOXXFER)?"DOXXFER " :"", 1393 (f & RC_MODCHG) ?"MODCHG " :"", 1394 (f & RC_OSUSP) ?"OSUSP " :"", 1395 (f & RC_OSBUSY) ?"OSBUSY " :"", 1396 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1397 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1398 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1399 1400 rcout(CD180_CAR, rc->rc_chan); 1401 1402 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1403 rc->rc_rcb->rcb_unit, rc->rc_chan, 1404 rcin(CD180_MSVR), 1405 rcin(CD180_IER), 1406 rcin(CD180_CCSR)); 1407} 1408#endif /* RCDEBUG */ 1409 1410static struct tty * 1411rcdevtotty(dev) 1412 dev_t dev; 1413{ 1414 int unit; 1415 1416 unit = GET_UNIT(dev); 1417 if (unit >= NRC * CD180_NCHAN) 1418 return NULL; 1419 return (&rc_tty[unit]); 1420} 1421 1422static void 1423rc_dtrwakeup(chan) 1424 void *chan; 1425{ 1426 struct rc_chans *rc; 1427 1428 rc = (struct rc_chans *)chan; 1429 rc->rc_flags &= ~RC_DTR_OFF; 1430 wakeup(&rc->rc_dtrwait); 1431} 1432 1433static void 1434rc_discard_output(rc) 1435 struct rc_chans *rc; 1436{ 1437 disable_intr(); 1438 if (rc->rc_flags & RC_DOXXFER) { 1439 rc_scheduled_event -= LOTS_OF_EVENTS; 1440 rc->rc_flags &= ~RC_DOXXFER; 1441 } 1442 rc->rc_optr = rc->rc_obufend; 1443 rc->rc_tp->t_state &= ~TS_BUSY; 1444 enable_intr(); 1445 ttwwakeup(rc->rc_tp); 1446} 1447 1448static void 1449rc_wakeup(chan) 1450 void *chan; 1451{ 1452 timeout(rc_wakeup, (caddr_t)NULL, 1); 1453 1454 if (rc_scheduled_event != 0) { 1455 int s; 1456 1457 s = splsofttty(); 1458 rcpoll(); 1459 splx(s); 1460 } 1461} 1462 1463static void 1464disc_optim(tp, t, rc) 1465 struct tty *tp; 1466 struct termios *t; 1467 struct rc_chans *rc; 1468{ 1469 1470 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1471 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1472 && (!(t->c_iflag & PARMRK) 1473 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1474 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1475 && linesw[tp->t_line].l_rint == ttyinput) 1476 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1477 else 1478 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1479 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1480} 1481 1482static void 1483rc_wait0(nec, unit, chan, line) 1484 int nec, unit, chan, line; 1485{ 1486 int rcnt; 1487 1488 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1489 DELAY(30); 1490 if (rcnt == 0) 1491 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1492 unit, chan, line); 1493} 1494 1495static rc_devsw_installed = 0; 1496 1497static void rc_drvinit(void *unused) 1498{ 1499 dev_t dev; 1500 1501 if( ! rc_devsw_installed ) { 1502 dev = makedev(CDEV_MAJOR, 0); 1503 cdevsw_add(&dev,&rc_cdevsw, NULL); 1504 rc_devsw_installed = 1; 1505 } 1506} 1507 1508SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1509 1510 1511#endif /* NRC */ 1512