rc.c revision 29368
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34 35#if NRC > 0 36 37/*#define RCDEBUG*/ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/fcntl.h> 46#include <sys/kernel.h> 47#ifdef DEVFS 48#include <sys/devfsext.h> 49#endif /*DEVFS*/ 50 51#include <machine/clock.h> 52 53#include <i386/isa/isa_device.h> 54 55#include <i386/isa/ic/cd180.h> 56#include <i386/isa/rcreg.h> 57 58 59/* Prototypes */ 60static int rcprobe __P((struct isa_device *)); 61static int rcattach __P((struct isa_device *)); 62 63/*- 64 * This space intentionally left blank to stop __LINE__ from screwing up 65 * regression tests :-(. 66 * 67 * 68 * 69 */ 70void rcpoll __P((void)); 71 72#define rcin(port) RC_IN (nec, port) 73#define rcout(port,v) RC_OUT (nec, port, v) 74 75#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 76#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 77 78#define RC_IBUFSIZE 256 79#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 80#define RC_OBUFSIZE 512 81#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 82#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 83#define LOTS_OF_EVENTS 64 84 85#define RC_FAKEID 0x10 86 87#define RC_PROBED 1 88#define RC_ATTACHED 2 89 90#define GET_UNIT(dev) (minor(dev) & 0x3F) 91#define CALLOUT(dev) (minor(dev) & 0x80) 92 93/* For isa routines */ 94struct isa_driver rcdriver = { 95 rcprobe, rcattach, "rc" 96}; 97 98static d_open_t rcopen; 99static d_close_t rcclose; 100static d_read_t rcread; 101static d_write_t rcwrite; 102static d_ioctl_t rcioctl; 103static d_stop_t rcstop; 104static d_devtotty_t rcdevtotty; 105 106#define CDEV_MAJOR 63 107static struct cdevsw rc_cdevsw = 108 { rcopen, rcclose, rcread, rcwrite, /*63*/ 109 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 110 ttpoll, nommap, NULL, "rc", NULL, -1 }; 111 112/* Per-board structure */ 113static struct rc_softc { 114 u_int rcb_probed; /* 1 - probed, 2 - attached */ 115 u_int rcb_addr; /* Base I/O addr */ 116 u_int rcb_unit; /* unit # */ 117 u_char rcb_dtr; /* DTR status */ 118 struct rc_chans *rcb_baserc; /* base rc ptr */ 119} rc_softc[NRC]; 120 121/* Per-channel structure */ 122static struct rc_chans { 123 struct rc_softc *rc_rcb; /* back ptr */ 124 u_short rc_flags; /* Misc. flags */ 125 int rc_chan; /* Channel # */ 126 u_char rc_ier; /* intr. enable reg */ 127 u_char rc_msvr; /* modem sig. status */ 128 u_char rc_cor2; /* options reg */ 129 u_char rc_pendcmd; /* special cmd pending */ 130 u_int rc_dtrwait; /* dtr timeout */ 131 u_int rc_dcdwaits; /* how many waits DCD in open */ 132 u_char rc_hotchar; /* end packed optimize */ 133 struct tty *rc_tp; /* tty struct */ 134 u_char *rc_iptr; /* Chars input buffer */ 135 u_char *rc_hiwat; /* hi-water mark */ 136 u_char *rc_bufend; /* end of buffer */ 137 u_char *rc_optr; /* ptr in output buf */ 138 u_char *rc_obufend; /* end of output buf */ 139 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 140 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 141#ifdef DEVFS 142 void *devfs_token; 143#endif 144} rc_chans[NRC * CD180_NCHAN]; 145 146static int rc_scheduled_event = 0; 147 148/* for pstat -t */ 149static struct tty rc_tty[NRC * CD180_NCHAN]; 150static const int nrc_tty = NRC * CD180_NCHAN; 151 152/* Flags */ 153#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 154#define RC_ACTOUT 0x0002 /* Dial-out port active */ 155#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 156#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 157#define RC_DORXFER 0x0010 /* RXFER event planned */ 158#define RC_DOXXFER 0x0020 /* XXFER event planned */ 159#define RC_MODCHG 0x0040 /* Modem status changed */ 160#define RC_OSUSP 0x0080 /* Output suspended */ 161#define RC_OSBUSY 0x0100 /* start() routine in progress */ 162#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 163#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 164#define RC_SEND_RDY 0x0800 /* ready to send */ 165 166/* Table for translation of RCSR status bits to internal form */ 167static int rc_rcsrt[16] = { 168 0, TTY_OE, TTY_FE, 169 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 170 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 171 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 172 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 173 TTY_BI|TTY_PE|TTY_FE|TTY_OE 174}; 175 176/* Static prototypes */ 177static void rc_hwreset __P((int, int, unsigned int)); 178static int rc_test __P((int, int)); 179static void rc_discard_output __P((struct rc_chans *)); 180static void rc_hardclose __P((struct rc_chans *)); 181static int rc_modctl __P((struct rc_chans *, int, int)); 182static void rc_start __P((struct tty *)); 183static int rc_param __P((struct tty *, struct termios *)); 184static void rc_reinit __P((struct rc_softc *)); 185#ifdef RCDEBUG 186static void printrcflags(); 187#endif 188static timeout_t rc_dtrwakeup; 189static timeout_t rc_wakeup; 190static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 191static void rc_wait0 __P((int nec, int unit, int chan, int line)); 192 193/**********************************************/ 194 195/* Quick device probing */ 196static int 197rcprobe(dvp) 198 struct isa_device *dvp; 199{ 200 int irq = ffs(dvp->id_irq) - 1; 201 register int nec = dvp->id_iobase; 202 203 if (dvp->id_unit > NRC) 204 return 0; 205 if (!RC_VALIDADDR(nec)) { 206 printf("rc%d: illegal base address %x\n", nec); 207 return 0; 208 } 209 if (!RC_VALIDIRQ(irq)) { 210 printf("rc%d: illegal IRQ value %d\n", irq); 211 return 0; 212 } 213 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 214 rcout(CD180_PPRH, 0x11); 215 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 216 return 0; 217 /* Now, test the board more thoroughly, with diagnostic */ 218 if (rc_test(nec, dvp->id_unit)) 219 return 0; 220 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 221 222 return 0xF; 223} 224 225static int 226rcattach(dvp) 227 struct isa_device *dvp; 228{ 229 register int chan, nec = dvp->id_iobase; 230 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 231 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 232 static int rc_wakeup_started = 0; 233 struct tty *tp; 234 235 /* Thorooughly test the device */ 236 if (rcb->rcb_probed != RC_PROBED) 237 return 0; 238 rcb->rcb_addr = nec; 239 rcb->rcb_dtr = 0; 240 rcb->rcb_baserc = rc; 241 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 242 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 243 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 244 245 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 246 rc->rc_rcb = rcb; 247 rc->rc_chan = chan; 248 rc->rc_iptr = rc->rc_ibuf; 249 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 250 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 251 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 252 rc->rc_cor2 = rc->rc_pendcmd = 0; 253 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 254 rc->rc_dtrwait = 3 * hz; 255 rc->rc_dcdwaits= 0; 256 rc->rc_hotchar = 0; 257 tp = rc->rc_tp = &rc_tty[chan]; 258 ttychars(tp); 259 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 260 tp->t_cflag = TTYDEF_CFLAG; 261 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 262#ifdef DEVFS 263/* FIX THIS to reflect real devices */ 264 rc->devfs_token = 265 devfs_add_devswf(&rc_cdevsw, 266 (dvp->id_unit * CD180_NCHAN) + chan, 267 DV_CHR, 0, 0, 0600, "rc%d.%d", 268 dvp->id_unit, chan); 269#endif 270 } 271 rcb->rcb_probed = RC_ATTACHED; 272 if (!rc_wakeup_started) { 273 rc_wakeup((void *)NULL); 274 rc_wakeup_started = 0; 275 } 276 return 1; 277} 278 279/* RC interrupt handling */ 280void rcintr(unit) 281 int unit; 282{ 283 register struct rc_softc *rcb = &rc_softc[unit]; 284 register struct rc_chans *rc; 285 register int nec, resid; 286 register u_char val, iack, bsr, ucnt, *optr; 287 int good_data, t_state; 288 289 if (rcb->rcb_probed != RC_ATTACHED) { 290 printf("rc%d: bogus interrupt\n", unit); 291 return; 292 } 293 nec = rcb->rcb_addr; 294 295 bsr = ~(rcin(RC_BSR)); 296 297 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 298 printf("rc%d: extra interrupt\n", unit); 299 rcout(CD180_EOIR, 0); 300 return; 301 } 302 303 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 304#ifdef RCDEBUG_DETAILED 305 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 306 (bsr & RC_BSR_TOUT)?"TOUT ":"", 307 (bsr & RC_BSR_RXINT)?"RXINT ":"", 308 (bsr & RC_BSR_TXINT)?"TXINT ":"", 309 (bsr & RC_BSR_MOINT)?"MOINT":""); 310#endif 311 if (bsr & RC_BSR_TOUT) { 312 printf("rc%d: hardware failure, reset board\n", unit); 313 rcout(RC_CTOUT, 0); 314 rc_reinit(rcb); 315 return; 316 } 317 if (bsr & RC_BSR_RXINT) { 318 iack = rcin(RC_PILR_RX); 319 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 320 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 321 printf("rc%d: fake rxint: %02x\n", unit, iack); 322 goto more_intrs; 323 } 324 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 325 t_state = rc->rc_tp->t_state; 326 /* Do RTS flow control stuff */ 327 if ( (rc->rc_flags & RC_RTSFLOW) 328 || !(t_state & TS_ISOPEN) 329 ) { 330 if ( ( !(t_state & TS_ISOPEN) 331 || (t_state & TS_TBLOCK) 332 ) 333 && (rc->rc_msvr & MSVR_RTS) 334 ) 335 rcout(CD180_MSVR, 336 rc->rc_msvr &= ~MSVR_RTS); 337 else if (!(rc->rc_msvr & MSVR_RTS)) 338 rcout(CD180_MSVR, 339 rc->rc_msvr |= MSVR_RTS); 340 } 341 ucnt = rcin(CD180_RDCR) & 0xF; 342 resid = 0; 343 344 if (t_state & TS_ISOPEN) { 345 /* check for input buffer overflow */ 346 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 347 resid = ucnt; 348 ucnt = rc->rc_bufend - rc->rc_iptr; 349 resid -= ucnt; 350 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 351 rc->rc_flags |= RC_WAS_BUFOVFL; 352 rc_scheduled_event++; 353 } 354 } 355 optr = rc->rc_iptr; 356 /* check foor good data */ 357 if (good_data) { 358 while (ucnt-- > 0) { 359 val = rcin(CD180_RDR); 360 optr[0] = val; 361 optr[INPUT_FLAGS_SHIFT] = 0; 362 optr++; 363 rc_scheduled_event++; 364 if (val != 0 && val == rc->rc_hotchar) 365 setsofttty(); 366 } 367 } else { 368 /* Store also status data */ 369 while (ucnt-- > 0) { 370 iack = rcin(CD180_RCSR); 371 if (iack & RCSR_Timeout) 372 break; 373 if ( (iack & RCSR_OE) 374 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 375 rc->rc_flags |= RC_WAS_SILOVFL; 376 rc_scheduled_event++; 377 } 378 val = rcin(CD180_RDR); 379 /* 380 Don't store PE if IGNPAR and BREAK if IGNBRK, 381 this hack allows "raw" tty optimization 382 works even if IGN* is set. 383 */ 384 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 385 || (!(iack & (RCSR_PE|RCSR_FE)) 386 || !(rc->rc_tp->t_iflag & IGNPAR)) 387 && (!(iack & RCSR_Break) 388 || !(rc->rc_tp->t_iflag & IGNBRK))) { 389 if ( (iack & (RCSR_PE|RCSR_FE)) 390 && (t_state & TS_CAN_BYPASS_L_RINT) 391 && ((iack & RCSR_FE) 392 || (iack & RCSR_PE) 393 && (rc->rc_tp->t_iflag & INPCK))) 394 val = 0; 395 else if (val != 0 && val == rc->rc_hotchar) 396 setsofttty(); 397 optr[0] = val; 398 optr[INPUT_FLAGS_SHIFT] = iack; 399 optr++; 400 rc_scheduled_event++; 401 } 402 } 403 } 404 rc->rc_iptr = optr; 405 rc->rc_flags |= RC_DORXFER; 406 } else 407 resid = ucnt; 408 /* Clear FIFO if necessary */ 409 while (resid-- > 0) { 410 if (!good_data) 411 iack = rcin(CD180_RCSR); 412 else 413 iack = 0; 414 if (iack & RCSR_Timeout) 415 break; 416 (void) rcin(CD180_RDR); 417 } 418 goto more_intrs; 419 } 420 if (bsr & RC_BSR_MOINT) { 421 iack = rcin(RC_PILR_MODEM); 422 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 423 printf("rc%d: fake moint: %02x\n", unit, iack); 424 goto more_intrs; 425 } 426 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 427 iack = rcin(CD180_MCR); 428 rc->rc_msvr = rcin(CD180_MSVR); 429 rcout(CD180_MCR, 0); 430#ifdef RCDEBUG 431 printrcflags(rc, "moint"); 432#endif 433 if (rc->rc_flags & RC_CTSFLOW) { 434 if (rc->rc_msvr & MSVR_CTS) 435 rc->rc_flags |= RC_SEND_RDY; 436 else 437 rc->rc_flags &= ~RC_SEND_RDY; 438 } else 439 rc->rc_flags |= RC_SEND_RDY; 440 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 441 rc_scheduled_event += LOTS_OF_EVENTS; 442 rc->rc_flags |= RC_MODCHG; 443 setsofttty(); 444 } 445 goto more_intrs; 446 } 447 if (bsr & RC_BSR_TXINT) { 448 iack = rcin(RC_PILR_TX); 449 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 450 printf("rc%d: fake txint: %02x\n", unit, iack); 451 goto more_intrs; 452 } 453 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 454 if ( (rc->rc_flags & RC_OSUSP) 455 || !(rc->rc_flags & RC_SEND_RDY) 456 ) 457 goto more_intrs; 458 /* Handle breaks and other stuff */ 459 if (rc->rc_pendcmd) { 460 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 461 rcout(CD180_TDR, CD180_C_ESC); 462 rcout(CD180_TDR, rc->rc_pendcmd); 463 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 464 rc->rc_pendcmd = 0; 465 goto more_intrs; 466 } 467 optr = rc->rc_optr; 468 resid = rc->rc_obufend - optr; 469 if (resid > CD180_NFIFO) 470 resid = CD180_NFIFO; 471 while (resid-- > 0) 472 rcout(CD180_TDR, *optr++); 473 rc->rc_optr = optr; 474 475 /* output completed? */ 476 if (optr >= rc->rc_obufend) { 477 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 478#ifdef RCDEBUG 479 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 480#endif 481 if (!(rc->rc_flags & RC_DOXXFER)) { 482 rc_scheduled_event += LOTS_OF_EVENTS; 483 rc->rc_flags |= RC_DOXXFER; 484 setsofttty(); 485 } 486 } 487 } 488 more_intrs: 489 rcout(CD180_EOIR, 0); /* end of interrupt */ 490 rcout(RC_CTOUT, 0); 491 bsr = ~(rcin(RC_BSR)); 492 } 493} 494 495/* Feed characters to output buffer */ 496static void rc_start(tp) 497register struct tty *tp; 498{ 499 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 500 register int nec = rc->rc_rcb->rcb_addr, s; 501 502 if (rc->rc_flags & RC_OSBUSY) 503 return; 504 s = spltty(); 505 rc->rc_flags |= RC_OSBUSY; 506 disable_intr(); 507 if (tp->t_state & TS_TTSTOP) 508 rc->rc_flags |= RC_OSUSP; 509 else 510 rc->rc_flags &= ~RC_OSUSP; 511 /* Do RTS flow control stuff */ 512 if ( (rc->rc_flags & RC_RTSFLOW) 513 && (tp->t_state & TS_TBLOCK) 514 && (rc->rc_msvr & MSVR_RTS) 515 ) { 516 rcout(CD180_CAR, rc->rc_chan); 517 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 518 } else if (!(rc->rc_msvr & MSVR_RTS)) { 519 rcout(CD180_CAR, rc->rc_chan); 520 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 521 } 522 enable_intr(); 523 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 524 goto out; 525#ifdef RCDEBUG 526 printrcflags(rc, "rcstart"); 527#endif 528 ttwwakeup(tp); 529#ifdef RCDEBUG 530 printf("rcstart: outq = %d obuf = %d\n", 531 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 532#endif 533 if (tp->t_state & TS_BUSY) 534 goto out; /* output still in progress ... */ 535 536 if (tp->t_outq.c_cc > 0) { 537 u_int ocnt; 538 539 tp->t_state |= TS_BUSY; 540 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 541 disable_intr(); 542 rc->rc_optr = rc->rc_obuf; 543 rc->rc_obufend = rc->rc_optr + ocnt; 544 enable_intr(); 545 if (!(rc->rc_ier & IER_TxRdy)) { 546#ifdef RCDEBUG 547 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 548#endif 549 rcout(CD180_CAR, rc->rc_chan); 550 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 551 } 552 } 553out: 554 rc->rc_flags &= ~RC_OSBUSY; 555 (void) splx(s); 556} 557 558/* Handle delayed events. */ 559void rcpoll() 560{ 561 register struct rc_chans *rc; 562 register struct rc_softc *rcb; 563 register u_char *tptr, *eptr; 564 register struct tty *tp; 565 register int chan, icnt, nec, unit; 566 567 if (rc_scheduled_event == 0) 568 return; 569repeat: 570 for (unit = 0; unit < NRC; unit++) { 571 rcb = &rc_softc[unit]; 572 rc = rcb->rcb_baserc; 573 nec = rc->rc_rcb->rcb_addr; 574 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 575 tp = rc->rc_tp; 576#ifdef RCDEBUG 577 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 578 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 579 printrcflags(rc, "rcevent"); 580#endif 581 if (rc->rc_flags & RC_WAS_BUFOVFL) { 582 disable_intr(); 583 rc->rc_flags &= ~RC_WAS_BUFOVFL; 584 rc_scheduled_event--; 585 enable_intr(); 586 printf("rc%d/%d: interrupt-level buffer overflow\n", 587 unit, chan); 588 } 589 if (rc->rc_flags & RC_WAS_SILOVFL) { 590 disable_intr(); 591 rc->rc_flags &= ~RC_WAS_SILOVFL; 592 rc_scheduled_event--; 593 enable_intr(); 594 printf("rc%d/%d: silo overflow\n", 595 unit, chan); 596 } 597 if (rc->rc_flags & RC_MODCHG) { 598 disable_intr(); 599 rc->rc_flags &= ~RC_MODCHG; 600 rc_scheduled_event -= LOTS_OF_EVENTS; 601 enable_intr(); 602 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 603 } 604 if (rc->rc_flags & RC_DORXFER) { 605 disable_intr(); 606 rc->rc_flags &= ~RC_DORXFER; 607 eptr = rc->rc_iptr; 608 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 609 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 610 else 611 tptr = rc->rc_ibuf; 612 icnt = eptr - tptr; 613 if (icnt > 0) { 614 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 615 rc->rc_iptr = rc->rc_ibuf; 616 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 617 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 618 } else { 619 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 620 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 621 rc->rc_hiwat = 622 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 623 } 624 if ( (rc->rc_flags & RC_RTSFLOW) 625 && (tp->t_state & TS_ISOPEN) 626 && !(tp->t_state & TS_TBLOCK) 627 && !(rc->rc_msvr & MSVR_RTS) 628 ) { 629 rcout(CD180_CAR, chan); 630 rcout(CD180_MSVR, 631 rc->rc_msvr |= MSVR_RTS); 632 } 633 rc_scheduled_event -= icnt; 634 } 635 enable_intr(); 636 637 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 638 goto done1; 639 640 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 641 && !(tp->t_state & TS_LOCAL)) { 642 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 643 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 644 && !(tp->t_state & TS_TBLOCK)) 645 ttyblock(tp); 646 tk_nin += icnt; 647 tk_rawcc += icnt; 648 tp->t_rawcc += icnt; 649 if (b_to_q(tptr, icnt, &tp->t_rawq)) 650 printf("rc%d/%d: tty-level buffer overflow\n", 651 unit, chan); 652 ttwakeup(tp); 653 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 654 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 655 tp->t_state &= ~TS_TTSTOP; 656 tp->t_lflag &= ~FLUSHO; 657 rc_start(tp); 658 } 659 } else { 660 for (; tptr < eptr; tptr++) 661 (*linesw[tp->t_line].l_rint) 662 (tptr[0] | 663 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 664 } 665done1: ; 666 } 667 if (rc->rc_flags & RC_DOXXFER) { 668 disable_intr(); 669 rc_scheduled_event -= LOTS_OF_EVENTS; 670 rc->rc_flags &= ~RC_DOXXFER; 671 rc->rc_tp->t_state &= ~TS_BUSY; 672 enable_intr(); 673 (*linesw[tp->t_line].l_start)(tp); 674 } 675 } 676 if (rc_scheduled_event == 0) 677 break; 678 } 679 if (rc_scheduled_event >= LOTS_OF_EVENTS) 680 goto repeat; 681} 682 683static void 684rcstop(tp, rw) 685 register struct tty *tp; 686 int rw; 687{ 688 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 689 u_char *tptr, *eptr; 690 691#ifdef RCDEBUG 692 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 693 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 694#endif 695 if (rw & FWRITE) 696 rc_discard_output(rc); 697 disable_intr(); 698 if (rw & FREAD) { 699 rc->rc_flags &= ~RC_DORXFER; 700 eptr = rc->rc_iptr; 701 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 702 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 703 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 704 } else { 705 tptr = rc->rc_ibuf; 706 rc->rc_iptr = rc->rc_ibuf; 707 } 708 rc_scheduled_event -= eptr - tptr; 709 } 710 if (tp->t_state & TS_TTSTOP) 711 rc->rc_flags |= RC_OSUSP; 712 else 713 rc->rc_flags &= ~RC_OSUSP; 714 enable_intr(); 715} 716 717static int 718rcopen(dev, flag, mode, p) 719 dev_t dev; 720 int flag, mode; 721 struct proc *p; 722{ 723 register struct rc_chans *rc; 724 register struct tty *tp; 725 int unit, nec, s, error = 0; 726 727 unit = GET_UNIT(dev); 728 if (unit >= NRC * CD180_NCHAN) 729 return ENXIO; 730 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 731 return ENXIO; 732 rc = &rc_chans[unit]; 733 tp = rc->rc_tp; 734 nec = rc->rc_rcb->rcb_addr; 735#ifdef RCDEBUG 736 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 737#endif 738 s = spltty(); 739 740again: 741 while (rc->rc_flags & RC_DTR_OFF) { 742 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 743 if (error != 0) 744 goto out; 745 } 746 if (tp->t_state & TS_ISOPEN) { 747 if (CALLOUT(dev)) { 748 if (!(rc->rc_flags & RC_ACTOUT)) { 749 error = EBUSY; 750 goto out; 751 } 752 } else { 753 if (rc->rc_flags & RC_ACTOUT) { 754 if (flag & O_NONBLOCK) { 755 error = EBUSY; 756 goto out; 757 } 758 if (error = tsleep(&rc->rc_rcb, 759 TTIPRI|PCATCH, "rcbi", 0)) 760 goto out; 761 goto again; 762 } 763 } 764 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 765 error = EBUSY; 766 goto out; 767 } 768 } else { 769 tp->t_oproc = rc_start; 770 tp->t_param = rc_param; 771 tp->t_dev = dev; 772 773 if (CALLOUT(dev)) 774 tp->t_cflag |= CLOCAL; 775 else 776 tp->t_cflag &= ~CLOCAL; 777 778 error = rc_param(tp, &tp->t_termios); 779 if (error) 780 goto out; 781 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 782 783 ttsetwater(tp); 784 785 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 786 (*linesw[tp->t_line].l_modem)(tp, 1); 787 } 788 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 789 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 790 rc->rc_dcdwaits++; 791 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 792 rc->rc_dcdwaits--; 793 if (error != 0) 794 goto out; 795 goto again; 796 } 797 error = (*linesw[tp->t_line].l_open)(dev, tp); 798 disc_optim(tp, &tp->t_termios, rc); 799 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 800 rc->rc_flags |= RC_ACTOUT; 801out: 802 (void) splx(s); 803 804 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 805 rc_hardclose(rc); 806 807 return error; 808} 809 810static int 811rcclose(dev, flag, mode, p) 812 dev_t dev; 813 int flag, mode; 814 struct proc *p; 815{ 816 register struct rc_chans *rc; 817 register struct tty *tp; 818 int s, unit = GET_UNIT(dev); 819 820 if (unit >= NRC * CD180_NCHAN) 821 return ENXIO; 822 rc = &rc_chans[unit]; 823 tp = rc->rc_tp; 824#ifdef RCDEBUG 825 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 826#endif 827 s = spltty(); 828 (*linesw[tp->t_line].l_close)(tp, flag); 829 disc_optim(tp, &tp->t_termios, rc); 830 rcstop(tp, FREAD | FWRITE); 831 rc_hardclose(rc); 832 ttyclose(tp); 833 splx(s); 834 return 0; 835} 836 837static void rc_hardclose(rc) 838register struct rc_chans *rc; 839{ 840 register int s, nec = rc->rc_rcb->rcb_addr; 841 register struct tty *tp = rc->rc_tp; 842 843 s = spltty(); 844 rcout(CD180_CAR, rc->rc_chan); 845 846 /* Disable rx/tx intrs */ 847 rcout(CD180_IER, rc->rc_ier = 0); 848 if ( (tp->t_cflag & HUPCL) 849 || !(rc->rc_flags & RC_ACTOUT) 850 && !(rc->rc_msvr & MSVR_CD) 851 && !(tp->t_cflag & CLOCAL) 852 || !(tp->t_state & TS_ISOPEN) 853 ) { 854 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 855 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 856 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 857 if (rc->rc_dtrwait) { 858 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 859 rc->rc_flags |= RC_DTR_OFF; 860 } 861 } 862 rc->rc_flags &= ~RC_ACTOUT; 863 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 864 wakeup(TSA_CARR_ON(tp)); 865 (void) splx(s); 866} 867 868/* Read from line */ 869static int 870rcread(dev, uio, flag) 871 dev_t dev; 872 struct uio *uio; 873 int flag; 874{ 875 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 876 877 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 878} 879 880/* Write to line */ 881static int 882rcwrite(dev, uio, flag) 883 dev_t dev; 884 struct uio *uio; 885 int flag; 886{ 887 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 888 889 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 890} 891 892/* Reset the bastard */ 893static void rc_hwreset(unit, nec, chipid) 894 register int unit, nec; 895 unsigned int chipid; 896{ 897 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 898 DELAY(20000); 899 WAITFORCCR(unit, -1); 900 901 rcout(RC_CTOUT, 0); /* Clear timeout */ 902 rcout(CD180_GIVR, chipid); 903 rcout(CD180_GICR, 0); 904 905 /* Set Prescaler Registers (1 msec) */ 906 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 907 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 908 909 /* Initialize Priority Interrupt Level Registers */ 910 rcout(CD180_PILR1, RC_PILR_MODEM); 911 rcout(CD180_PILR2, RC_PILR_TX); 912 rcout(CD180_PILR3, RC_PILR_RX); 913 914 /* Reset DTR */ 915 rcout(RC_DTREG, ~0); 916} 917 918/* Set channel parameters */ 919static int rc_param(tp, ts) 920 register struct tty *tp; 921 struct termios *ts; 922{ 923 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 924 register int nec = rc->rc_rcb->rcb_addr; 925 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 926 927 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 928 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 929 ) 930 return (EINVAL); 931 if (ts->c_ispeed == 0) 932 ts->c_ispeed = ts->c_ospeed; 933 odivs = RC_BRD(ts->c_ospeed); 934 idivs = RC_BRD(ts->c_ispeed); 935 936 s = spltty(); 937 938 /* Select channel */ 939 rcout(CD180_CAR, rc->rc_chan); 940 941 /* If speed == 0, hangup line */ 942 if (ts->c_ospeed == 0) { 943 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 944 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 945 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 946 } 947 948 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 949 cflag = ts->c_cflag; 950 iflag = ts->c_iflag; 951 lflag = ts->c_lflag; 952 953 if (idivs > 0) { 954 rcout(CD180_RBPRL, idivs & 0xFF); 955 rcout(CD180_RBPRH, idivs >> 8); 956 } 957 if (odivs > 0) { 958 rcout(CD180_TBPRL, odivs & 0xFF); 959 rcout(CD180_TBPRH, odivs >> 8); 960 } 961 962 /* set timeout value */ 963 if (ts->c_ispeed > 0) { 964 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 965 966 if ( !(lflag & ICANON) 967 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 968 && ts->c_cc[VTIME] * 10 > itm) 969 itm = ts->c_cc[VTIME] * 10; 970 971 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 972 } 973 974 switch (cflag & CSIZE) { 975 case CS5: val = COR1_5BITS; break; 976 case CS6: val = COR1_6BITS; break; 977 case CS7: val = COR1_7BITS; break; 978 default: 979 case CS8: val = COR1_8BITS; break; 980 } 981 if (cflag & PARENB) { 982 val |= COR1_NORMPAR; 983 if (cflag & PARODD) 984 val |= COR1_ODDP; 985 if (!(cflag & INPCK)) 986 val |= COR1_Ignore; 987 } else 988 val |= COR1_Ignore; 989 if (cflag & CSTOPB) 990 val |= COR1_2SB; 991 rcout(CD180_COR1, val); 992 993 /* Set FIFO threshold */ 994 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 995 inpflow = 0; 996 if ( (iflag & IXOFF) 997 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 998 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 999 || (iflag & IXANY) 1000 ) 1001 ) 1002 ) { 1003 inpflow = 1; 1004 val |= COR3_SCDE|COR3_FCT; 1005 } 1006 rcout(CD180_COR3, val); 1007 1008 /* Initialize on-chip automatic flow control */ 1009 val = 0; 1010 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1011 if (cflag & CCTS_OFLOW) { 1012 rc->rc_flags |= RC_CTSFLOW; 1013 val |= COR2_CtsAE; 1014 } else 1015 rc->rc_flags |= RC_SEND_RDY; 1016 if (tp->t_state & TS_TTSTOP) 1017 rc->rc_flags |= RC_OSUSP; 1018 else 1019 rc->rc_flags &= ~RC_OSUSP; 1020 if (cflag & CRTS_IFLOW) 1021 rc->rc_flags |= RC_RTSFLOW; 1022 else 1023 rc->rc_flags &= ~RC_RTSFLOW; 1024 1025 if (inpflow) { 1026 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1027 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1028 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1029 val |= COR2_TxIBE; 1030 if (iflag & IXANY) 1031 val |= COR2_IXM; 1032 } 1033 1034 rcout(CD180_COR2, rc->rc_cor2 = val); 1035 1036 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1037 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1038 1039 disc_optim(tp, ts, rc); 1040 1041 /* modem ctl */ 1042 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1043 if (cflag & CCTS_OFLOW) 1044 val |= MCOR1_CTSzd; 1045 rcout(CD180_MCOR1, val); 1046 1047 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1048 if (cflag & CCTS_OFLOW) 1049 val |= MCOR2_CTSod; 1050 rcout(CD180_MCOR2, val); 1051 1052 /* enable i/o and interrupts */ 1053 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1054 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1055 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1056 1057 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1058 if (cflag & CCTS_OFLOW) 1059 rc->rc_ier |= IER_CTS; 1060 if (cflag & CREAD) 1061 rc->rc_ier |= IER_RxData; 1062 if (tp->t_state & TS_BUSY) 1063 rc->rc_ier |= IER_TxRdy; 1064 if (ts->c_ospeed != 0) 1065 rc_modctl(rc, TIOCM_DTR, DMBIS); 1066 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1067 rc->rc_flags |= RC_SEND_RDY; 1068 rcout(CD180_IER, rc->rc_ier); 1069 (void) splx(s); 1070 return 0; 1071} 1072 1073/* Re-initialize board after bogus interrupts */ 1074static void rc_reinit(rcb) 1075struct rc_softc *rcb; 1076{ 1077 register struct rc_chans *rc, *rce; 1078 register int nec; 1079 1080 nec = rcb->rcb_addr; 1081 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1082 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1083 rce = rc + CD180_NCHAN; 1084 for (; rc < rce; rc++) 1085 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1086} 1087 1088static int 1089rcioctl(dev, cmd, data, flag, p) 1090dev_t dev; 1091int cmd, flag; 1092caddr_t data; 1093struct proc *p; 1094{ 1095 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1096 register int s, error; 1097 struct tty *tp = rc->rc_tp; 1098 1099 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1100 if (error >= 0) 1101 return (error); 1102 error = ttioctl(tp, cmd, data, flag); 1103 disc_optim(tp, &tp->t_termios, rc); 1104 if (error >= 0) 1105 return (error); 1106 s = spltty(); 1107 1108 switch (cmd) { 1109 case TIOCSBRK: 1110 rc->rc_pendcmd = CD180_C_SBRK; 1111 break; 1112 1113 case TIOCCBRK: 1114 rc->rc_pendcmd = CD180_C_EBRK; 1115 break; 1116 1117 case TIOCSDTR: 1118 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1119 break; 1120 1121 case TIOCCDTR: 1122 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1123 break; 1124 1125 case TIOCMGET: 1126 *(int *) data = rc_modctl(rc, 0, DMGET); 1127 break; 1128 1129 case TIOCMSET: 1130 (void) rc_modctl(rc, *(int *) data, DMSET); 1131 break; 1132 1133 case TIOCMBIC: 1134 (void) rc_modctl(rc, *(int *) data, DMBIC); 1135 break; 1136 1137 case TIOCMBIS: 1138 (void) rc_modctl(rc, *(int *) data, DMBIS); 1139 break; 1140 1141 case TIOCMSDTRWAIT: 1142 error = suser(p->p_ucred, &p->p_acflag); 1143 if (error != 0) { 1144 splx(s); 1145 return (error); 1146 } 1147 rc->rc_dtrwait = *(int *)data * hz / 100; 1148 break; 1149 1150 case TIOCMGDTRWAIT: 1151 *(int *)data = rc->rc_dtrwait * 100 / hz; 1152 break; 1153 1154 default: 1155 (void) splx(s); 1156 return ENOTTY; 1157 } 1158 (void) splx(s); 1159 return 0; 1160} 1161 1162 1163/* Modem control routines */ 1164 1165static int rc_modctl(rc, bits, cmd) 1166register struct rc_chans *rc; 1167int bits, cmd; 1168{ 1169 register int nec = rc->rc_rcb->rcb_addr; 1170 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1171 1172 rcout(CD180_CAR, rc->rc_chan); 1173 1174 switch (cmd) { 1175 case DMSET: 1176 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1177 ~(*dtr |= 1 << rc->rc_chan) : 1178 ~(*dtr &= ~(1 << rc->rc_chan))); 1179 msvr = rcin(CD180_MSVR); 1180 if (bits & TIOCM_RTS) 1181 msvr |= MSVR_RTS; 1182 else 1183 msvr &= ~MSVR_RTS; 1184 if (bits & TIOCM_DTR) 1185 msvr |= MSVR_DTR; 1186 else 1187 msvr &= ~MSVR_DTR; 1188 rcout(CD180_MSVR, msvr); 1189 break; 1190 1191 case DMBIS: 1192 if (bits & TIOCM_DTR) 1193 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1194 msvr = rcin(CD180_MSVR); 1195 if (bits & TIOCM_RTS) 1196 msvr |= MSVR_RTS; 1197 if (bits & TIOCM_DTR) 1198 msvr |= MSVR_DTR; 1199 rcout(CD180_MSVR, msvr); 1200 break; 1201 1202 case DMGET: 1203 bits = TIOCM_LE; 1204 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1205 1206 if (msvr & MSVR_RTS) 1207 bits |= TIOCM_RTS; 1208 if (msvr & MSVR_CTS) 1209 bits |= TIOCM_CTS; 1210 if (msvr & MSVR_DSR) 1211 bits |= TIOCM_DSR; 1212 if (msvr & MSVR_DTR) 1213 bits |= TIOCM_DTR; 1214 if (msvr & MSVR_CD) 1215 bits |= TIOCM_CD; 1216 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1217 bits |= TIOCM_RI; 1218 return bits; 1219 1220 case DMBIC: 1221 if (bits & TIOCM_DTR) 1222 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1223 msvr = rcin(CD180_MSVR); 1224 if (bits & TIOCM_RTS) 1225 msvr &= ~MSVR_RTS; 1226 if (bits & TIOCM_DTR) 1227 msvr &= ~MSVR_DTR; 1228 rcout(CD180_MSVR, msvr); 1229 break; 1230 } 1231 rc->rc_msvr = rcin(CD180_MSVR); 1232 return 0; 1233} 1234 1235/* Test the board. */ 1236int rc_test(nec, unit) 1237 register int nec; 1238 int unit; 1239{ 1240 int chan = 0; 1241 int i = 0, rcnt, old_level; 1242 unsigned int iack, chipid; 1243 unsigned short divs; 1244 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1245#define CTLEN 8 1246#define ERR(s) { \ 1247 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1248 (void) splx(old_level); return 1; } 1249 1250 struct rtest { 1251 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1252 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1253 int rxptr; /* RX pointer */ 1254 int txptr; /* TX pointer */ 1255 } tchans[CD180_NCHAN]; 1256 1257 old_level = spltty(); 1258 1259 chipid = RC_FAKEID; 1260 1261 /* First, reset board to inital state */ 1262 rc_hwreset(unit, nec, chipid); 1263 1264 divs = RC_BRD(19200); 1265 1266 /* Initialize channels */ 1267 for (chan = 0; chan < CD180_NCHAN; chan++) { 1268 1269 /* Select and reset channel */ 1270 rcout(CD180_CAR, chan); 1271 CCRCMD(unit, chan, CCR_ResetChan); 1272 WAITFORCCR(unit, chan); 1273 1274 /* Set speed */ 1275 rcout(CD180_RBPRL, divs & 0xFF); 1276 rcout(CD180_RBPRH, divs >> 8); 1277 rcout(CD180_TBPRL, divs & 0xFF); 1278 rcout(CD180_TBPRH, divs >> 8); 1279 1280 /* set timeout value */ 1281 rcout(CD180_RTPR, 0); 1282 1283 /* Establish local loopback */ 1284 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1285 rcout(CD180_COR2, COR2_LLM); 1286 rcout(CD180_COR3, CD180_NFIFO); 1287 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1288 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1289 WAITFORCCR(unit, chan); 1290 rcout(CD180_MSVR, MSVR_RTS); 1291 1292 /* Fill TXBUF with test data */ 1293 for (i = 0; i < CD180_NFIFO; i++) { 1294 tchans[chan].txbuf[i] = ctest[i]; 1295 tchans[chan].rxbuf[i] = 0; 1296 } 1297 tchans[chan].txptr = tchans[chan].rxptr = 0; 1298 1299 /* Now, start transmit */ 1300 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1301 } 1302 /* Pseudo-interrupt poll stuff */ 1303 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1304 i = ~(rcin(RC_BSR)); 1305 if (i & RC_BSR_TOUT) 1306 ERR(("BSR timeout bit set\n")) 1307 else if (i & RC_BSR_TXINT) { 1308 iack = rcin(RC_PILR_TX); 1309 if (iack != (GIVR_IT_TDI | chipid)) 1310 ERR(("Bad TX intr ack (%02x != %02x)\n", 1311 iack, GIVR_IT_TDI | chipid)); 1312 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1313 /* If no more data to transmit, disable TX intr */ 1314 if (tchans[chan].txptr >= CD180_NFIFO) { 1315 iack = rcin(CD180_IER); 1316 rcout(CD180_IER, iack & ~IER_TxMpty); 1317 } else { 1318 for (iack = tchans[chan].txptr; 1319 iack < CD180_NFIFO; iack++) 1320 rcout(CD180_TDR, 1321 tchans[chan].txbuf[iack]); 1322 tchans[chan].txptr = iack; 1323 } 1324 rcout(CD180_EOIR, 0); 1325 } else if (i & RC_BSR_RXINT) { 1326 u_char ucnt; 1327 1328 iack = rcin(RC_PILR_RX); 1329 if (iack != (GIVR_IT_RGDI | chipid) && 1330 iack != (GIVR_IT_REI | chipid)) 1331 ERR(("Bad RX intr ack (%02x != %02x)\n", 1332 iack, GIVR_IT_RGDI | chipid)) 1333 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1334 ucnt = rcin(CD180_RDCR) & 0xF; 1335 while (ucnt-- > 0) { 1336 iack = rcin(CD180_RCSR); 1337 if (iack & RCSR_Timeout) 1338 break; 1339 if (iack & 0xF) 1340 ERR(("Bad char chan %d (RCSR = %02X)\n", 1341 chan, iack)) 1342 if (tchans[chan].rxptr > CD180_NFIFO) 1343 ERR(("Got extra chars chan %d\n", 1344 chan)) 1345 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1346 rcin(CD180_RDR); 1347 } 1348 rcout(CD180_EOIR, 0); 1349 } 1350 rcout(RC_CTOUT, 0); 1351 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1352 if (tchans[chan].rxptr >= CD180_NFIFO) 1353 iack++; 1354 if (iack == CD180_NCHAN) 1355 break; 1356 } 1357 for (chan = 0; chan < CD180_NCHAN; chan++) { 1358 /* Select and reset channel */ 1359 rcout(CD180_CAR, chan); 1360 CCRCMD(unit, chan, CCR_ResetChan); 1361 } 1362 1363 if (!rcnt) 1364 ERR(("looses characters during local loopback\n")) 1365 /* Now, check data */ 1366 for (chan = 0; chan < CD180_NCHAN; chan++) 1367 for (i = 0; i < CD180_NFIFO; i++) 1368 if (ctest[i] != tchans[chan].rxbuf[i]) 1369 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1370 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1371 (void) splx(old_level); 1372 return 0; 1373} 1374 1375#ifdef RCDEBUG 1376static void printrcflags(rc, comment) 1377struct rc_chans *rc; 1378char *comment; 1379{ 1380 u_short f = rc->rc_flags; 1381 register int nec = rc->rc_rcb->rcb_addr; 1382 1383 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1384 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1385 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1386 (f & RC_ACTOUT) ?"ACTOUT " :"", 1387 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1388 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1389 (f & RC_DORXFER)?"DORXFER " :"", 1390 (f & RC_DOXXFER)?"DOXXFER " :"", 1391 (f & RC_MODCHG) ?"MODCHG " :"", 1392 (f & RC_OSUSP) ?"OSUSP " :"", 1393 (f & RC_OSBUSY) ?"OSBUSY " :"", 1394 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1395 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1396 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1397 1398 rcout(CD180_CAR, rc->rc_chan); 1399 1400 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1401 rc->rc_rcb->rcb_unit, rc->rc_chan, 1402 rcin(CD180_MSVR), 1403 rcin(CD180_IER), 1404 rcin(CD180_CCSR)); 1405} 1406#endif /* RCDEBUG */ 1407 1408static struct tty * 1409rcdevtotty(dev) 1410 dev_t dev; 1411{ 1412 int unit; 1413 1414 unit = GET_UNIT(dev); 1415 if (unit >= NRC * CD180_NCHAN) 1416 return NULL; 1417 return (&rc_tty[unit]); 1418} 1419 1420static void 1421rc_dtrwakeup(chan) 1422 void *chan; 1423{ 1424 struct rc_chans *rc; 1425 1426 rc = (struct rc_chans *)chan; 1427 rc->rc_flags &= ~RC_DTR_OFF; 1428 wakeup(&rc->rc_dtrwait); 1429} 1430 1431static void 1432rc_discard_output(rc) 1433 struct rc_chans *rc; 1434{ 1435 disable_intr(); 1436 if (rc->rc_flags & RC_DOXXFER) { 1437 rc_scheduled_event -= LOTS_OF_EVENTS; 1438 rc->rc_flags &= ~RC_DOXXFER; 1439 } 1440 rc->rc_optr = rc->rc_obufend; 1441 rc->rc_tp->t_state &= ~TS_BUSY; 1442 enable_intr(); 1443 ttwwakeup(rc->rc_tp); 1444} 1445 1446static void 1447rc_wakeup(chan) 1448 void *chan; 1449{ 1450 timeout(rc_wakeup, (caddr_t)NULL, 1); 1451 1452 if (rc_scheduled_event != 0) { 1453 int s; 1454 1455 s = splsofttty(); 1456 rcpoll(); 1457 splx(s); 1458 } 1459} 1460 1461static void 1462disc_optim(tp, t, rc) 1463 struct tty *tp; 1464 struct termios *t; 1465 struct rc_chans *rc; 1466{ 1467 1468 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1469 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1470 && (!(t->c_iflag & PARMRK) 1471 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1472 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1473 && linesw[tp->t_line].l_rint == ttyinput) 1474 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1475 else 1476 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1477 if (tp->t_line == SLIPDISC) 1478 rc->rc_hotchar = 0xc0; 1479 else if (tp->t_line == PPPDISC) 1480 rc->rc_hotchar = 0x7e; 1481 else 1482 rc->rc_hotchar = 0; 1483} 1484 1485static void 1486rc_wait0(nec, unit, chan, line) 1487 int nec, unit, chan, line; 1488{ 1489 int rcnt; 1490 1491 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1492 DELAY(30); 1493 if (rcnt == 0) 1494 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1495 unit, chan, line); 1496} 1497 1498static rc_devsw_installed = 0; 1499 1500static void rc_drvinit(void *unused) 1501{ 1502 dev_t dev; 1503 1504 if( ! rc_devsw_installed ) { 1505 dev = makedev(CDEV_MAJOR, 0); 1506 cdevsw_add(&dev,&rc_cdevsw, NULL); 1507 rc_devsw_installed = 1; 1508 } 1509} 1510 1511SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1512 1513 1514#endif /* NRC */ 1515