rc.c revision 19123
167754Smsmith/* 267754Smsmith * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 367754Smsmith * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 467754Smsmith * All rights reserved. 567754Smsmith * 667754Smsmith * Redistribution and use in source and binary forms, with or without 767754Smsmith * modification, are permitted provided that the following conditions 867754Smsmith * are met: 967754Smsmith * 1. Redistributions of source code must retain the above copyright 1067754Smsmith * notice, this list of conditions and the following disclaimer. 1167754Smsmith * 2. Redistributions in binary form must reproduce the above copyright 12193267Sjkim * notice, this list of conditions and the following disclaimer in the 1370243Smsmith * documentation and/or other materials provided with the distribution. 1467754Smsmith * 1567754Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 1667754Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1767754Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1867754Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 1967754Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2067754Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2167754Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2267754Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2367754Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2467754Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2567754Smsmith * SUCH DAMAGE. 2667754Smsmith */ 2767754Smsmith 2867754Smsmith/* 2967754Smsmith * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 3067754Smsmith * 3167754Smsmith */ 3267754Smsmith 3367754Smsmith#include "opt_comconsole.h" 3467754Smsmith#include "rc.h" 3567754Smsmith 3667754Smsmith#if NRC > 0 3767754Smsmith 3867754Smsmith/*#define RCDEBUG*/ 3967754Smsmith 4067754Smsmith#include <sys/param.h> 4167754Smsmith#include <sys/systm.h> 4267754Smsmith#include <sys/ioctl.h> 4367754Smsmith#include <sys/tty.h> 4467754Smsmith#include <sys/proc.h> 4567754Smsmith#include <sys/conf.h> 4667754Smsmith#include <sys/dkstat.h> 4767754Smsmith#include <sys/file.h> 4867754Smsmith#include <sys/uio.h> 4967754Smsmith#include <sys/kernel.h> 5067754Smsmith#include <sys/syslog.h> 5167754Smsmith#ifdef DEVFS 5267754Smsmith#include <sys/devfsext.h> 5367754Smsmith#endif /*DEVFS*/ 5467754Smsmith 5567754Smsmith#include <machine/clock.h> 5667754Smsmith 5767754Smsmith#include <i386/isa/isa_device.h> 5867754Smsmith#include <i386/isa/sioreg.h> 5967754Smsmith 6067754Smsmith#include <i386/isa/ic/cd180.h> 6167754Smsmith#include <i386/isa/rcreg.h> 6267754Smsmith 6367754Smsmith 6467754Smsmith/* Prototypes */ 6567754Smsmithstatic int rcprobe __P((struct isa_device *)); 6667754Smsmithstatic int rcattach __P((struct isa_device *)); 6767754Smsmith 6867754Smsmith/*- 6967754Smsmith * This space intentionally left blank to stop __LINE__ from screwing up 7067754Smsmith * regression tests :-(. 7167754Smsmith * 7267754Smsmith * 7367754Smsmith * 7467754Smsmith */ 7567754Smsmithvoid rcpoll __P((void)); 7667754Smsmith 7767754Smsmith#define rcin(port) RC_IN (nec, port) 7867754Smsmith#define rcout(port,v) RC_OUT (nec, port, v) 7967754Smsmith 8067754Smsmith#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 8167754Smsmith#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 8267754Smsmith 8367754Smsmith#define RC_IBUFSIZE 256 8467754Smsmith#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 8567754Smsmith#define RC_OBUFSIZE 512 8667754Smsmith#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 8767754Smsmith#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 8867754Smsmith#define LOTS_OF_EVENTS 64 8967754Smsmith 9067754Smsmith#define RC_FAKEID 0x10 9167754Smsmith 9267754Smsmith#define RC_PROBED 1 9367754Smsmith#define RC_ATTACHED 2 9467754Smsmith 9567754Smsmith#define GET_UNIT(dev) (minor(dev) & 0x3F) 9667754Smsmith#define CALLOUT(dev) (minor(dev) & 0x80) 9767754Smsmith 9867754Smsmith/* For isa routines */ 9967754Smsmithstruct isa_driver rcdriver = { 10067754Smsmith rcprobe, rcattach, "rc" 10167754Smsmith}; 10267754Smsmith 10367754Smsmithstatic d_open_t rcopen; 10467754Smsmithstatic d_close_t rcclose; 10567754Smsmithstatic d_read_t rcread; 10667754Smsmithstatic d_write_t rcwrite; 10767754Smsmithstatic d_ioctl_t rcioctl; 10867754Smsmithstatic d_stop_t rcstop; 10967754Smsmithstatic d_devtotty_t rcdevtotty; 11067754Smsmith 11167754Smsmith#define CDEV_MAJOR 63 11267754Smsmithstatic struct cdevsw rc_cdevsw = 11367754Smsmith { rcopen, rcclose, rcread, rcwrite, /*63*/ 11467754Smsmith rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 11567754Smsmith ttselect, nommap, NULL, "rc", NULL, -1 }; 11667754Smsmith 11767754Smsmith/* Per-board structure */ 11867754Smsmithstatic struct rc_softc { 119193251Sjkim u_int rcb_probed; /* 1 - probed, 2 - attached */ 120193267Sjkim u_int rcb_addr; /* Base I/O addr */ 121193251Sjkim u_int rcb_unit; /* unit # */ 122193267Sjkim u_char rcb_dtr; /* DTR status */ 123193267Sjkim struct rc_chans *rcb_baserc; /* base rc ptr */ 12467754Smsmith} rc_softc[NRC]; 12567754Smsmith 12677424Smsmith/* Per-channel structure */ 12791116Smsmithstatic struct rc_chans { 12867754Smsmith struct rc_softc *rc_rcb; /* back ptr */ 12967754Smsmith u_short rc_flags; /* Misc. flags */ 130117521Snjl int rc_chan; /* Channel # */ 13167754Smsmith u_char rc_ier; /* intr. enable reg */ 13267754Smsmith u_char rc_msvr; /* modem sig. status */ 13367754Smsmith u_char rc_cor2; /* options reg */ 13467754Smsmith u_char rc_pendcmd; /* special cmd pending */ 135151937Sjkim u_int rc_dtrwait; /* dtr timeout */ 136151937Sjkim u_int rc_dcdwaits; /* how many waits DCD in open */ 137151937Sjkim u_char rc_hotchar; /* end packed optimize */ 13867754Smsmith struct tty *rc_tp; /* tty struct */ 13967754Smsmith u_char *rc_iptr; /* Chars input buffer */ 14067754Smsmith u_char *rc_hiwat; /* hi-water mark */ 14167754Smsmith u_char *rc_bufend; /* end of buffer */ 14267754Smsmith u_char *rc_optr; /* ptr in output buf */ 14367754Smsmith u_char *rc_obufend; /* end of output buf */ 14467754Smsmith u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 14567754Smsmith u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 14667754Smsmith#ifdef DEVFS 14767754Smsmith void *devfs_token; 14867754Smsmith#endif 14967754Smsmith} rc_chans[NRC * CD180_NCHAN]; 15067754Smsmith 15167754Smsmithstatic int rc_scheduled_event = 0; 15267754Smsmith 15367754Smsmith/* for pstat -t */ 15467754Smsmithstatic struct tty rc_tty[NRC * CD180_NCHAN]; 15569450Smsmithstatic const int nrc_tty = NRC * CD180_NCHAN; 15667754Smsmith 15767754Smsmith/* Flags */ 15867754Smsmith#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 15991116Smsmith#define RC_ACTOUT 0x0002 /* Dial-out port active */ 16083174Smsmith#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 16183174Smsmith#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 16277424Smsmith#define RC_DORXFER 0x0010 /* RXFER event planned */ 16377424Smsmith#define RC_DOXXFER 0x0020 /* XXFER event planned */ 16467754Smsmith#define RC_MODCHG 0x0040 /* Modem status changed */ 16567754Smsmith#define RC_OSUSP 0x0080 /* Output suspended */ 16667754Smsmith#define RC_OSBUSY 0x0100 /* start() routine in progress */ 16767754Smsmith#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 16867754Smsmith#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 16969746Smsmith#define RC_SEND_RDY 0x0800 /* ready to send */ 17069746Smsmith 17167754Smsmith/* Table for translation of RCSR status bits to internal form */ 17267754Smsmithstatic int rc_rcsrt[16] = { 17385756Smsmith 0, TTY_OE, TTY_FE, 17469450Smsmith TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 17567754Smsmith TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 17667754Smsmith TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 17767754Smsmith TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 178167802Sjkim TTY_BI|TTY_PE|TTY_FE|TTY_OE 17967754Smsmith}; 180167802Sjkim 181167802Sjkim/* Static prototypes */ 182167802Sjkimstatic void rc_hwreset __P((int, int, unsigned int)); 183167802Sjkimstatic int rc_test __P((int, int)); 184167802Sjkimstatic void rc_discard_output __P((struct rc_chans *)); 185167802Sjkimstatic void rc_hardclose __P((struct rc_chans *)); 186167802Sjkimstatic int rc_modctl __P((struct rc_chans *, int, int)); 187167802Sjkimstatic void rc_start __P((struct tty *)); 188167802Sjkimstatic int rc_param __P((struct tty *, struct termios *)); 189167802Sjkimstatic void rc_reinit __P((struct rc_softc *)); 190167802Sjkim#ifdef RCDEBUG 191167802Sjkimstatic void printrcflags(); 192167802Sjkim#endif 193167802Sjkimstatic timeout_t rc_dtrwakeup; 19491116Smsmithstatic timeout_t rc_wakeup; 195167802Sjkimstatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 196167802Sjkimstatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 19791116Smsmith 19867754Smsmith/**********************************************/ 199167802Sjkim 200167802Sjkim/* Quick device probing */ 201167802Sjkimstatic int 20267754Smsmithrcprobe(dvp) 203167802Sjkim struct isa_device *dvp; 20467754Smsmith{ 20567754Smsmith int irq = ffs(dvp->id_irq) - 1; 206167802Sjkim register int nec = dvp->id_iobase; 20767754Smsmith 208167802Sjkim if (dvp->id_unit > NRC) 20969746Smsmith return 0; 21067754Smsmith if (!RC_VALIDADDR(nec)) { 21167754Smsmith printf("rc%d: illegal base address %x\n", nec); 21267754Smsmith return 0; 21367754Smsmith } 21467754Smsmith if (!RC_VALIDIRQ(irq)) { 21567754Smsmith printf("rc%d: illegal IRQ value %d\n", irq); 21667754Smsmith return 0; 217167802Sjkim } 21867754Smsmith rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 219167802Sjkim rcout(CD180_PPRH, 0x11); 220117521Snjl if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 22167754Smsmith return 0; 22283174Smsmith /* Now, test the board more thoroughly, with diagnostic */ 22367754Smsmith if (rc_test(nec, dvp->id_unit)) 22467754Smsmith return 0; 22567754Smsmith rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 22691116Smsmith 22767754Smsmith return 0xF; 22867754Smsmith} 22967754Smsmith 23067754Smsmithstatic int 23167754Smsmithrcattach(dvp) 23267754Smsmith struct isa_device *dvp; 23367754Smsmith{ 23467754Smsmith register int chan, nec = dvp->id_iobase; 23567754Smsmith struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 23667754Smsmith struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 23767754Smsmith static int rc_wakeup_started = 0; 23867754Smsmith struct tty *tp; 23967754Smsmith 24091116Smsmith /* Thorooughly test the device */ 24167754Smsmith if (rcb->rcb_probed != RC_PROBED) 24267754Smsmith return 0; 24367754Smsmith rcb->rcb_addr = nec; 24467754Smsmith rcb->rcb_dtr = 0; 24567754Smsmith rcb->rcb_baserc = rc; 24691116Smsmith /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 24767754Smsmith printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 24891116Smsmith CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 24967754Smsmith 25067754Smsmith for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 25167754Smsmith rc->rc_rcb = rcb; 25267754Smsmith rc->rc_chan = chan; 25391116Smsmith rc->rc_iptr = rc->rc_ibuf; 25491116Smsmith rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 25567754Smsmith rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 25691116Smsmith rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 25767754Smsmith rc->rc_cor2 = rc->rc_pendcmd = 0; 25867754Smsmith rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 25967754Smsmith rc->rc_dtrwait = 3 * hz; 26067754Smsmith rc->rc_dcdwaits= 0; 26167754Smsmith rc->rc_hotchar = 0; 26267754Smsmith tp = rc->rc_tp = &rc_tty[chan]; 26391116Smsmith ttychars(tp); 26467754Smsmith tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 26567754Smsmith tp->t_cflag = TTYDEF_CFLAG; 26667754Smsmith tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 26767754Smsmith#ifdef DEVFS 26867754Smsmith/* FIX THIS to reflect real devices */ 26991116Smsmith rc->devfs_token = 27067754Smsmith devfs_add_devswf(&rc_cdevsw, 27191116Smsmith (dvp->id_unit * CD180_NCHAN) + chan, 27291116Smsmith DV_CHR, 0, 0, 0600, "rc%d.%d", 27391116Smsmith dvp->id_unit, chan); 27491116Smsmith#endif 27591116Smsmith } 27691116Smsmith rcb->rcb_probed = RC_ATTACHED; 27785756Smsmith if (!rc_wakeup_started) { 27867754Smsmith rc_wakeup((void *)NULL); 27967754Smsmith rc_wakeup_started = 0; 28067754Smsmith } 28167754Smsmith return 1; 28267754Smsmith} 28367754Smsmith 28491116Smsmith/* RC interrupt handling */ 28567754Smsmithvoid rcintr(unit) 286114237Snjl int unit; 28791116Smsmith{ 28867754Smsmith register struct rc_softc *rcb = &rc_softc[unit]; 28967754Smsmith register struct rc_chans *rc; 29067754Smsmith register int nec, resid; 29167754Smsmith register u_char val, iack, bsr, ucnt, *optr; 29267754Smsmith int good_data, t_state; 29367754Smsmith 294123315Snjl if (rcb->rcb_probed != RC_ATTACHED) { 29567754Smsmith printf("rc%d: bogus interrupt\n", unit); 296114237Snjl return; 29767754Smsmith } 29867754Smsmith nec = rcb->rcb_addr; 29967754Smsmith 30067754Smsmith bsr = ~(rcin(RC_BSR)); 30167754Smsmith 30291116Smsmith if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 30367754Smsmith printf("rc%d: extra interrupt\n", unit); 30467754Smsmith rcout(CD180_EOIR, 0); 30567754Smsmith return; 306167802Sjkim } 30767754Smsmith 308167802Sjkim while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 309117521Snjl#ifdef RCDEBUG_DETAILED 31067754Smsmith printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 31167754Smsmith (bsr & RC_BSR_TOUT)?"TOUT ":"", 31267754Smsmith (bsr & RC_BSR_RXINT)?"RXINT ":"", 31367754Smsmith (bsr & RC_BSR_TXINT)?"TXINT ":"", 314151937Sjkim (bsr & RC_BSR_MOINT)?"MOINT":""); 31567754Smsmith#endif 31667754Smsmith if (bsr & RC_BSR_TOUT) { 31767754Smsmith printf("rc%d: hardware failure, reset board\n", unit); 31867754Smsmith rcout(RC_CTOUT, 0); 31967754Smsmith rc_reinit(rcb); 32067754Smsmith return; 32167754Smsmith } 32267754Smsmith if (bsr & RC_BSR_RXINT) { 32367754Smsmith iack = rcin(RC_PILR_RX); 32467754Smsmith good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 32567754Smsmith if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 32667754Smsmith printf("rc%d: fake rxint: %02x\n", unit, iack); 327117521Snjl goto more_intrs; 32867754Smsmith } 32967754Smsmith rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 33067754Smsmith t_state = rc->rc_tp->t_state; 331151937Sjkim /* Do RTS flow control stuff */ 332117521Snjl if ( (rc->rc_flags & RC_RTSFLOW) 333117521Snjl || !(t_state & TS_ISOPEN) 334117521Snjl ) { 33567754Smsmith if ( ( !(t_state & TS_ISOPEN) 33667754Smsmith || (t_state & TS_TBLOCK) 33767754Smsmith ) 33867754Smsmith && (rc->rc_msvr & MSVR_RTS) 339117521Snjl ) 34067754Smsmith rcout(CD180_MSVR, 34167754Smsmith rc->rc_msvr &= ~MSVR_RTS); 34267754Smsmith else if (!(rc->rc_msvr & MSVR_RTS)) 34367754Smsmith rcout(CD180_MSVR, 344117521Snjl rc->rc_msvr |= MSVR_RTS); 345117521Snjl } 346117521Snjl ucnt = rcin(CD180_RDCR) & 0xF; 347117521Snjl resid = 0; 348117521Snjl 349117521Snjl if (t_state & TS_ISOPEN) { 350167802Sjkim /* check for input buffer overflow */ 351151937Sjkim if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 352151937Sjkim resid = ucnt; 353151937Sjkim ucnt = rc->rc_bufend - rc->rc_iptr; 354151937Sjkim resid -= ucnt; 355151937Sjkim if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 35691116Smsmith rc->rc_flags |= RC_WAS_BUFOVFL; 35791116Smsmith rc_scheduled_event++; 35891116Smsmith } 359151937Sjkim } 36091116Smsmith optr = rc->rc_iptr; 36167754Smsmith /* check foor good data */ 36285756Smsmith if (good_data) { 36367754Smsmith while (ucnt-- > 0) { 36467754Smsmith val = rcin(CD180_RDR); 36591116Smsmith optr[0] = val; 366193267Sjkim optr[INPUT_FLAGS_SHIFT] = 0; 367151937Sjkim optr++; 36867754Smsmith rc_scheduled_event++; 36967754Smsmith if (val != 0 && val == rc->rc_hotchar) 370117521Snjl setsofttty(); 37167754Smsmith } 372117521Snjl } else { 373117521Snjl /* Store also status data */ 374151937Sjkim while (ucnt-- > 0) { 375151937Sjkim iack = rcin(CD180_RCSR); 376151937Sjkim if (iack & RCSR_Timeout) 377117521Snjl break; 378193267Sjkim if ( (iack & RCSR_OE) 379193267Sjkim && !(rc->rc_flags & RC_WAS_SILOVFL)) { 380193267Sjkim rc->rc_flags |= RC_WAS_SILOVFL; 381193267Sjkim rc_scheduled_event++; 382193267Sjkim } 38391116Smsmith val = rcin(CD180_RDR); 38491116Smsmith /* 38591116Smsmith Don't store PE if IGNPAR and BREAK if IGNBRK, 386151937Sjkim this hack allows "raw" tty optimization 38791116Smsmith works even if IGN* is set. 38867754Smsmith */ 389117521Snjl if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 390117521Snjl || (!(iack & (RCSR_PE|RCSR_FE)) 391151937Sjkim || !(rc->rc_tp->t_iflag & IGNPAR)) 39267754Smsmith && (!(iack & RCSR_Break) 393117521Snjl || !(rc->rc_tp->t_iflag & IGNBRK))) { 394117521Snjl if ( (iack & (RCSR_PE|RCSR_FE)) 395129684Snjl && (t_state & TS_CAN_BYPASS_L_RINT) 396123315Snjl && ((iack & RCSR_FE) 397117521Snjl || (iack & RCSR_PE) 398151937Sjkim && (rc->rc_tp->t_iflag & INPCK))) 399117521Snjl val = 0; 400117521Snjl else if (val != 0 && val == rc->rc_hotchar) 40167754Smsmith setsofttty(); 402117521Snjl optr[0] = val; 40367754Smsmith optr[INPUT_FLAGS_SHIFT] = iack; 404151937Sjkim optr++; 405117521Snjl rc_scheduled_event++; 406117521Snjl } 407151937Sjkim } 408117521Snjl } 40967754Smsmith rc->rc_iptr = optr; 410117521Snjl rc->rc_flags |= RC_DORXFER; 41167754Smsmith } else 412151937Sjkim resid = ucnt; 413117521Snjl /* Clear FIFO if necessary */ 414117521Snjl while (resid-- > 0) { 415151937Sjkim if (!good_data) 416117521Snjl iack = rcin(CD180_RCSR); 417117521Snjl else 418117521Snjl iack = 0; 419117521Snjl if (iack & RCSR_Timeout) 420117521Snjl break; 421117521Snjl (void) rcin(CD180_RDR); 422117521Snjl } 423167802Sjkim goto more_intrs; 424151937Sjkim } 425117521Snjl if (bsr & RC_BSR_MOINT) { 426117521Snjl iack = rcin(RC_PILR_MODEM); 427117521Snjl if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 428117521Snjl printf("rc%d: fake moint: %02x\n", unit, iack); 429151937Sjkim goto more_intrs; 430117521Snjl } 431117521Snjl rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 432151937Sjkim iack = rcin(CD180_MCR); 433117521Snjl rc->rc_msvr = rcin(CD180_MSVR); 434117521Snjl rcout(CD180_MCR, 0); 435117521Snjl#ifdef RCDEBUG 436117521Snjl printrcflags(rc, "moint"); 437123315Snjl#endif 438151937Sjkim if (rc->rc_flags & RC_CTSFLOW) { 439117521Snjl if (rc->rc_msvr & MSVR_CTS) 440117521Snjl rc->rc_flags |= RC_SEND_RDY; 441151937Sjkim else 442117521Snjl rc->rc_flags &= ~RC_SEND_RDY; 443117521Snjl } else 444126372Snjl rc->rc_flags |= RC_SEND_RDY; 445126372Snjl if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 446151937Sjkim rc_scheduled_event += LOTS_OF_EVENTS; 447126372Snjl rc->rc_flags |= RC_MODCHG; 448126372Snjl setsofttty(); 449151937Sjkim } 450126372Snjl goto more_intrs; 45167754Smsmith } 45267754Smsmith if (bsr & RC_BSR_TXINT) { 453117521Snjl iack = rcin(RC_PILR_TX); 45467754Smsmith if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 455117521Snjl printf("rc%d: fake txint: %02x\n", unit, iack); 456117521Snjl goto more_intrs; 45767754Smsmith } 458117521Snjl rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 45967754Smsmith if ( (rc->rc_flags & RC_OSUSP) 46067754Smsmith || !(rc->rc_flags & RC_SEND_RDY) 461117521Snjl ) 462117521Snjl goto more_intrs; 463117521Snjl /* Handle breaks and other stuff */ 464151937Sjkim if (rc->rc_pendcmd) { 465117521Snjl rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 466117521Snjl rcout(CD180_TDR, CD180_C_ESC); 46767754Smsmith rcout(CD180_TDR, rc->rc_pendcmd); 468117521Snjl rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 46967754Smsmith rc->rc_pendcmd = 0; 47067754Smsmith goto more_intrs; 47167754Smsmith } 472117521Snjl optr = rc->rc_optr; 473167802Sjkim resid = rc->rc_obufend - optr; 474117521Snjl if (resid > CD180_NFIFO) 47567754Smsmith resid = CD180_NFIFO; 476167802Sjkim while (resid-- > 0) 47767754Smsmith rcout(CD180_TDR, *optr++); 478117521Snjl rc->rc_optr = optr; 47967754Smsmith 48067754Smsmith /* output completed? */ 481167802Sjkim if (optr >= rc->rc_obufend) { 482167802Sjkim rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 483193267Sjkim#ifdef RCDEBUG 484193267Sjkim printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 485193267Sjkim#endif 486193267Sjkim if (!(rc->rc_flags & RC_DOXXFER)) { 487193267Sjkim rc_scheduled_event += LOTS_OF_EVENTS; 488193267Sjkim rc->rc_flags |= RC_DOXXFER; 489193267Sjkim setsofttty(); 490193267Sjkim } 491193267Sjkim } 492193267Sjkim } 493193267Sjkim more_intrs: 494193267Sjkim rcout(CD180_EOIR, 0); /* end of interrupt */ 495193267Sjkim rcout(RC_CTOUT, 0); 496193267Sjkim bsr = ~(rcin(RC_BSR)); 497193267Sjkim } 498193267Sjkim} 499193267Sjkim 500193267Sjkim/* Feed characters to output buffer */ 501193267Sjkimstatic void rc_start(tp) 502193267Sjkimregister struct tty *tp; 503193267Sjkim{ 504193267Sjkim register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 505193267Sjkim register int nec = rc->rc_rcb->rcb_addr, s; 506193267Sjkim 507193267Sjkim if (rc->rc_flags & RC_OSBUSY) 508193267Sjkim return; 509193267Sjkim s = spltty(); 510193267Sjkim rc->rc_flags |= RC_OSBUSY; 511193267Sjkim disable_intr(); 512193267Sjkim if (tp->t_state & TS_TTSTOP) 513193267Sjkim rc->rc_flags |= RC_OSUSP; 514193267Sjkim else 515193267Sjkim rc->rc_flags &= ~RC_OSUSP; 516193267Sjkim /* Do RTS flow control stuff */ 517193267Sjkim if ( (rc->rc_flags & RC_RTSFLOW) 518193267Sjkim && (tp->t_state & TS_TBLOCK) 519193267Sjkim && (rc->rc_msvr & MSVR_RTS) 520193267Sjkim ) { 521193267Sjkim rcout(CD180_CAR, rc->rc_chan); 522193267Sjkim rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 523193267Sjkim } else if (!(rc->rc_msvr & MSVR_RTS)) { 524193267Sjkim rcout(CD180_CAR, rc->rc_chan); 525193267Sjkim rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 526193267Sjkim } 527193267Sjkim enable_intr(); 528193267Sjkim if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 529193267Sjkim goto out; 530193267Sjkim#ifdef RCDEBUG 531193267Sjkim printrcflags(rc, "rcstart"); 532193267Sjkim#endif 533193267Sjkim ttwwakeup(tp); 534193267Sjkim#ifdef RCDEBUG 535193267Sjkim printf("rcstart: outq = %d obuf = %d\n", 536193267Sjkim tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 537193267Sjkim#endif 538193267Sjkim if (tp->t_state & TS_BUSY) 539193267Sjkim goto out; /* output still in progress ... */ 540193267Sjkim 541193267Sjkim if (tp->t_outq.c_cc > 0) { 542193267Sjkim u_int ocnt; 543193267Sjkim 544193267Sjkim tp->t_state |= TS_BUSY; 545193267Sjkim ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 546193267Sjkim disable_intr(); 547193267Sjkim rc->rc_optr = rc->rc_obuf; 548193267Sjkim rc->rc_obufend = rc->rc_optr + ocnt; 549193267Sjkim enable_intr(); 550193267Sjkim if (!(rc->rc_ier & IER_TxRdy)) { 551193267Sjkim#ifdef RCDEBUG 552193267Sjkim printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 553193267Sjkim#endif 554193267Sjkim rcout(CD180_CAR, rc->rc_chan); 555193267Sjkim rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 556193267Sjkim } 557193267Sjkim } 558193267Sjkimout: 559193267Sjkim rc->rc_flags &= ~RC_OSBUSY; 560193267Sjkim (void) splx(s); 561193267Sjkim} 562193267Sjkim 563193267Sjkim/* Handle delayed events. */ 564193267Sjkimvoid rcpoll() 565193267Sjkim{ 566193267Sjkim register struct rc_chans *rc; 567193267Sjkim register struct rc_softc *rcb; 568193267Sjkim register u_char *tptr, *eptr; 569193267Sjkim register struct tty *tp; 570193267Sjkim register int chan, icnt, nec, unit; 571193267Sjkim 572193267Sjkim if (rc_scheduled_event == 0) 573193267Sjkim return; 574193267Sjkimrepeat: 575193267Sjkim for (unit = 0; unit < NRC; unit++) { 576193267Sjkim rcb = &rc_softc[unit]; 577193267Sjkim rc = rcb->rcb_baserc; 578193267Sjkim nec = rc->rc_rcb->rcb_addr; 579193267Sjkim for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 580193267Sjkim tp = rc->rc_tp; 581193267Sjkim#ifdef RCDEBUG 582193267Sjkim if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 583193267Sjkim RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 584193267Sjkim printrcflags(rc, "rcevent"); 585193267Sjkim#endif 586193267Sjkim if (rc->rc_flags & RC_WAS_BUFOVFL) { 587193267Sjkim disable_intr(); 588193267Sjkim rc->rc_flags &= ~RC_WAS_BUFOVFL; 589193267Sjkim rc_scheduled_event--; 590193267Sjkim enable_intr(); 591193267Sjkim printf("rc%d/%d: interrupt-level buffer overflow\n", 592193267Sjkim unit, chan); 593193267Sjkim } 594193267Sjkim if (rc->rc_flags & RC_WAS_SILOVFL) { 595193267Sjkim disable_intr(); 596193267Sjkim rc->rc_flags &= ~RC_WAS_SILOVFL; 597193267Sjkim rc_scheduled_event--; 598193267Sjkim enable_intr(); 599193267Sjkim printf("rc%d/%d: silo overflow\n", 600193267Sjkim unit, chan); 601193267Sjkim } 602193267Sjkim if (rc->rc_flags & RC_MODCHG) { 603193267Sjkim disable_intr(); 604193267Sjkim rc->rc_flags &= ~RC_MODCHG; 605193267Sjkim rc_scheduled_event -= LOTS_OF_EVENTS; 606193267Sjkim enable_intr(); 607193267Sjkim (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 608193267Sjkim } 609193267Sjkim if (rc->rc_flags & RC_DORXFER) { 610193267Sjkim disable_intr(); 611193267Sjkim rc->rc_flags &= ~RC_DORXFER; 612193267Sjkim eptr = rc->rc_iptr; 613193267Sjkim if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 614193267Sjkim tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 615193267Sjkim else 616193267Sjkim tptr = rc->rc_ibuf; 617193267Sjkim icnt = eptr - tptr; 618193267Sjkim if (icnt > 0) { 619193267Sjkim if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 620193267Sjkim rc->rc_iptr = rc->rc_ibuf; 621193267Sjkim rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 622193267Sjkim rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 623193267Sjkim } else { 624193267Sjkim rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 625193267Sjkim rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 626193267Sjkim rc->rc_hiwat = 627193267Sjkim &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 628193267Sjkim } 629193267Sjkim if ( (rc->rc_flags & RC_RTSFLOW) 630193267Sjkim && (tp->t_state & TS_ISOPEN) 631193267Sjkim && !(tp->t_state & TS_TBLOCK) 632193267Sjkim && !(rc->rc_msvr & MSVR_RTS) 633193267Sjkim ) { 634193267Sjkim rcout(CD180_CAR, chan); 635193267Sjkim rcout(CD180_MSVR, 636193267Sjkim rc->rc_msvr |= MSVR_RTS); 637193267Sjkim } 638193267Sjkim rc_scheduled_event -= icnt; 639193267Sjkim } 640193267Sjkim enable_intr(); 641193267Sjkim 642193267Sjkim if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 643193267Sjkim goto done1; 644193267Sjkim 645 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 646 && !(tp->t_state & TS_LOCAL)) { 647 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 648 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 649 && !(tp->t_state & TS_TBLOCK)) 650 ttyblock(tp); 651 tk_nin += icnt; 652 tk_rawcc += icnt; 653 tp->t_rawcc += icnt; 654 if (b_to_q(tptr, icnt, &tp->t_rawq)) 655 printf("rc%d/%d: tty-level buffer overflow\n", 656 unit, chan); 657 ttwakeup(tp); 658 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 659 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 660 tp->t_state &= ~TS_TTSTOP; 661 tp->t_lflag &= ~FLUSHO; 662 rc_start(tp); 663 } 664 } else { 665 for (; tptr < eptr; tptr++) 666 (*linesw[tp->t_line].l_rint) 667 (tptr[0] | 668 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 669 } 670done1: 671 } 672 if (rc->rc_flags & RC_DOXXFER) { 673 disable_intr(); 674 rc_scheduled_event -= LOTS_OF_EVENTS; 675 rc->rc_flags &= ~RC_DOXXFER; 676 rc->rc_tp->t_state &= ~TS_BUSY; 677 enable_intr(); 678 (*linesw[tp->t_line].l_start)(tp); 679 } 680 } 681 if (rc_scheduled_event == 0) 682 break; 683 } 684 if (rc_scheduled_event >= LOTS_OF_EVENTS) 685 goto repeat; 686} 687 688static void 689rcstop(tp, rw) 690 register struct tty *tp; 691 int rw; 692{ 693 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 694 u_char *tptr, *eptr; 695 696#ifdef RCDEBUG 697 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 698 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 699#endif 700 if (rw & FWRITE) 701 rc_discard_output(rc); 702 disable_intr(); 703 if (rw & FREAD) { 704 rc->rc_flags &= ~RC_DORXFER; 705 eptr = rc->rc_iptr; 706 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 707 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 708 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 709 } else { 710 tptr = rc->rc_ibuf; 711 rc->rc_iptr = rc->rc_ibuf; 712 } 713 rc_scheduled_event -= eptr - tptr; 714 } 715 if (tp->t_state & TS_TTSTOP) 716 rc->rc_flags |= RC_OSUSP; 717 else 718 rc->rc_flags &= ~RC_OSUSP; 719 enable_intr(); 720} 721 722static int 723rcopen(dev, flag, mode, p) 724 dev_t dev; 725 int flag, mode; 726 struct proc *p; 727{ 728 register struct rc_chans *rc; 729 register struct tty *tp; 730 int unit, nec, s, error = 0; 731 732 unit = GET_UNIT(dev); 733 if (unit >= NRC * CD180_NCHAN) 734 return ENXIO; 735 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 736 return ENXIO; 737 rc = &rc_chans[unit]; 738 tp = rc->rc_tp; 739 nec = rc->rc_rcb->rcb_addr; 740#ifdef RCDEBUG 741 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 742#endif 743 s = spltty(); 744 745again: 746 while (rc->rc_flags & RC_DTR_OFF) { 747 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 748 if (error != 0) 749 goto out; 750 } 751 if (tp->t_state & TS_ISOPEN) { 752 if (CALLOUT(dev)) { 753 if (!(rc->rc_flags & RC_ACTOUT)) { 754 error = EBUSY; 755 goto out; 756 } 757 } else { 758 if (rc->rc_flags & RC_ACTOUT) { 759 if (flag & O_NONBLOCK) { 760 error = EBUSY; 761 goto out; 762 } 763 if (error = tsleep(&rc->rc_rcb, 764 TTIPRI|PCATCH, "rcbi", 0)) 765 goto out; 766 goto again; 767 } 768 } 769 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 770 error = EBUSY; 771 goto out; 772 } 773 } else { 774 tp->t_oproc = rc_start; 775 tp->t_param = rc_param; 776 tp->t_dev = dev; 777 778 if (CALLOUT(dev)) 779 tp->t_cflag |= CLOCAL; 780 else 781 tp->t_cflag &= ~CLOCAL; 782 783 error = rc_param(tp, &tp->t_termios); 784 if (error) 785 goto out; 786 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 787 788 ttsetwater(tp); 789 790 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 791 (*linesw[tp->t_line].l_modem)(tp, 1); 792 } 793 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 794 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 795 rc->rc_dcdwaits++; 796 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 797 rc->rc_dcdwaits--; 798 if (error != 0) 799 goto out; 800 goto again; 801 } 802 error = (*linesw[tp->t_line].l_open)(dev, tp); 803 disc_optim(tp, &tp->t_termios, rc); 804 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 805 rc->rc_flags |= RC_ACTOUT; 806out: 807 (void) splx(s); 808 809 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 810 rc_hardclose(rc); 811 812 return error; 813} 814 815static int 816rcclose(dev, flag, mode, p) 817 dev_t dev; 818 int flag, mode; 819 struct proc *p; 820{ 821 register struct rc_chans *rc; 822 register struct tty *tp; 823 int s, unit = GET_UNIT(dev); 824 825 if (unit >= NRC * CD180_NCHAN) 826 return ENXIO; 827 rc = &rc_chans[unit]; 828 tp = rc->rc_tp; 829#ifdef RCDEBUG 830 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 831#endif 832 s = spltty(); 833 (*linesw[tp->t_line].l_close)(tp, flag); 834 disc_optim(tp, &tp->t_termios, rc); 835 rcstop(tp, FREAD | FWRITE); 836 rc_hardclose(rc); 837 ttyclose(tp); 838 splx(s); 839 return 0; 840} 841 842static void rc_hardclose(rc) 843register struct rc_chans *rc; 844{ 845 register int s, nec = rc->rc_rcb->rcb_addr; 846 register struct tty *tp = rc->rc_tp; 847 848 s = spltty(); 849 rcout(CD180_CAR, rc->rc_chan); 850 851 /* Disable rx/tx intrs */ 852 rcout(CD180_IER, rc->rc_ier = 0); 853 if ( (tp->t_cflag & HUPCL) 854 || !(rc->rc_flags & RC_ACTOUT) 855 && !(rc->rc_msvr & MSVR_CD) 856 && !(tp->t_cflag & CLOCAL) 857 || !(tp->t_state & TS_ISOPEN) 858 ) { 859 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 860 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 861 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 862 if (rc->rc_dtrwait) { 863 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 864 rc->rc_flags |= RC_DTR_OFF; 865 } 866 } 867 rc->rc_flags &= ~RC_ACTOUT; 868 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 869 wakeup(TSA_CARR_ON(tp)); 870 (void) splx(s); 871} 872 873/* Read from line */ 874static int 875rcread(dev, uio, flag) 876 dev_t dev; 877 struct uio *uio; 878 int flag; 879{ 880 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 881 882 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 883} 884 885/* Write to line */ 886static int 887rcwrite(dev, uio, flag) 888 dev_t dev; 889 struct uio *uio; 890 int flag; 891{ 892 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 893 894 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 895} 896 897/* Reset the bastard */ 898static void rc_hwreset(unit, nec, chipid) 899 register int unit, nec; 900 unsigned int chipid; 901{ 902 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 903 DELAY(20000); 904 WAITFORCCR(unit, -1); 905 906 rcout(RC_CTOUT, 0); /* Clear timeout */ 907 rcout(CD180_GIVR, chipid); 908 rcout(CD180_GICR, 0); 909 910 /* Set Prescaler Registers (1 msec) */ 911 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 912 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 913 914 /* Initialize Priority Interrupt Level Registers */ 915 rcout(CD180_PILR1, RC_PILR_MODEM); 916 rcout(CD180_PILR2, RC_PILR_TX); 917 rcout(CD180_PILR3, RC_PILR_RX); 918 919 /* Reset DTR */ 920 rcout(RC_DTREG, ~0); 921} 922 923/* Set channel parameters */ 924static int rc_param(tp, ts) 925 register struct tty *tp; 926 struct termios *ts; 927{ 928 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 929 register int nec = rc->rc_rcb->rcb_addr; 930 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 931 932 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 933 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 934 ) 935 return (EINVAL); 936 if (ts->c_ispeed == 0) 937 ts->c_ispeed = ts->c_ospeed; 938 odivs = RC_BRD(ts->c_ospeed); 939 idivs = RC_BRD(ts->c_ispeed); 940 941 s = spltty(); 942 943 /* Select channel */ 944 rcout(CD180_CAR, rc->rc_chan); 945 946 /* If speed == 0, hangup line */ 947 if (ts->c_ospeed == 0) { 948 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 949 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 950 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 951 } 952 953 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 954 cflag = ts->c_cflag; 955 iflag = ts->c_iflag; 956 lflag = ts->c_lflag; 957 958 if (idivs > 0) { 959 rcout(CD180_RBPRL, idivs & 0xFF); 960 rcout(CD180_RBPRH, idivs >> 8); 961 } 962 if (odivs > 0) { 963 rcout(CD180_TBPRL, odivs & 0xFF); 964 rcout(CD180_TBPRH, odivs >> 8); 965 } 966 967 /* set timeout value */ 968 if (ts->c_ispeed > 0) { 969 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 970 971 if ( !(lflag & ICANON) 972 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 973 && ts->c_cc[VTIME] * 10 > itm) 974 itm = ts->c_cc[VTIME] * 10; 975 976 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 977 } 978 979 switch (cflag & CSIZE) { 980 case CS5: val = COR1_5BITS; break; 981 case CS6: val = COR1_6BITS; break; 982 case CS7: val = COR1_7BITS; break; 983 default: 984 case CS8: val = COR1_8BITS; break; 985 } 986 if (cflag & PARENB) { 987 val |= COR1_NORMPAR; 988 if (cflag & PARODD) 989 val |= COR1_ODDP; 990 if (!(cflag & INPCK)) 991 val |= COR1_Ignore; 992 } else 993 val |= COR1_Ignore; 994 if (cflag & CSTOPB) 995 val |= COR1_2SB; 996 rcout(CD180_COR1, val); 997 998 /* Set FIFO threshold */ 999 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1000 inpflow = 0; 1001 if ( (iflag & IXOFF) 1002 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1003 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1004 || (iflag & IXANY) 1005 ) 1006 ) 1007 ) { 1008 inpflow = 1; 1009 val |= COR3_SCDE|COR3_FCT; 1010 } 1011 rcout(CD180_COR3, val); 1012 1013 /* Initialize on-chip automatic flow control */ 1014 val = 0; 1015 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1016 if (cflag & CCTS_OFLOW) { 1017 rc->rc_flags |= RC_CTSFLOW; 1018 val |= COR2_CtsAE; 1019 } else 1020 rc->rc_flags |= RC_SEND_RDY; 1021 if (tp->t_state & TS_TTSTOP) 1022 rc->rc_flags |= RC_OSUSP; 1023 else 1024 rc->rc_flags &= ~RC_OSUSP; 1025 if (cflag & CRTS_IFLOW) 1026 rc->rc_flags |= RC_RTSFLOW; 1027 else 1028 rc->rc_flags &= ~RC_RTSFLOW; 1029 1030 if (inpflow) { 1031 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1032 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1033 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1034 val |= COR2_TxIBE; 1035 if (iflag & IXANY) 1036 val |= COR2_IXM; 1037 } 1038 1039 rcout(CD180_COR2, rc->rc_cor2 = val); 1040 1041 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1042 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1043 1044 disc_optim(tp, ts, rc); 1045 1046 /* modem ctl */ 1047 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1048 if (cflag & CCTS_OFLOW) 1049 val |= MCOR1_CTSzd; 1050 rcout(CD180_MCOR1, val); 1051 1052 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1053 if (cflag & CCTS_OFLOW) 1054 val |= MCOR2_CTSod; 1055 rcout(CD180_MCOR2, val); 1056 1057 /* enable i/o and interrupts */ 1058 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1059 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1060 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1061 1062 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1063 if (cflag & CCTS_OFLOW) 1064 rc->rc_ier |= IER_CTS; 1065 if (cflag & CREAD) 1066 rc->rc_ier |= IER_RxData; 1067 if (tp->t_state & TS_BUSY) 1068 rc->rc_ier |= IER_TxRdy; 1069 if (ts->c_ospeed != 0) 1070 rc_modctl(rc, TIOCM_DTR, DMBIS); 1071 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1072 rc->rc_flags |= RC_SEND_RDY; 1073 rcout(CD180_IER, rc->rc_ier); 1074 (void) splx(s); 1075 return 0; 1076} 1077 1078/* Re-initialize board after bogus interrupts */ 1079static void rc_reinit(rcb) 1080struct rc_softc *rcb; 1081{ 1082 register struct rc_chans *rc, *rce; 1083 register int nec; 1084 1085 nec = rcb->rcb_addr; 1086 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1087 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1088 rce = rc + CD180_NCHAN; 1089 for (; rc < rce; rc++) 1090 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1091} 1092 1093static int 1094rcioctl(dev, cmd, data, flag, p) 1095dev_t dev; 1096int cmd, flag; 1097caddr_t data; 1098struct proc *p; 1099{ 1100 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1101 register int s, error; 1102 struct tty *tp = rc->rc_tp; 1103 1104 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1105 if (error >= 0) 1106 return (error); 1107 error = ttioctl(tp, cmd, data, flag); 1108 disc_optim(tp, &tp->t_termios, rc); 1109 if (error >= 0) 1110 return (error); 1111 s = spltty(); 1112 1113 switch (cmd) { 1114 case TIOCSBRK: 1115 rc->rc_pendcmd = CD180_C_SBRK; 1116 break; 1117 1118 case TIOCCBRK: 1119 rc->rc_pendcmd = CD180_C_EBRK; 1120 break; 1121 1122 case TIOCSDTR: 1123 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1124 break; 1125 1126 case TIOCCDTR: 1127 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1128 break; 1129 1130 case TIOCMGET: 1131 *(int *) data = rc_modctl(rc, 0, DMGET); 1132 break; 1133 1134 case TIOCMSET: 1135 (void) rc_modctl(rc, *(int *) data, DMSET); 1136 break; 1137 1138 case TIOCMBIC: 1139 (void) rc_modctl(rc, *(int *) data, DMBIC); 1140 break; 1141 1142 case TIOCMBIS: 1143 (void) rc_modctl(rc, *(int *) data, DMBIS); 1144 break; 1145 1146 case TIOCMSDTRWAIT: 1147 error = suser(p->p_ucred, &p->p_acflag); 1148 if (error != 0) { 1149 splx(s); 1150 return (error); 1151 } 1152 rc->rc_dtrwait = *(int *)data * hz / 100; 1153 break; 1154 1155 case TIOCMGDTRWAIT: 1156 *(int *)data = rc->rc_dtrwait * 100 / hz; 1157 break; 1158 1159 default: 1160 (void) splx(s); 1161 return ENOTTY; 1162 } 1163 (void) splx(s); 1164 return 0; 1165} 1166 1167 1168/* Modem control routines */ 1169 1170static int rc_modctl(rc, bits, cmd) 1171register struct rc_chans *rc; 1172int bits, cmd; 1173{ 1174 register int nec = rc->rc_rcb->rcb_addr; 1175 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1176 1177 rcout(CD180_CAR, rc->rc_chan); 1178 1179 switch (cmd) { 1180 case DMSET: 1181 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1182 ~(*dtr |= 1 << rc->rc_chan) : 1183 ~(*dtr &= ~(1 << rc->rc_chan))); 1184 msvr = rcin(CD180_MSVR); 1185 if (bits & TIOCM_RTS) 1186 msvr |= MSVR_RTS; 1187 else 1188 msvr &= ~MSVR_RTS; 1189 if (bits & TIOCM_DTR) 1190 msvr |= MSVR_DTR; 1191 else 1192 msvr &= ~MSVR_DTR; 1193 rcout(CD180_MSVR, msvr); 1194 break; 1195 1196 case DMBIS: 1197 if (bits & TIOCM_DTR) 1198 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1199 msvr = rcin(CD180_MSVR); 1200 if (bits & TIOCM_RTS) 1201 msvr |= MSVR_RTS; 1202 if (bits & TIOCM_DTR) 1203 msvr |= MSVR_DTR; 1204 rcout(CD180_MSVR, msvr); 1205 break; 1206 1207 case DMGET: 1208 bits = TIOCM_LE; 1209 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1210 1211 if (msvr & MSVR_RTS) 1212 bits |= TIOCM_RTS; 1213 if (msvr & MSVR_CTS) 1214 bits |= TIOCM_CTS; 1215 if (msvr & MSVR_DSR) 1216 bits |= TIOCM_DSR; 1217 if (msvr & MSVR_DTR) 1218 bits |= TIOCM_DTR; 1219 if (msvr & MSVR_CD) 1220 bits |= TIOCM_CD; 1221 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1222 bits |= TIOCM_RI; 1223 return bits; 1224 1225 case DMBIC: 1226 if (bits & TIOCM_DTR) 1227 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1228 msvr = rcin(CD180_MSVR); 1229 if (bits & TIOCM_RTS) 1230 msvr &= ~MSVR_RTS; 1231 if (bits & TIOCM_DTR) 1232 msvr &= ~MSVR_DTR; 1233 rcout(CD180_MSVR, msvr); 1234 break; 1235 } 1236 rc->rc_msvr = rcin(CD180_MSVR); 1237 return 0; 1238} 1239 1240/* Test the board. */ 1241int rc_test(nec, unit) 1242 register int nec; 1243 int unit; 1244{ 1245 int chan = 0; 1246 int i = 0, rcnt, old_level; 1247 unsigned int iack, chipid; 1248 unsigned short divs; 1249 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1250#define CTLEN 8 1251#define ERR(s) { \ 1252 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1253 (void) splx(old_level); return 1; } 1254 1255 struct rtest { 1256 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1257 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1258 int rxptr; /* RX pointer */ 1259 int txptr; /* TX pointer */ 1260 } tchans[CD180_NCHAN]; 1261 1262 old_level = spltty(); 1263 1264 chipid = RC_FAKEID; 1265 1266 /* First, reset board to inital state */ 1267 rc_hwreset(unit, nec, chipid); 1268 1269 divs = RC_BRD(19200); 1270 1271 /* Initialize channels */ 1272 for (chan = 0; chan < CD180_NCHAN; chan++) { 1273 1274 /* Select and reset channel */ 1275 rcout(CD180_CAR, chan); 1276 CCRCMD(unit, chan, CCR_ResetChan); 1277 WAITFORCCR(unit, chan); 1278 1279 /* Set speed */ 1280 rcout(CD180_RBPRL, divs & 0xFF); 1281 rcout(CD180_RBPRH, divs >> 8); 1282 rcout(CD180_TBPRL, divs & 0xFF); 1283 rcout(CD180_TBPRH, divs >> 8); 1284 1285 /* set timeout value */ 1286 rcout(CD180_RTPR, 0); 1287 1288 /* Establish local loopback */ 1289 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1290 rcout(CD180_COR2, COR2_LLM); 1291 rcout(CD180_COR3, CD180_NFIFO); 1292 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1293 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1294 WAITFORCCR(unit, chan); 1295 rcout(CD180_MSVR, MSVR_RTS); 1296 1297 /* Fill TXBUF with test data */ 1298 for (i = 0; i < CD180_NFIFO; i++) { 1299 tchans[chan].txbuf[i] = ctest[i]; 1300 tchans[chan].rxbuf[i] = 0; 1301 } 1302 tchans[chan].txptr = tchans[chan].rxptr = 0; 1303 1304 /* Now, start transmit */ 1305 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1306 } 1307 /* Pseudo-interrupt poll stuff */ 1308 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1309 i = ~(rcin(RC_BSR)); 1310 if (i & RC_BSR_TOUT) 1311 ERR(("BSR timeout bit set\n")) 1312 else if (i & RC_BSR_TXINT) { 1313 iack = rcin(RC_PILR_TX); 1314 if (iack != (GIVR_IT_TDI | chipid)) 1315 ERR(("Bad TX intr ack (%02x != %02x)\n", 1316 iack, GIVR_IT_TDI | chipid)); 1317 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1318 /* If no more data to transmit, disable TX intr */ 1319 if (tchans[chan].txptr >= CD180_NFIFO) { 1320 iack = rcin(CD180_IER); 1321 rcout(CD180_IER, iack & ~IER_TxMpty); 1322 } else { 1323 for (iack = tchans[chan].txptr; 1324 iack < CD180_NFIFO; iack++) 1325 rcout(CD180_TDR, 1326 tchans[chan].txbuf[iack]); 1327 tchans[chan].txptr = iack; 1328 } 1329 rcout(CD180_EOIR, 0); 1330 } else if (i & RC_BSR_RXINT) { 1331 u_char ucnt; 1332 1333 iack = rcin(RC_PILR_RX); 1334 if (iack != (GIVR_IT_RGDI | chipid) && 1335 iack != (GIVR_IT_REI | chipid)) 1336 ERR(("Bad RX intr ack (%02x != %02x)\n", 1337 iack, GIVR_IT_RGDI | chipid)) 1338 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1339 ucnt = rcin(CD180_RDCR) & 0xF; 1340 while (ucnt-- > 0) { 1341 iack = rcin(CD180_RCSR); 1342 if (iack & RCSR_Timeout) 1343 break; 1344 if (iack & 0xF) 1345 ERR(("Bad char chan %d (RCSR = %02X)\n", 1346 chan, iack)) 1347 if (tchans[chan].rxptr > CD180_NFIFO) 1348 ERR(("Got extra chars chan %d\n", 1349 chan)) 1350 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1351 rcin(CD180_RDR); 1352 } 1353 rcout(CD180_EOIR, 0); 1354 } 1355 rcout(RC_CTOUT, 0); 1356 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1357 if (tchans[chan].rxptr >= CD180_NFIFO) 1358 iack++; 1359 if (iack == CD180_NCHAN) 1360 break; 1361 } 1362 for (chan = 0; chan < CD180_NCHAN; chan++) { 1363 /* Select and reset channel */ 1364 rcout(CD180_CAR, chan); 1365 CCRCMD(unit, chan, CCR_ResetChan); 1366 } 1367 1368 if (!rcnt) 1369 ERR(("looses characters during local loopback\n")) 1370 /* Now, check data */ 1371 for (chan = 0; chan < CD180_NCHAN; chan++) 1372 for (i = 0; i < CD180_NFIFO; i++) 1373 if (ctest[i] != tchans[chan].rxbuf[i]) 1374 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1375 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1376 (void) splx(old_level); 1377 return 0; 1378} 1379 1380#ifdef RCDEBUG 1381static void printrcflags(rc, comment) 1382struct rc_chans *rc; 1383char *comment; 1384{ 1385 u_short f = rc->rc_flags; 1386 register int nec = rc->rc_rcb->rcb_addr; 1387 1388 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1389 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1390 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1391 (f & RC_ACTOUT) ?"ACTOUT " :"", 1392 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1393 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1394 (f & RC_DORXFER)?"DORXFER " :"", 1395 (f & RC_DOXXFER)?"DOXXFER " :"", 1396 (f & RC_MODCHG) ?"MODCHG " :"", 1397 (f & RC_OSUSP) ?"OSUSP " :"", 1398 (f & RC_OSBUSY) ?"OSBUSY " :"", 1399 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1400 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1401 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1402 1403 rcout(CD180_CAR, rc->rc_chan); 1404 1405 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1406 rc->rc_rcb->rcb_unit, rc->rc_chan, 1407 rcin(CD180_MSVR), 1408 rcin(CD180_IER), 1409 rcin(CD180_CCSR)); 1410} 1411#endif /* RCDEBUG */ 1412 1413static struct tty * 1414rcdevtotty(dev) 1415 dev_t dev; 1416{ 1417 int unit; 1418 1419 unit = GET_UNIT(dev); 1420 if (unit >= NRC * CD180_NCHAN) 1421 return NULL; 1422 return (&rc_tty[unit]); 1423} 1424 1425static void 1426rc_dtrwakeup(chan) 1427 void *chan; 1428{ 1429 struct rc_chans *rc; 1430 1431 rc = (struct rc_chans *)chan; 1432 rc->rc_flags &= ~RC_DTR_OFF; 1433 wakeup(&rc->rc_dtrwait); 1434} 1435 1436static void 1437rc_discard_output(rc) 1438 struct rc_chans *rc; 1439{ 1440 disable_intr(); 1441 if (rc->rc_flags & RC_DOXXFER) { 1442 rc_scheduled_event -= LOTS_OF_EVENTS; 1443 rc->rc_flags &= ~RC_DOXXFER; 1444 } 1445 rc->rc_optr = rc->rc_obufend; 1446 rc->rc_tp->t_state &= ~TS_BUSY; 1447 enable_intr(); 1448 ttwwakeup(rc->rc_tp); 1449} 1450 1451static void 1452rc_wakeup(chan) 1453 void *chan; 1454{ 1455 timeout(rc_wakeup, (caddr_t)NULL, 1); 1456 1457 if (rc_scheduled_event != 0) { 1458 int s; 1459 1460 s = splsofttty(); 1461 rcpoll(); 1462 splx(s); 1463 } 1464} 1465 1466static void 1467disc_optim(tp, t, rc) 1468 struct tty *tp; 1469 struct termios *t; 1470 struct rc_chans *rc; 1471{ 1472 1473 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1474 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1475 && (!(t->c_iflag & PARMRK) 1476 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1477 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1478 && linesw[tp->t_line].l_rint == ttyinput) 1479 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1480 else 1481 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1482 if (tp->t_line == SLIPDISC) 1483 rc->rc_hotchar = 0xc0; 1484 else if (tp->t_line == PPPDISC) 1485 rc->rc_hotchar = 0x7e; 1486 else 1487 rc->rc_hotchar = 0; 1488} 1489 1490static void 1491rc_wait0(nec, unit, chan, line) 1492 int nec, unit, chan, line; 1493{ 1494 int rcnt; 1495 1496 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1497 DELAY(30); 1498 if (rcnt == 0) 1499 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1500 unit, chan, line); 1501} 1502 1503static rc_devsw_installed = 0; 1504 1505static void rc_drvinit(void *unused) 1506{ 1507 dev_t dev; 1508 1509 if( ! rc_devsw_installed ) { 1510 dev = makedev(CDEV_MAJOR, 0); 1511 cdevsw_add(&dev,&rc_cdevsw, NULL); 1512 rc_devsw_installed = 1; 1513 } 1514} 1515 1516SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1517 1518 1519#endif /* NRC */ 1520