rc.c revision 18084
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#ifdef DEVFS 50#include <sys/devfsext.h> 51#endif /*DEVFS*/ 52 53#include <machine/clock.h> 54 55#include <i386/isa/isa_device.h> 56#include <i386/isa/sioreg.h> 57 58#include <i386/isa/ic/cd180.h> 59#include <i386/isa/rcreg.h> 60 61 62/* Prototypes */ 63static int rcprobe __P((struct isa_device *)); 64static int rcattach __P((struct isa_device *)); 65 66/*- 67 * This space intentionally left blank to stop __LINE__ from screwing up 68 * regression tests :-(. 69 * 70 * 71 * 72 */ 73void rcpoll __P((void)); 74 75#define rcin(port) RC_IN (nec, port) 76#define rcout(port,v) RC_OUT (nec, port, v) 77 78#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 79#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 80 81#define RC_IBUFSIZE 256 82#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 83#define RC_OBUFSIZE 512 84#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 85#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 86#define LOTS_OF_EVENTS 64 87 88#define RC_FAKEID 0x10 89 90#define RC_PROBED 1 91#define RC_ATTACHED 2 92 93#define GET_UNIT(dev) (minor(dev) & 0x3F) 94#define CALLOUT(dev) (minor(dev) & 0x80) 95 96/* For isa routines */ 97struct isa_driver rcdriver = { 98 rcprobe, rcattach, "rc" 99}; 100 101static d_open_t rcopen; 102static d_close_t rcclose; 103static d_read_t rcread; 104static d_write_t rcwrite; 105static d_ioctl_t rcioctl; 106static d_stop_t rcstop; 107static d_devtotty_t rcdevtotty; 108 109#define CDEV_MAJOR 63 110static struct cdevsw rc_cdevsw = 111 { rcopen, rcclose, rcread, rcwrite, /*63*/ 112 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 113 ttselect, nommap, NULL, "rc", NULL, -1 }; 114 115/* Per-board structure */ 116static struct rc_softc { 117 u_int rcb_probed; /* 1 - probed, 2 - attached */ 118 u_int rcb_addr; /* Base I/O addr */ 119 u_int rcb_unit; /* unit # */ 120 u_char rcb_dtr; /* DTR status */ 121 struct rc_chans *rcb_baserc; /* base rc ptr */ 122} rc_softc[NRC]; 123 124/* Per-channel structure */ 125static struct rc_chans { 126 struct rc_softc *rc_rcb; /* back ptr */ 127 u_short rc_flags; /* Misc. flags */ 128 int rc_chan; /* Channel # */ 129 u_char rc_ier; /* intr. enable reg */ 130 u_char rc_msvr; /* modem sig. status */ 131 u_char rc_cor2; /* options reg */ 132 u_char rc_pendcmd; /* special cmd pending */ 133 u_int rc_dtrwait; /* dtr timeout */ 134 u_int rc_dcdwaits; /* how many waits DCD in open */ 135 u_char rc_hotchar; /* end packed optimize */ 136 struct tty *rc_tp; /* tty struct */ 137 u_char *rc_iptr; /* Chars input buffer */ 138 u_char *rc_hiwat; /* hi-water mark */ 139 u_char *rc_bufend; /* end of buffer */ 140 u_char *rc_optr; /* ptr in output buf */ 141 u_char *rc_obufend; /* end of output buf */ 142 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 143 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 144#ifdef DEVFS 145 void *devfs_token; 146#endif 147} rc_chans[NRC * CD180_NCHAN]; 148 149static int rc_scheduled_event = 0; 150 151/* for pstat -t */ 152static struct tty rc_tty[NRC * CD180_NCHAN]; 153static const int nrc_tty = NRC * CD180_NCHAN; 154 155/* Flags */ 156#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 157#define RC_ACTOUT 0x0002 /* Dial-out port active */ 158#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 159#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 160#define RC_DORXFER 0x0010 /* RXFER event planned */ 161#define RC_DOXXFER 0x0020 /* XXFER event planned */ 162#define RC_MODCHG 0x0040 /* Modem status changed */ 163#define RC_OSUSP 0x0080 /* Output suspended */ 164#define RC_OSBUSY 0x0100 /* start() routine in progress */ 165#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 166#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 167#define RC_SEND_RDY 0x0800 /* ready to send */ 168 169/* Table for translation of RCSR status bits to internal form */ 170static int rc_rcsrt[16] = { 171 0, TTY_OE, TTY_FE, 172 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 173 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 174 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 175 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 176 TTY_BI|TTY_PE|TTY_FE|TTY_OE 177}; 178 179/* Static prototypes */ 180static void rc_hwreset __P((int, int, unsigned int)); 181static int rc_test __P((int, int)); 182static void rc_discard_output __P((struct rc_chans *)); 183static void rc_hardclose __P((struct rc_chans *)); 184static int rc_modctl __P((struct rc_chans *, int, int)); 185static void rc_start __P((struct tty *)); 186static int rc_param __P((struct tty *, struct termios *)); 187static void rc_reinit __P((struct rc_softc *)); 188#ifdef RCDEBUG 189static void printrcflags(); 190#endif 191static timeout_t rc_dtrwakeup; 192static timeout_t rc_wakeup; 193static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 194static void rc_wait0 __P((int nec, int unit, int chan, int line)); 195 196/**********************************************/ 197 198/* Quick device probing */ 199static int 200rcprobe(dvp) 201 struct isa_device *dvp; 202{ 203 int irq = ffs(dvp->id_irq) - 1; 204 register int nec = dvp->id_iobase; 205 206 if (dvp->id_unit > NRC) 207 return 0; 208 if (!RC_VALIDADDR(nec)) { 209 printf("rc%d: illegal base address %x\n", nec); 210 return 0; 211 } 212 if (!RC_VALIDIRQ(irq)) { 213 printf("rc%d: illegal IRQ value %d\n", irq); 214 return 0; 215 } 216 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 217 rcout(CD180_PPRH, 0x11); 218 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 219 return 0; 220 /* Now, test the board more thoroughly, with diagnostic */ 221 if (rc_test(nec, dvp->id_unit)) 222 return 0; 223 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 224 225 return 0xF; 226} 227 228static int 229rcattach(dvp) 230 struct isa_device *dvp; 231{ 232 register int chan, nec = dvp->id_iobase; 233 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 234 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 235 static int rc_wakeup_started = 0; 236 struct tty *tp; 237 238 /* Thorooughly test the device */ 239 if (rcb->rcb_probed != RC_PROBED) 240 return 0; 241 rcb->rcb_addr = nec; 242 rcb->rcb_dtr = 0; 243 rcb->rcb_baserc = rc; 244 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 245 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 246 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 247 248 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 249 rc->rc_rcb = rcb; 250 rc->rc_chan = chan; 251 rc->rc_iptr = rc->rc_ibuf; 252 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 253 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 254 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 255 rc->rc_cor2 = rc->rc_pendcmd = 0; 256 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 257 rc->rc_dtrwait = 3 * hz; 258 rc->rc_dcdwaits= 0; 259 rc->rc_hotchar = 0; 260 tp = rc->rc_tp = &rc_tty[chan]; 261 ttychars(tp); 262 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 263 tp->t_cflag = TTYDEF_CFLAG; 264 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 265#ifdef DEVFS 266/* FIX THIS to reflect real devices */ 267 rc->devfs_token = 268 devfs_add_devswf(&rc_cdevsw, 269 (dvp->id_unit * CD180_NCHAN) + chan, 270 DV_CHR, 0, 0, 0600, "rc%d.%d", 271 dvp->id_unit, chan); 272#endif 273 } 274 rcb->rcb_probed = RC_ATTACHED; 275 if (!rc_wakeup_started) { 276 rc_wakeup((void *)NULL); 277 rc_wakeup_started = 0; 278 } 279 return 1; 280} 281 282/* RC interrupt handling */ 283void rcintr(unit) 284 int unit; 285{ 286 register struct rc_softc *rcb = &rc_softc[unit]; 287 register struct rc_chans *rc; 288 register int nec, resid; 289 register u_char val, iack, bsr, ucnt, *optr; 290 int good_data, t_state; 291 292 if (rcb->rcb_probed != RC_ATTACHED) { 293 printf("rc%d: bogus interrupt\n", unit); 294 return; 295 } 296 nec = rcb->rcb_addr; 297 298 bsr = ~(rcin(RC_BSR)); 299 300 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 301 printf("rc%d: extra interrupt\n", unit); 302 rcout(CD180_EOIR, 0); 303 return; 304 } 305 306 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 307#ifdef RCDEBUG_DETAILED 308 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 309 (bsr & RC_BSR_TOUT)?"TOUT ":"", 310 (bsr & RC_BSR_RXINT)?"RXINT ":"", 311 (bsr & RC_BSR_TXINT)?"TXINT ":"", 312 (bsr & RC_BSR_MOINT)?"MOINT":""); 313#endif 314 if (bsr & RC_BSR_TOUT) { 315 printf("rc%d: hardware failure, reset board\n", unit); 316 rcout(RC_CTOUT, 0); 317 rc_reinit(rcb); 318 return; 319 } 320 if (bsr & RC_BSR_RXINT) { 321 iack = rcin(RC_PILR_RX); 322 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 323 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 324 printf("rc%d: fake rxint: %02x\n", unit, iack); 325 goto more_intrs; 326 } 327 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 328 t_state = rc->rc_tp->t_state; 329 /* Do RTS flow control stuff */ 330 if ( (rc->rc_flags & RC_RTSFLOW) 331 || !(t_state & TS_ISOPEN) 332 ) { 333 if ( ( !(t_state & TS_ISOPEN) 334 || (t_state & TS_TBLOCK) 335 ) 336 && (rc->rc_msvr & MSVR_RTS) 337 ) 338 rcout(CD180_MSVR, 339 rc->rc_msvr &= ~MSVR_RTS); 340 else if (!(rc->rc_msvr & MSVR_RTS)) 341 rcout(CD180_MSVR, 342 rc->rc_msvr |= MSVR_RTS); 343 } 344 ucnt = rcin(CD180_RDCR) & 0xF; 345 resid = 0; 346 347 if (t_state & TS_ISOPEN) { 348 /* check for input buffer overflow */ 349 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 350 resid = ucnt; 351 ucnt = rc->rc_bufend - rc->rc_iptr; 352 resid -= ucnt; 353 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 354 rc->rc_flags |= RC_WAS_BUFOVFL; 355 rc_scheduled_event++; 356 } 357 } 358 optr = rc->rc_iptr; 359 /* check foor good data */ 360 if (good_data) { 361 while (ucnt-- > 0) { 362 val = rcin(CD180_RDR); 363 optr[0] = val; 364 optr[INPUT_FLAGS_SHIFT] = 0; 365 optr++; 366 rc_scheduled_event++; 367 if (val != 0 && val == rc->rc_hotchar) 368 setsofttty(); 369 } 370 } else { 371 /* Store also status data */ 372 while (ucnt-- > 0) { 373 iack = rcin(CD180_RCSR); 374 if (iack & RCSR_Timeout) 375 break; 376 if ( (iack & RCSR_OE) 377 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 378 rc->rc_flags |= RC_WAS_SILOVFL; 379 rc_scheduled_event++; 380 } 381 val = rcin(CD180_RDR); 382 /* 383 Don't store PE if IGNPAR and BREAK if IGNBRK, 384 this hack allows "raw" tty optimization 385 works even if IGN* is set. 386 */ 387 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 388 || (!(iack & (RCSR_PE|RCSR_FE)) 389 || !(rc->rc_tp->t_iflag & IGNPAR)) 390 && (!(iack & RCSR_Break) 391 || !(rc->rc_tp->t_iflag & IGNBRK))) { 392 if ( (iack & (RCSR_PE|RCSR_FE)) 393 && (t_state & TS_CAN_BYPASS_L_RINT) 394 && ((iack & RCSR_FE) 395 || (iack & RCSR_PE) 396 && (rc->rc_tp->t_iflag & INPCK))) 397 val = 0; 398 else if (val != 0 && val == rc->rc_hotchar) 399 setsofttty(); 400 optr[0] = val; 401 optr[INPUT_FLAGS_SHIFT] = iack; 402 optr++; 403 rc_scheduled_event++; 404 } 405 } 406 } 407 rc->rc_iptr = optr; 408 rc->rc_flags |= RC_DORXFER; 409 } else 410 resid = ucnt; 411 /* Clear FIFO if necessary */ 412 while (resid-- > 0) { 413 if (!good_data) 414 iack = rcin(CD180_RCSR); 415 else 416 iack = 0; 417 if (iack & RCSR_Timeout) 418 break; 419 (void) rcin(CD180_RDR); 420 } 421 goto more_intrs; 422 } 423 if (bsr & RC_BSR_MOINT) { 424 iack = rcin(RC_PILR_MODEM); 425 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 426 printf("rc%d: fake moint: %02x\n", unit, iack); 427 goto more_intrs; 428 } 429 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 430 iack = rcin(CD180_MCR); 431 rc->rc_msvr = rcin(CD180_MSVR); 432 rcout(CD180_MCR, 0); 433#ifdef RCDEBUG 434 printrcflags(rc, "moint"); 435#endif 436 if (rc->rc_flags & RC_CTSFLOW) { 437 if (rc->rc_msvr & MSVR_CTS) 438 rc->rc_flags |= RC_SEND_RDY; 439 else 440 rc->rc_flags &= ~RC_SEND_RDY; 441 } else 442 rc->rc_flags |= RC_SEND_RDY; 443 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 444 rc_scheduled_event += LOTS_OF_EVENTS; 445 rc->rc_flags |= RC_MODCHG; 446 setsofttty(); 447 } 448 goto more_intrs; 449 } 450 if (bsr & RC_BSR_TXINT) { 451 iack = rcin(RC_PILR_TX); 452 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 453 printf("rc%d: fake txint: %02x\n", unit, iack); 454 goto more_intrs; 455 } 456 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 457 if ( (rc->rc_flags & RC_OSUSP) 458 || !(rc->rc_flags & RC_SEND_RDY) 459 ) 460 goto more_intrs; 461 /* Handle breaks and other stuff */ 462 if (rc->rc_pendcmd) { 463 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 464 rcout(CD180_TDR, CD180_C_ESC); 465 rcout(CD180_TDR, rc->rc_pendcmd); 466 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 467 rc->rc_pendcmd = 0; 468 goto more_intrs; 469 } 470 optr = rc->rc_optr; 471 resid = rc->rc_obufend - optr; 472 if (resid > CD180_NFIFO) 473 resid = CD180_NFIFO; 474 while (resid-- > 0) 475 rcout(CD180_TDR, *optr++); 476 rc->rc_optr = optr; 477 478 /* output completed? */ 479 if (optr >= rc->rc_obufend) { 480 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 481#ifdef RCDEBUG 482 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 483#endif 484 if (!(rc->rc_flags & RC_DOXXFER)) { 485 rc_scheduled_event += LOTS_OF_EVENTS; 486 rc->rc_flags |= RC_DOXXFER; 487 setsofttty(); 488 } 489 } 490 } 491 more_intrs: 492 rcout(CD180_EOIR, 0); /* end of interrupt */ 493 rcout(RC_CTOUT, 0); 494 bsr = ~(rcin(RC_BSR)); 495 } 496} 497 498/* Feed characters to output buffer */ 499static void rc_start(tp) 500register struct tty *tp; 501{ 502 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 503 register int nec = rc->rc_rcb->rcb_addr, s; 504 505 if (rc->rc_flags & RC_OSBUSY) 506 return; 507 s = spltty(); 508 rc->rc_flags |= RC_OSBUSY; 509 disable_intr(); 510 if (tp->t_state & TS_TTSTOP) 511 rc->rc_flags |= RC_OSUSP; 512 else 513 rc->rc_flags &= ~RC_OSUSP; 514 /* Do RTS flow control stuff */ 515 if ( (rc->rc_flags & RC_RTSFLOW) 516 && (tp->t_state & TS_TBLOCK) 517 && (rc->rc_msvr & MSVR_RTS) 518 ) { 519 rcout(CD180_CAR, rc->rc_chan); 520 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 521 } else if (!(rc->rc_msvr & MSVR_RTS)) { 522 rcout(CD180_CAR, rc->rc_chan); 523 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 524 } 525 enable_intr(); 526 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 527 goto out; 528#ifdef RCDEBUG 529 printrcflags(rc, "rcstart"); 530#endif 531 ttwwakeup(tp); 532#ifdef RCDEBUG 533 printf("rcstart: outq = %d obuf = %d\n", 534 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 535#endif 536 if (tp->t_state & TS_BUSY) 537 goto out; /* output still in progress ... */ 538 539 if (tp->t_outq.c_cc > 0) { 540 u_int ocnt; 541 542 tp->t_state |= TS_BUSY; 543 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 544 disable_intr(); 545 rc->rc_optr = rc->rc_obuf; 546 rc->rc_obufend = rc->rc_optr + ocnt; 547 enable_intr(); 548 if (!(rc->rc_ier & IER_TxRdy)) { 549#ifdef RCDEBUG 550 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 551#endif 552 rcout(CD180_CAR, rc->rc_chan); 553 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 554 } 555 } 556out: 557 rc->rc_flags &= ~RC_OSBUSY; 558 (void) splx(s); 559} 560 561/* Handle delayed events. */ 562void rcpoll() 563{ 564 register struct rc_chans *rc; 565 register struct rc_softc *rcb; 566 register u_char *tptr, *eptr; 567 register struct tty *tp; 568 register int chan, icnt, nec, unit; 569 570 if (rc_scheduled_event == 0) 571 return; 572repeat: 573 for (unit = 0; unit < NRC; unit++) { 574 rcb = &rc_softc[unit]; 575 rc = rcb->rcb_baserc; 576 nec = rc->rc_rcb->rcb_addr; 577 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 578 tp = rc->rc_tp; 579#ifdef RCDEBUG 580 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 581 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 582 printrcflags(rc, "rcevent"); 583#endif 584 if (rc->rc_flags & RC_WAS_BUFOVFL) { 585 disable_intr(); 586 rc->rc_flags &= ~RC_WAS_BUFOVFL; 587 rc_scheduled_event--; 588 enable_intr(); 589 printf("rc%d/%d: interrupt-level buffer overflow\n", 590 unit, chan); 591 } 592 if (rc->rc_flags & RC_WAS_SILOVFL) { 593 disable_intr(); 594 rc->rc_flags &= ~RC_WAS_SILOVFL; 595 rc_scheduled_event--; 596 enable_intr(); 597 printf("rc%d/%d: silo overflow\n", 598 unit, chan); 599 } 600 if (rc->rc_flags & RC_MODCHG) { 601 disable_intr(); 602 rc->rc_flags &= ~RC_MODCHG; 603 rc_scheduled_event -= LOTS_OF_EVENTS; 604 enable_intr(); 605 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 606 } 607 if (rc->rc_flags & RC_DORXFER) { 608 disable_intr(); 609 rc->rc_flags &= ~RC_DORXFER; 610 eptr = rc->rc_iptr; 611 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 612 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 613 else 614 tptr = rc->rc_ibuf; 615 icnt = eptr - tptr; 616 if (icnt > 0) { 617 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 618 rc->rc_iptr = rc->rc_ibuf; 619 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 620 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 621 } else { 622 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 623 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 624 rc->rc_hiwat = 625 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 626 } 627 if ( (rc->rc_flags & RC_RTSFLOW) 628 && (tp->t_state & TS_ISOPEN) 629 && !(tp->t_state & TS_TBLOCK) 630 && !(rc->rc_msvr & MSVR_RTS) 631 ) { 632 rcout(CD180_CAR, chan); 633 rcout(CD180_MSVR, 634 rc->rc_msvr |= MSVR_RTS); 635 } 636 rc_scheduled_event -= icnt; 637 } 638 enable_intr(); 639 640 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 641 goto done1; 642 643 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 644 && !(tp->t_state & TS_LOCAL)) { 645 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 646 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 647 && !(tp->t_state & TS_TBLOCK)) 648 ttyblock(tp); 649 tk_nin += icnt; 650 tk_rawcc += icnt; 651 tp->t_rawcc += icnt; 652 if (b_to_q(tptr, icnt, &tp->t_rawq)) 653 printf("rc%d/%d: tty-level buffer overflow\n", 654 unit, chan); 655 ttwakeup(tp); 656 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 657 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 658 tp->t_state &= ~TS_TTSTOP; 659 tp->t_lflag &= ~FLUSHO; 660 rc_start(tp); 661 } 662 } else { 663 for (; tptr < eptr; tptr++) 664 (*linesw[tp->t_line].l_rint) 665 (tptr[0] | 666 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 667 } 668done1: 669 } 670 if (rc->rc_flags & RC_DOXXFER) { 671 disable_intr(); 672 rc_scheduled_event -= LOTS_OF_EVENTS; 673 rc->rc_flags &= ~RC_DOXXFER; 674 rc->rc_tp->t_state &= ~TS_BUSY; 675 enable_intr(); 676 (*linesw[tp->t_line].l_start)(tp); 677 } 678 } 679 if (rc_scheduled_event == 0) 680 break; 681 } 682 if (rc_scheduled_event >= LOTS_OF_EVENTS) 683 goto repeat; 684} 685 686static void 687rcstop(tp, rw) 688 register struct tty *tp; 689 int rw; 690{ 691 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 692 u_char *tptr, *eptr; 693 694#ifdef RCDEBUG 695 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 696 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 697#endif 698 if (rw & FWRITE) 699 rc_discard_output(rc); 700 disable_intr(); 701 if (rw & FREAD) { 702 rc->rc_flags &= ~RC_DORXFER; 703 eptr = rc->rc_iptr; 704 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 705 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 706 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 707 } else { 708 tptr = rc->rc_ibuf; 709 rc->rc_iptr = rc->rc_ibuf; 710 } 711 rc_scheduled_event -= eptr - tptr; 712 } 713 if (tp->t_state & TS_TTSTOP) 714 rc->rc_flags |= RC_OSUSP; 715 else 716 rc->rc_flags &= ~RC_OSUSP; 717 enable_intr(); 718} 719 720static int 721rcopen(dev, flag, mode, p) 722 dev_t dev; 723 int flag, mode; 724 struct proc *p; 725{ 726 register struct rc_chans *rc; 727 register struct tty *tp; 728 int unit, nec, s, error = 0; 729 730 unit = GET_UNIT(dev); 731 if (unit >= NRC * CD180_NCHAN) 732 return ENXIO; 733 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 734 return ENXIO; 735 rc = &rc_chans[unit]; 736 tp = rc->rc_tp; 737 nec = rc->rc_rcb->rcb_addr; 738#ifdef RCDEBUG 739 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 740#endif 741 s = spltty(); 742 743again: 744 while (rc->rc_flags & RC_DTR_OFF) { 745 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 746 if (error != 0) 747 goto out; 748 } 749 if (tp->t_state & TS_ISOPEN) { 750 if (CALLOUT(dev)) { 751 if (!(rc->rc_flags & RC_ACTOUT)) { 752 error = EBUSY; 753 goto out; 754 } 755 } else { 756 if (rc->rc_flags & RC_ACTOUT) { 757 if (flag & O_NONBLOCK) { 758 error = EBUSY; 759 goto out; 760 } 761 if (error = tsleep(&rc->rc_rcb, 762 TTIPRI|PCATCH, "rcbi", 0)) 763 goto out; 764 goto again; 765 } 766 } 767 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 768 error = EBUSY; 769 goto out; 770 } 771 } else { 772 tp->t_oproc = rc_start; 773 tp->t_param = rc_param; 774 tp->t_dev = dev; 775 776 if (CALLOUT(dev)) 777 tp->t_cflag |= CLOCAL; 778 else 779 tp->t_cflag &= ~CLOCAL; 780 781 error = rc_param(tp, &tp->t_termios); 782 if (error) 783 goto out; 784 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 785 786 ttsetwater(tp); 787 788 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 789 (*linesw[tp->t_line].l_modem)(tp, 1); 790 } 791 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 792 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 793 rc->rc_dcdwaits++; 794 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 795 rc->rc_dcdwaits--; 796 if (error != 0) 797 goto out; 798 goto again; 799 } 800 error = (*linesw[tp->t_line].l_open)(dev, tp); 801 disc_optim(tp, &tp->t_termios, rc); 802 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 803 rc->rc_flags |= RC_ACTOUT; 804out: 805 (void) splx(s); 806 807 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 808 rc_hardclose(rc); 809 810 return error; 811} 812 813static int 814rcclose(dev, flag, mode, p) 815 dev_t dev; 816 int flag, mode; 817 struct proc *p; 818{ 819 register struct rc_chans *rc; 820 register struct tty *tp; 821 int s, unit = GET_UNIT(dev); 822 823 if (unit >= NRC * CD180_NCHAN) 824 return ENXIO; 825 rc = &rc_chans[unit]; 826 tp = rc->rc_tp; 827#ifdef RCDEBUG 828 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 829#endif 830 s = spltty(); 831 (*linesw[tp->t_line].l_close)(tp, flag); 832 disc_optim(tp, &tp->t_termios, rc); 833 rcstop(tp, FREAD | FWRITE); 834 rc_hardclose(rc); 835 ttyclose(tp); 836 splx(s); 837 return 0; 838} 839 840static void rc_hardclose(rc) 841register struct rc_chans *rc; 842{ 843 register int s, nec = rc->rc_rcb->rcb_addr; 844 register struct tty *tp = rc->rc_tp; 845 846 s = spltty(); 847 rcout(CD180_CAR, rc->rc_chan); 848 849 /* Disable rx/tx intrs */ 850 rcout(CD180_IER, rc->rc_ier = 0); 851 if ( (tp->t_cflag & HUPCL) 852 || !(rc->rc_flags & RC_ACTOUT) 853 && !(rc->rc_msvr & MSVR_CD) 854 && !(tp->t_cflag & CLOCAL) 855 || !(tp->t_state & TS_ISOPEN) 856 ) { 857 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 858 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 859 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 860 if (rc->rc_dtrwait) { 861 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 862 rc->rc_flags |= RC_DTR_OFF; 863 } 864 } 865 rc->rc_flags &= ~RC_ACTOUT; 866 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 867 wakeup(TSA_CARR_ON(tp)); 868 (void) splx(s); 869} 870 871/* Read from line */ 872static int 873rcread(dev, uio, flag) 874 dev_t dev; 875 struct uio *uio; 876 int flag; 877{ 878 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 879 880 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 881} 882 883/* Write to line */ 884static int 885rcwrite(dev, uio, flag) 886 dev_t dev; 887 struct uio *uio; 888 int flag; 889{ 890 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 891 892 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 893} 894 895/* Reset the bastard */ 896static void rc_hwreset(unit, nec, chipid) 897 register int unit, nec; 898 unsigned int chipid; 899{ 900 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 901 DELAY(20000); 902 WAITFORCCR(unit, -1); 903 904 rcout(RC_CTOUT, 0); /* Clear timeout */ 905 rcout(CD180_GIVR, chipid); 906 rcout(CD180_GICR, 0); 907 908 /* Set Prescaler Registers (1 msec) */ 909 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 910 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 911 912 /* Initialize Priority Interrupt Level Registers */ 913 rcout(CD180_PILR1, RC_PILR_MODEM); 914 rcout(CD180_PILR2, RC_PILR_TX); 915 rcout(CD180_PILR3, RC_PILR_RX); 916 917 /* Reset DTR */ 918 rcout(RC_DTREG, ~0); 919} 920 921/* Set channel parameters */ 922static int rc_param(tp, ts) 923 register struct tty *tp; 924 struct termios *ts; 925{ 926 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 927 register int nec = rc->rc_rcb->rcb_addr; 928 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 929 930 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 931 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 932 ) 933 return (EINVAL); 934 if (ts->c_ispeed == 0) 935 ts->c_ispeed = ts->c_ospeed; 936 odivs = RC_BRD(ts->c_ospeed); 937 idivs = RC_BRD(ts->c_ispeed); 938 939 s = spltty(); 940 941 /* Select channel */ 942 rcout(CD180_CAR, rc->rc_chan); 943 944 /* If speed == 0, hangup line */ 945 if (ts->c_ospeed == 0) { 946 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 947 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 948 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 949 } 950 951 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 952 cflag = ts->c_cflag; 953 iflag = ts->c_iflag; 954 lflag = ts->c_lflag; 955 956 if (idivs > 0) { 957 rcout(CD180_RBPRL, idivs & 0xFF); 958 rcout(CD180_RBPRH, idivs >> 8); 959 } 960 if (odivs > 0) { 961 rcout(CD180_TBPRL, odivs & 0xFF); 962 rcout(CD180_TBPRH, odivs >> 8); 963 } 964 965 /* set timeout value */ 966 if (ts->c_ispeed > 0) { 967 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 968 969 if ( !(lflag & ICANON) 970 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 971 && ts->c_cc[VTIME] * 10 > itm) 972 itm = ts->c_cc[VTIME] * 10; 973 974 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 975 } 976 977 switch (cflag & CSIZE) { 978 case CS5: val = COR1_5BITS; break; 979 case CS6: val = COR1_6BITS; break; 980 case CS7: val = COR1_7BITS; break; 981 default: 982 case CS8: val = COR1_8BITS; break; 983 } 984 if (cflag & PARENB) { 985 val |= COR1_NORMPAR; 986 if (cflag & PARODD) 987 val |= COR1_ODDP; 988 if (!(cflag & INPCK)) 989 val |= COR1_Ignore; 990 } else 991 val |= COR1_Ignore; 992 if (cflag & CSTOPB) 993 val |= COR1_2SB; 994 rcout(CD180_COR1, val); 995 996 /* Set FIFO threshold */ 997 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 998 inpflow = 0; 999 if ( (iflag & IXOFF) 1000 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1001 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1002 || (iflag & IXANY) 1003 ) 1004 ) 1005 ) { 1006 inpflow = 1; 1007 val |= COR3_SCDE|COR3_FCT; 1008 } 1009 rcout(CD180_COR3, val); 1010 1011 /* Initialize on-chip automatic flow control */ 1012 val = 0; 1013 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1014 if (cflag & CCTS_OFLOW) { 1015 rc->rc_flags |= RC_CTSFLOW; 1016 val |= COR2_CtsAE; 1017 } else 1018 rc->rc_flags |= RC_SEND_RDY; 1019 if (tp->t_state & TS_TTSTOP) 1020 rc->rc_flags |= RC_OSUSP; 1021 else 1022 rc->rc_flags &= ~RC_OSUSP; 1023 if (cflag & CRTS_IFLOW) 1024 rc->rc_flags |= RC_RTSFLOW; 1025 else 1026 rc->rc_flags &= ~RC_RTSFLOW; 1027 1028 if (inpflow) { 1029 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1030 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1031 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1032 val |= COR2_TxIBE; 1033 if (iflag & IXANY) 1034 val |= COR2_IXM; 1035 } 1036 1037 rcout(CD180_COR2, rc->rc_cor2 = val); 1038 1039 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1040 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1041 1042 disc_optim(tp, ts, rc); 1043 1044 /* modem ctl */ 1045 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1046 if (cflag & CCTS_OFLOW) 1047 val |= MCOR1_CTSzd; 1048 rcout(CD180_MCOR1, val); 1049 1050 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1051 if (cflag & CCTS_OFLOW) 1052 val |= MCOR2_CTSod; 1053 rcout(CD180_MCOR2, val); 1054 1055 /* enable i/o and interrupts */ 1056 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1057 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1058 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1059 1060 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1061 if (cflag & CCTS_OFLOW) 1062 rc->rc_ier |= IER_CTS; 1063 if (cflag & CREAD) 1064 rc->rc_ier |= IER_RxData; 1065 if (tp->t_state & TS_BUSY) 1066 rc->rc_ier |= IER_TxRdy; 1067 if (ts->c_ospeed != 0) 1068 rc_modctl(rc, TIOCM_DTR, DMBIS); 1069 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1070 rc->rc_flags |= RC_SEND_RDY; 1071 rcout(CD180_IER, rc->rc_ier); 1072 (void) splx(s); 1073 return 0; 1074} 1075 1076/* Re-initialize board after bogus interrupts */ 1077static void rc_reinit(rcb) 1078struct rc_softc *rcb; 1079{ 1080 register struct rc_chans *rc, *rce; 1081 register int nec; 1082 1083 nec = rcb->rcb_addr; 1084 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1085 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1086 rce = rc + CD180_NCHAN; 1087 for (; rc < rce; rc++) 1088 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1089} 1090 1091static int 1092rcioctl(dev, cmd, data, flag, p) 1093dev_t dev; 1094int cmd, flag; 1095caddr_t data; 1096struct proc *p; 1097{ 1098 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1099 register int s, error; 1100 struct tty *tp = rc->rc_tp; 1101 1102 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1103 if (error >= 0) 1104 return (error); 1105 error = ttioctl(tp, cmd, data, flag); 1106 disc_optim(tp, &tp->t_termios, rc); 1107 if (error >= 0) 1108 return (error); 1109 s = spltty(); 1110 1111 switch (cmd) { 1112 case TIOCSBRK: 1113 rc->rc_pendcmd = CD180_C_SBRK; 1114 break; 1115 1116 case TIOCCBRK: 1117 rc->rc_pendcmd = CD180_C_EBRK; 1118 break; 1119 1120 case TIOCSDTR: 1121 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1122 break; 1123 1124 case TIOCCDTR: 1125 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1126 break; 1127 1128 case TIOCMGET: 1129 *(int *) data = rc_modctl(rc, 0, DMGET); 1130 break; 1131 1132 case TIOCMSET: 1133 (void) rc_modctl(rc, *(int *) data, DMSET); 1134 break; 1135 1136 case TIOCMBIC: 1137 (void) rc_modctl(rc, *(int *) data, DMBIC); 1138 break; 1139 1140 case TIOCMBIS: 1141 (void) rc_modctl(rc, *(int *) data, DMBIS); 1142 break; 1143 1144 case TIOCMSDTRWAIT: 1145 error = suser(p->p_ucred, &p->p_acflag); 1146 if (error != 0) { 1147 splx(s); 1148 return (error); 1149 } 1150 rc->rc_dtrwait = *(int *)data * hz / 100; 1151 break; 1152 1153 case TIOCMGDTRWAIT: 1154 *(int *)data = rc->rc_dtrwait * 100 / hz; 1155 break; 1156 1157 default: 1158 (void) splx(s); 1159 return ENOTTY; 1160 } 1161 (void) splx(s); 1162 return 0; 1163} 1164 1165 1166/* Modem control routines */ 1167 1168static int rc_modctl(rc, bits, cmd) 1169register struct rc_chans *rc; 1170int bits, cmd; 1171{ 1172 register int nec = rc->rc_rcb->rcb_addr; 1173 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1174 1175 rcout(CD180_CAR, rc->rc_chan); 1176 1177 switch (cmd) { 1178 case DMSET: 1179 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1180 ~(*dtr |= 1 << rc->rc_chan) : 1181 ~(*dtr &= ~(1 << rc->rc_chan))); 1182 msvr = rcin(CD180_MSVR); 1183 if (bits & TIOCM_RTS) 1184 msvr |= MSVR_RTS; 1185 else 1186 msvr &= ~MSVR_RTS; 1187 if (bits & TIOCM_DTR) 1188 msvr |= MSVR_DTR; 1189 else 1190 msvr &= ~MSVR_DTR; 1191 rcout(CD180_MSVR, msvr); 1192 break; 1193 1194 case DMBIS: 1195 if (bits & TIOCM_DTR) 1196 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1197 msvr = rcin(CD180_MSVR); 1198 if (bits & TIOCM_RTS) 1199 msvr |= MSVR_RTS; 1200 if (bits & TIOCM_DTR) 1201 msvr |= MSVR_DTR; 1202 rcout(CD180_MSVR, msvr); 1203 break; 1204 1205 case DMGET: 1206 bits = TIOCM_LE; 1207 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1208 1209 if (msvr & MSVR_RTS) 1210 bits |= TIOCM_RTS; 1211 if (msvr & MSVR_CTS) 1212 bits |= TIOCM_CTS; 1213 if (msvr & MSVR_DSR) 1214 bits |= TIOCM_DSR; 1215 if (msvr & MSVR_DTR) 1216 bits |= TIOCM_DTR; 1217 if (msvr & MSVR_CD) 1218 bits |= TIOCM_CD; 1219 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1220 bits |= TIOCM_RI; 1221 return bits; 1222 1223 case DMBIC: 1224 if (bits & TIOCM_DTR) 1225 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1226 msvr = rcin(CD180_MSVR); 1227 if (bits & TIOCM_RTS) 1228 msvr &= ~MSVR_RTS; 1229 if (bits & TIOCM_DTR) 1230 msvr &= ~MSVR_DTR; 1231 rcout(CD180_MSVR, msvr); 1232 break; 1233 } 1234 rc->rc_msvr = rcin(CD180_MSVR); 1235 return 0; 1236} 1237 1238/* Test the board. */ 1239int rc_test(nec, unit) 1240 register int nec; 1241 int unit; 1242{ 1243 int chan = 0; 1244 int i = 0, rcnt, old_level; 1245 unsigned int iack, chipid; 1246 unsigned short divs; 1247 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1248#define CTLEN 8 1249#define ERR(s) { \ 1250 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1251 (void) splx(old_level); return 1; } 1252 1253 struct rtest { 1254 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1255 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1256 int rxptr; /* RX pointer */ 1257 int txptr; /* TX pointer */ 1258 } tchans[CD180_NCHAN]; 1259 1260 old_level = spltty(); 1261 1262 chipid = RC_FAKEID; 1263 1264 /* First, reset board to inital state */ 1265 rc_hwreset(unit, nec, chipid); 1266 1267 divs = RC_BRD(19200); 1268 1269 /* Initialize channels */ 1270 for (chan = 0; chan < CD180_NCHAN; chan++) { 1271 1272 /* Select and reset channel */ 1273 rcout(CD180_CAR, chan); 1274 CCRCMD(unit, chan, CCR_ResetChan); 1275 WAITFORCCR(unit, chan); 1276 1277 /* Set speed */ 1278 rcout(CD180_RBPRL, divs & 0xFF); 1279 rcout(CD180_RBPRH, divs >> 8); 1280 rcout(CD180_TBPRL, divs & 0xFF); 1281 rcout(CD180_TBPRH, divs >> 8); 1282 1283 /* set timeout value */ 1284 rcout(CD180_RTPR, 0); 1285 1286 /* Establish local loopback */ 1287 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1288 rcout(CD180_COR2, COR2_LLM); 1289 rcout(CD180_COR3, CD180_NFIFO); 1290 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1291 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1292 WAITFORCCR(unit, chan); 1293 rcout(CD180_MSVR, MSVR_RTS); 1294 1295 /* Fill TXBUF with test data */ 1296 for (i = 0; i < CD180_NFIFO; i++) { 1297 tchans[chan].txbuf[i] = ctest[i]; 1298 tchans[chan].rxbuf[i] = 0; 1299 } 1300 tchans[chan].txptr = tchans[chan].rxptr = 0; 1301 1302 /* Now, start transmit */ 1303 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1304 } 1305 /* Pseudo-interrupt poll stuff */ 1306 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1307 i = ~(rcin(RC_BSR)); 1308 if (i & RC_BSR_TOUT) 1309 ERR(("BSR timeout bit set\n")) 1310 else if (i & RC_BSR_TXINT) { 1311 iack = rcin(RC_PILR_TX); 1312 if (iack != (GIVR_IT_TDI | chipid)) 1313 ERR(("Bad TX intr ack (%02x != %02x)\n", 1314 iack, GIVR_IT_TDI | chipid)); 1315 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1316 /* If no more data to transmit, disable TX intr */ 1317 if (tchans[chan].txptr >= CD180_NFIFO) { 1318 iack = rcin(CD180_IER); 1319 rcout(CD180_IER, iack & ~IER_TxMpty); 1320 } else { 1321 for (iack = tchans[chan].txptr; 1322 iack < CD180_NFIFO; iack++) 1323 rcout(CD180_TDR, 1324 tchans[chan].txbuf[iack]); 1325 tchans[chan].txptr = iack; 1326 } 1327 rcout(CD180_EOIR, 0); 1328 } else if (i & RC_BSR_RXINT) { 1329 u_char ucnt; 1330 1331 iack = rcin(RC_PILR_RX); 1332 if (iack != (GIVR_IT_RGDI | chipid) && 1333 iack != (GIVR_IT_REI | chipid)) 1334 ERR(("Bad RX intr ack (%02x != %02x)\n", 1335 iack, GIVR_IT_RGDI | chipid)) 1336 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1337 ucnt = rcin(CD180_RDCR) & 0xF; 1338 while (ucnt-- > 0) { 1339 iack = rcin(CD180_RCSR); 1340 if (iack & RCSR_Timeout) 1341 break; 1342 if (iack & 0xF) 1343 ERR(("Bad char chan %d (RCSR = %02X)\n", 1344 chan, iack)) 1345 if (tchans[chan].rxptr > CD180_NFIFO) 1346 ERR(("Got extra chars chan %d\n", 1347 chan)) 1348 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1349 rcin(CD180_RDR); 1350 } 1351 rcout(CD180_EOIR, 0); 1352 } 1353 rcout(RC_CTOUT, 0); 1354 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1355 if (tchans[chan].rxptr >= CD180_NFIFO) 1356 iack++; 1357 if (iack == CD180_NCHAN) 1358 break; 1359 } 1360 for (chan = 0; chan < CD180_NCHAN; chan++) { 1361 /* Select and reset channel */ 1362 rcout(CD180_CAR, chan); 1363 CCRCMD(unit, chan, CCR_ResetChan); 1364 } 1365 1366 if (!rcnt) 1367 ERR(("looses characters during local loopback\n")) 1368 /* Now, check data */ 1369 for (chan = 0; chan < CD180_NCHAN; chan++) 1370 for (i = 0; i < CD180_NFIFO; i++) 1371 if (ctest[i] != tchans[chan].rxbuf[i]) 1372 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1373 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1374 (void) splx(old_level); 1375 return 0; 1376} 1377 1378#ifdef RCDEBUG 1379static void printrcflags(rc, comment) 1380struct rc_chans *rc; 1381char *comment; 1382{ 1383 u_short f = rc->rc_flags; 1384 register int nec = rc->rc_rcb->rcb_addr; 1385 1386 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1387 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1388 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1389 (f & RC_ACTOUT) ?"ACTOUT " :"", 1390 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1391 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1392 (f & RC_DORXFER)?"DORXFER " :"", 1393 (f & RC_DOXXFER)?"DOXXFER " :"", 1394 (f & RC_MODCHG) ?"MODCHG " :"", 1395 (f & RC_OSUSP) ?"OSUSP " :"", 1396 (f & RC_OSBUSY) ?"OSBUSY " :"", 1397 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1398 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1399 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1400 1401 rcout(CD180_CAR, rc->rc_chan); 1402 1403 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1404 rc->rc_rcb->rcb_unit, rc->rc_chan, 1405 rcin(CD180_MSVR), 1406 rcin(CD180_IER), 1407 rcin(CD180_CCSR)); 1408} 1409#endif /* RCDEBUG */ 1410 1411static struct tty * 1412rcdevtotty(dev) 1413 dev_t dev; 1414{ 1415 int unit; 1416 1417 unit = GET_UNIT(dev); 1418 if (unit >= NRC * CD180_NCHAN) 1419 return NULL; 1420 return (&rc_tty[unit]); 1421} 1422 1423static void 1424rc_dtrwakeup(chan) 1425 void *chan; 1426{ 1427 struct rc_chans *rc; 1428 1429 rc = (struct rc_chans *)chan; 1430 rc->rc_flags &= ~RC_DTR_OFF; 1431 wakeup(&rc->rc_dtrwait); 1432} 1433 1434static void 1435rc_discard_output(rc) 1436 struct rc_chans *rc; 1437{ 1438 disable_intr(); 1439 if (rc->rc_flags & RC_DOXXFER) { 1440 rc_scheduled_event -= LOTS_OF_EVENTS; 1441 rc->rc_flags &= ~RC_DOXXFER; 1442 } 1443 rc->rc_optr = rc->rc_obufend; 1444 rc->rc_tp->t_state &= ~TS_BUSY; 1445 enable_intr(); 1446 ttwwakeup(rc->rc_tp); 1447} 1448 1449static void 1450rc_wakeup(chan) 1451 void *chan; 1452{ 1453 timeout(rc_wakeup, (caddr_t)NULL, 1); 1454 1455 if (rc_scheduled_event != 0) { 1456 int s; 1457 1458 s = splsofttty(); 1459 rcpoll(); 1460 splx(s); 1461 } 1462} 1463 1464static void 1465disc_optim(tp, t, rc) 1466 struct tty *tp; 1467 struct termios *t; 1468 struct rc_chans *rc; 1469{ 1470 1471 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1472 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1473 && (!(t->c_iflag & PARMRK) 1474 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1475 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1476 && linesw[tp->t_line].l_rint == ttyinput) 1477 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1478 else 1479 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1480 if (tp->t_line == SLIPDISC) 1481 rc->rc_hotchar = 0xc0; 1482 else if (tp->t_line == PPPDISC) 1483 rc->rc_hotchar = 0x7e; 1484 else 1485 rc->rc_hotchar = 0; 1486} 1487 1488static void 1489rc_wait0(nec, unit, chan, line) 1490 int nec, unit, chan, line; 1491{ 1492 int rcnt; 1493 1494 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1495 DELAY(30); 1496 if (rcnt == 0) 1497 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1498 unit, chan, line); 1499} 1500 1501static rc_devsw_installed = 0; 1502 1503static void rc_drvinit(void *unused) 1504{ 1505 dev_t dev; 1506 1507 if( ! rc_devsw_installed ) { 1508 dev = makedev(CDEV_MAJOR, 0); 1509 cdevsw_add(&dev,&rc_cdevsw, NULL); 1510 rc_devsw_installed = 1; 1511 } 1512} 1513 1514SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1515 1516 1517#endif /* NRC */ 1518