rc.c revision 16471
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#include <sys/devconf.h> 50#ifdef DEVFS 51#include <sys/devfsext.h> 52#endif /*DEVFS*/ 53 54#include <machine/clock.h> 55 56#include <i386/isa/isa_device.h> 57#include <i386/isa/sioreg.h> 58 59#include <i386/isa/ic/cd180.h> 60#include <i386/isa/rcreg.h> 61 62 63/* Prototypes */ 64static int rcprobe __P((struct isa_device *)); 65static int rcattach __P((struct isa_device *)); 66 67/*- 68 * This space intentionally left blank to stop __LINE__ from screwing up 69 * regression tests :-(. 70 * 71 * 72 * 73 */ 74void rcpoll __P((void)); 75 76#define rcin(port) RC_IN (nec, port) 77#define rcout(port,v) RC_OUT (nec, port, v) 78 79#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 80#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 81 82#define RC_IBUFSIZE 256 83#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 84#define RC_OBUFSIZE 512 85#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 86#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 87#define LOTS_OF_EVENTS 64 88 89#define RC_FAKEID 0x10 90 91#define RC_PROBED 1 92#define RC_ATTACHED 2 93 94#define GET_UNIT(dev) (minor(dev) & 0x3F) 95#define CALLOUT(dev) (minor(dev) & 0x80) 96 97/* For isa routines */ 98struct isa_driver rcdriver = { 99 rcprobe, rcattach, "rc" 100}; 101 102static d_open_t rcopen; 103static d_close_t rcclose; 104static d_read_t rcread; 105static d_write_t rcwrite; 106static d_ioctl_t rcioctl; 107static d_stop_t rcstop; 108static d_devtotty_t rcdevtotty; 109 110#define CDEV_MAJOR 63 111static struct cdevsw rc_cdevsw = 112 { rcopen, rcclose, rcread, rcwrite, /*63*/ 113 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 114 ttselect, nommap, NULL, "rc", NULL, -1 }; 115 116/* Per-board structure */ 117static struct rc_softc { 118 u_int rcb_probed; /* 1 - probed, 2 - attached */ 119 u_int rcb_addr; /* Base I/O addr */ 120 u_int rcb_unit; /* unit # */ 121 u_char rcb_dtr; /* DTR status */ 122 struct rc_chans *rcb_baserc; /* base rc ptr */ 123} rc_softc[NRC]; 124 125/* Per-channel structure */ 126static struct rc_chans { 127 struct rc_softc *rc_rcb; /* back ptr */ 128 u_short rc_flags; /* Misc. flags */ 129 int rc_chan; /* Channel # */ 130 u_char rc_ier; /* intr. enable reg */ 131 u_char rc_msvr; /* modem sig. status */ 132 u_char rc_cor2; /* options reg */ 133 u_char rc_pendcmd; /* special cmd pending */ 134 u_int rc_dtrwait; /* dtr timeout */ 135 u_int rc_dcdwaits; /* how many waits DCD in open */ 136 u_char rc_hotchar; /* end packed optimize */ 137 struct tty *rc_tp; /* tty struct */ 138 u_char *rc_iptr; /* Chars input buffer */ 139 u_char *rc_hiwat; /* hi-water mark */ 140 u_char *rc_bufend; /* end of buffer */ 141 u_char *rc_optr; /* ptr in output buf */ 142 u_char *rc_obufend; /* end of output buf */ 143 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 144 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 145#ifdef DEVFS 146 void *devfs_token; 147#endif 148} rc_chans[NRC * CD180_NCHAN]; 149 150static int rc_scheduled_event = 0; 151 152/* for pstat -t */ 153static struct tty rc_tty[NRC * CD180_NCHAN]; 154static const int nrc_tty = NRC * CD180_NCHAN; 155 156/* Flags */ 157#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 158#define RC_ACTOUT 0x0002 /* Dial-out port active */ 159#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 160#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 161#define RC_DORXFER 0x0010 /* RXFER event planned */ 162#define RC_DOXXFER 0x0020 /* XXFER event planned */ 163#define RC_MODCHG 0x0040 /* Modem status changed */ 164#define RC_OSUSP 0x0080 /* Output suspended */ 165#define RC_OSBUSY 0x0100 /* start() routine in progress */ 166#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 167#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 168#define RC_SEND_RDY 0x0800 /* ready to send */ 169 170/* Table for translation of RCSR status bits to internal form */ 171static int rc_rcsrt[16] = { 172 0, TTY_OE, TTY_FE, 173 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 174 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 175 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 176 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 177 TTY_BI|TTY_PE|TTY_FE|TTY_OE 178}; 179 180/* Static prototypes */ 181static void rc_hwreset __P((int, int, unsigned int)); 182static int rc_test __P((int, int)); 183static void rc_discard_output __P((struct rc_chans *)); 184static void rc_hardclose __P((struct rc_chans *)); 185static int rc_modctl __P((struct rc_chans *, int, int)); 186static void rc_start __P((struct tty *)); 187static int rc_param __P((struct tty *, struct termios *)); 188static void rc_registerdev __P((struct isa_device *id)); 189static void rc_reinit __P((struct rc_softc *)); 190#ifdef RCDEBUG 191static void printrcflags(); 192#endif 193static timeout_t rc_dtrwakeup; 194static timeout_t rc_wakeup; 195static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 196static void rc_wait0 __P((int nec, int unit, int chan, int line)); 197 198/**********************************************/ 199 200/* Quick device probing */ 201static int 202rcprobe(dvp) 203 struct isa_device *dvp; 204{ 205 int irq = ffs(dvp->id_irq) - 1; 206 register int nec = dvp->id_iobase; 207 208 if (dvp->id_unit > NRC) 209 return 0; 210 if (!RC_VALIDADDR(nec)) { 211 printf("rc%d: illegal base address %x\n", nec); 212 return 0; 213 } 214 if (!RC_VALIDIRQ(irq)) { 215 printf("rc%d: illegal IRQ value %d\n", irq); 216 return 0; 217 } 218 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 219 rcout(CD180_PPRH, 0x11); 220 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 221 return 0; 222 /* Now, test the board more thoroughly, with diagnostic */ 223 if (rc_test(nec, dvp->id_unit)) 224 return 0; 225 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 226 227 return 0xF; 228} 229 230static struct kern_devconf kdc_rc[NRC] = { { 231 0, 0, 0, /* filled in by dev_attach */ 232 "rc", 0, { MDDT_ISA, 0, "tty" }, 233 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 234 &kdc_isa0, /* parent */ 235 0, /* parentdata */ 236 DC_UNCONFIGURED, /* state */ 237 "RISCom/8 multiport card", 238 DC_CLS_SERIAL /* class */ 239} }; 240 241static void 242rc_registerdev(id) 243 struct isa_device *id; 244{ 245 int unit; 246 247 unit = id->id_unit; 248 if (unit != 0) 249 kdc_rc[unit] = kdc_rc[0]; 250 kdc_rc[unit].kdc_unit = unit; 251 kdc_rc[unit].kdc_isa = id; 252 kdc_rc[unit].kdc_state = DC_UNKNOWN; 253 dev_attach(&kdc_rc[unit]); 254} 255 256static int 257rcattach(dvp) 258 struct isa_device *dvp; 259{ 260 register int chan, nec = dvp->id_iobase; 261 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 262 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 263 static int rc_wakeup_started = 0; 264 struct tty *tp; 265 266 /* Thorooughly test the device */ 267 if (rcb->rcb_probed != RC_PROBED) 268 return 0; 269 rcb->rcb_addr = nec; 270 rcb->rcb_dtr = 0; 271 rcb->rcb_baserc = rc; 272 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 273 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 274 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 275 276 rc_registerdev(dvp); 277 278 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 279 rc->rc_rcb = rcb; 280 rc->rc_chan = chan; 281 rc->rc_iptr = rc->rc_ibuf; 282 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 283 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 284 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 285 rc->rc_cor2 = rc->rc_pendcmd = 0; 286 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 287 rc->rc_dtrwait = 3 * hz; 288 rc->rc_dcdwaits= 0; 289 rc->rc_hotchar = 0; 290 tp = rc->rc_tp = &rc_tty[chan]; 291 ttychars(tp); 292 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 293 tp->t_cflag = TTYDEF_CFLAG; 294 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 295#ifdef DEVFS 296/* FIX THIS to reflect real devices */ 297 rc->devfs_token = 298 devfs_add_devswf(&rc_cdevsw, 299 (dvp->id_unit * CD180_NCHAN) + chan, 300 DV_CHR, 0, 0, 0600, "rc%d.%d", 301 dvp->id_unit, chan); 302#endif 303 } 304 rcb->rcb_probed = RC_ATTACHED; 305 if (!rc_wakeup_started) { 306 rc_wakeup((void *)NULL); 307 rc_wakeup_started = 0; 308 } 309 return 1; 310} 311 312/* RC interrupt handling */ 313void rcintr(unit) 314 int unit; 315{ 316 register struct rc_softc *rcb = &rc_softc[unit]; 317 register struct rc_chans *rc; 318 register int nec, resid; 319 register u_char val, iack, bsr, ucnt, *optr; 320 int good_data, t_state; 321 322 if (rcb->rcb_probed != RC_ATTACHED) { 323 printf("rc%d: bogus interrupt\n", unit); 324 return; 325 } 326 nec = rcb->rcb_addr; 327 328 bsr = ~(rcin(RC_BSR)); 329 330 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 331 printf("rc%d: extra interrupt\n", unit); 332 rcout(CD180_EOIR, 0); 333 return; 334 } 335 336 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 337#ifdef RCDEBUG_DETAILED 338 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 339 (bsr & RC_BSR_TOUT)?"TOUT ":"", 340 (bsr & RC_BSR_RXINT)?"RXINT ":"", 341 (bsr & RC_BSR_TXINT)?"TXINT ":"", 342 (bsr & RC_BSR_MOINT)?"MOINT":""); 343#endif 344 if (bsr & RC_BSR_TOUT) { 345 printf("rc%d: hardware failure, reset board\n", unit); 346 rcout(RC_CTOUT, 0); 347 rc_reinit(rcb); 348 return; 349 } 350 if (bsr & RC_BSR_RXINT) { 351 iack = rcin(RC_PILR_RX); 352 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 353 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 354 printf("rc%d: fake rxint: %02x\n", unit, iack); 355 goto more_intrs; 356 } 357 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 358 t_state = rc->rc_tp->t_state; 359 /* Do RTS flow control stuff */ 360 if ( (rc->rc_flags & RC_RTSFLOW) 361 || !(t_state & TS_ISOPEN) 362 ) { 363 if ( ( !(t_state & TS_ISOPEN) 364 || (t_state & TS_TBLOCK) 365 ) 366 && (rc->rc_msvr & MSVR_RTS) 367 ) 368 rcout(CD180_MSVR, 369 rc->rc_msvr &= ~MSVR_RTS); 370 else if (!(rc->rc_msvr & MSVR_RTS)) 371 rcout(CD180_MSVR, 372 rc->rc_msvr |= MSVR_RTS); 373 } 374 ucnt = rcin(CD180_RDCR) & 0xF; 375 resid = 0; 376 377 if (t_state & TS_ISOPEN) { 378 /* check for input buffer overflow */ 379 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 380 resid = ucnt; 381 ucnt = rc->rc_bufend - rc->rc_iptr; 382 resid -= ucnt; 383 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 384 rc->rc_flags |= RC_WAS_BUFOVFL; 385 rc_scheduled_event++; 386 } 387 } 388 optr = rc->rc_iptr; 389 /* check foor good data */ 390 if (good_data) { 391 while (ucnt-- > 0) { 392 val = rcin(CD180_RDR); 393 optr[0] = val; 394 optr[INPUT_FLAGS_SHIFT] = 0; 395 optr++; 396 rc_scheduled_event++; 397 if (val != 0 && val == rc->rc_hotchar) 398 setsofttty(); 399 } 400 } else { 401 /* Store also status data */ 402 while (ucnt-- > 0) { 403 iack = rcin(CD180_RCSR); 404 if (iack & RCSR_Timeout) 405 break; 406 if ( (iack & RCSR_OE) 407 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 408 rc->rc_flags |= RC_WAS_SILOVFL; 409 rc_scheduled_event++; 410 } 411 val = rcin(CD180_RDR); 412 /* 413 Don't store PE if IGNPAR and BREAK if IGNBRK, 414 this hack allows "raw" tty optimization 415 works even if IGN* is set. 416 */ 417 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 418 || (!(iack & (RCSR_PE|RCSR_FE)) 419 || !(rc->rc_tp->t_iflag & IGNPAR)) 420 && (!(iack & RCSR_Break) 421 || !(rc->rc_tp->t_iflag & IGNBRK))) { 422 if ( (iack & (RCSR_PE|RCSR_FE)) 423 && (t_state & TS_CAN_BYPASS_L_RINT) 424 && ((iack & RCSR_FE) 425 || (iack & RCSR_PE) 426 && (rc->rc_tp->t_iflag & INPCK))) 427 val = 0; 428 else if (val != 0 && val == rc->rc_hotchar) 429 setsofttty(); 430 optr[0] = val; 431 optr[INPUT_FLAGS_SHIFT] = iack; 432 optr++; 433 rc_scheduled_event++; 434 } 435 } 436 } 437 rc->rc_iptr = optr; 438 rc->rc_flags |= RC_DORXFER; 439 } else 440 resid = ucnt; 441 /* Clear FIFO if necessary */ 442 while (resid-- > 0) { 443 if (!good_data) 444 iack = rcin(CD180_RCSR); 445 else 446 iack = 0; 447 if (iack & RCSR_Timeout) 448 break; 449 (void) rcin(CD180_RDR); 450 } 451 goto more_intrs; 452 } 453 if (bsr & RC_BSR_MOINT) { 454 iack = rcin(RC_PILR_MODEM); 455 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 456 printf("rc%d: fake moint: %02x\n", unit, iack); 457 goto more_intrs; 458 } 459 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 460 iack = rcin(CD180_MCR); 461 rc->rc_msvr = rcin(CD180_MSVR); 462 rcout(CD180_MCR, 0); 463#ifdef RCDEBUG 464 printrcflags(rc, "moint"); 465#endif 466 if (rc->rc_flags & RC_CTSFLOW) { 467 if (rc->rc_msvr & MSVR_CTS) 468 rc->rc_flags |= RC_SEND_RDY; 469 else 470 rc->rc_flags &= ~RC_SEND_RDY; 471 } else 472 rc->rc_flags |= RC_SEND_RDY; 473 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 474 rc_scheduled_event += LOTS_OF_EVENTS; 475 rc->rc_flags |= RC_MODCHG; 476 setsofttty(); 477 } 478 goto more_intrs; 479 } 480 if (bsr & RC_BSR_TXINT) { 481 iack = rcin(RC_PILR_TX); 482 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 483 printf("rc%d: fake txint: %02x\n", unit, iack); 484 goto more_intrs; 485 } 486 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 487 if ( (rc->rc_flags & RC_OSUSP) 488 || !(rc->rc_flags & RC_SEND_RDY) 489 ) 490 goto more_intrs; 491 /* Handle breaks and other stuff */ 492 if (rc->rc_pendcmd) { 493 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 494 rcout(CD180_TDR, CD180_C_ESC); 495 rcout(CD180_TDR, rc->rc_pendcmd); 496 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 497 rc->rc_pendcmd = 0; 498 goto more_intrs; 499 } 500 optr = rc->rc_optr; 501 resid = rc->rc_obufend - optr; 502 if (resid > CD180_NFIFO) 503 resid = CD180_NFIFO; 504 while (resid-- > 0) 505 rcout(CD180_TDR, *optr++); 506 rc->rc_optr = optr; 507 508 /* output completed? */ 509 if (optr >= rc->rc_obufend) { 510 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 511#ifdef RCDEBUG 512 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 513#endif 514 if (!(rc->rc_flags & RC_DOXXFER)) { 515 rc_scheduled_event += LOTS_OF_EVENTS; 516 rc->rc_flags |= RC_DOXXFER; 517 setsofttty(); 518 } 519 } 520 } 521 more_intrs: 522 rcout(CD180_EOIR, 0); /* end of interrupt */ 523 rcout(RC_CTOUT, 0); 524 bsr = ~(rcin(RC_BSR)); 525 } 526} 527 528/* Feed characters to output buffer */ 529static void rc_start(tp) 530register struct tty *tp; 531{ 532 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 533 register int nec = rc->rc_rcb->rcb_addr, s; 534 535 if (rc->rc_flags & RC_OSBUSY) 536 return; 537 s = spltty(); 538 rc->rc_flags |= RC_OSBUSY; 539 disable_intr(); 540 if (tp->t_state & TS_TTSTOP) 541 rc->rc_flags |= RC_OSUSP; 542 else 543 rc->rc_flags &= ~RC_OSUSP; 544 /* Do RTS flow control stuff */ 545 if ( (rc->rc_flags & RC_RTSFLOW) 546 && (tp->t_state & TS_TBLOCK) 547 && (rc->rc_msvr & MSVR_RTS) 548 ) { 549 rcout(CD180_CAR, rc->rc_chan); 550 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 551 } else if (!(rc->rc_msvr & MSVR_RTS)) { 552 rcout(CD180_CAR, rc->rc_chan); 553 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 554 } 555 enable_intr(); 556 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 557 goto out; 558#ifdef RCDEBUG 559 printrcflags(rc, "rcstart"); 560#endif 561 ttwwakeup(tp); 562#ifdef RCDEBUG 563 printf("rcstart: outq = %d obuf = %d\n", 564 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 565#endif 566 if (tp->t_state & TS_BUSY) 567 goto out; /* output still in progress ... */ 568 569 if (tp->t_outq.c_cc > 0) { 570 u_int ocnt; 571 572 tp->t_state |= TS_BUSY; 573 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 574 disable_intr(); 575 rc->rc_optr = rc->rc_obuf; 576 rc->rc_obufend = rc->rc_optr + ocnt; 577 enable_intr(); 578 if (!(rc->rc_ier & IER_TxRdy)) { 579#ifdef RCDEBUG 580 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 581#endif 582 rcout(CD180_CAR, rc->rc_chan); 583 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 584 } 585 } 586out: 587 rc->rc_flags &= ~RC_OSBUSY; 588 (void) splx(s); 589} 590 591/* Handle delayed events. */ 592void rcpoll() 593{ 594 register struct rc_chans *rc; 595 register struct rc_softc *rcb; 596 register u_char *tptr, *eptr; 597 register struct tty *tp; 598 register int chan, icnt, nec, unit; 599 600 if (rc_scheduled_event == 0) 601 return; 602repeat: 603 for (unit = 0; unit < NRC; unit++) { 604 rcb = &rc_softc[unit]; 605 rc = rcb->rcb_baserc; 606 nec = rc->rc_rcb->rcb_addr; 607 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 608 tp = rc->rc_tp; 609#ifdef RCDEBUG 610 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 611 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 612 printrcflags(rc, "rcevent"); 613#endif 614 if (rc->rc_flags & RC_WAS_BUFOVFL) { 615 disable_intr(); 616 rc->rc_flags &= ~RC_WAS_BUFOVFL; 617 rc_scheduled_event--; 618 enable_intr(); 619 printf("rc%d/%d: interrupt-level buffer overflow\n", 620 unit, chan); 621 } 622 if (rc->rc_flags & RC_WAS_SILOVFL) { 623 disable_intr(); 624 rc->rc_flags &= ~RC_WAS_SILOVFL; 625 rc_scheduled_event--; 626 enable_intr(); 627 printf("rc%d/%d: silo overflow\n", 628 unit, chan); 629 } 630 if (rc->rc_flags & RC_MODCHG) { 631 disable_intr(); 632 rc->rc_flags &= ~RC_MODCHG; 633 rc_scheduled_event -= LOTS_OF_EVENTS; 634 enable_intr(); 635 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 636 } 637 if (rc->rc_flags & RC_DORXFER) { 638 disable_intr(); 639 rc->rc_flags &= ~RC_DORXFER; 640 eptr = rc->rc_iptr; 641 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 642 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 643 else 644 tptr = rc->rc_ibuf; 645 icnt = eptr - tptr; 646 if (icnt > 0) { 647 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 648 rc->rc_iptr = rc->rc_ibuf; 649 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 650 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 651 } else { 652 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 653 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 654 rc->rc_hiwat = 655 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 656 } 657 if ( (rc->rc_flags & RC_RTSFLOW) 658 && (tp->t_state & TS_ISOPEN) 659 && !(tp->t_state & TS_TBLOCK) 660 && !(rc->rc_msvr & MSVR_RTS) 661 ) { 662 rcout(CD180_CAR, chan); 663 rcout(CD180_MSVR, 664 rc->rc_msvr |= MSVR_RTS); 665 } 666 rc_scheduled_event -= icnt; 667 } 668 enable_intr(); 669 670 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 671 goto done1; 672 673 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 674 && !(tp->t_state & TS_LOCAL)) { 675 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 676 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 677 && !(tp->t_state & TS_TBLOCK)) 678 ttyblock(tp); 679 tk_nin += icnt; 680 tk_rawcc += icnt; 681 tp->t_rawcc += icnt; 682 if (b_to_q(tptr, icnt, &tp->t_rawq)) 683 printf("rc%d/%d: tty-level buffer overflow\n", 684 unit, chan); 685 ttwakeup(tp); 686 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 687 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 688 tp->t_state &= ~TS_TTSTOP; 689 tp->t_lflag &= ~FLUSHO; 690 rc_start(tp); 691 } 692 } else { 693 for (; tptr < eptr; tptr++) 694 (*linesw[tp->t_line].l_rint) 695 (tptr[0] | 696 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 697 } 698done1: 699 } 700 if (rc->rc_flags & RC_DOXXFER) { 701 disable_intr(); 702 rc_scheduled_event -= LOTS_OF_EVENTS; 703 rc->rc_flags &= ~RC_DOXXFER; 704 rc->rc_tp->t_state &= ~TS_BUSY; 705 enable_intr(); 706 (*linesw[tp->t_line].l_start)(tp); 707 } 708 } 709 if (rc_scheduled_event == 0) 710 break; 711 } 712 if (rc_scheduled_event >= LOTS_OF_EVENTS) 713 goto repeat; 714} 715 716static void 717rcstop(tp, rw) 718 register struct tty *tp; 719 int rw; 720{ 721 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 722 u_char *tptr, *eptr; 723 724#ifdef RCDEBUG 725 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 726 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 727#endif 728 if (rw & FWRITE) 729 rc_discard_output(rc); 730 disable_intr(); 731 if (rw & FREAD) { 732 rc->rc_flags &= ~RC_DORXFER; 733 eptr = rc->rc_iptr; 734 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 735 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 736 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 737 } else { 738 tptr = rc->rc_ibuf; 739 rc->rc_iptr = rc->rc_ibuf; 740 } 741 rc_scheduled_event -= eptr - tptr; 742 } 743 if (tp->t_state & TS_TTSTOP) 744 rc->rc_flags |= RC_OSUSP; 745 else 746 rc->rc_flags &= ~RC_OSUSP; 747 enable_intr(); 748} 749 750static int 751rcopen(dev, flag, mode, p) 752 dev_t dev; 753 int flag, mode; 754 struct proc *p; 755{ 756 register struct rc_chans *rc; 757 register struct tty *tp; 758 int unit, nec, s, error = 0; 759 760 unit = GET_UNIT(dev); 761 if (unit >= NRC * CD180_NCHAN) 762 return ENXIO; 763 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 764 return ENXIO; 765 rc = &rc_chans[unit]; 766 tp = rc->rc_tp; 767 nec = rc->rc_rcb->rcb_addr; 768#ifdef RCDEBUG 769 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 770#endif 771 s = spltty(); 772 773again: 774 while (rc->rc_flags & RC_DTR_OFF) { 775 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 776 if (error != 0) 777 goto out; 778 } 779 if (tp->t_state & TS_ISOPEN) { 780 if (CALLOUT(dev)) { 781 if (!(rc->rc_flags & RC_ACTOUT)) { 782 error = EBUSY; 783 goto out; 784 } 785 } else { 786 if (rc->rc_flags & RC_ACTOUT) { 787 if (flag & O_NONBLOCK) { 788 error = EBUSY; 789 goto out; 790 } 791 if (error = tsleep(&rc->rc_rcb, 792 TTIPRI|PCATCH, "rcbi", 0)) 793 goto out; 794 goto again; 795 } 796 } 797 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 798 error = EBUSY; 799 goto out; 800 } 801 } else { 802 tp->t_oproc = rc_start; 803 tp->t_param = rc_param; 804 tp->t_dev = dev; 805 806 if (CALLOUT(dev)) 807 tp->t_cflag |= CLOCAL; 808 else 809 tp->t_cflag &= ~CLOCAL; 810 811 error = rc_param(tp, &tp->t_termios); 812 if (error) 813 goto out; 814 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 815 816 ttsetwater(tp); 817 818 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 819 (*linesw[tp->t_line].l_modem)(tp, 1); 820 } 821 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 822 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 823 rc->rc_dcdwaits++; 824 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 825 rc->rc_dcdwaits--; 826 if (error != 0) 827 goto out; 828 goto again; 829 } 830 error = (*linesw[tp->t_line].l_open)(dev, tp); 831 disc_optim(tp, &tp->t_termios, rc); 832 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 833 rc->rc_flags |= RC_ACTOUT; 834out: 835 (void) splx(s); 836 837 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 838 rc_hardclose(rc); 839 840 return error; 841} 842 843static int 844rcclose(dev, flag, mode, p) 845 dev_t dev; 846 int flag, mode; 847 struct proc *p; 848{ 849 register struct rc_chans *rc; 850 register struct tty *tp; 851 int s, unit = GET_UNIT(dev); 852 853 if (unit >= NRC * CD180_NCHAN) 854 return ENXIO; 855 rc = &rc_chans[unit]; 856 tp = rc->rc_tp; 857#ifdef RCDEBUG 858 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 859#endif 860 s = spltty(); 861 (*linesw[tp->t_line].l_close)(tp, flag); 862 disc_optim(tp, &tp->t_termios, rc); 863 rcstop(tp, FREAD | FWRITE); 864 rc_hardclose(rc); 865 ttyclose(tp); 866 splx(s); 867 return 0; 868} 869 870static void rc_hardclose(rc) 871register struct rc_chans *rc; 872{ 873 register int s, nec = rc->rc_rcb->rcb_addr; 874 register struct tty *tp = rc->rc_tp; 875 876 s = spltty(); 877 rcout(CD180_CAR, rc->rc_chan); 878 879 /* Disable rx/tx intrs */ 880 rcout(CD180_IER, rc->rc_ier = 0); 881 if ( (tp->t_cflag & HUPCL) 882 || !(rc->rc_flags & RC_ACTOUT) 883 && !(rc->rc_msvr & MSVR_CD) 884 && !(tp->t_cflag & CLOCAL) 885 || !(tp->t_state & TS_ISOPEN) 886 ) { 887 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 888 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 889 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 890 if (rc->rc_dtrwait) { 891 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 892 rc->rc_flags |= RC_DTR_OFF; 893 } 894 } 895 rc->rc_flags &= ~RC_ACTOUT; 896 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 897 wakeup(TSA_CARR_ON(tp)); 898 (void) splx(s); 899} 900 901/* Read from line */ 902static int 903rcread(dev, uio, flag) 904 dev_t dev; 905 struct uio *uio; 906 int flag; 907{ 908 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 909 910 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 911} 912 913/* Write to line */ 914static int 915rcwrite(dev, uio, flag) 916 dev_t dev; 917 struct uio *uio; 918 int flag; 919{ 920 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 921 922 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 923} 924 925/* Reset the bastard */ 926static void rc_hwreset(unit, nec, chipid) 927 register int unit, nec; 928 unsigned int chipid; 929{ 930 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 931 DELAY(20000); 932 WAITFORCCR(unit, -1); 933 934 rcout(RC_CTOUT, 0); /* Clear timeout */ 935 rcout(CD180_GIVR, chipid); 936 rcout(CD180_GICR, 0); 937 938 /* Set Prescaler Registers (1 msec) */ 939 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 940 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 941 942 /* Initialize Priority Interrupt Level Registers */ 943 rcout(CD180_PILR1, RC_PILR_MODEM); 944 rcout(CD180_PILR2, RC_PILR_TX); 945 rcout(CD180_PILR3, RC_PILR_RX); 946 947 /* Reset DTR */ 948 rcout(RC_DTREG, ~0); 949} 950 951/* Set channel parameters */ 952static int rc_param(tp, ts) 953 register struct tty *tp; 954 struct termios *ts; 955{ 956 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 957 register int nec = rc->rc_rcb->rcb_addr; 958 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 959 960 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 961 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 962 ) 963 return (EINVAL); 964 if (ts->c_ispeed == 0) 965 ts->c_ispeed = ts->c_ospeed; 966 odivs = RC_BRD(ts->c_ospeed); 967 idivs = RC_BRD(ts->c_ispeed); 968 969 s = spltty(); 970 971 /* Select channel */ 972 rcout(CD180_CAR, rc->rc_chan); 973 974 /* If speed == 0, hangup line */ 975 if (ts->c_ospeed == 0) { 976 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 977 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 978 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 979 } 980 981 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 982 cflag = ts->c_cflag; 983 iflag = ts->c_iflag; 984 lflag = ts->c_lflag; 985 986 if (idivs > 0) { 987 rcout(CD180_RBPRL, idivs & 0xFF); 988 rcout(CD180_RBPRH, idivs >> 8); 989 } 990 if (odivs > 0) { 991 rcout(CD180_TBPRL, odivs & 0xFF); 992 rcout(CD180_TBPRH, odivs >> 8); 993 } 994 995 /* set timeout value */ 996 if (ts->c_ispeed > 0) { 997 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 998 999 if ( !(lflag & ICANON) 1000 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1001 && ts->c_cc[VTIME] * 10 > itm) 1002 itm = ts->c_cc[VTIME] * 10; 1003 1004 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 1005 } 1006 1007 switch (cflag & CSIZE) { 1008 case CS5: val = COR1_5BITS; break; 1009 case CS6: val = COR1_6BITS; break; 1010 case CS7: val = COR1_7BITS; break; 1011 default: 1012 case CS8: val = COR1_8BITS; break; 1013 } 1014 if (cflag & PARENB) { 1015 val |= COR1_NORMPAR; 1016 if (cflag & PARODD) 1017 val |= COR1_ODDP; 1018 if (!(cflag & INPCK)) 1019 val |= COR1_Ignore; 1020 } else 1021 val |= COR1_Ignore; 1022 if (cflag & CSTOPB) 1023 val |= COR1_2SB; 1024 rcout(CD180_COR1, val); 1025 1026 /* Set FIFO threshold */ 1027 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1028 inpflow = 0; 1029 if ( (iflag & IXOFF) 1030 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1031 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1032 || (iflag & IXANY) 1033 ) 1034 ) 1035 ) { 1036 inpflow = 1; 1037 val |= COR3_SCDE|COR3_FCT; 1038 } 1039 rcout(CD180_COR3, val); 1040 1041 /* Initialize on-chip automatic flow control */ 1042 val = 0; 1043 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1044 if (cflag & CCTS_OFLOW) { 1045 rc->rc_flags |= RC_CTSFLOW; 1046 val |= COR2_CtsAE; 1047 } else 1048 rc->rc_flags |= RC_SEND_RDY; 1049 if (tp->t_state & TS_TTSTOP) 1050 rc->rc_flags |= RC_OSUSP; 1051 else 1052 rc->rc_flags &= ~RC_OSUSP; 1053 if (cflag & CRTS_IFLOW) 1054 rc->rc_flags |= RC_RTSFLOW; 1055 else 1056 rc->rc_flags &= ~RC_RTSFLOW; 1057 1058 if (inpflow) { 1059 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1060 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1061 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1062 val |= COR2_TxIBE; 1063 if (iflag & IXANY) 1064 val |= COR2_IXM; 1065 } 1066 1067 rcout(CD180_COR2, rc->rc_cor2 = val); 1068 1069 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1070 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1071 1072 disc_optim(tp, ts, rc); 1073 1074 /* modem ctl */ 1075 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1076 if (cflag & CCTS_OFLOW) 1077 val |= MCOR1_CTSzd; 1078 rcout(CD180_MCOR1, val); 1079 1080 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1081 if (cflag & CCTS_OFLOW) 1082 val |= MCOR2_CTSod; 1083 rcout(CD180_MCOR2, val); 1084 1085 /* enable i/o and interrupts */ 1086 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1087 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1088 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1089 1090 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1091 if (cflag & CCTS_OFLOW) 1092 rc->rc_ier |= IER_CTS; 1093 if (cflag & CREAD) 1094 rc->rc_ier |= IER_RxData; 1095 if (tp->t_state & TS_BUSY) 1096 rc->rc_ier |= IER_TxRdy; 1097 if (ts->c_ospeed != 0) 1098 rc_modctl(rc, TIOCM_DTR, DMBIS); 1099 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1100 rc->rc_flags |= RC_SEND_RDY; 1101 rcout(CD180_IER, rc->rc_ier); 1102 (void) splx(s); 1103 return 0; 1104} 1105 1106/* Re-initialize board after bogus interrupts */ 1107static void rc_reinit(rcb) 1108struct rc_softc *rcb; 1109{ 1110 register struct rc_chans *rc, *rce; 1111 register int nec; 1112 1113 nec = rcb->rcb_addr; 1114 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1115 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1116 rce = rc + CD180_NCHAN; 1117 for (; rc < rce; rc++) 1118 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1119} 1120 1121static int 1122rcioctl(dev, cmd, data, flag, p) 1123dev_t dev; 1124int cmd, flag; 1125caddr_t data; 1126struct proc *p; 1127{ 1128 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1129 register int s, error; 1130 struct tty *tp = rc->rc_tp; 1131 1132 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1133 if (error >= 0) 1134 return (error); 1135 error = ttioctl(tp, cmd, data, flag); 1136 disc_optim(tp, &tp->t_termios, rc); 1137 if (error >= 0) 1138 return (error); 1139 s = spltty(); 1140 1141 switch (cmd) { 1142 case TIOCSBRK: 1143 rc->rc_pendcmd = CD180_C_SBRK; 1144 break; 1145 1146 case TIOCCBRK: 1147 rc->rc_pendcmd = CD180_C_EBRK; 1148 break; 1149 1150 case TIOCSDTR: 1151 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1152 break; 1153 1154 case TIOCCDTR: 1155 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1156 break; 1157 1158 case TIOCMGET: 1159 *(int *) data = rc_modctl(rc, 0, DMGET); 1160 break; 1161 1162 case TIOCMSET: 1163 (void) rc_modctl(rc, *(int *) data, DMSET); 1164 break; 1165 1166 case TIOCMBIC: 1167 (void) rc_modctl(rc, *(int *) data, DMBIC); 1168 break; 1169 1170 case TIOCMBIS: 1171 (void) rc_modctl(rc, *(int *) data, DMBIS); 1172 break; 1173 1174 case TIOCMSDTRWAIT: 1175 error = suser(p->p_ucred, &p->p_acflag); 1176 if (error != 0) { 1177 splx(s); 1178 return (error); 1179 } 1180 rc->rc_dtrwait = *(int *)data * hz / 100; 1181 break; 1182 1183 case TIOCMGDTRWAIT: 1184 *(int *)data = rc->rc_dtrwait * 100 / hz; 1185 break; 1186 1187 default: 1188 (void) splx(s); 1189 return ENOTTY; 1190 } 1191 (void) splx(s); 1192 return 0; 1193} 1194 1195 1196/* Modem control routines */ 1197 1198static int rc_modctl(rc, bits, cmd) 1199register struct rc_chans *rc; 1200int bits, cmd; 1201{ 1202 register int nec = rc->rc_rcb->rcb_addr; 1203 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1204 1205 rcout(CD180_CAR, rc->rc_chan); 1206 1207 switch (cmd) { 1208 case DMSET: 1209 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1210 ~(*dtr |= 1 << rc->rc_chan) : 1211 ~(*dtr &= ~(1 << rc->rc_chan))); 1212 msvr = rcin(CD180_MSVR); 1213 if (bits & TIOCM_RTS) 1214 msvr |= MSVR_RTS; 1215 else 1216 msvr &= ~MSVR_RTS; 1217 if (bits & TIOCM_DTR) 1218 msvr |= MSVR_DTR; 1219 else 1220 msvr &= ~MSVR_DTR; 1221 rcout(CD180_MSVR, msvr); 1222 break; 1223 1224 case DMBIS: 1225 if (bits & TIOCM_DTR) 1226 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1227 msvr = rcin(CD180_MSVR); 1228 if (bits & TIOCM_RTS) 1229 msvr |= MSVR_RTS; 1230 if (bits & TIOCM_DTR) 1231 msvr |= MSVR_DTR; 1232 rcout(CD180_MSVR, msvr); 1233 break; 1234 1235 case DMGET: 1236 bits = TIOCM_LE; 1237 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1238 1239 if (msvr & MSVR_RTS) 1240 bits |= TIOCM_RTS; 1241 if (msvr & MSVR_CTS) 1242 bits |= TIOCM_CTS; 1243 if (msvr & MSVR_DSR) 1244 bits |= TIOCM_DSR; 1245 if (msvr & MSVR_DTR) 1246 bits |= TIOCM_DTR; 1247 if (msvr & MSVR_CD) 1248 bits |= TIOCM_CD; 1249 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1250 bits |= TIOCM_RI; 1251 return bits; 1252 1253 case DMBIC: 1254 if (bits & TIOCM_DTR) 1255 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1256 msvr = rcin(CD180_MSVR); 1257 if (bits & TIOCM_RTS) 1258 msvr &= ~MSVR_RTS; 1259 if (bits & TIOCM_DTR) 1260 msvr &= ~MSVR_DTR; 1261 rcout(CD180_MSVR, msvr); 1262 break; 1263 } 1264 rc->rc_msvr = rcin(CD180_MSVR); 1265 return 0; 1266} 1267 1268/* Test the board. */ 1269int rc_test(nec, unit) 1270 register int nec; 1271 int unit; 1272{ 1273 int chan = 0; 1274 int i = 0, rcnt, old_level; 1275 unsigned int iack, chipid; 1276 unsigned short divs; 1277 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1278#define CTLEN 8 1279#define ERR(s) { \ 1280 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1281 (void) splx(old_level); return 1; } 1282 1283 struct rtest { 1284 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1285 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1286 int rxptr; /* RX pointer */ 1287 int txptr; /* TX pointer */ 1288 } tchans[CD180_NCHAN]; 1289 1290 old_level = spltty(); 1291 1292 chipid = RC_FAKEID; 1293 1294 /* First, reset board to inital state */ 1295 rc_hwreset(unit, nec, chipid); 1296 1297 divs = RC_BRD(19200); 1298 1299 /* Initialize channels */ 1300 for (chan = 0; chan < CD180_NCHAN; chan++) { 1301 1302 /* Select and reset channel */ 1303 rcout(CD180_CAR, chan); 1304 CCRCMD(unit, chan, CCR_ResetChan); 1305 WAITFORCCR(unit, chan); 1306 1307 /* Set speed */ 1308 rcout(CD180_RBPRL, divs & 0xFF); 1309 rcout(CD180_RBPRH, divs >> 8); 1310 rcout(CD180_TBPRL, divs & 0xFF); 1311 rcout(CD180_TBPRH, divs >> 8); 1312 1313 /* set timeout value */ 1314 rcout(CD180_RTPR, 0); 1315 1316 /* Establish local loopback */ 1317 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1318 rcout(CD180_COR2, COR2_LLM); 1319 rcout(CD180_COR3, CD180_NFIFO); 1320 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1321 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1322 WAITFORCCR(unit, chan); 1323 rcout(CD180_MSVR, MSVR_RTS); 1324 1325 /* Fill TXBUF with test data */ 1326 for (i = 0; i < CD180_NFIFO; i++) { 1327 tchans[chan].txbuf[i] = ctest[i]; 1328 tchans[chan].rxbuf[i] = 0; 1329 } 1330 tchans[chan].txptr = tchans[chan].rxptr = 0; 1331 1332 /* Now, start transmit */ 1333 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1334 } 1335 /* Pseudo-interrupt poll stuff */ 1336 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1337 i = ~(rcin(RC_BSR)); 1338 if (i & RC_BSR_TOUT) 1339 ERR(("BSR timeout bit set\n")) 1340 else if (i & RC_BSR_TXINT) { 1341 iack = rcin(RC_PILR_TX); 1342 if (iack != (GIVR_IT_TDI | chipid)) 1343 ERR(("Bad TX intr ack (%02x != %02x)\n", 1344 iack, GIVR_IT_TDI | chipid)); 1345 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1346 /* If no more data to transmit, disable TX intr */ 1347 if (tchans[chan].txptr >= CD180_NFIFO) { 1348 iack = rcin(CD180_IER); 1349 rcout(CD180_IER, iack & ~IER_TxMpty); 1350 } else { 1351 for (iack = tchans[chan].txptr; 1352 iack < CD180_NFIFO; iack++) 1353 rcout(CD180_TDR, 1354 tchans[chan].txbuf[iack]); 1355 tchans[chan].txptr = iack; 1356 } 1357 rcout(CD180_EOIR, 0); 1358 } else if (i & RC_BSR_RXINT) { 1359 u_char ucnt; 1360 1361 iack = rcin(RC_PILR_RX); 1362 if (iack != (GIVR_IT_RGDI | chipid) && 1363 iack != (GIVR_IT_REI | chipid)) 1364 ERR(("Bad RX intr ack (%02x != %02x)\n", 1365 iack, GIVR_IT_RGDI | chipid)) 1366 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1367 ucnt = rcin(CD180_RDCR) & 0xF; 1368 while (ucnt-- > 0) { 1369 iack = rcin(CD180_RCSR); 1370 if (iack & RCSR_Timeout) 1371 break; 1372 if (iack & 0xF) 1373 ERR(("Bad char chan %d (RCSR = %02X)\n", 1374 chan, iack)) 1375 if (tchans[chan].rxptr > CD180_NFIFO) 1376 ERR(("Got extra chars chan %d\n", 1377 chan)) 1378 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1379 rcin(CD180_RDR); 1380 } 1381 rcout(CD180_EOIR, 0); 1382 } 1383 rcout(RC_CTOUT, 0); 1384 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1385 if (tchans[chan].rxptr >= CD180_NFIFO) 1386 iack++; 1387 if (iack == CD180_NCHAN) 1388 break; 1389 } 1390 for (chan = 0; chan < CD180_NCHAN; chan++) { 1391 /* Select and reset channel */ 1392 rcout(CD180_CAR, chan); 1393 CCRCMD(unit, chan, CCR_ResetChan); 1394 } 1395 1396 if (!rcnt) 1397 ERR(("looses characters during local loopback\n")) 1398 /* Now, check data */ 1399 for (chan = 0; chan < CD180_NCHAN; chan++) 1400 for (i = 0; i < CD180_NFIFO; i++) 1401 if (ctest[i] != tchans[chan].rxbuf[i]) 1402 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1403 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1404 (void) splx(old_level); 1405 return 0; 1406} 1407 1408#ifdef RCDEBUG 1409static void printrcflags(rc, comment) 1410struct rc_chans *rc; 1411char *comment; 1412{ 1413 u_short f = rc->rc_flags; 1414 register int nec = rc->rc_rcb->rcb_addr; 1415 1416 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1417 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1418 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1419 (f & RC_ACTOUT) ?"ACTOUT " :"", 1420 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1421 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1422 (f & RC_DORXFER)?"DORXFER " :"", 1423 (f & RC_DOXXFER)?"DOXXFER " :"", 1424 (f & RC_MODCHG) ?"MODCHG " :"", 1425 (f & RC_OSUSP) ?"OSUSP " :"", 1426 (f & RC_OSBUSY) ?"OSBUSY " :"", 1427 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1428 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1429 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1430 1431 rcout(CD180_CAR, rc->rc_chan); 1432 1433 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1434 rc->rc_rcb->rcb_unit, rc->rc_chan, 1435 rcin(CD180_MSVR), 1436 rcin(CD180_IER), 1437 rcin(CD180_CCSR)); 1438} 1439#endif /* RCDEBUG */ 1440 1441static struct tty * 1442rcdevtotty(dev) 1443 dev_t dev; 1444{ 1445 int unit; 1446 1447 unit = GET_UNIT(dev); 1448 if (unit >= NRC * CD180_NCHAN) 1449 return NULL; 1450 return (&rc_tty[unit]); 1451} 1452 1453static void 1454rc_dtrwakeup(chan) 1455 void *chan; 1456{ 1457 struct rc_chans *rc; 1458 1459 rc = (struct rc_chans *)chan; 1460 rc->rc_flags &= ~RC_DTR_OFF; 1461 wakeup(&rc->rc_dtrwait); 1462} 1463 1464static void 1465rc_discard_output(rc) 1466 struct rc_chans *rc; 1467{ 1468 disable_intr(); 1469 if (rc->rc_flags & RC_DOXXFER) { 1470 rc_scheduled_event -= LOTS_OF_EVENTS; 1471 rc->rc_flags &= ~RC_DOXXFER; 1472 } 1473 rc->rc_optr = rc->rc_obufend; 1474 rc->rc_tp->t_state &= ~TS_BUSY; 1475 enable_intr(); 1476 ttwwakeup(rc->rc_tp); 1477} 1478 1479static void 1480rc_wakeup(chan) 1481 void *chan; 1482{ 1483 timeout(rc_wakeup, (caddr_t)NULL, 1); 1484 1485 if (rc_scheduled_event != 0) { 1486 int s; 1487 1488 s = splsofttty(); 1489 rcpoll(); 1490 splx(s); 1491 } 1492} 1493 1494static void 1495disc_optim(tp, t, rc) 1496 struct tty *tp; 1497 struct termios *t; 1498 struct rc_chans *rc; 1499{ 1500 1501 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1502 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1503 && (!(t->c_iflag & PARMRK) 1504 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1505 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1506 && linesw[tp->t_line].l_rint == ttyinput) 1507 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1508 else 1509 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1510 if (tp->t_line == SLIPDISC) 1511 rc->rc_hotchar = 0xc0; 1512 else if (tp->t_line == PPPDISC) 1513 rc->rc_hotchar = 0x7e; 1514 else 1515 rc->rc_hotchar = 0; 1516} 1517 1518static void 1519rc_wait0(nec, unit, chan, line) 1520 int nec, unit, chan, line; 1521{ 1522 int rcnt; 1523 1524 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1525 DELAY(30); 1526 if (rcnt == 0) 1527 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1528 unit, chan, line); 1529} 1530 1531static rc_devsw_installed = 0; 1532 1533static void rc_drvinit(void *unused) 1534{ 1535 dev_t dev; 1536 1537 if( ! rc_devsw_installed ) { 1538 dev = makedev(CDEV_MAJOR, 0); 1539 cdevsw_add(&dev,&rc_cdevsw, NULL); 1540 rc_devsw_installed = 1; 1541 } 1542} 1543 1544SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1545 1546 1547#endif /* NRC */ 1548