rc.c revision 16322
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#include <sys/devconf.h> 50#ifdef DEVFS 51#include <sys/devfsext.h> 52#endif /*DEVFS*/ 53 54#include <machine/clock.h> 55 56#include <i386/isa/isa.h> 57#include <i386/isa/isa_device.h> 58#include <i386/isa/sioreg.h> 59 60#include <i386/isa/ic/cd180.h> 61#include <i386/isa/rcreg.h> 62 63 64/* Prototypes */ 65static int rcprobe __P((struct isa_device *)); 66static int rcattach __P((struct isa_device *)); 67 68/*- 69 * This space intentionally left blank to stop __LINE__ from screwing up 70 * regression tests :-(. 71 * 72 * 73 * 74 */ 75void rcpoll __P((void)); 76 77#define rcin(port) RC_IN (nec, port) 78#define rcout(port,v) RC_OUT (nec, port, v) 79 80#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 81#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 82 83#define RC_IBUFSIZE 256 84#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 85#define RC_OBUFSIZE 512 86#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 87#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 88#define LOTS_OF_EVENTS 64 89 90#define RC_FAKEID 0x10 91 92#define RC_PROBED 1 93#define RC_ATTACHED 2 94 95#define GET_UNIT(dev) (minor(dev) & 0x3F) 96#define CALLOUT(dev) (minor(dev) & 0x80) 97 98/* For isa routines */ 99struct isa_driver rcdriver = { 100 rcprobe, rcattach, "rc" 101}; 102 103static d_open_t rcopen; 104static d_close_t rcclose; 105static d_read_t rcread; 106static d_write_t rcwrite; 107static d_ioctl_t rcioctl; 108static d_stop_t rcstop; 109static d_devtotty_t rcdevtotty; 110 111#define CDEV_MAJOR 63 112static struct cdevsw rc_cdevsw = 113 { rcopen, rcclose, rcread, rcwrite, /*63*/ 114 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 115 ttselect, nommap, NULL, "rc", NULL, -1 }; 116 117/* Per-board structure */ 118static struct rc_softc { 119 u_int rcb_probed; /* 1 - probed, 2 - attached */ 120 u_int rcb_addr; /* Base I/O addr */ 121 u_int rcb_unit; /* unit # */ 122 u_char rcb_dtr; /* DTR status */ 123 struct rc_chans *rcb_baserc; /* base rc ptr */ 124} rc_softc[NRC]; 125 126/* Per-channel structure */ 127static struct rc_chans { 128 struct rc_softc *rc_rcb; /* back ptr */ 129 u_short rc_flags; /* Misc. flags */ 130 int rc_chan; /* Channel # */ 131 u_char rc_ier; /* intr. enable reg */ 132 u_char rc_msvr; /* modem sig. status */ 133 u_char rc_cor2; /* options reg */ 134 u_char rc_pendcmd; /* special cmd pending */ 135 u_int rc_dtrwait; /* dtr timeout */ 136 u_int rc_dcdwaits; /* how many waits DCD in open */ 137 u_char rc_hotchar; /* end packed optimize */ 138 struct tty *rc_tp; /* tty struct */ 139 u_char *rc_iptr; /* Chars input buffer */ 140 u_char *rc_hiwat; /* hi-water mark */ 141 u_char *rc_bufend; /* end of buffer */ 142 u_char *rc_optr; /* ptr in output buf */ 143 u_char *rc_obufend; /* end of output buf */ 144 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 145 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 146#ifdef DEVFS 147 void *devfs_token; 148#endif 149} rc_chans[NRC * CD180_NCHAN]; 150 151static int rc_scheduled_event = 0; 152 153/* for pstat -t */ 154static struct tty rc_tty[NRC * CD180_NCHAN]; 155static const int nrc_tty = NRC * CD180_NCHAN; 156 157/* Flags */ 158#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 159#define RC_ACTOUT 0x0002 /* Dial-out port active */ 160#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 161#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 162#define RC_DORXFER 0x0010 /* RXFER event planned */ 163#define RC_DOXXFER 0x0020 /* XXFER event planned */ 164#define RC_MODCHG 0x0040 /* Modem status changed */ 165#define RC_OSUSP 0x0080 /* Output suspended */ 166#define RC_OSBUSY 0x0100 /* start() routine in progress */ 167#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 168#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 169#define RC_SEND_RDY 0x0800 /* ready to send */ 170 171/* Table for translation of RCSR status bits to internal form */ 172static int rc_rcsrt[16] = { 173 0, TTY_OE, TTY_FE, 174 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 175 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 176 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 177 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 178 TTY_BI|TTY_PE|TTY_FE|TTY_OE 179}; 180 181/* Static prototypes */ 182static void rc_hwreset __P((int, int, unsigned int)); 183static int rc_test __P((int, int)); 184static void rc_discard_output __P((struct rc_chans *)); 185static void rc_hardclose __P((struct rc_chans *)); 186static int rc_modctl __P((struct rc_chans *, int, int)); 187static void rc_start __P((struct tty *)); 188static int rc_param __P((struct tty *, struct termios *)); 189static void rc_registerdev __P((struct isa_device *id)); 190static void rc_reinit __P((struct rc_softc *)); 191#ifdef RCDEBUG 192static void printrcflags(); 193#endif 194static timeout_t rc_dtrwakeup; 195static timeout_t rc_wakeup; 196static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 197static void rc_wait0 __P((int nec, int unit, int chan, int line)); 198 199/**********************************************/ 200 201/* Quick device probing */ 202static int 203rcprobe(dvp) 204 struct isa_device *dvp; 205{ 206 int irq = ffs(dvp->id_irq) - 1; 207 register int nec = dvp->id_iobase; 208 209 if (dvp->id_unit > NRC) 210 return 0; 211 if (!RC_VALIDADDR(nec)) { 212 printf("rc%d: illegal base address %x\n", nec); 213 return 0; 214 } 215 if (!RC_VALIDIRQ(irq)) { 216 printf("rc%d: illegal IRQ value %d\n", irq); 217 return 0; 218 } 219 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 220 rcout(CD180_PPRH, 0x11); 221 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 222 return 0; 223 /* Now, test the board more thoroughly, with diagnostic */ 224 if (rc_test(nec, dvp->id_unit)) 225 return 0; 226 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 227 228 return 0xF; 229} 230 231static struct kern_devconf kdc_rc[NRC] = { { 232 0, 0, 0, /* filled in by dev_attach */ 233 "rc", 0, { MDDT_ISA, 0, "tty" }, 234 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 235 &kdc_isa0, /* parent */ 236 0, /* parentdata */ 237 DC_UNCONFIGURED, /* state */ 238 "RISCom/8 multiport card", 239 DC_CLS_SERIAL /* class */ 240} }; 241 242static void 243rc_registerdev(id) 244 struct isa_device *id; 245{ 246 int unit; 247 248 unit = id->id_unit; 249 if (unit != 0) 250 kdc_rc[unit] = kdc_rc[0]; 251 kdc_rc[unit].kdc_unit = unit; 252 kdc_rc[unit].kdc_isa = id; 253 kdc_rc[unit].kdc_state = DC_UNKNOWN; 254 dev_attach(&kdc_rc[unit]); 255} 256 257static int 258rcattach(dvp) 259 struct isa_device *dvp; 260{ 261 register int chan, nec = dvp->id_iobase; 262 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 263 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 264 static int rc_wakeup_started = 0; 265 struct tty *tp; 266 267 /* Thorooughly test the device */ 268 if (rcb->rcb_probed != RC_PROBED) 269 return 0; 270 rcb->rcb_addr = nec; 271 rcb->rcb_dtr = 0; 272 rcb->rcb_baserc = rc; 273 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 274 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 275 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 276 277 rc_registerdev(dvp); 278 279 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 280 rc->rc_rcb = rcb; 281 rc->rc_chan = chan; 282 rc->rc_iptr = rc->rc_ibuf; 283 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 284 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 285 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 286 rc->rc_cor2 = rc->rc_pendcmd = 0; 287 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 288 rc->rc_dtrwait = 3 * hz; 289 rc->rc_dcdwaits= 0; 290 rc->rc_hotchar = 0; 291 tp = rc->rc_tp = &rc_tty[chan]; 292 ttychars(tp); 293 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 294 tp->t_cflag = TTYDEF_CFLAG; 295 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 296#ifdef DEVFS 297/* FIX THIS to reflect real devices */ 298 rc->devfs_token = 299 devfs_add_devswf(&rc_cdevsw, 300 (dvp->id_unit * CD180_NCHAN) + chan, 301 DV_CHR, 0, 0, 0600, "rc%d.%d", 302 dvp->id_unit, chan); 303#endif 304 } 305 rcb->rcb_probed = RC_ATTACHED; 306 if (!rc_wakeup_started) { 307 rc_wakeup((void *)NULL); 308 rc_wakeup_started = 0; 309 } 310 return 1; 311} 312 313/* RC interrupt handling */ 314void rcintr(unit) 315 int unit; 316{ 317 register struct rc_softc *rcb = &rc_softc[unit]; 318 register struct rc_chans *rc; 319 register int nec, resid; 320 register u_char val, iack, bsr, ucnt, *optr; 321 int good_data, t_state; 322 323 if (rcb->rcb_probed != RC_ATTACHED) { 324 printf("rc%d: bogus interrupt\n", unit); 325 return; 326 } 327 nec = rcb->rcb_addr; 328 329 bsr = ~(rcin(RC_BSR)); 330 331 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 332 printf("rc%d: extra interrupt\n", unit); 333 rcout(CD180_EOIR, 0); 334 return; 335 } 336 337 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 338#ifdef RCDEBUG_DETAILED 339 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 340 (bsr & RC_BSR_TOUT)?"TOUT ":"", 341 (bsr & RC_BSR_RXINT)?"RXINT ":"", 342 (bsr & RC_BSR_TXINT)?"TXINT ":"", 343 (bsr & RC_BSR_MOINT)?"MOINT":""); 344#endif 345 if (bsr & RC_BSR_TOUT) { 346 printf("rc%d: hardware failure, reset board\n", unit); 347 rcout(RC_CTOUT, 0); 348 rc_reinit(rcb); 349 return; 350 } 351 if (bsr & RC_BSR_RXINT) { 352 iack = rcin(RC_PILR_RX); 353 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 354 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 355 printf("rc%d: fake rxint: %02x\n", unit, iack); 356 goto more_intrs; 357 } 358 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 359 t_state = rc->rc_tp->t_state; 360 /* Do RTS flow control stuff */ 361 if ( (rc->rc_flags & RC_RTSFLOW) 362 || !(t_state & TS_ISOPEN) 363 ) { 364 if ( ( !(t_state & TS_ISOPEN) 365 || (t_state & TS_TBLOCK) 366 ) 367 && (rc->rc_msvr & MSVR_RTS) 368 ) 369 rcout(CD180_MSVR, 370 rc->rc_msvr &= ~MSVR_RTS); 371 else if (!(rc->rc_msvr & MSVR_RTS)) 372 rcout(CD180_MSVR, 373 rc->rc_msvr |= MSVR_RTS); 374 } 375 ucnt = rcin(CD180_RDCR) & 0xF; 376 resid = 0; 377 378 if (t_state & TS_ISOPEN) { 379 /* check for input buffer overflow */ 380 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 381 resid = ucnt; 382 ucnt = rc->rc_bufend - rc->rc_iptr; 383 resid -= ucnt; 384 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 385 rc->rc_flags |= RC_WAS_BUFOVFL; 386 rc_scheduled_event++; 387 } 388 } 389 optr = rc->rc_iptr; 390 /* check foor good data */ 391 if (good_data) { 392 while (ucnt-- > 0) { 393 val = rcin(CD180_RDR); 394 optr[0] = val; 395 optr[INPUT_FLAGS_SHIFT] = 0; 396 optr++; 397 rc_scheduled_event++; 398 if (val != 0 && val == rc->rc_hotchar) 399 setsofttty(); 400 } 401 } else { 402 /* Store also status data */ 403 while (ucnt-- > 0) { 404 iack = rcin(CD180_RCSR); 405 if (iack & RCSR_Timeout) 406 break; 407 if ( (iack & RCSR_OE) 408 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 409 rc->rc_flags |= RC_WAS_SILOVFL; 410 rc_scheduled_event++; 411 } 412 val = rcin(CD180_RDR); 413 /* 414 Don't store PE if IGNPAR and BREAK if IGNBRK, 415 this hack allows "raw" tty optimization 416 works even if IGN* is set. 417 */ 418 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 419 || (!(iack & (RCSR_PE|RCSR_FE)) 420 || !(rc->rc_tp->t_iflag & IGNPAR)) 421 && (!(iack & RCSR_Break) 422 || !(rc->rc_tp->t_iflag & IGNBRK))) { 423 if ( (iack & (RCSR_PE|RCSR_FE)) 424 && (t_state & TS_CAN_BYPASS_L_RINT) 425 && ((iack & RCSR_FE) 426 || (iack & RCSR_PE) 427 && (rc->rc_tp->t_iflag & INPCK))) 428 val = 0; 429 else if (val != 0 && val == rc->rc_hotchar) 430 setsofttty(); 431 optr[0] = val; 432 optr[INPUT_FLAGS_SHIFT] = iack; 433 optr++; 434 rc_scheduled_event++; 435 } 436 } 437 } 438 rc->rc_iptr = optr; 439 rc->rc_flags |= RC_DORXFER; 440 } else 441 resid = ucnt; 442 /* Clear FIFO if necessary */ 443 while (resid-- > 0) { 444 if (!good_data) 445 iack = rcin(CD180_RCSR); 446 else 447 iack = 0; 448 if (iack & RCSR_Timeout) 449 break; 450 (void) rcin(CD180_RDR); 451 } 452 goto more_intrs; 453 } 454 if (bsr & RC_BSR_MOINT) { 455 iack = rcin(RC_PILR_MODEM); 456 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 457 printf("rc%d: fake moint: %02x\n", unit, iack); 458 goto more_intrs; 459 } 460 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 461 iack = rcin(CD180_MCR); 462 rc->rc_msvr = rcin(CD180_MSVR); 463 rcout(CD180_MCR, 0); 464#ifdef RCDEBUG 465 printrcflags(rc, "moint"); 466#endif 467 if (rc->rc_flags & RC_CTSFLOW) { 468 if (rc->rc_msvr & MSVR_CTS) 469 rc->rc_flags |= RC_SEND_RDY; 470 else 471 rc->rc_flags &= ~RC_SEND_RDY; 472 } else 473 rc->rc_flags |= RC_SEND_RDY; 474 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 475 rc_scheduled_event += LOTS_OF_EVENTS; 476 rc->rc_flags |= RC_MODCHG; 477 setsofttty(); 478 } 479 goto more_intrs; 480 } 481 if (bsr & RC_BSR_TXINT) { 482 iack = rcin(RC_PILR_TX); 483 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 484 printf("rc%d: fake txint: %02x\n", unit, iack); 485 goto more_intrs; 486 } 487 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 488 if ( (rc->rc_flags & RC_OSUSP) 489 || !(rc->rc_flags & RC_SEND_RDY) 490 ) 491 goto more_intrs; 492 /* Handle breaks and other stuff */ 493 if (rc->rc_pendcmd) { 494 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 495 rcout(CD180_TDR, CD180_C_ESC); 496 rcout(CD180_TDR, rc->rc_pendcmd); 497 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 498 rc->rc_pendcmd = 0; 499 goto more_intrs; 500 } 501 optr = rc->rc_optr; 502 resid = rc->rc_obufend - optr; 503 if (resid > CD180_NFIFO) 504 resid = CD180_NFIFO; 505 while (resid-- > 0) 506 rcout(CD180_TDR, *optr++); 507 rc->rc_optr = optr; 508 509 /* output completed? */ 510 if (optr >= rc->rc_obufend) { 511 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 512#ifdef RCDEBUG 513 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 514#endif 515 if (!(rc->rc_flags & RC_DOXXFER)) { 516 rc_scheduled_event += LOTS_OF_EVENTS; 517 rc->rc_flags |= RC_DOXXFER; 518 setsofttty(); 519 } 520 } 521 } 522 more_intrs: 523 rcout(CD180_EOIR, 0); /* end of interrupt */ 524 rcout(RC_CTOUT, 0); 525 bsr = ~(rcin(RC_BSR)); 526 } 527} 528 529/* Feed characters to output buffer */ 530static void rc_start(tp) 531register struct tty *tp; 532{ 533 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 534 register int nec = rc->rc_rcb->rcb_addr, s; 535 536 if (rc->rc_flags & RC_OSBUSY) 537 return; 538 s = spltty(); 539 rc->rc_flags |= RC_OSBUSY; 540 disable_intr(); 541 if (tp->t_state & TS_TTSTOP) 542 rc->rc_flags |= RC_OSUSP; 543 else 544 rc->rc_flags &= ~RC_OSUSP; 545 /* Do RTS flow control stuff */ 546 if ( (rc->rc_flags & RC_RTSFLOW) 547 && (tp->t_state & TS_TBLOCK) 548 && (rc->rc_msvr & MSVR_RTS) 549 ) { 550 rcout(CD180_CAR, rc->rc_chan); 551 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 552 } else if (!(rc->rc_msvr & MSVR_RTS)) { 553 rcout(CD180_CAR, rc->rc_chan); 554 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 555 } 556 enable_intr(); 557 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 558 goto out; 559#ifdef RCDEBUG 560 printrcflags(rc, "rcstart"); 561#endif 562 ttwwakeup(tp); 563#ifdef RCDEBUG 564 printf("rcstart: outq = %d obuf = %d\n", 565 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 566#endif 567 if (tp->t_state & TS_BUSY) 568 goto out; /* output still in progress ... */ 569 570 if (tp->t_outq.c_cc > 0) { 571 u_int ocnt; 572 573 tp->t_state |= TS_BUSY; 574 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 575 disable_intr(); 576 rc->rc_optr = rc->rc_obuf; 577 rc->rc_obufend = rc->rc_optr + ocnt; 578 enable_intr(); 579 if (!(rc->rc_ier & IER_TxRdy)) { 580#ifdef RCDEBUG 581 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 582#endif 583 rcout(CD180_CAR, rc->rc_chan); 584 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 585 } 586 } 587out: 588 rc->rc_flags &= ~RC_OSBUSY; 589 (void) splx(s); 590} 591 592/* Handle delayed events. */ 593void rcpoll() 594{ 595 register struct rc_chans *rc; 596 register struct rc_softc *rcb; 597 register u_char *tptr, *eptr; 598 register struct tty *tp; 599 register int chan, icnt, nec, unit; 600 601 if (rc_scheduled_event == 0) 602 return; 603repeat: 604 for (unit = 0; unit < NRC; unit++) { 605 rcb = &rc_softc[unit]; 606 rc = rcb->rcb_baserc; 607 nec = rc->rc_rcb->rcb_addr; 608 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 609 tp = rc->rc_tp; 610#ifdef RCDEBUG 611 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 612 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 613 printrcflags(rc, "rcevent"); 614#endif 615 if (rc->rc_flags & RC_WAS_BUFOVFL) { 616 disable_intr(); 617 rc->rc_flags &= ~RC_WAS_BUFOVFL; 618 rc_scheduled_event--; 619 enable_intr(); 620 printf("rc%d/%d: interrupt-level buffer overflow\n", 621 unit, chan); 622 } 623 if (rc->rc_flags & RC_WAS_SILOVFL) { 624 disable_intr(); 625 rc->rc_flags &= ~RC_WAS_SILOVFL; 626 rc_scheduled_event--; 627 enable_intr(); 628 printf("rc%d/%d: silo overflow\n", 629 unit, chan); 630 } 631 if (rc->rc_flags & RC_MODCHG) { 632 disable_intr(); 633 rc->rc_flags &= ~RC_MODCHG; 634 rc_scheduled_event -= LOTS_OF_EVENTS; 635 enable_intr(); 636 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 637 } 638 if (rc->rc_flags & RC_DORXFER) { 639 disable_intr(); 640 rc->rc_flags &= ~RC_DORXFER; 641 eptr = rc->rc_iptr; 642 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 643 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 644 else 645 tptr = rc->rc_ibuf; 646 icnt = eptr - tptr; 647 if (icnt > 0) { 648 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 649 rc->rc_iptr = rc->rc_ibuf; 650 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 651 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 652 } else { 653 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 654 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 655 rc->rc_hiwat = 656 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 657 } 658 if ( (rc->rc_flags & RC_RTSFLOW) 659 && (tp->t_state & TS_ISOPEN) 660 && !(tp->t_state & TS_TBLOCK) 661 && !(rc->rc_msvr & MSVR_RTS) 662 ) { 663 rcout(CD180_CAR, chan); 664 rcout(CD180_MSVR, 665 rc->rc_msvr |= MSVR_RTS); 666 } 667 rc_scheduled_event -= icnt; 668 } 669 enable_intr(); 670 671 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 672 goto done1; 673 674 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 675 && !(tp->t_state & TS_LOCAL)) { 676 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 677 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 678 && !(tp->t_state & TS_TBLOCK)) 679 ttyblock(tp); 680 tk_nin += icnt; 681 tk_rawcc += icnt; 682 tp->t_rawcc += icnt; 683 if (b_to_q(tptr, icnt, &tp->t_rawq)) 684 printf("rc%d/%d: tty-level buffer overflow\n", 685 unit, chan); 686 ttwakeup(tp); 687 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 688 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 689 tp->t_state &= ~TS_TTSTOP; 690 tp->t_lflag &= ~FLUSHO; 691 rc_start(tp); 692 } 693 } else { 694 for (; tptr < eptr; tptr++) 695 (*linesw[tp->t_line].l_rint) 696 (tptr[0] | 697 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 698 } 699done1: 700 } 701 if (rc->rc_flags & RC_DOXXFER) { 702 disable_intr(); 703 rc_scheduled_event -= LOTS_OF_EVENTS; 704 rc->rc_flags &= ~RC_DOXXFER; 705 rc->rc_tp->t_state &= ~TS_BUSY; 706 enable_intr(); 707 (*linesw[tp->t_line].l_start)(tp); 708 } 709 } 710 if (rc_scheduled_event == 0) 711 break; 712 } 713 if (rc_scheduled_event >= LOTS_OF_EVENTS) 714 goto repeat; 715} 716 717static void 718rcstop(tp, rw) 719 register struct tty *tp; 720 int rw; 721{ 722 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 723 u_char *tptr, *eptr; 724 725#ifdef RCDEBUG 726 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 727 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 728#endif 729 if (rw & FWRITE) 730 rc_discard_output(rc); 731 disable_intr(); 732 if (rw & FREAD) { 733 rc->rc_flags &= ~RC_DORXFER; 734 eptr = rc->rc_iptr; 735 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 736 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 737 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 738 } else { 739 tptr = rc->rc_ibuf; 740 rc->rc_iptr = rc->rc_ibuf; 741 } 742 rc_scheduled_event -= eptr - tptr; 743 } 744 if (tp->t_state & TS_TTSTOP) 745 rc->rc_flags |= RC_OSUSP; 746 else 747 rc->rc_flags &= ~RC_OSUSP; 748 enable_intr(); 749} 750 751static int 752rcopen(dev, flag, mode, p) 753 dev_t dev; 754 int flag, mode; 755 struct proc *p; 756{ 757 register struct rc_chans *rc; 758 register struct tty *tp; 759 int unit, nec, s, error = 0; 760 761 unit = GET_UNIT(dev); 762 if (unit >= NRC * CD180_NCHAN) 763 return ENXIO; 764 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 765 return ENXIO; 766 rc = &rc_chans[unit]; 767 tp = rc->rc_tp; 768 nec = rc->rc_rcb->rcb_addr; 769#ifdef RCDEBUG 770 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 771#endif 772 s = spltty(); 773 774again: 775 while (rc->rc_flags & RC_DTR_OFF) { 776 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 777 if (error != 0) 778 goto out; 779 } 780 if (tp->t_state & TS_ISOPEN) { 781 if (CALLOUT(dev)) { 782 if (!(rc->rc_flags & RC_ACTOUT)) { 783 error = EBUSY; 784 goto out; 785 } 786 } else { 787 if (rc->rc_flags & RC_ACTOUT) { 788 if (flag & O_NONBLOCK) { 789 error = EBUSY; 790 goto out; 791 } 792 if (error = tsleep(&rc->rc_rcb, 793 TTIPRI|PCATCH, "rcbi", 0)) 794 goto out; 795 goto again; 796 } 797 } 798 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 799 error = EBUSY; 800 goto out; 801 } 802 } else { 803 tp->t_oproc = rc_start; 804 tp->t_param = rc_param; 805 tp->t_dev = dev; 806 807 if (CALLOUT(dev)) 808 tp->t_cflag |= CLOCAL; 809 else 810 tp->t_cflag &= ~CLOCAL; 811 812 error = rc_param(tp, &tp->t_termios); 813 if (error) 814 goto out; 815 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 816 817 ttsetwater(tp); 818 819 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 820 (*linesw[tp->t_line].l_modem)(tp, 1); 821 } 822 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 823 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 824 rc->rc_dcdwaits++; 825 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 826 rc->rc_dcdwaits--; 827 if (error != 0) 828 goto out; 829 goto again; 830 } 831 error = (*linesw[tp->t_line].l_open)(dev, tp); 832 disc_optim(tp, &tp->t_termios, rc); 833 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 834 rc->rc_flags |= RC_ACTOUT; 835out: 836 (void) splx(s); 837 838 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 839 rc_hardclose(rc); 840 841 return error; 842} 843 844static int 845rcclose(dev, flag, mode, p) 846 dev_t dev; 847 int flag, mode; 848 struct proc *p; 849{ 850 register struct rc_chans *rc; 851 register struct tty *tp; 852 int s, unit = GET_UNIT(dev); 853 854 if (unit >= NRC * CD180_NCHAN) 855 return ENXIO; 856 rc = &rc_chans[unit]; 857 tp = rc->rc_tp; 858#ifdef RCDEBUG 859 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 860#endif 861 s = spltty(); 862 (*linesw[tp->t_line].l_close)(tp, flag); 863 disc_optim(tp, &tp->t_termios, rc); 864 rcstop(tp, FREAD | FWRITE); 865 rc_hardclose(rc); 866 ttyclose(tp); 867 splx(s); 868 return 0; 869} 870 871static void rc_hardclose(rc) 872register struct rc_chans *rc; 873{ 874 register int s, nec = rc->rc_rcb->rcb_addr; 875 register struct tty *tp = rc->rc_tp; 876 877 s = spltty(); 878 rcout(CD180_CAR, rc->rc_chan); 879 880 /* Disable rx/tx intrs */ 881 rcout(CD180_IER, rc->rc_ier = 0); 882 if ( (tp->t_cflag & HUPCL) 883 || !(rc->rc_flags & RC_ACTOUT) 884 && !(rc->rc_msvr & MSVR_CD) 885 && !(tp->t_cflag & CLOCAL) 886 || !(tp->t_state & TS_ISOPEN) 887 ) { 888 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 889 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 890 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 891 if (rc->rc_dtrwait) { 892 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 893 rc->rc_flags |= RC_DTR_OFF; 894 } 895 } 896 rc->rc_flags &= ~RC_ACTOUT; 897 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 898 wakeup(TSA_CARR_ON(tp)); 899 (void) splx(s); 900} 901 902/* Read from line */ 903static int 904rcread(dev, uio, flag) 905 dev_t dev; 906 struct uio *uio; 907 int flag; 908{ 909 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 910 911 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 912} 913 914/* Write to line */ 915static int 916rcwrite(dev, uio, flag) 917 dev_t dev; 918 struct uio *uio; 919 int flag; 920{ 921 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 922 923 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 924} 925 926/* Reset the bastard */ 927static void rc_hwreset(unit, nec, chipid) 928 register int unit, nec; 929 unsigned int chipid; 930{ 931 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 932 DELAY(20000); 933 WAITFORCCR(unit, -1); 934 935 rcout(RC_CTOUT, 0); /* Clear timeout */ 936 rcout(CD180_GIVR, chipid); 937 rcout(CD180_GICR, 0); 938 939 /* Set Prescaler Registers (1 msec) */ 940 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 941 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 942 943 /* Initialize Priority Interrupt Level Registers */ 944 rcout(CD180_PILR1, RC_PILR_MODEM); 945 rcout(CD180_PILR2, RC_PILR_TX); 946 rcout(CD180_PILR3, RC_PILR_RX); 947 948 /* Reset DTR */ 949 rcout(RC_DTREG, ~0); 950} 951 952/* Set channel parameters */ 953static int rc_param(tp, ts) 954 register struct tty *tp; 955 struct termios *ts; 956{ 957 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 958 register int nec = rc->rc_rcb->rcb_addr; 959 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 960 961 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 962 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 963 ) 964 return (EINVAL); 965 if (ts->c_ispeed == 0) 966 ts->c_ispeed = ts->c_ospeed; 967 odivs = RC_BRD(ts->c_ospeed); 968 idivs = RC_BRD(ts->c_ispeed); 969 970 s = spltty(); 971 972 /* Select channel */ 973 rcout(CD180_CAR, rc->rc_chan); 974 975 /* If speed == 0, hangup line */ 976 if (ts->c_ospeed == 0) { 977 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 978 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 979 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 980 } 981 982 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 983 cflag = ts->c_cflag; 984 iflag = ts->c_iflag; 985 lflag = ts->c_lflag; 986 987 if (idivs > 0) { 988 rcout(CD180_RBPRL, idivs & 0xFF); 989 rcout(CD180_RBPRH, idivs >> 8); 990 } 991 if (odivs > 0) { 992 rcout(CD180_TBPRL, odivs & 0xFF); 993 rcout(CD180_TBPRH, odivs >> 8); 994 } 995 996 /* set timeout value */ 997 if (ts->c_ispeed > 0) { 998 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 999 1000 if ( !(lflag & ICANON) 1001 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1002 && ts->c_cc[VTIME] * 10 > itm) 1003 itm = ts->c_cc[VTIME] * 10; 1004 1005 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 1006 } 1007 1008 switch (cflag & CSIZE) { 1009 case CS5: val = COR1_5BITS; break; 1010 case CS6: val = COR1_6BITS; break; 1011 case CS7: val = COR1_7BITS; break; 1012 default: 1013 case CS8: val = COR1_8BITS; break; 1014 } 1015 if (cflag & PARENB) { 1016 val |= COR1_NORMPAR; 1017 if (cflag & PARODD) 1018 val |= COR1_ODDP; 1019 if (!(cflag & INPCK)) 1020 val |= COR1_Ignore; 1021 } else 1022 val |= COR1_Ignore; 1023 if (cflag & CSTOPB) 1024 val |= COR1_2SB; 1025 rcout(CD180_COR1, val); 1026 1027 /* Set FIFO threshold */ 1028 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1029 inpflow = 0; 1030 if ( (iflag & IXOFF) 1031 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1032 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1033 || (iflag & IXANY) 1034 ) 1035 ) 1036 ) { 1037 inpflow = 1; 1038 val |= COR3_SCDE|COR3_FCT; 1039 } 1040 rcout(CD180_COR3, val); 1041 1042 /* Initialize on-chip automatic flow control */ 1043 val = 0; 1044 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1045 if (cflag & CCTS_OFLOW) { 1046 rc->rc_flags |= RC_CTSFLOW; 1047 val |= COR2_CtsAE; 1048 } else 1049 rc->rc_flags |= RC_SEND_RDY; 1050 if (tp->t_state & TS_TTSTOP) 1051 rc->rc_flags |= RC_OSUSP; 1052 else 1053 rc->rc_flags &= ~RC_OSUSP; 1054 if (cflag & CRTS_IFLOW) 1055 rc->rc_flags |= RC_RTSFLOW; 1056 else 1057 rc->rc_flags &= ~RC_RTSFLOW; 1058 1059 if (inpflow) { 1060 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1061 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1062 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1063 val |= COR2_TxIBE; 1064 if (iflag & IXANY) 1065 val |= COR2_IXM; 1066 } 1067 1068 rcout(CD180_COR2, rc->rc_cor2 = val); 1069 1070 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1071 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1072 1073 disc_optim(tp, ts, rc); 1074 1075 /* modem ctl */ 1076 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1077 if (cflag & CCTS_OFLOW) 1078 val |= MCOR1_CTSzd; 1079 rcout(CD180_MCOR1, val); 1080 1081 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1082 if (cflag & CCTS_OFLOW) 1083 val |= MCOR2_CTSod; 1084 rcout(CD180_MCOR2, val); 1085 1086 /* enable i/o and interrupts */ 1087 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1088 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1089 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1090 1091 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1092 if (cflag & CCTS_OFLOW) 1093 rc->rc_ier |= IER_CTS; 1094 if (cflag & CREAD) 1095 rc->rc_ier |= IER_RxData; 1096 if (tp->t_state & TS_BUSY) 1097 rc->rc_ier |= IER_TxRdy; 1098 if (ts->c_ospeed != 0) 1099 rc_modctl(rc, TIOCM_DTR, DMBIS); 1100 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1101 rc->rc_flags |= RC_SEND_RDY; 1102 rcout(CD180_IER, rc->rc_ier); 1103 (void) splx(s); 1104 return 0; 1105} 1106 1107/* Re-initialize board after bogus interrupts */ 1108static void rc_reinit(rcb) 1109struct rc_softc *rcb; 1110{ 1111 register struct rc_chans *rc, *rce; 1112 register int nec; 1113 1114 nec = rcb->rcb_addr; 1115 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1116 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1117 rce = rc + CD180_NCHAN; 1118 for (; rc < rce; rc++) 1119 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1120} 1121 1122static int 1123rcioctl(dev, cmd, data, flag, p) 1124dev_t dev; 1125int cmd, flag; 1126caddr_t data; 1127struct proc *p; 1128{ 1129 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1130 register int s, error; 1131 struct tty *tp = rc->rc_tp; 1132 1133 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1134 if (error >= 0) 1135 return (error); 1136 error = ttioctl(tp, cmd, data, flag); 1137 disc_optim(tp, &tp->t_termios, rc); 1138 if (error >= 0) 1139 return (error); 1140 s = spltty(); 1141 1142 switch (cmd) { 1143 case TIOCSBRK: 1144 rc->rc_pendcmd = CD180_C_SBRK; 1145 break; 1146 1147 case TIOCCBRK: 1148 rc->rc_pendcmd = CD180_C_EBRK; 1149 break; 1150 1151 case TIOCSDTR: 1152 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1153 break; 1154 1155 case TIOCCDTR: 1156 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1157 break; 1158 1159 case TIOCMGET: 1160 *(int *) data = rc_modctl(rc, 0, DMGET); 1161 break; 1162 1163 case TIOCMSET: 1164 (void) rc_modctl(rc, *(int *) data, DMSET); 1165 break; 1166 1167 case TIOCMBIC: 1168 (void) rc_modctl(rc, *(int *) data, DMBIC); 1169 break; 1170 1171 case TIOCMBIS: 1172 (void) rc_modctl(rc, *(int *) data, DMBIS); 1173 break; 1174 1175 case TIOCMSDTRWAIT: 1176 error = suser(p->p_ucred, &p->p_acflag); 1177 if (error != 0) { 1178 splx(s); 1179 return (error); 1180 } 1181 rc->rc_dtrwait = *(int *)data * hz / 100; 1182 break; 1183 1184 case TIOCMGDTRWAIT: 1185 *(int *)data = rc->rc_dtrwait * 100 / hz; 1186 break; 1187 1188 default: 1189 (void) splx(s); 1190 return ENOTTY; 1191 } 1192 (void) splx(s); 1193 return 0; 1194} 1195 1196 1197/* Modem control routines */ 1198 1199static int rc_modctl(rc, bits, cmd) 1200register struct rc_chans *rc; 1201int bits, cmd; 1202{ 1203 register int nec = rc->rc_rcb->rcb_addr; 1204 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1205 1206 rcout(CD180_CAR, rc->rc_chan); 1207 1208 switch (cmd) { 1209 case DMSET: 1210 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1211 ~(*dtr |= 1 << rc->rc_chan) : 1212 ~(*dtr &= ~(1 << rc->rc_chan))); 1213 msvr = rcin(CD180_MSVR); 1214 if (bits & TIOCM_RTS) 1215 msvr |= MSVR_RTS; 1216 else 1217 msvr &= ~MSVR_RTS; 1218 if (bits & TIOCM_DTR) 1219 msvr |= MSVR_DTR; 1220 else 1221 msvr &= ~MSVR_DTR; 1222 rcout(CD180_MSVR, msvr); 1223 break; 1224 1225 case DMBIS: 1226 if (bits & TIOCM_DTR) 1227 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1228 msvr = rcin(CD180_MSVR); 1229 if (bits & TIOCM_RTS) 1230 msvr |= MSVR_RTS; 1231 if (bits & TIOCM_DTR) 1232 msvr |= MSVR_DTR; 1233 rcout(CD180_MSVR, msvr); 1234 break; 1235 1236 case DMGET: 1237 bits = TIOCM_LE; 1238 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1239 1240 if (msvr & MSVR_RTS) 1241 bits |= TIOCM_RTS; 1242 if (msvr & MSVR_CTS) 1243 bits |= TIOCM_CTS; 1244 if (msvr & MSVR_DSR) 1245 bits |= TIOCM_DSR; 1246 if (msvr & MSVR_DTR) 1247 bits |= TIOCM_DTR; 1248 if (msvr & MSVR_CD) 1249 bits |= TIOCM_CD; 1250 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1251 bits |= TIOCM_RI; 1252 return bits; 1253 1254 case DMBIC: 1255 if (bits & TIOCM_DTR) 1256 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1257 msvr = rcin(CD180_MSVR); 1258 if (bits & TIOCM_RTS) 1259 msvr &= ~MSVR_RTS; 1260 if (bits & TIOCM_DTR) 1261 msvr &= ~MSVR_DTR; 1262 rcout(CD180_MSVR, msvr); 1263 break; 1264 } 1265 rc->rc_msvr = rcin(CD180_MSVR); 1266 return 0; 1267} 1268 1269/* Test the board. */ 1270int rc_test(nec, unit) 1271 register int nec; 1272 int unit; 1273{ 1274 int chan = 0; 1275 int i = 0, rcnt, old_level; 1276 unsigned int iack, chipid; 1277 unsigned short divs; 1278 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1279#define CTLEN 8 1280#define ERR(s) { \ 1281 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1282 (void) splx(old_level); return 1; } 1283 1284 struct rtest { 1285 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1286 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1287 int rxptr; /* RX pointer */ 1288 int txptr; /* TX pointer */ 1289 } tchans[CD180_NCHAN]; 1290 1291 old_level = spltty(); 1292 1293 chipid = RC_FAKEID; 1294 1295 /* First, reset board to inital state */ 1296 rc_hwreset(unit, nec, chipid); 1297 1298 divs = RC_BRD(19200); 1299 1300 /* Initialize channels */ 1301 for (chan = 0; chan < CD180_NCHAN; chan++) { 1302 1303 /* Select and reset channel */ 1304 rcout(CD180_CAR, chan); 1305 CCRCMD(unit, chan, CCR_ResetChan); 1306 WAITFORCCR(unit, chan); 1307 1308 /* Set speed */ 1309 rcout(CD180_RBPRL, divs & 0xFF); 1310 rcout(CD180_RBPRH, divs >> 8); 1311 rcout(CD180_TBPRL, divs & 0xFF); 1312 rcout(CD180_TBPRH, divs >> 8); 1313 1314 /* set timeout value */ 1315 rcout(CD180_RTPR, 0); 1316 1317 /* Establish local loopback */ 1318 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1319 rcout(CD180_COR2, COR2_LLM); 1320 rcout(CD180_COR3, CD180_NFIFO); 1321 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1322 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1323 WAITFORCCR(unit, chan); 1324 rcout(CD180_MSVR, MSVR_RTS); 1325 1326 /* Fill TXBUF with test data */ 1327 for (i = 0; i < CD180_NFIFO; i++) { 1328 tchans[chan].txbuf[i] = ctest[i]; 1329 tchans[chan].rxbuf[i] = 0; 1330 } 1331 tchans[chan].txptr = tchans[chan].rxptr = 0; 1332 1333 /* Now, start transmit */ 1334 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1335 } 1336 /* Pseudo-interrupt poll stuff */ 1337 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1338 i = ~(rcin(RC_BSR)); 1339 if (i & RC_BSR_TOUT) 1340 ERR(("BSR timeout bit set\n")) 1341 else if (i & RC_BSR_TXINT) { 1342 iack = rcin(RC_PILR_TX); 1343 if (iack != (GIVR_IT_TDI | chipid)) 1344 ERR(("Bad TX intr ack (%02x != %02x)\n", 1345 iack, GIVR_IT_TDI | chipid)); 1346 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1347 /* If no more data to transmit, disable TX intr */ 1348 if (tchans[chan].txptr >= CD180_NFIFO) { 1349 iack = rcin(CD180_IER); 1350 rcout(CD180_IER, iack & ~IER_TxMpty); 1351 } else { 1352 for (iack = tchans[chan].txptr; 1353 iack < CD180_NFIFO; iack++) 1354 rcout(CD180_TDR, 1355 tchans[chan].txbuf[iack]); 1356 tchans[chan].txptr = iack; 1357 } 1358 rcout(CD180_EOIR, 0); 1359 } else if (i & RC_BSR_RXINT) { 1360 u_char ucnt; 1361 1362 iack = rcin(RC_PILR_RX); 1363 if (iack != (GIVR_IT_RGDI | chipid) && 1364 iack != (GIVR_IT_REI | chipid)) 1365 ERR(("Bad RX intr ack (%02x != %02x)\n", 1366 iack, GIVR_IT_RGDI | chipid)) 1367 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1368 ucnt = rcin(CD180_RDCR) & 0xF; 1369 while (ucnt-- > 0) { 1370 iack = rcin(CD180_RCSR); 1371 if (iack & RCSR_Timeout) 1372 break; 1373 if (iack & 0xF) 1374 ERR(("Bad char chan %d (RCSR = %02X)\n", 1375 chan, iack)) 1376 if (tchans[chan].rxptr > CD180_NFIFO) 1377 ERR(("Got extra chars chan %d\n", 1378 chan)) 1379 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1380 rcin(CD180_RDR); 1381 } 1382 rcout(CD180_EOIR, 0); 1383 } 1384 rcout(RC_CTOUT, 0); 1385 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1386 if (tchans[chan].rxptr >= CD180_NFIFO) 1387 iack++; 1388 if (iack == CD180_NCHAN) 1389 break; 1390 } 1391 for (chan = 0; chan < CD180_NCHAN; chan++) { 1392 /* Select and reset channel */ 1393 rcout(CD180_CAR, chan); 1394 CCRCMD(unit, chan, CCR_ResetChan); 1395 } 1396 1397 if (!rcnt) 1398 ERR(("looses characters during local loopback\n")) 1399 /* Now, check data */ 1400 for (chan = 0; chan < CD180_NCHAN; chan++) 1401 for (i = 0; i < CD180_NFIFO; i++) 1402 if (ctest[i] != tchans[chan].rxbuf[i]) 1403 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1404 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1405 (void) splx(old_level); 1406 return 0; 1407} 1408 1409#ifdef RCDEBUG 1410static void printrcflags(rc, comment) 1411struct rc_chans *rc; 1412char *comment; 1413{ 1414 u_short f = rc->rc_flags; 1415 register int nec = rc->rc_rcb->rcb_addr; 1416 1417 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1418 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1419 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1420 (f & RC_ACTOUT) ?"ACTOUT " :"", 1421 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1422 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1423 (f & RC_DORXFER)?"DORXFER " :"", 1424 (f & RC_DOXXFER)?"DOXXFER " :"", 1425 (f & RC_MODCHG) ?"MODCHG " :"", 1426 (f & RC_OSUSP) ?"OSUSP " :"", 1427 (f & RC_OSBUSY) ?"OSBUSY " :"", 1428 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1429 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1430 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1431 1432 rcout(CD180_CAR, rc->rc_chan); 1433 1434 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1435 rc->rc_rcb->rcb_unit, rc->rc_chan, 1436 rcin(CD180_MSVR), 1437 rcin(CD180_IER), 1438 rcin(CD180_CCSR)); 1439} 1440#endif /* RCDEBUG */ 1441 1442static struct tty * 1443rcdevtotty(dev) 1444 dev_t dev; 1445{ 1446 int unit; 1447 1448 unit = GET_UNIT(dev); 1449 if (unit >= NRC * CD180_NCHAN) 1450 return NULL; 1451 return (&rc_tty[unit]); 1452} 1453 1454static void 1455rc_dtrwakeup(chan) 1456 void *chan; 1457{ 1458 struct rc_chans *rc; 1459 1460 rc = (struct rc_chans *)chan; 1461 rc->rc_flags &= ~RC_DTR_OFF; 1462 wakeup(&rc->rc_dtrwait); 1463} 1464 1465static void 1466rc_discard_output(rc) 1467 struct rc_chans *rc; 1468{ 1469 disable_intr(); 1470 if (rc->rc_flags & RC_DOXXFER) { 1471 rc_scheduled_event -= LOTS_OF_EVENTS; 1472 rc->rc_flags &= ~RC_DOXXFER; 1473 } 1474 rc->rc_optr = rc->rc_obufend; 1475 rc->rc_tp->t_state &= ~TS_BUSY; 1476 enable_intr(); 1477 ttwwakeup(rc->rc_tp); 1478} 1479 1480static void 1481rc_wakeup(chan) 1482 void *chan; 1483{ 1484 timeout(rc_wakeup, (caddr_t)NULL, 1); 1485 1486 if (rc_scheduled_event != 0) { 1487 int s; 1488 1489 s = splsofttty(); 1490 rcpoll(); 1491 splx(s); 1492 } 1493} 1494 1495static void 1496disc_optim(tp, t, rc) 1497 struct tty *tp; 1498 struct termios *t; 1499 struct rc_chans *rc; 1500{ 1501 1502 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1503 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1504 && (!(t->c_iflag & PARMRK) 1505 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1506 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1507 && linesw[tp->t_line].l_rint == ttyinput) 1508 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1509 else 1510 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1511 if (tp->t_line == SLIPDISC) 1512 rc->rc_hotchar = 0xc0; 1513 else if (tp->t_line == PPPDISC) 1514 rc->rc_hotchar = 0x7e; 1515 else 1516 rc->rc_hotchar = 0; 1517} 1518 1519static void 1520rc_wait0(nec, unit, chan, line) 1521 int nec, unit, chan, line; 1522{ 1523 int rcnt; 1524 1525 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1526 DELAY(30); 1527 if (rcnt == 0) 1528 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1529 unit, chan, line); 1530} 1531 1532static rc_devsw_installed = 0; 1533 1534static void rc_drvinit(void *unused) 1535{ 1536 dev_t dev; 1537 1538 if( ! rc_devsw_installed ) { 1539 dev = makedev(CDEV_MAJOR, 0); 1540 cdevsw_add(&dev,&rc_cdevsw, NULL); 1541 rc_devsw_installed = 1; 1542 } 1543} 1544 1545SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1546 1547 1548#endif /* NRC */ 1549