rc.c revision 130585
1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/rc/rc.c 130585 2004-06-16 09:47:26Z phk $
29 */
30
31/*
32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
33 *
34 */
35
36/*#define RCDEBUG*/
37
38#include "opt_tty.h"
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/conf.h>
44#include <sys/fcntl.h>
45#include <sys/interrupt.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/module.h>
49#include <sys/tty.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54#include <dev/ic/cd180.h>
55#include <dev/rc/rcreg.h>
56#include <isa/isavar.h>
57
58#define	IOBASE_ADDRS	14
59
60#define	DEV_TO_RC(dev)		(struct rc_chans *)((dev)->si_drv1)
61#define	TTY_TO_RC(tty)		DEV_TO_RC((tty)->t_dev)
62
63#define rcin(sc, port)		RC_IN(sc, port)
64#define rcout(sc, port, v)	RC_OUT(sc, port, v)
65
66#define WAITFORCCR(sc, chan)	rc_wait0((sc), (chan), __LINE__)
67
68#define CCRCMD(sc, chan, cmd) do {					\
69	WAITFORCCR((sc), (chan));					\
70	rcout((sc), CD180_CCR, (cmd));					\
71} while (0)
72
73#define RC_IBUFSIZE     256
74#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
75#define RC_OBUFSIZE     512
76#define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
77#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
78#define LOTS_OF_EVENTS  64
79
80#define RC_FAKEID       0x10
81
82#define CALLOUT(dev)    (((intptr_t)(dev)->si_drv2) != 0)
83
84/* Per-channel structure */
85struct rc_chans  {
86	struct rc_softc *rc_rcb;                /* back ptr             */
87	struct cdev *rc_dev;		/* non-callout device	*/
88	struct cdev *rc_cdev;		/* callout device	*/
89	u_short          rc_flags;              /* Misc. flags          */
90	int              rc_chan;               /* Channel #            */
91	u_char           rc_ier;                /* intr. enable reg     */
92	u_char           rc_msvr;               /* modem sig. status    */
93	u_char           rc_cor2;               /* options reg          */
94	u_char           rc_pendcmd;            /* special cmd pending  */
95	u_int            rc_dtrwait;            /* dtr timeout          */
96	u_int            rc_dcdwaits;           /* how many waits DCD in open */
97	u_char		 rc_hotchar;		/* end packed optimize */
98	struct tty       rc_tp;                 /* tty struct           */
99	u_char          *rc_iptr;               /* Chars input buffer         */
100	u_char          *rc_hiwat;              /* hi-water mark        */
101	u_char          *rc_bufend;             /* end of buffer        */
102	u_char          *rc_optr;               /* ptr in output buf    */
103	u_char          *rc_obufend;            /* end of output buf    */
104	u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
105	u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
106	struct callout	 rc_dtrcallout;
107};
108
109/* Per-board structure */
110struct rc_softc {
111	device_t	 sc_dev;
112	struct resource *sc_irq;
113	struct resource *sc_port[IOBASE_ADDRS];
114	int		 sc_irqrid;
115	void		*sc_hwicookie;
116	bus_space_tag_t  sc_bt;
117	bus_space_handle_t sc_bh;
118	u_int            sc_unit;       /* unit #               */
119	u_char           sc_dtr;        /* DTR status           */
120	int		 sc_opencount;
121	int		 sc_scheduled_event;
122	void		*sc_swicookie;
123	struct rc_chans  sc_channels[CD180_NCHAN]; /* channels */
124};
125
126/* Static prototypes */
127static void rc_release_resources(device_t dev);
128static void rc_intr(void *);
129static void rc_hwreset(struct rc_softc *, unsigned int);
130static int  rc_test(struct rc_softc *);
131static void rc_discard_output(struct rc_chans *);
132static void rc_hardclose(struct rc_chans *);
133static int  rc_modctl(struct rc_chans *, int, int);
134static void rc_start(struct tty *);
135static void rc_stop(struct tty *, int rw);
136static int  rc_param(struct tty *, struct termios *);
137static void rc_pollcard(void *);
138static void rc_reinit(struct rc_softc *);
139#ifdef RCDEBUG
140static void printrcflags();
141#endif
142static void rc_dtrwakeup(void *);
143static void rc_wait0(struct rc_softc *sc, int chan, int line);
144
145static	d_open_t	rcopen;
146static	d_close_t	rcclose;
147static	d_ioctl_t	rcioctl;
148
149static struct cdevsw rc_cdevsw = {
150	.d_version =	D_VERSION,
151	.d_open =	rcopen,
152	.d_close =	rcclose,
153	.d_ioctl =	rcioctl,
154	.d_name =	"rc",
155	.d_flags =	D_TTY | D_NEEDGIANT,
156};
157
158static devclass_t rc_devclass;
159
160/* Flags */
161#define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
162#define RC_ACTOUT       0x0002          /* Dial-out port active         */
163#define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
164#define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
165#define RC_DORXFER      0x0010          /* RXFER event planned          */
166#define RC_DOXXFER      0x0020          /* XXFER event planned          */
167#define RC_MODCHG       0x0040          /* Modem status changed         */
168#define RC_OSUSP        0x0080          /* Output suspended             */
169#define RC_OSBUSY       0x0100          /* start() routine in progress  */
170#define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
171#define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
172#define RC_SEND_RDY     0x0800          /* ready to send */
173
174/* Table for translation of RCSR status bits to internal form */
175static int rc_rcsrt[16] = {
176	0,             TTY_OE,               TTY_FE,
177	TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
178	TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
179	TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
180	TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
181	TTY_BI|TTY_PE|TTY_FE|TTY_OE
182};
183
184static int rc_ports[] =
185    { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 };
186static int iobase_addrs[IOBASE_ADDRS] =
187    { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000,
188      0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 };
189
190/**********************************************/
191
192static int
193rc_probe(device_t dev)
194{
195	u_int port;
196	int i, found;
197
198	/*
199	 * We don't know of any PnP ID's for these cards.
200	 */
201	if (isa_get_logicalid(dev) != 0)
202		return (ENXIO);
203
204	/*
205	 * We have to have an IO port hint that is valid.
206	 */
207	port = isa_get_port(dev);
208	if (port == -1)
209		return (ENXIO);
210	found = 0;
211	for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++)
212		if (rc_ports[i] == port) {
213			found = 1;
214			break;
215		}
216	if (!found)
217		return (ENXIO);
218
219	/*
220	 * We have to have an IRQ hint.
221	 */
222	if (isa_get_irq(dev) == -1)
223		return (ENXIO);
224
225	device_set_desc(dev, "SDL Riscom/8");
226	return (0);
227}
228
229static int
230rc_attach(device_t dev)
231{
232 	struct rc_chans *rc;
233	struct tty *tp;
234	struct rc_softc *sc;
235	u_int port;
236	int base, chan, error, i, x;
237	struct cdev *cdev;
238
239	sc = device_get_softc(dev);
240	sc->sc_dev = dev;
241
242	/*
243	 * We need to have IO ports.  Lots of them.  We need
244	 * the following ranges relative to the base port:
245	 * 0x0    -   0x10
246	 * 0x400  -  0x410
247	 * 0x800  -  0x810
248	 * 0xc00  -  0xc10
249	 * 0x1400 - 0x1410
250	 * 0x1800 - 0x1810
251	 * 0x1c00 - 0x1c10
252	 * 0x2000 - 0x2010
253	 * 0x3000 - 0x3010
254	 * 0x3400 - 0x3410
255	 * 0x3800 - 0x3810
256	 * 0x3c00 - 0x3c10
257	 * 0x4000 - 0x4010
258	 * 0x8000 - 0x8010
259	 */
260	port = isa_get_port(dev);
261	for (i = 0; i < IOBASE_ADDRS; i++)
262		if (bus_set_resource(dev, SYS_RES_IOPORT, i,
263		    port + iobase_addrs[i], 0x10) != 0)
264			return (ENXIO);
265	error = ENOMEM;
266	for (i = 0; i < IOBASE_ADDRS; i++) {
267		x = i;
268		sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x,
269		    0ul, ~0ul, 0x10, RF_ACTIVE);
270		if (x != i) {
271			device_printf(dev, "ioport %d was rid %d\n", i, x);
272			goto fail;
273		}
274		if (sc->sc_port[i] == NULL) {
275			device_printf(dev, "failed to alloc ioports %x-%x\n",
276			    port + iobase_addrs[i],
277			    port + iobase_addrs[i] + 0x10);
278			goto fail;
279		}
280	}
281	sc->sc_bt = rman_get_bustag(sc->sc_port[0]);
282	sc->sc_bh = rman_get_bushandle(sc->sc_port[0]);
283
284	sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
285	    RF_ACTIVE);
286	if (sc->sc_irq == NULL) {
287		device_printf(dev, "failed to alloc IRQ\n");
288		goto fail;
289	}
290
291	/*
292	 * Now do some actual tests to make sure it works.
293	 */
294	error = ENXIO;
295	rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */
296	rcout(sc, CD180_PPRH, 0x11);
297	if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11)
298		goto fail;
299	if (rc_test(sc))
300		goto fail;
301
302	/*
303	 * Ok, start actually hooking things up.
304	 */
305	sc->sc_unit = device_get_unit(dev);
306	/*sc->sc_chipid = 0x10 + device_get_unit(dev);*/
307	device_printf(dev, "%d chans, firmware rev. %c\n",
308		CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A');
309	rc = sc->sc_channels;
310	base = CD180_NCHAN * sc->sc_unit;
311	for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
312		rc->rc_rcb     = sc;
313		rc->rc_chan    = chan;
314		rc->rc_iptr    = rc->rc_ibuf;
315		rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
316		rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
317		rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
318		rc->rc_dtrwait = 3 * hz;
319		callout_init(&rc->rc_dtrcallout, 0);
320		tp = &rc->rc_tp;
321		ttychars(tp);
322		tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
323		tp->t_cflag = TTYDEF_CFLAG;
324		tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
325		cdev = make_dev(&rc_cdevsw, chan + base,
326		    UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base);
327		cdev->si_drv1 = rc;
328		cdev->si_drv2 = 0;
329		cdev->si_tty = tp;
330		rc->rc_dev = cdev;
331		cdev = make_dev(&rc_cdevsw, chan + base + 128,
332		    UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base);
333		cdev->si_drv1 = rc;
334		cdev->si_drv2 = (void *)1;
335		cdev->si_tty = tp;
336		rc->rc_cdev = cdev;
337	}
338
339	error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc,
340	    &sc->sc_hwicookie);
341	if (error) {
342		device_printf(dev, "failed to register interrupt handler\n");
343		goto fail;
344	}
345
346	swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0,
347	    &sc->sc_swicookie);
348	return (0);
349
350fail:
351	rc_release_resources(dev);
352	return (error);
353}
354
355static int
356rc_detach(device_t dev)
357{
358	struct rc_softc *sc;
359	struct rc_chans *rc;
360	int error, i, s;
361
362	sc = device_get_softc(dev);
363	if (sc->sc_opencount > 0)
364		return (EBUSY);
365	sc->sc_opencount = -1;
366
367	rc = sc->sc_channels;
368	for (i = 0; i < CD180_NCHAN; i++, rc++) {
369		destroy_dev(rc->rc_dev);
370		destroy_dev(rc->rc_cdev);
371	}
372
373	rc = sc->sc_channels;
374	s = splsoftclock();
375	for (i = 0; i < CD180_NCHAN; i++) {
376		if ((rc->rc_flags & RC_DTR_OFF) &&
377		    !callout_stop(&rc->rc_dtrcallout))
378			tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0);
379	}
380
381	error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie);
382	if (error)
383		device_printf(dev, "failed to deregister interrupt handler\n");
384	ithread_remove_handler(sc->sc_swicookie);
385	rc_release_resources(dev);
386
387	return (0);
388}
389
390static void
391rc_release_resources(device_t dev)
392{
393	struct rc_softc *sc;
394	int i;
395
396	sc = device_get_softc(dev);
397	if (sc->sc_irq != NULL) {
398		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
399		    sc->sc_irq);
400		sc->sc_irq = NULL;
401	}
402	for (i = 0; i < IOBASE_ADDRS; i++) {
403		if (sc->sc_port[i] == NULL)
404			break;
405		bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]);
406		sc->sc_port[i] = NULL;
407	}
408}
409
410/* RC interrupt handling */
411static void
412rc_intr(void *arg)
413{
414	struct rc_softc        *sc;
415	struct rc_chans        *rc;
416	int                    resid, chan;
417	u_char                 val, iack, bsr, ucnt, *optr;
418	int                    good_data, t_state;
419
420	sc = (struct rc_softc *)arg;
421	bsr = ~(rcin(sc, RC_BSR));
422	if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
423		device_printf(sc->sc_dev, "extra interrupt\n");
424		rcout(sc, CD180_EOIR, 0);
425		return;
426	}
427
428	while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
429#ifdef RCDEBUG_DETAILED
430		device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr,
431			(bsr & RC_BSR_TOUT)?"TOUT ":"",
432			(bsr & RC_BSR_RXINT)?"RXINT ":"",
433			(bsr & RC_BSR_TXINT)?"TXINT ":"",
434			(bsr & RC_BSR_MOINT)?"MOINT":"");
435#endif
436		if (bsr & RC_BSR_TOUT) {
437			device_printf(sc->sc_dev,
438			    "hardware failure, reset board\n");
439			rcout(sc, RC_CTOUT, 0);
440			rc_reinit(sc);
441			return;
442		}
443		if (bsr & RC_BSR_RXINT) {
444			iack = rcin(sc, RC_PILR_RX);
445			good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
446			if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
447				device_printf(sc->sc_dev,
448				    "fake rxint: %02x\n", iack);
449				goto more_intrs;
450			}
451			chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
452			rc = &sc->sc_channels[chan];
453			t_state = rc->rc_tp.t_state;
454			/* Do RTS flow control stuff */
455			if (  (rc->rc_flags & RC_RTSFLOW)
456			    || !(t_state & TS_ISOPEN)
457			   ) {
458				if (  (   !(t_state & TS_ISOPEN)
459				       || (t_state & TS_TBLOCK)
460				      )
461				    && (rc->rc_msvr & MSVR_RTS)
462				   )
463					rcout(sc, CD180_MSVR,
464						rc->rc_msvr &= ~MSVR_RTS);
465				else if (!(rc->rc_msvr & MSVR_RTS))
466					rcout(sc, CD180_MSVR,
467						rc->rc_msvr |= MSVR_RTS);
468			}
469			ucnt  = rcin(sc, CD180_RDCR) & 0xF;
470			resid = 0;
471
472			if (t_state & TS_ISOPEN) {
473				/* check for input buffer overflow */
474				if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
475					resid  = ucnt;
476					ucnt   = rc->rc_bufend - rc->rc_iptr;
477					resid -= ucnt;
478					if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
479						rc->rc_flags |= RC_WAS_BUFOVFL;
480						sc->sc_scheduled_event++;
481					}
482				}
483				optr = rc->rc_iptr;
484				/* check foor good data */
485				if (good_data) {
486					while (ucnt-- > 0) {
487						val = rcin(sc, CD180_RDR);
488						optr[0] = val;
489						optr[INPUT_FLAGS_SHIFT] = 0;
490						optr++;
491						sc->sc_scheduled_event++;
492						if (val != 0 && val == rc->rc_hotchar)
493							swi_sched(sc->sc_swicookie, 0);
494					}
495				} else {
496					/* Store also status data */
497					while (ucnt-- > 0) {
498						iack = rcin(sc, CD180_RCSR);
499						if (iack & RCSR_Timeout)
500							break;
501						if (   (iack & RCSR_OE)
502						    && !(rc->rc_flags & RC_WAS_SILOVFL)) {
503							rc->rc_flags |= RC_WAS_SILOVFL;
504							sc->sc_scheduled_event++;
505						}
506						val = rcin(sc, CD180_RDR);
507						/*
508						  Don't store PE if IGNPAR and BREAK if IGNBRK,
509						  this hack allows "raw" tty optimization
510						  works even if IGN* is set.
511						*/
512						if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
513						    || ((!(iack & (RCSR_PE|RCSR_FE))
514						    ||  !(rc->rc_tp.t_iflag & IGNPAR))
515						    && (!(iack & RCSR_Break)
516						    ||  !(rc->rc_tp.t_iflag & IGNBRK)))) {
517							if (   (iack & (RCSR_PE|RCSR_FE))
518							    && (t_state & TS_CAN_BYPASS_L_RINT)
519							    && ((iack & RCSR_FE)
520							    ||  ((iack & RCSR_PE)
521							    &&  (rc->rc_tp.t_iflag & INPCK))))
522								val = 0;
523							else if (val != 0 && val == rc->rc_hotchar)
524								swi_sched(sc->sc_swicookie, 0);
525							optr[0] = val;
526							optr[INPUT_FLAGS_SHIFT] = iack;
527							optr++;
528							sc->sc_scheduled_event++;
529						}
530					}
531				}
532				rc->rc_iptr = optr;
533				rc->rc_flags |= RC_DORXFER;
534			} else
535				resid = ucnt;
536			/* Clear FIFO if necessary */
537			while (resid-- > 0) {
538				if (!good_data)
539					iack = rcin(sc, CD180_RCSR);
540				else
541					iack = 0;
542				if (iack & RCSR_Timeout)
543					break;
544				(void) rcin(sc, CD180_RDR);
545			}
546			goto more_intrs;
547		}
548		if (bsr & RC_BSR_MOINT) {
549			iack = rcin(sc, RC_PILR_MODEM);
550			if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
551				device_printf(sc->sc_dev, "fake moint: %02x\n",
552				    iack);
553				goto more_intrs;
554			}
555			chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
556			rc = &sc->sc_channels[chan];
557			iack = rcin(sc, CD180_MCR);
558			rc->rc_msvr = rcin(sc, CD180_MSVR);
559			rcout(sc, CD180_MCR, 0);
560#ifdef RCDEBUG
561			printrcflags(rc, "moint");
562#endif
563			if (rc->rc_flags & RC_CTSFLOW) {
564				if (rc->rc_msvr & MSVR_CTS)
565					rc->rc_flags |= RC_SEND_RDY;
566				else
567					rc->rc_flags &= ~RC_SEND_RDY;
568			} else
569				rc->rc_flags |= RC_SEND_RDY;
570			if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
571				sc->sc_scheduled_event += LOTS_OF_EVENTS;
572				rc->rc_flags |= RC_MODCHG;
573				swi_sched(sc->sc_swicookie, 0);
574			}
575			goto more_intrs;
576		}
577		if (bsr & RC_BSR_TXINT) {
578			iack = rcin(sc, RC_PILR_TX);
579			if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
580				device_printf(sc->sc_dev, "fake txint: %02x\n",
581				    iack);
582				goto more_intrs;
583			}
584			chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
585			rc = &sc->sc_channels[chan];
586			if (    (rc->rc_flags & RC_OSUSP)
587			    || !(rc->rc_flags & RC_SEND_RDY)
588			   )
589				goto more_intrs;
590			/* Handle breaks and other stuff */
591			if (rc->rc_pendcmd) {
592				rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC);
593				rcout(sc, CD180_TDR,  CD180_C_ESC);
594				rcout(sc, CD180_TDR,  rc->rc_pendcmd);
595				rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
596				rc->rc_pendcmd = 0;
597				goto more_intrs;
598			}
599			optr = rc->rc_optr;
600			resid = rc->rc_obufend - optr;
601			if (resid > CD180_NFIFO)
602				resid = CD180_NFIFO;
603			while (resid-- > 0)
604				rcout(sc, CD180_TDR, *optr++);
605			rc->rc_optr = optr;
606
607			/* output completed? */
608			if (optr >= rc->rc_obufend) {
609				rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy);
610#ifdef RCDEBUG
611				device_printf(sc->sc_dev,
612				    "channel %d: output completed\n",
613				    rc->rc_chan);
614#endif
615				if (!(rc->rc_flags & RC_DOXXFER)) {
616					sc->sc_scheduled_event += LOTS_OF_EVENTS;
617					rc->rc_flags |= RC_DOXXFER;
618					swi_sched(sc->sc_swicookie, 0);
619				}
620			}
621		}
622	more_intrs:
623		rcout(sc, CD180_EOIR, 0);   /* end of interrupt */
624		rcout(sc, RC_CTOUT, 0);
625		bsr = ~(rcin(sc, RC_BSR));
626	}
627}
628
629/* Feed characters to output buffer */
630static void
631rc_start(struct tty *tp)
632{
633	struct rc_softc *sc;
634	struct rc_chans *rc;
635	int s;
636
637	rc = TTY_TO_RC(tp);
638	if (rc->rc_flags & RC_OSBUSY)
639		return;
640	sc = rc->rc_rcb;
641	s = spltty();
642	rc->rc_flags |= RC_OSBUSY;
643	critical_enter();
644	if (tp->t_state & TS_TTSTOP)
645		rc->rc_flags |= RC_OSUSP;
646	else
647		rc->rc_flags &= ~RC_OSUSP;
648	/* Do RTS flow control stuff */
649	if (   (rc->rc_flags & RC_RTSFLOW)
650	    && (tp->t_state & TS_TBLOCK)
651	    && (rc->rc_msvr & MSVR_RTS)
652	   ) {
653		rcout(sc, CD180_CAR, rc->rc_chan);
654		rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
655	} else if (!(rc->rc_msvr & MSVR_RTS)) {
656		rcout(sc, CD180_CAR, rc->rc_chan);
657		rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
658	}
659	critical_exit();
660	if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
661		goto out;
662#ifdef RCDEBUG
663	printrcflags(rc, "rcstart");
664#endif
665	ttwwakeup(tp);
666#ifdef RCDEBUG
667	printf("rcstart: outq = %d obuf = %d\n",
668		tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
669#endif
670	if (tp->t_state & TS_BUSY)
671		goto out;    /* output still in progress ... */
672
673	if (tp->t_outq.c_cc > 0) {
674		u_int   ocnt;
675
676		tp->t_state |= TS_BUSY;
677		ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
678		critical_enter();
679		rc->rc_optr = rc->rc_obuf;
680		rc->rc_obufend = rc->rc_optr + ocnt;
681		critical_exit();
682		if (!(rc->rc_ier & IER_TxRdy)) {
683#ifdef RCDEBUG
684			device_printf(sc->sc_dev,
685			    "channel %d: rcstart enable txint\n", rc->rc_chan);
686#endif
687			rcout(sc, CD180_CAR, rc->rc_chan);
688			rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy);
689		}
690	}
691out:
692	rc->rc_flags &= ~RC_OSBUSY;
693	(void) splx(s);
694}
695
696/* Handle delayed events. */
697void
698rc_pollcard(void *arg)
699{
700	struct rc_softc *sc;
701	struct rc_chans *rc;
702	struct tty *tp;
703	u_char *tptr, *eptr;
704	int chan, icnt;
705
706	sc = (struct rc_softc *)arg;
707	if (sc->sc_scheduled_event == 0)
708		return;
709	do {
710		rc = sc->sc_channels;
711		for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
712			tp = &rc->rc_tp;
713#ifdef RCDEBUG
714			if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
715			    RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
716				printrcflags(rc, "rcevent");
717#endif
718			if (rc->rc_flags & RC_WAS_BUFOVFL) {
719				critical_enter();
720				rc->rc_flags &= ~RC_WAS_BUFOVFL;
721				sc->sc_scheduled_event--;
722				critical_exit();
723				device_printf(sc->sc_dev,
724			    "channel %d: interrupt-level buffer overflow\n",
725				     chan);
726			}
727			if (rc->rc_flags & RC_WAS_SILOVFL) {
728				critical_enter();
729				rc->rc_flags &= ~RC_WAS_SILOVFL;
730				sc->sc_scheduled_event--;
731				critical_exit();
732				device_printf(sc->sc_dev,
733				    "channel %d: silo overflow\n", chan);
734			}
735			if (rc->rc_flags & RC_MODCHG) {
736				critical_enter();
737				rc->rc_flags &= ~RC_MODCHG;
738				sc->sc_scheduled_event -= LOTS_OF_EVENTS;
739				critical_exit();
740				ttyld_modem(tp, !!(rc->rc_msvr & MSVR_CD));
741			}
742			if (rc->rc_flags & RC_DORXFER) {
743				critical_enter();
744				rc->rc_flags &= ~RC_DORXFER;
745				eptr = rc->rc_iptr;
746				if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
747					tptr = &rc->rc_ibuf[RC_IBUFSIZE];
748				else
749					tptr = rc->rc_ibuf;
750				icnt = eptr - tptr;
751				if (icnt > 0) {
752					if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
753						rc->rc_iptr   = rc->rc_ibuf;
754						rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
755						rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
756					} else {
757						rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
758						rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
759						rc->rc_hiwat  =
760							&rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
761					}
762					if (   (rc->rc_flags & RC_RTSFLOW)
763					    && (tp->t_state & TS_ISOPEN)
764					    && !(tp->t_state & TS_TBLOCK)
765					    && !(rc->rc_msvr & MSVR_RTS)
766					    ) {
767						rcout(sc, CD180_CAR, chan);
768						rcout(sc, CD180_MSVR,
769							rc->rc_msvr |= MSVR_RTS);
770					}
771					sc->sc_scheduled_event -= icnt;
772				}
773				critical_exit();
774
775				if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
776					goto done1;
777
778				if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
779				    && !(tp->t_state & TS_LOCAL)) {
780					if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
781					    && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
782					    && !(tp->t_state & TS_TBLOCK))
783						ttyblock(tp);
784					tk_nin += icnt;
785					tk_rawcc += icnt;
786					tp->t_rawcc += icnt;
787					if (b_to_q(tptr, icnt, &tp->t_rawq))
788						device_printf(sc->sc_dev,
789				    "channel %d: tty-level buffer overflow\n",
790						    chan);
791					ttwakeup(tp);
792					if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
793					    || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
794						tp->t_state &= ~TS_TTSTOP;
795						tp->t_lflag &= ~FLUSHO;
796						rc_start(tp);
797					}
798				} else {
799					for (; tptr < eptr; tptr++)
800						ttyld_rint(tp,
801						    (tptr[0] |
802						    rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF]));
803				}
804done1: ;
805			}
806			if (rc->rc_flags & RC_DOXXFER) {
807				critical_enter();
808				sc->sc_scheduled_event -= LOTS_OF_EVENTS;
809				rc->rc_flags &= ~RC_DOXXFER;
810				rc->rc_tp.t_state &= ~TS_BUSY;
811				critical_exit();
812				ttyld_start(tp);
813			}
814			if (sc->sc_scheduled_event == 0)
815				break;
816		}
817	} while (sc->sc_scheduled_event >= LOTS_OF_EVENTS);
818}
819
820static void
821rc_stop(struct tty *tp, int rw)
822{
823	struct rc_softc *sc;
824	struct rc_chans *rc;
825	u_char *tptr, *eptr;
826
827	rc = TTY_TO_RC(tp);
828	sc = rc->rc_rcb;
829#ifdef RCDEBUG
830	device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n",
831	    rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
832#endif
833	if (rw & FWRITE)
834		rc_discard_output(rc);
835	critical_enter();
836	if (rw & FREAD) {
837		rc->rc_flags &= ~RC_DORXFER;
838		eptr = rc->rc_iptr;
839		if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
840			tptr = &rc->rc_ibuf[RC_IBUFSIZE];
841			rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
842		} else {
843			tptr = rc->rc_ibuf;
844			rc->rc_iptr = rc->rc_ibuf;
845		}
846		sc->sc_scheduled_event -= eptr - tptr;
847	}
848	if (tp->t_state & TS_TTSTOP)
849		rc->rc_flags |= RC_OSUSP;
850	else
851		rc->rc_flags &= ~RC_OSUSP;
852	critical_exit();
853}
854
855static int
856rcopen(struct cdev *dev, int flag, int mode, d_thread_t *td)
857{
858	struct rc_softc *sc;
859	struct rc_chans *rc;
860	struct tty *tp;
861	int s, error = 0;
862
863	rc = DEV_TO_RC(dev);
864	sc = rc->rc_rcb;
865	tp = &rc->rc_tp;
866	if (sc->sc_opencount < 0)
867		return (ENXIO);
868	sc->sc_opencount++;
869#ifdef RCDEBUG
870	device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n",
871	    rc->rc_chan, dev);
872#endif
873	s = spltty();
874
875again:
876	while (rc->rc_flags & RC_DTR_OFF) {
877		error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
878		if (error != 0)
879			goto out;
880	}
881	if (tp->t_state & TS_ISOPEN) {
882		if (CALLOUT(dev)) {
883			if (!(rc->rc_flags & RC_ACTOUT)) {
884				error = EBUSY;
885				goto out;
886			}
887		} else {
888			if (rc->rc_flags & RC_ACTOUT) {
889				if (flag & O_NONBLOCK) {
890					error = EBUSY;
891					goto out;
892				}
893				error = tsleep(&rc->rc_rcb,
894				     TTIPRI|PCATCH, "rcbi", 0);
895				if (error)
896					goto out;
897				goto again;
898			}
899		}
900		if (tp->t_state & TS_XCLUDE &&
901		    suser(td)) {
902			error = EBUSY;
903			goto out;
904		}
905	} else {
906		tp->t_oproc   = rc_start;
907		tp->t_param   = rc_param;
908		tp->t_stop    = rc_stop;
909		tp->t_dev     = dev;
910
911		if (CALLOUT(dev))
912			tp->t_cflag |= CLOCAL;
913		else
914			tp->t_cflag &= ~CLOCAL;
915
916		error = rc_param(tp, &tp->t_termios);
917		if (error)
918			goto out;
919		(void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
920
921		if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
922			ttyld_modem(tp, 1);
923	}
924	if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
925	    && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
926		rc->rc_dcdwaits++;
927		error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0);
928		rc->rc_dcdwaits--;
929		if (error != 0)
930			goto out;
931		goto again;
932	}
933	error = ttyld_open(tp, dev);
934	rc->rc_hotchar = ttyldoptim(tp);
935	if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
936		rc->rc_flags |= RC_ACTOUT;
937out:
938	(void) splx(s);
939
940	if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
941		rc_hardclose(rc);
942
943	return error;
944}
945
946static int
947rcclose(struct cdev *dev, int flag, int mode, d_thread_t *td)
948{
949	struct rc_softc *sc;
950	struct rc_chans *rc;
951	struct tty *tp;
952	int  s;
953
954	rc = DEV_TO_RC(dev);
955	sc = rc->rc_rcb;
956	tp = &rc->rc_tp;
957#ifdef RCDEBUG
958	device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n",
959	    rc->rc_chan, dev);
960#endif
961	s = spltty();
962	ttyld_close(tp, flag);
963	rc->rc_hotchar = ttyldoptim(tp);
964	rc_hardclose(rc);
965	ttyclose(tp);
966	splx(s);
967	KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count"));
968	sc->sc_opencount--;
969	return 0;
970}
971
972static void
973rc_hardclose(struct rc_chans *rc)
974{
975	struct rc_softc *sc;
976	struct tty *tp;
977	int s;
978
979	tp = &rc->rc_tp;
980	sc = rc->rc_rcb;
981	s = spltty();
982	rcout(sc, CD180_CAR, rc->rc_chan);
983
984	/* Disable rx/tx intrs */
985	rcout(sc, CD180_IER, rc->rc_ier = 0);
986	if (   (tp->t_cflag & HUPCL)
987	    || (!(rc->rc_flags & RC_ACTOUT)
988	       && !(rc->rc_msvr & MSVR_CD)
989	       && !(tp->t_cflag & CLOCAL))
990	    || !(tp->t_state & TS_ISOPEN)
991	   ) {
992		CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
993		WAITFORCCR(sc, rc->rc_chan);
994		(void) rc_modctl(rc, TIOCM_RTS, DMSET);
995		if (rc->rc_dtrwait) {
996			callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait,
997			    rc_dtrwakeup, rc);
998			rc->rc_flags |= RC_DTR_OFF;
999		}
1000	}
1001	rc->rc_flags &= ~RC_ACTOUT;
1002	wakeup( &rc->rc_rcb);  /* wake bi */
1003	wakeup(TSA_CARR_ON(tp));
1004	(void) splx(s);
1005}
1006
1007/* Reset the bastard */
1008static void
1009rc_hwreset(struct rc_softc *sc, u_int chipid)
1010{
1011	CCRCMD(sc, -1, CCR_HWRESET);            /* Hardware reset */
1012	DELAY(20000);
1013	WAITFORCCR(sc, -1);
1014
1015	rcout(sc, RC_CTOUT, 0);             /* Clear timeout  */
1016	rcout(sc, CD180_GIVR,  chipid);
1017	rcout(sc, CD180_GICR,  0);
1018
1019	/* Set Prescaler Registers (1 msec) */
1020	rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
1021	rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
1022
1023	/* Initialize Priority Interrupt Level Registers */
1024	rcout(sc, CD180_PILR1, RC_PILR_MODEM);
1025	rcout(sc, CD180_PILR2, RC_PILR_TX);
1026	rcout(sc, CD180_PILR3, RC_PILR_RX);
1027
1028	/* Reset DTR */
1029	rcout(sc, RC_DTREG, ~0);
1030}
1031
1032/* Set channel parameters */
1033static int
1034rc_param(struct tty *tp, struct termios *ts)
1035{
1036	struct rc_softc *sc;
1037	struct rc_chans *rc;
1038	int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
1039
1040	if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
1041	    || ts->c_ispeed < 0 || ts->c_ispeed > 76800
1042	   )
1043		return (EINVAL);
1044	if (ts->c_ispeed == 0)
1045		ts->c_ispeed = ts->c_ospeed;
1046	odivs = RC_BRD(ts->c_ospeed);
1047	idivs = RC_BRD(ts->c_ispeed);
1048
1049	rc = TTY_TO_RC(tp);
1050	sc = rc->rc_rcb;
1051	s = spltty();
1052
1053	/* Select channel */
1054	rcout(sc, CD180_CAR, rc->rc_chan);
1055
1056	/* If speed == 0, hangup line */
1057	if (ts->c_ospeed == 0) {
1058		CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
1059		WAITFORCCR(sc, rc->rc_chan);
1060		(void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1061	}
1062
1063	tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1064	cflag = ts->c_cflag;
1065	iflag = ts->c_iflag;
1066	lflag = ts->c_lflag;
1067
1068	if (idivs > 0) {
1069		rcout(sc, CD180_RBPRL, idivs & 0xFF);
1070		rcout(sc, CD180_RBPRH, idivs >> 8);
1071	}
1072	if (odivs > 0) {
1073		rcout(sc, CD180_TBPRL, odivs & 0xFF);
1074		rcout(sc, CD180_TBPRH, odivs >> 8);
1075	}
1076
1077	/* set timeout value */
1078	if (ts->c_ispeed > 0) {
1079		int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
1080
1081		if (   !(lflag & ICANON)
1082		    && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
1083		    && ts->c_cc[VTIME] * 10 > itm)
1084			itm = ts->c_cc[VTIME] * 10;
1085
1086		rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255);
1087	}
1088
1089	switch (cflag & CSIZE) {
1090		case CS5:       val = COR1_5BITS;      break;
1091		case CS6:       val = COR1_6BITS;      break;
1092		case CS7:       val = COR1_7BITS;      break;
1093		default:
1094		case CS8:       val = COR1_8BITS;      break;
1095	}
1096	if (cflag & PARENB) {
1097		val |= COR1_NORMPAR;
1098		if (cflag & PARODD)
1099			val |= COR1_ODDP;
1100		if (!(cflag & INPCK))
1101			val |= COR1_Ignore;
1102	} else
1103		val |= COR1_Ignore;
1104	if (cflag & CSTOPB)
1105		val |= COR1_2SB;
1106	rcout(sc, CD180_COR1, val);
1107
1108	/* Set FIFO threshold */
1109	val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
1110	inpflow = 0;
1111	if (   (iflag & IXOFF)
1112	    && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
1113		&& (   ts->c_cc[VSTART] != _POSIX_VDISABLE
1114		    || (iflag & IXANY)
1115		   )
1116	       )
1117	   ) {
1118		inpflow = 1;
1119		val |= COR3_SCDE|COR3_FCT;
1120	}
1121	rcout(sc, CD180_COR3, val);
1122
1123	/* Initialize on-chip automatic flow control */
1124	val = 0;
1125	rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
1126	if (cflag & CCTS_OFLOW) {
1127		rc->rc_flags |= RC_CTSFLOW;
1128		val |= COR2_CtsAE;
1129	} else
1130		rc->rc_flags |= RC_SEND_RDY;
1131	if (tp->t_state & TS_TTSTOP)
1132		rc->rc_flags |= RC_OSUSP;
1133	else
1134		rc->rc_flags &= ~RC_OSUSP;
1135	if (cflag & CRTS_IFLOW)
1136		rc->rc_flags |= RC_RTSFLOW;
1137	else
1138		rc->rc_flags &= ~RC_RTSFLOW;
1139
1140	if (inpflow) {
1141		if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1142			rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]);
1143		rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]);
1144		val |= COR2_TxIBE;
1145		if (iflag & IXANY)
1146			val |= COR2_IXM;
1147	}
1148
1149	rcout(sc, CD180_COR2, rc->rc_cor2 = val);
1150
1151	CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1152
1153	rc->rc_hotchar = ttyldoptim(tp);
1154
1155	/* modem ctl */
1156	val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1157	if (cflag & CCTS_OFLOW)
1158		val |= MCOR1_CTSzd;
1159	rcout(sc, CD180_MCOR1, val);
1160
1161	val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1162	if (cflag & CCTS_OFLOW)
1163		val |= MCOR2_CTSod;
1164	rcout(sc, CD180_MCOR2, val);
1165
1166	/* enable i/o and interrupts */
1167	CCRCMD(sc, rc->rc_chan,
1168		CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1169	WAITFORCCR(sc, rc->rc_chan);
1170
1171	rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1172	if (cflag & CCTS_OFLOW)
1173		rc->rc_ier |= IER_CTS;
1174	if (cflag & CREAD)
1175		rc->rc_ier |= IER_RxData;
1176	if (tp->t_state & TS_BUSY)
1177		rc->rc_ier |= IER_TxRdy;
1178	if (ts->c_ospeed != 0)
1179		rc_modctl(rc, TIOCM_DTR, DMBIS);
1180	if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1181		rc->rc_flags |= RC_SEND_RDY;
1182	rcout(sc, CD180_IER, rc->rc_ier);
1183	(void) splx(s);
1184	return 0;
1185}
1186
1187/* Re-initialize board after bogus interrupts */
1188static void
1189rc_reinit(struct rc_softc *sc)
1190{
1191	struct rc_chans *rc;
1192	int i;
1193
1194	rc_hwreset(sc, RC_FAKEID);
1195	rc = sc->sc_channels;
1196	for (i = 0; i < CD180_NCHAN; i++, rc++)
1197		(void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios);
1198}
1199
1200static int
1201rcioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, d_thread_t *td)
1202{
1203	struct rc_chans *rc;
1204	struct tty *tp;
1205	int s, error;
1206
1207	rc = DEV_TO_RC(dev);
1208	tp = &rc->rc_tp;
1209	error = ttyioctl(dev, cmd, data, flag, td);
1210	rc->rc_hotchar = ttyldoptim(tp);
1211	if (error != ENOTTY)
1212		return (error);
1213	s = spltty();
1214
1215	switch (cmd) {
1216	    case TIOCSBRK:
1217		rc->rc_pendcmd = CD180_C_SBRK;
1218		break;
1219
1220	    case TIOCCBRK:
1221		rc->rc_pendcmd = CD180_C_EBRK;
1222		break;
1223
1224	    case TIOCSDTR:
1225		(void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1226		break;
1227
1228	    case TIOCCDTR:
1229		(void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1230		break;
1231
1232	    case TIOCMGET:
1233		*(int *) data = rc_modctl(rc, 0, DMGET);
1234		break;
1235
1236	    case TIOCMSET:
1237		(void) rc_modctl(rc, *(int *) data, DMSET);
1238		break;
1239
1240	    case TIOCMBIC:
1241		(void) rc_modctl(rc, *(int *) data, DMBIC);
1242		break;
1243
1244	    case TIOCMBIS:
1245		(void) rc_modctl(rc, *(int *) data, DMBIS);
1246		break;
1247
1248	    case TIOCMSDTRWAIT:
1249		error = suser(td);
1250		if (error != 0) {
1251			splx(s);
1252			return (error);
1253		}
1254		rc->rc_dtrwait = *(int *)data * hz / 100;
1255		break;
1256
1257	    case TIOCMGDTRWAIT:
1258		*(int *)data = rc->rc_dtrwait * 100 / hz;
1259		break;
1260
1261	    default:
1262		(void) splx(s);
1263		return ENOTTY;
1264	}
1265	(void) splx(s);
1266	return 0;
1267}
1268
1269
1270/* Modem control routines */
1271
1272static int
1273rc_modctl(struct rc_chans *rc, int bits, int cmd)
1274{
1275	struct rc_softc *sc;
1276	u_char *dtr;
1277	u_char msvr;
1278
1279	sc = rc->rc_rcb;
1280	dtr = &sc->sc_dtr;
1281	rcout(sc, CD180_CAR, rc->rc_chan);
1282
1283	switch (cmd) {
1284	    case DMSET:
1285		rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ?
1286				~(*dtr |= 1 << rc->rc_chan) :
1287				~(*dtr &= ~(1 << rc->rc_chan)));
1288		msvr = rcin(sc, CD180_MSVR);
1289		if (bits & TIOCM_RTS)
1290			msvr |= MSVR_RTS;
1291		else
1292			msvr &= ~MSVR_RTS;
1293		if (bits & TIOCM_DTR)
1294			msvr |= MSVR_DTR;
1295		else
1296			msvr &= ~MSVR_DTR;
1297		rcout(sc, CD180_MSVR, msvr);
1298		break;
1299
1300	    case DMBIS:
1301		if (bits & TIOCM_DTR)
1302			rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1303		msvr = rcin(sc, CD180_MSVR);
1304		if (bits & TIOCM_RTS)
1305			msvr |= MSVR_RTS;
1306		if (bits & TIOCM_DTR)
1307			msvr |= MSVR_DTR;
1308		rcout(sc, CD180_MSVR, msvr);
1309		break;
1310
1311	    case DMGET:
1312		bits = TIOCM_LE;
1313		msvr = rc->rc_msvr = rcin(sc, CD180_MSVR);
1314
1315		if (msvr & MSVR_RTS)
1316			bits |= TIOCM_RTS;
1317		if (msvr & MSVR_CTS)
1318			bits |= TIOCM_CTS;
1319		if (msvr & MSVR_DSR)
1320			bits |= TIOCM_DSR;
1321		if (msvr & MSVR_DTR)
1322			bits |= TIOCM_DTR;
1323		if (msvr & MSVR_CD)
1324			bits |= TIOCM_CD;
1325		if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan))
1326			bits |= TIOCM_RI;
1327		return bits;
1328
1329	    case DMBIC:
1330		if (bits & TIOCM_DTR)
1331			rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1332		msvr = rcin(sc, CD180_MSVR);
1333		if (bits & TIOCM_RTS)
1334			msvr &= ~MSVR_RTS;
1335		if (bits & TIOCM_DTR)
1336			msvr &= ~MSVR_DTR;
1337		rcout(sc, CD180_MSVR, msvr);
1338		break;
1339	}
1340	rc->rc_msvr = rcin(sc, CD180_MSVR);
1341	return 0;
1342}
1343
1344#define ERR(s) do {							\
1345	device_printf(sc->sc_dev, "%s", "");				\
1346	printf s ;							\
1347	printf("\n");							\
1348	(void) splx(old_level);						\
1349	return 1;							\
1350} while (0)
1351
1352/* Test the board. */
1353int
1354rc_test(struct rc_softc *sc)
1355{
1356	int     chan = 0;
1357	int     i = 0, rcnt, old_level;
1358	unsigned int    iack, chipid;
1359	unsigned short  divs;
1360	static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1361#define CTLEN   8
1362
1363	struct rtest {
1364		u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1365		u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1366		int     rxptr;                  /* RX pointer */
1367		int     txptr;                  /* TX pointer */
1368	} tchans[CD180_NCHAN];
1369
1370	old_level = spltty();
1371
1372	chipid = RC_FAKEID;
1373
1374	/* First, reset board to inital state */
1375	rc_hwreset(sc, chipid);
1376
1377	divs = RC_BRD(19200);
1378
1379	/* Initialize channels */
1380	for (chan = 0; chan < CD180_NCHAN; chan++) {
1381
1382		/* Select and reset channel */
1383		rcout(sc, CD180_CAR, chan);
1384		CCRCMD(sc, chan, CCR_ResetChan);
1385		WAITFORCCR(sc, chan);
1386
1387		/* Set speed */
1388		rcout(sc, CD180_RBPRL, divs & 0xFF);
1389		rcout(sc, CD180_RBPRH, divs >> 8);
1390		rcout(sc, CD180_TBPRL, divs & 0xFF);
1391		rcout(sc, CD180_TBPRH, divs >> 8);
1392
1393		/* set timeout value */
1394		rcout(sc, CD180_RTPR,  0);
1395
1396		/* Establish local loopback */
1397		rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1398		rcout(sc, CD180_COR2, COR2_LLM);
1399		rcout(sc, CD180_COR3, CD180_NFIFO);
1400		CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1401		CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN);
1402		WAITFORCCR(sc, chan);
1403		rcout(sc, CD180_MSVR, MSVR_RTS);
1404
1405		/* Fill TXBUF with test data */
1406		for (i = 0; i < CD180_NFIFO; i++) {
1407			tchans[chan].txbuf[i] = ctest[i];
1408			tchans[chan].rxbuf[i] = 0;
1409		}
1410		tchans[chan].txptr = tchans[chan].rxptr = 0;
1411
1412		/* Now, start transmit */
1413		rcout(sc, CD180_IER, IER_TxMpty|IER_RxData);
1414	}
1415	/* Pseudo-interrupt poll stuff */
1416	for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1417		i = ~(rcin(sc, RC_BSR));
1418		if (i & RC_BSR_TOUT)
1419			ERR(("BSR timeout bit set\n"));
1420		else if (i & RC_BSR_TXINT) {
1421			iack = rcin(sc, RC_PILR_TX);
1422			if (iack != (GIVR_IT_TDI | chipid))
1423				ERR(("Bad TX intr ack (%02x != %02x)\n",
1424					iack, GIVR_IT_TDI | chipid));
1425			chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1426			/* If no more data to transmit, disable TX intr */
1427			if (tchans[chan].txptr >= CD180_NFIFO) {
1428				iack = rcin(sc, CD180_IER);
1429				rcout(sc, CD180_IER, iack & ~IER_TxMpty);
1430			} else {
1431				for (iack = tchans[chan].txptr;
1432				    iack < CD180_NFIFO; iack++)
1433					rcout(sc, CD180_TDR,
1434					    tchans[chan].txbuf[iack]);
1435				tchans[chan].txptr = iack;
1436			}
1437			rcout(sc, CD180_EOIR, 0);
1438		} else if (i & RC_BSR_RXINT) {
1439			u_char ucnt;
1440
1441			iack = rcin(sc, RC_PILR_RX);
1442			if (iack != (GIVR_IT_RGDI | chipid) &&
1443			    iack != (GIVR_IT_REI  | chipid))
1444				ERR(("Bad RX intr ack (%02x != %02x)\n",
1445					iack, GIVR_IT_RGDI | chipid));
1446			chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1447			ucnt = rcin(sc, CD180_RDCR) & 0xF;
1448			while (ucnt-- > 0) {
1449				iack = rcin(sc, CD180_RCSR);
1450				if (iack & RCSR_Timeout)
1451					break;
1452				if (iack & 0xF)
1453					ERR(("Bad char chan %d (RCSR = %02X)\n",
1454					    chan, iack));
1455				if (tchans[chan].rxptr > CD180_NFIFO)
1456					ERR(("Got extra chars chan %d\n",
1457					    chan));
1458				tchans[chan].rxbuf[tchans[chan].rxptr++] =
1459					rcin(sc, CD180_RDR);
1460			}
1461			rcout(sc, CD180_EOIR, 0);
1462		}
1463		rcout(sc, RC_CTOUT, 0);
1464		for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1465			if (tchans[chan].rxptr >= CD180_NFIFO)
1466				iack++;
1467		if (iack == CD180_NCHAN)
1468			break;
1469	}
1470	for (chan = 0; chan < CD180_NCHAN; chan++) {
1471		/* Select and reset channel */
1472		rcout(sc, CD180_CAR, chan);
1473		CCRCMD(sc, chan, CCR_ResetChan);
1474	}
1475
1476	if (!rcnt)
1477		ERR(("looses characters during local loopback\n"));
1478	/* Now, check data */
1479	for (chan = 0; chan < CD180_NCHAN; chan++)
1480		for (i = 0; i < CD180_NFIFO; i++)
1481			if (ctest[i] != tchans[chan].rxbuf[i])
1482				ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1483				    chan, i, ctest[i], tchans[chan].rxbuf[i]));
1484	(void) splx(old_level);
1485	return 0;
1486}
1487
1488#ifdef RCDEBUG
1489static void
1490printrcflags(struct rc_chans *rc, char *comment)
1491{
1492	struct rc_softc *sc;
1493	u_short f = rc->rc_flags;
1494
1495	sc = rc->rc_rcb;
1496	printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1497		rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1498		(f & RC_DTR_OFF)?"DTR_OFF " :"",
1499		(f & RC_ACTOUT) ?"ACTOUT " :"",
1500		(f & RC_RTSFLOW)?"RTSFLOW " :"",
1501		(f & RC_CTSFLOW)?"CTSFLOW " :"",
1502		(f & RC_DORXFER)?"DORXFER " :"",
1503		(f & RC_DOXXFER)?"DOXXFER " :"",
1504		(f & RC_MODCHG) ?"MODCHG "  :"",
1505		(f & RC_OSUSP)  ?"OSUSP " :"",
1506		(f & RC_OSBUSY) ?"OSBUSY " :"",
1507		(f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1508		(f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1509		(f & RC_SEND_RDY) ?"SEND_RDY":"");
1510
1511	rcout(sc, CD180_CAR, rc->rc_chan);
1512
1513	printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1514		rc->rc_rcb->rcb_unit, rc->rc_chan,
1515		rcin(sc, CD180_MSVR),
1516		rcin(sc, CD180_IER),
1517		rcin(sc, CD180_CCSR));
1518}
1519#endif /* RCDEBUG */
1520
1521static void
1522rc_dtrwakeup(void *arg)
1523{
1524	struct rc_chans  *rc;
1525
1526	rc = (struct rc_chans *)arg;
1527	rc->rc_flags &= ~RC_DTR_OFF;
1528	wakeup(&rc->rc_dtrwait);
1529}
1530
1531static void
1532rc_discard_output(struct rc_chans *rc)
1533{
1534	critical_enter();
1535	if (rc->rc_flags & RC_DOXXFER) {
1536		rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS;
1537		rc->rc_flags &= ~RC_DOXXFER;
1538	}
1539	rc->rc_optr = rc->rc_obufend;
1540	rc->rc_tp.t_state &= ~TS_BUSY;
1541	critical_exit();
1542	ttwwakeup(&rc->rc_tp);
1543}
1544
1545static void
1546rc_wait0(struct rc_softc *sc, int chan, int line)
1547{
1548	int rcnt;
1549
1550	for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--)
1551		DELAY(30);
1552	if (rcnt == 0)
1553		device_printf(sc->sc_dev,
1554		    "channel %d command timeout, rc.c line: %d\n", chan, line);
1555}
1556
1557static device_method_t rc_methods[] = {
1558	/* Device interface */
1559	DEVMETHOD(device_probe,		rc_probe),
1560	DEVMETHOD(device_attach,	rc_attach),
1561	DEVMETHOD(device_detach,	rc_detach),
1562	{ 0, 0 }
1563};
1564
1565static driver_t rc_driver = {
1566	"rc",
1567	rc_methods, sizeof(struct rc_softc),
1568};
1569
1570DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0);
1571