rc.c revision 129939
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/rc/rc.c 129939 2004-06-01 11:57:15Z phk $ 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36/*#define RCDEBUG*/ 37 38#include "opt_tty.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/conf.h> 44#include <sys/fcntl.h> 45#include <sys/interrupt.h> 46#include <sys/kernel.h> 47#include <sys/malloc.h> 48#include <sys/module.h> 49#include <sys/tty.h> 50#include <machine/bus.h> 51#include <machine/resource.h> 52#include <sys/rman.h> 53 54#include <dev/ic/cd180.h> 55#include <dev/rc/rcreg.h> 56#include <isa/isavar.h> 57 58#define IOBASE_ADDRS 14 59 60#define DEV_TO_RC(dev) (struct rc_chans *)((dev)->si_drv1) 61#define TTY_TO_RC(tty) DEV_TO_RC((tty)->t_dev) 62 63#define rcin(sc, port) RC_IN(sc, port) 64#define rcout(sc, port, v) RC_OUT(sc, port, v) 65 66#define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__) 67 68#define CCRCMD(sc, chan, cmd) do { \ 69 WAITFORCCR((sc), (chan)); \ 70 rcout((sc), CD180_CCR, (cmd)); \ 71} while (0) 72 73#define RC_IBUFSIZE 256 74#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 75#define RC_OBUFSIZE 512 76#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 77#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 78#define LOTS_OF_EVENTS 64 79 80#define RC_FAKEID 0x10 81 82#define CALLOUT(dev) (((intptr_t)(dev)->si_drv2) != 0) 83 84/* Per-channel structure */ 85struct rc_chans { 86 struct rc_softc *rc_rcb; /* back ptr */ 87 dev_t rc_dev; /* non-callout device */ 88 dev_t rc_cdev; /* callout device */ 89 u_short rc_flags; /* Misc. flags */ 90 int rc_chan; /* Channel # */ 91 u_char rc_ier; /* intr. enable reg */ 92 u_char rc_msvr; /* modem sig. status */ 93 u_char rc_cor2; /* options reg */ 94 u_char rc_pendcmd; /* special cmd pending */ 95 u_int rc_dtrwait; /* dtr timeout */ 96 u_int rc_dcdwaits; /* how many waits DCD in open */ 97 u_char rc_hotchar; /* end packed optimize */ 98 struct tty rc_tp; /* tty struct */ 99 u_char *rc_iptr; /* Chars input buffer */ 100 u_char *rc_hiwat; /* hi-water mark */ 101 u_char *rc_bufend; /* end of buffer */ 102 u_char *rc_optr; /* ptr in output buf */ 103 u_char *rc_obufend; /* end of output buf */ 104 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 105 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 106 struct callout rc_dtrcallout; 107}; 108 109/* Per-board structure */ 110struct rc_softc { 111 device_t sc_dev; 112 struct resource *sc_irq; 113 struct resource *sc_port[IOBASE_ADDRS]; 114 int sc_irqrid; 115 void *sc_hwicookie; 116 bus_space_tag_t sc_bt; 117 bus_space_handle_t sc_bh; 118 u_int sc_unit; /* unit # */ 119 u_char sc_dtr; /* DTR status */ 120 int sc_opencount; 121 int sc_scheduled_event; 122 void *sc_swicookie; 123 struct rc_chans sc_channels[CD180_NCHAN]; /* channels */ 124}; 125 126/* Static prototypes */ 127static void rc_release_resources(device_t dev); 128static void rc_intr(void *); 129static void rc_hwreset(struct rc_softc *, unsigned int); 130static int rc_test(struct rc_softc *); 131static void rc_discard_output(struct rc_chans *); 132static void rc_hardclose(struct rc_chans *); 133static int rc_modctl(struct rc_chans *, int, int); 134static void rc_start(struct tty *); 135static void rc_stop(struct tty *, int rw); 136static int rc_param(struct tty *, struct termios *); 137static void rc_pollcard(void *); 138static void rc_reinit(struct rc_softc *); 139#ifdef RCDEBUG 140static void printrcflags(); 141#endif 142static void rc_dtrwakeup(void *); 143static void disc_optim(struct tty *tp, struct termios *t, struct rc_chans *); 144static void rc_wait0(struct rc_softc *sc, int chan, int line); 145 146static d_open_t rcopen; 147static d_close_t rcclose; 148static d_ioctl_t rcioctl; 149 150static struct cdevsw rc_cdevsw = { 151 .d_version = D_VERSION, 152 .d_open = rcopen, 153 .d_close = rcclose, 154 .d_ioctl = rcioctl, 155 .d_name = "rc", 156 .d_flags = D_TTY | D_NEEDGIANT, 157}; 158 159static devclass_t rc_devclass; 160 161/* Flags */ 162#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 163#define RC_ACTOUT 0x0002 /* Dial-out port active */ 164#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 165#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 166#define RC_DORXFER 0x0010 /* RXFER event planned */ 167#define RC_DOXXFER 0x0020 /* XXFER event planned */ 168#define RC_MODCHG 0x0040 /* Modem status changed */ 169#define RC_OSUSP 0x0080 /* Output suspended */ 170#define RC_OSBUSY 0x0100 /* start() routine in progress */ 171#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 172#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 173#define RC_SEND_RDY 0x0800 /* ready to send */ 174 175/* Table for translation of RCSR status bits to internal form */ 176static int rc_rcsrt[16] = { 177 0, TTY_OE, TTY_FE, 178 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 179 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 180 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 181 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 182 TTY_BI|TTY_PE|TTY_FE|TTY_OE 183}; 184 185static int rc_ports[] = 186 { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 }; 187static int iobase_addrs[IOBASE_ADDRS] = 188 { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000, 189 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 }; 190 191/**********************************************/ 192 193static int 194rc_probe(device_t dev) 195{ 196 u_int port; 197 int i, found; 198 199 /* 200 * We don't know of any PnP ID's for these cards. 201 */ 202 if (isa_get_logicalid(dev) != 0) 203 return (ENXIO); 204 205 /* 206 * We have to have an IO port hint that is valid. 207 */ 208 port = isa_get_port(dev); 209 if (port == -1) 210 return (ENXIO); 211 found = 0; 212 for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++) 213 if (rc_ports[i] == port) { 214 found = 1; 215 break; 216 } 217 if (!found) 218 return (ENXIO); 219 220 /* 221 * We have to have an IRQ hint. 222 */ 223 if (isa_get_irq(dev) == -1) 224 return (ENXIO); 225 226 device_set_desc(dev, "SDL Riscom/8"); 227 return (0); 228} 229 230static int 231rc_attach(device_t dev) 232{ 233 struct rc_chans *rc; 234 struct tty *tp; 235 struct rc_softc *sc; 236 u_int port; 237 int base, chan, error, i, x; 238 dev_t cdev; 239 240 sc = device_get_softc(dev); 241 sc->sc_dev = dev; 242 243 /* 244 * We need to have IO ports. Lots of them. We need 245 * the following ranges relative to the base port: 246 * 0x0 - 0x10 247 * 0x400 - 0x410 248 * 0x800 - 0x810 249 * 0xc00 - 0xc10 250 * 0x1400 - 0x1410 251 * 0x1800 - 0x1810 252 * 0x1c00 - 0x1c10 253 * 0x2000 - 0x2010 254 * 0x3000 - 0x3010 255 * 0x3400 - 0x3410 256 * 0x3800 - 0x3810 257 * 0x3c00 - 0x3c10 258 * 0x4000 - 0x4010 259 * 0x8000 - 0x8010 260 */ 261 port = isa_get_port(dev); 262 for (i = 0; i < IOBASE_ADDRS; i++) 263 if (bus_set_resource(dev, SYS_RES_IOPORT, i, 264 port + iobase_addrs[i], 0x10) != 0) 265 return (ENXIO); 266 error = ENOMEM; 267 for (i = 0; i < IOBASE_ADDRS; i++) { 268 x = i; 269 sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x, 270 0ul, ~0ul, 0x10, RF_ACTIVE); 271 if (x != i) { 272 device_printf(dev, "ioport %d was rid %d\n", i, x); 273 goto fail; 274 } 275 if (sc->sc_port[i] == NULL) { 276 device_printf(dev, "failed to alloc ioports %x-%x\n", 277 port + iobase_addrs[i], 278 port + iobase_addrs[i] + 0x10); 279 goto fail; 280 } 281 } 282 sc->sc_bt = rman_get_bustag(sc->sc_port[0]); 283 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]); 284 285 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid, 286 RF_ACTIVE); 287 if (sc->sc_irq == NULL) { 288 device_printf(dev, "failed to alloc IRQ\n"); 289 goto fail; 290 } 291 292 /* 293 * Now do some actual tests to make sure it works. 294 */ 295 error = ENXIO; 296 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 297 rcout(sc, CD180_PPRH, 0x11); 298 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11) 299 goto fail; 300 if (rc_test(sc)) 301 goto fail; 302 303 /* 304 * Ok, start actually hooking things up. 305 */ 306 sc->sc_unit = device_get_unit(dev); 307 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/ 308 device_printf(dev, "%d chans, firmware rev. %c\n", 309 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A'); 310 rc = sc->sc_channels; 311 base = CD180_NCHAN * sc->sc_unit; 312 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 313 rc->rc_rcb = sc; 314 rc->rc_chan = chan; 315 rc->rc_iptr = rc->rc_ibuf; 316 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 317 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 318 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 319 rc->rc_dtrwait = 3 * hz; 320 callout_init(&rc->rc_dtrcallout, 0); 321 tp = &rc->rc_tp; 322 ttychars(tp); 323 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 324 tp->t_cflag = TTYDEF_CFLAG; 325 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 326 cdev = make_dev(&rc_cdevsw, chan + base, 327 UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base); 328 cdev->si_drv1 = rc; 329 cdev->si_drv2 = 0; 330 cdev->si_tty = tp; 331 rc->rc_dev = cdev; 332 cdev = make_dev(&rc_cdevsw, chan + base + 128, 333 UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base); 334 cdev->si_drv1 = rc; 335 cdev->si_drv2 = (void *)1; 336 cdev->si_tty = tp; 337 rc->rc_cdev = cdev; 338 } 339 340 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc, 341 &sc->sc_hwicookie); 342 if (error) { 343 device_printf(dev, "failed to register interrupt handler\n"); 344 goto fail; 345 } 346 347 swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0, 348 &sc->sc_swicookie); 349 return (0); 350 351fail: 352 rc_release_resources(dev); 353 return (error); 354} 355 356static int 357rc_detach(device_t dev) 358{ 359 struct rc_softc *sc; 360 struct rc_chans *rc; 361 int error, i, s; 362 363 sc = device_get_softc(dev); 364 if (sc->sc_opencount > 0) 365 return (EBUSY); 366 sc->sc_opencount = -1; 367 368 rc = sc->sc_channels; 369 for (i = 0; i < CD180_NCHAN; i++, rc++) { 370 destroy_dev(rc->rc_dev); 371 destroy_dev(rc->rc_cdev); 372 } 373 374 rc = sc->sc_channels; 375 s = splsoftclock(); 376 for (i = 0; i < CD180_NCHAN; i++) { 377 if ((rc->rc_flags & RC_DTR_OFF) && 378 !callout_stop(&rc->rc_dtrcallout)) 379 tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0); 380 } 381 382 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie); 383 if (error) 384 device_printf(dev, "failed to deregister interrupt handler\n"); 385 ithread_remove_handler(sc->sc_swicookie); 386 rc_release_resources(dev); 387 388 return (0); 389} 390 391static void 392rc_release_resources(device_t dev) 393{ 394 struct rc_softc *sc; 395 int i; 396 397 sc = device_get_softc(dev); 398 if (sc->sc_irq != NULL) { 399 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, 400 sc->sc_irq); 401 sc->sc_irq = NULL; 402 } 403 for (i = 0; i < IOBASE_ADDRS; i++) { 404 if (sc->sc_port[i] == NULL) 405 break; 406 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]); 407 sc->sc_port[i] = NULL; 408 } 409} 410 411/* RC interrupt handling */ 412static void 413rc_intr(void *arg) 414{ 415 struct rc_softc *sc; 416 struct rc_chans *rc; 417 int resid, chan; 418 u_char val, iack, bsr, ucnt, *optr; 419 int good_data, t_state; 420 421 sc = (struct rc_softc *)arg; 422 bsr = ~(rcin(sc, RC_BSR)); 423 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 424 device_printf(sc->sc_dev, "extra interrupt\n"); 425 rcout(sc, CD180_EOIR, 0); 426 return; 427 } 428 429 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 430#ifdef RCDEBUG_DETAILED 431 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr, 432 (bsr & RC_BSR_TOUT)?"TOUT ":"", 433 (bsr & RC_BSR_RXINT)?"RXINT ":"", 434 (bsr & RC_BSR_TXINT)?"TXINT ":"", 435 (bsr & RC_BSR_MOINT)?"MOINT":""); 436#endif 437 if (bsr & RC_BSR_TOUT) { 438 device_printf(sc->sc_dev, 439 "hardware failure, reset board\n"); 440 rcout(sc, RC_CTOUT, 0); 441 rc_reinit(sc); 442 return; 443 } 444 if (bsr & RC_BSR_RXINT) { 445 iack = rcin(sc, RC_PILR_RX); 446 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 447 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 448 device_printf(sc->sc_dev, 449 "fake rxint: %02x\n", iack); 450 goto more_intrs; 451 } 452 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 453 rc = &sc->sc_channels[chan]; 454 t_state = rc->rc_tp.t_state; 455 /* Do RTS flow control stuff */ 456 if ( (rc->rc_flags & RC_RTSFLOW) 457 || !(t_state & TS_ISOPEN) 458 ) { 459 if ( ( !(t_state & TS_ISOPEN) 460 || (t_state & TS_TBLOCK) 461 ) 462 && (rc->rc_msvr & MSVR_RTS) 463 ) 464 rcout(sc, CD180_MSVR, 465 rc->rc_msvr &= ~MSVR_RTS); 466 else if (!(rc->rc_msvr & MSVR_RTS)) 467 rcout(sc, CD180_MSVR, 468 rc->rc_msvr |= MSVR_RTS); 469 } 470 ucnt = rcin(sc, CD180_RDCR) & 0xF; 471 resid = 0; 472 473 if (t_state & TS_ISOPEN) { 474 /* check for input buffer overflow */ 475 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 476 resid = ucnt; 477 ucnt = rc->rc_bufend - rc->rc_iptr; 478 resid -= ucnt; 479 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 480 rc->rc_flags |= RC_WAS_BUFOVFL; 481 sc->sc_scheduled_event++; 482 } 483 } 484 optr = rc->rc_iptr; 485 /* check foor good data */ 486 if (good_data) { 487 while (ucnt-- > 0) { 488 val = rcin(sc, CD180_RDR); 489 optr[0] = val; 490 optr[INPUT_FLAGS_SHIFT] = 0; 491 optr++; 492 sc->sc_scheduled_event++; 493 if (val != 0 && val == rc->rc_hotchar) 494 swi_sched(sc->sc_swicookie, 0); 495 } 496 } else { 497 /* Store also status data */ 498 while (ucnt-- > 0) { 499 iack = rcin(sc, CD180_RCSR); 500 if (iack & RCSR_Timeout) 501 break; 502 if ( (iack & RCSR_OE) 503 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 504 rc->rc_flags |= RC_WAS_SILOVFL; 505 sc->sc_scheduled_event++; 506 } 507 val = rcin(sc, CD180_RDR); 508 /* 509 Don't store PE if IGNPAR and BREAK if IGNBRK, 510 this hack allows "raw" tty optimization 511 works even if IGN* is set. 512 */ 513 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 514 || ((!(iack & (RCSR_PE|RCSR_FE)) 515 || !(rc->rc_tp.t_iflag & IGNPAR)) 516 && (!(iack & RCSR_Break) 517 || !(rc->rc_tp.t_iflag & IGNBRK)))) { 518 if ( (iack & (RCSR_PE|RCSR_FE)) 519 && (t_state & TS_CAN_BYPASS_L_RINT) 520 && ((iack & RCSR_FE) 521 || ((iack & RCSR_PE) 522 && (rc->rc_tp.t_iflag & INPCK)))) 523 val = 0; 524 else if (val != 0 && val == rc->rc_hotchar) 525 swi_sched(sc->sc_swicookie, 0); 526 optr[0] = val; 527 optr[INPUT_FLAGS_SHIFT] = iack; 528 optr++; 529 sc->sc_scheduled_event++; 530 } 531 } 532 } 533 rc->rc_iptr = optr; 534 rc->rc_flags |= RC_DORXFER; 535 } else 536 resid = ucnt; 537 /* Clear FIFO if necessary */ 538 while (resid-- > 0) { 539 if (!good_data) 540 iack = rcin(sc, CD180_RCSR); 541 else 542 iack = 0; 543 if (iack & RCSR_Timeout) 544 break; 545 (void) rcin(sc, CD180_RDR); 546 } 547 goto more_intrs; 548 } 549 if (bsr & RC_BSR_MOINT) { 550 iack = rcin(sc, RC_PILR_MODEM); 551 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 552 device_printf(sc->sc_dev, "fake moint: %02x\n", 553 iack); 554 goto more_intrs; 555 } 556 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 557 rc = &sc->sc_channels[chan]; 558 iack = rcin(sc, CD180_MCR); 559 rc->rc_msvr = rcin(sc, CD180_MSVR); 560 rcout(sc, CD180_MCR, 0); 561#ifdef RCDEBUG 562 printrcflags(rc, "moint"); 563#endif 564 if (rc->rc_flags & RC_CTSFLOW) { 565 if (rc->rc_msvr & MSVR_CTS) 566 rc->rc_flags |= RC_SEND_RDY; 567 else 568 rc->rc_flags &= ~RC_SEND_RDY; 569 } else 570 rc->rc_flags |= RC_SEND_RDY; 571 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 572 sc->sc_scheduled_event += LOTS_OF_EVENTS; 573 rc->rc_flags |= RC_MODCHG; 574 swi_sched(sc->sc_swicookie, 0); 575 } 576 goto more_intrs; 577 } 578 if (bsr & RC_BSR_TXINT) { 579 iack = rcin(sc, RC_PILR_TX); 580 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 581 device_printf(sc->sc_dev, "fake txint: %02x\n", 582 iack); 583 goto more_intrs; 584 } 585 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 586 rc = &sc->sc_channels[chan]; 587 if ( (rc->rc_flags & RC_OSUSP) 588 || !(rc->rc_flags & RC_SEND_RDY) 589 ) 590 goto more_intrs; 591 /* Handle breaks and other stuff */ 592 if (rc->rc_pendcmd) { 593 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC); 594 rcout(sc, CD180_TDR, CD180_C_ESC); 595 rcout(sc, CD180_TDR, rc->rc_pendcmd); 596 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 597 rc->rc_pendcmd = 0; 598 goto more_intrs; 599 } 600 optr = rc->rc_optr; 601 resid = rc->rc_obufend - optr; 602 if (resid > CD180_NFIFO) 603 resid = CD180_NFIFO; 604 while (resid-- > 0) 605 rcout(sc, CD180_TDR, *optr++); 606 rc->rc_optr = optr; 607 608 /* output completed? */ 609 if (optr >= rc->rc_obufend) { 610 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy); 611#ifdef RCDEBUG 612 device_printf(sc->sc_dev, 613 "channel %d: output completed\n", 614 rc->rc_chan); 615#endif 616 if (!(rc->rc_flags & RC_DOXXFER)) { 617 sc->sc_scheduled_event += LOTS_OF_EVENTS; 618 rc->rc_flags |= RC_DOXXFER; 619 swi_sched(sc->sc_swicookie, 0); 620 } 621 } 622 } 623 more_intrs: 624 rcout(sc, CD180_EOIR, 0); /* end of interrupt */ 625 rcout(sc, RC_CTOUT, 0); 626 bsr = ~(rcin(sc, RC_BSR)); 627 } 628} 629 630/* Feed characters to output buffer */ 631static void 632rc_start(struct tty *tp) 633{ 634 struct rc_softc *sc; 635 struct rc_chans *rc; 636 int s; 637 638 rc = TTY_TO_RC(tp); 639 if (rc->rc_flags & RC_OSBUSY) 640 return; 641 sc = rc->rc_rcb; 642 s = spltty(); 643 rc->rc_flags |= RC_OSBUSY; 644 critical_enter(); 645 if (tp->t_state & TS_TTSTOP) 646 rc->rc_flags |= RC_OSUSP; 647 else 648 rc->rc_flags &= ~RC_OSUSP; 649 /* Do RTS flow control stuff */ 650 if ( (rc->rc_flags & RC_RTSFLOW) 651 && (tp->t_state & TS_TBLOCK) 652 && (rc->rc_msvr & MSVR_RTS) 653 ) { 654 rcout(sc, CD180_CAR, rc->rc_chan); 655 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 656 } else if (!(rc->rc_msvr & MSVR_RTS)) { 657 rcout(sc, CD180_CAR, rc->rc_chan); 658 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 659 } 660 critical_exit(); 661 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 662 goto out; 663#ifdef RCDEBUG 664 printrcflags(rc, "rcstart"); 665#endif 666 ttwwakeup(tp); 667#ifdef RCDEBUG 668 printf("rcstart: outq = %d obuf = %d\n", 669 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 670#endif 671 if (tp->t_state & TS_BUSY) 672 goto out; /* output still in progress ... */ 673 674 if (tp->t_outq.c_cc > 0) { 675 u_int ocnt; 676 677 tp->t_state |= TS_BUSY; 678 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 679 critical_enter(); 680 rc->rc_optr = rc->rc_obuf; 681 rc->rc_obufend = rc->rc_optr + ocnt; 682 critical_exit(); 683 if (!(rc->rc_ier & IER_TxRdy)) { 684#ifdef RCDEBUG 685 device_printf(sc->sc_dev, 686 "channel %d: rcstart enable txint\n", rc->rc_chan); 687#endif 688 rcout(sc, CD180_CAR, rc->rc_chan); 689 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy); 690 } 691 } 692out: 693 rc->rc_flags &= ~RC_OSBUSY; 694 (void) splx(s); 695} 696 697/* Handle delayed events. */ 698void 699rc_pollcard(void *arg) 700{ 701 struct rc_softc *sc; 702 struct rc_chans *rc; 703 struct tty *tp; 704 u_char *tptr, *eptr; 705 int chan, icnt; 706 707 sc = (struct rc_softc *)arg; 708 if (sc->sc_scheduled_event == 0) 709 return; 710 do { 711 rc = sc->sc_channels; 712 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 713 tp = &rc->rc_tp; 714#ifdef RCDEBUG 715 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 716 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 717 printrcflags(rc, "rcevent"); 718#endif 719 if (rc->rc_flags & RC_WAS_BUFOVFL) { 720 critical_enter(); 721 rc->rc_flags &= ~RC_WAS_BUFOVFL; 722 sc->sc_scheduled_event--; 723 critical_exit(); 724 device_printf(sc->sc_dev, 725 "channel %d: interrupt-level buffer overflow\n", 726 chan); 727 } 728 if (rc->rc_flags & RC_WAS_SILOVFL) { 729 critical_enter(); 730 rc->rc_flags &= ~RC_WAS_SILOVFL; 731 sc->sc_scheduled_event--; 732 critical_exit(); 733 device_printf(sc->sc_dev, 734 "channel %d: silo overflow\n", chan); 735 } 736 if (rc->rc_flags & RC_MODCHG) { 737 critical_enter(); 738 rc->rc_flags &= ~RC_MODCHG; 739 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 740 critical_exit(); 741 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 742 } 743 if (rc->rc_flags & RC_DORXFER) { 744 critical_enter(); 745 rc->rc_flags &= ~RC_DORXFER; 746 eptr = rc->rc_iptr; 747 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 748 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 749 else 750 tptr = rc->rc_ibuf; 751 icnt = eptr - tptr; 752 if (icnt > 0) { 753 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 754 rc->rc_iptr = rc->rc_ibuf; 755 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 756 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 757 } else { 758 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 759 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 760 rc->rc_hiwat = 761 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 762 } 763 if ( (rc->rc_flags & RC_RTSFLOW) 764 && (tp->t_state & TS_ISOPEN) 765 && !(tp->t_state & TS_TBLOCK) 766 && !(rc->rc_msvr & MSVR_RTS) 767 ) { 768 rcout(sc, CD180_CAR, chan); 769 rcout(sc, CD180_MSVR, 770 rc->rc_msvr |= MSVR_RTS); 771 } 772 sc->sc_scheduled_event -= icnt; 773 } 774 critical_exit(); 775 776 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 777 goto done1; 778 779 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 780 && !(tp->t_state & TS_LOCAL)) { 781 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 782 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 783 && !(tp->t_state & TS_TBLOCK)) 784 ttyblock(tp); 785 tk_nin += icnt; 786 tk_rawcc += icnt; 787 tp->t_rawcc += icnt; 788 if (b_to_q(tptr, icnt, &tp->t_rawq)) 789 device_printf(sc->sc_dev, 790 "channel %d: tty-level buffer overflow\n", 791 chan); 792 ttwakeup(tp); 793 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 794 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 795 tp->t_state &= ~TS_TTSTOP; 796 tp->t_lflag &= ~FLUSHO; 797 rc_start(tp); 798 } 799 } else { 800 for (; tptr < eptr; tptr++) 801 (*linesw[tp->t_line].l_rint) 802 (tptr[0] | 803 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 804 } 805done1: ; 806 } 807 if (rc->rc_flags & RC_DOXXFER) { 808 critical_enter(); 809 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 810 rc->rc_flags &= ~RC_DOXXFER; 811 rc->rc_tp.t_state &= ~TS_BUSY; 812 critical_exit(); 813 (*linesw[tp->t_line].l_start)(tp); 814 } 815 if (sc->sc_scheduled_event == 0) 816 break; 817 } 818 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS); 819} 820 821static void 822rc_stop(struct tty *tp, int rw) 823{ 824 struct rc_softc *sc; 825 struct rc_chans *rc; 826 u_char *tptr, *eptr; 827 828 rc = TTY_TO_RC(tp); 829 sc = rc->rc_rcb; 830#ifdef RCDEBUG 831 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n", 832 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 833#endif 834 if (rw & FWRITE) 835 rc_discard_output(rc); 836 critical_enter(); 837 if (rw & FREAD) { 838 rc->rc_flags &= ~RC_DORXFER; 839 eptr = rc->rc_iptr; 840 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 841 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 842 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 843 } else { 844 tptr = rc->rc_ibuf; 845 rc->rc_iptr = rc->rc_ibuf; 846 } 847 sc->sc_scheduled_event -= eptr - tptr; 848 } 849 if (tp->t_state & TS_TTSTOP) 850 rc->rc_flags |= RC_OSUSP; 851 else 852 rc->rc_flags &= ~RC_OSUSP; 853 critical_exit(); 854} 855 856static int 857rcopen(dev_t dev, int flag, int mode, d_thread_t *td) 858{ 859 struct rc_softc *sc; 860 struct rc_chans *rc; 861 struct tty *tp; 862 int s, error = 0; 863 864 rc = DEV_TO_RC(dev); 865 sc = rc->rc_rcb; 866 tp = &rc->rc_tp; 867 if (sc->sc_opencount < 0) 868 return (ENXIO); 869 sc->sc_opencount++; 870#ifdef RCDEBUG 871 device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n", 872 rc->rc_chan, dev); 873#endif 874 s = spltty(); 875 876again: 877 while (rc->rc_flags & RC_DTR_OFF) { 878 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 879 if (error != 0) 880 goto out; 881 } 882 if (tp->t_state & TS_ISOPEN) { 883 if (CALLOUT(dev)) { 884 if (!(rc->rc_flags & RC_ACTOUT)) { 885 error = EBUSY; 886 goto out; 887 } 888 } else { 889 if (rc->rc_flags & RC_ACTOUT) { 890 if (flag & O_NONBLOCK) { 891 error = EBUSY; 892 goto out; 893 } 894 error = tsleep(&rc->rc_rcb, 895 TTIPRI|PCATCH, "rcbi", 0); 896 if (error) 897 goto out; 898 goto again; 899 } 900 } 901 if (tp->t_state & TS_XCLUDE && 902 suser(td)) { 903 error = EBUSY; 904 goto out; 905 } 906 } else { 907 tp->t_oproc = rc_start; 908 tp->t_param = rc_param; 909 tp->t_stop = rc_stop; 910 tp->t_dev = dev; 911 912 if (CALLOUT(dev)) 913 tp->t_cflag |= CLOCAL; 914 else 915 tp->t_cflag &= ~CLOCAL; 916 917 error = rc_param(tp, &tp->t_termios); 918 if (error) 919 goto out; 920 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 921 922 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 923 (*linesw[tp->t_line].l_modem)(tp, 1); 924 } 925 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 926 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 927 rc->rc_dcdwaits++; 928 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 929 rc->rc_dcdwaits--; 930 if (error != 0) 931 goto out; 932 goto again; 933 } 934 error = (*linesw[tp->t_line].l_open)(dev, tp); 935 disc_optim(tp, &tp->t_termios, rc); 936 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 937 rc->rc_flags |= RC_ACTOUT; 938out: 939 (void) splx(s); 940 941 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 942 rc_hardclose(rc); 943 944 return error; 945} 946 947static int 948rcclose(dev_t dev, int flag, int mode, d_thread_t *td) 949{ 950 struct rc_softc *sc; 951 struct rc_chans *rc; 952 struct tty *tp; 953 int s; 954 955 rc = DEV_TO_RC(dev); 956 sc = rc->rc_rcb; 957 tp = &rc->rc_tp; 958#ifdef RCDEBUG 959 device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n", 960 rc->rc_chan, dev); 961#endif 962 s = spltty(); 963 (*linesw[tp->t_line].l_close)(tp, flag); 964 disc_optim(tp, &tp->t_termios, rc); 965 rc_hardclose(rc); 966 ttyclose(tp); 967 splx(s); 968 KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count")); 969 sc->sc_opencount--; 970 return 0; 971} 972 973static void 974rc_hardclose(struct rc_chans *rc) 975{ 976 struct rc_softc *sc; 977 struct tty *tp; 978 int s; 979 980 tp = &rc->rc_tp; 981 sc = rc->rc_rcb; 982 s = spltty(); 983 rcout(sc, CD180_CAR, rc->rc_chan); 984 985 /* Disable rx/tx intrs */ 986 rcout(sc, CD180_IER, rc->rc_ier = 0); 987 if ( (tp->t_cflag & HUPCL) 988 || (!(rc->rc_flags & RC_ACTOUT) 989 && !(rc->rc_msvr & MSVR_CD) 990 && !(tp->t_cflag & CLOCAL)) 991 || !(tp->t_state & TS_ISOPEN) 992 ) { 993 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 994 WAITFORCCR(sc, rc->rc_chan); 995 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 996 if (rc->rc_dtrwait) { 997 callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait, 998 rc_dtrwakeup, rc); 999 rc->rc_flags |= RC_DTR_OFF; 1000 } 1001 } 1002 rc->rc_flags &= ~RC_ACTOUT; 1003 wakeup( &rc->rc_rcb); /* wake bi */ 1004 wakeup(TSA_CARR_ON(tp)); 1005 (void) splx(s); 1006} 1007 1008/* Reset the bastard */ 1009static void 1010rc_hwreset(struct rc_softc *sc, u_int chipid) 1011{ 1012 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */ 1013 DELAY(20000); 1014 WAITFORCCR(sc, -1); 1015 1016 rcout(sc, RC_CTOUT, 0); /* Clear timeout */ 1017 rcout(sc, CD180_GIVR, chipid); 1018 rcout(sc, CD180_GICR, 0); 1019 1020 /* Set Prescaler Registers (1 msec) */ 1021 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 1022 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 1023 1024 /* Initialize Priority Interrupt Level Registers */ 1025 rcout(sc, CD180_PILR1, RC_PILR_MODEM); 1026 rcout(sc, CD180_PILR2, RC_PILR_TX); 1027 rcout(sc, CD180_PILR3, RC_PILR_RX); 1028 1029 /* Reset DTR */ 1030 rcout(sc, RC_DTREG, ~0); 1031} 1032 1033/* Set channel parameters */ 1034static int 1035rc_param(struct tty *tp, struct termios *ts) 1036{ 1037 struct rc_softc *sc; 1038 struct rc_chans *rc; 1039 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 1040 1041 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 1042 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 1043 ) 1044 return (EINVAL); 1045 if (ts->c_ispeed == 0) 1046 ts->c_ispeed = ts->c_ospeed; 1047 odivs = RC_BRD(ts->c_ospeed); 1048 idivs = RC_BRD(ts->c_ispeed); 1049 1050 rc = TTY_TO_RC(tp); 1051 sc = rc->rc_rcb; 1052 s = spltty(); 1053 1054 /* Select channel */ 1055 rcout(sc, CD180_CAR, rc->rc_chan); 1056 1057 /* If speed == 0, hangup line */ 1058 if (ts->c_ospeed == 0) { 1059 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 1060 WAITFORCCR(sc, rc->rc_chan); 1061 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1062 } 1063 1064 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1065 cflag = ts->c_cflag; 1066 iflag = ts->c_iflag; 1067 lflag = ts->c_lflag; 1068 1069 if (idivs > 0) { 1070 rcout(sc, CD180_RBPRL, idivs & 0xFF); 1071 rcout(sc, CD180_RBPRH, idivs >> 8); 1072 } 1073 if (odivs > 0) { 1074 rcout(sc, CD180_TBPRL, odivs & 0xFF); 1075 rcout(sc, CD180_TBPRH, odivs >> 8); 1076 } 1077 1078 /* set timeout value */ 1079 if (ts->c_ispeed > 0) { 1080 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 1081 1082 if ( !(lflag & ICANON) 1083 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1084 && ts->c_cc[VTIME] * 10 > itm) 1085 itm = ts->c_cc[VTIME] * 10; 1086 1087 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255); 1088 } 1089 1090 switch (cflag & CSIZE) { 1091 case CS5: val = COR1_5BITS; break; 1092 case CS6: val = COR1_6BITS; break; 1093 case CS7: val = COR1_7BITS; break; 1094 default: 1095 case CS8: val = COR1_8BITS; break; 1096 } 1097 if (cflag & PARENB) { 1098 val |= COR1_NORMPAR; 1099 if (cflag & PARODD) 1100 val |= COR1_ODDP; 1101 if (!(cflag & INPCK)) 1102 val |= COR1_Ignore; 1103 } else 1104 val |= COR1_Ignore; 1105 if (cflag & CSTOPB) 1106 val |= COR1_2SB; 1107 rcout(sc, CD180_COR1, val); 1108 1109 /* Set FIFO threshold */ 1110 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1111 inpflow = 0; 1112 if ( (iflag & IXOFF) 1113 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1114 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1115 || (iflag & IXANY) 1116 ) 1117 ) 1118 ) { 1119 inpflow = 1; 1120 val |= COR3_SCDE|COR3_FCT; 1121 } 1122 rcout(sc, CD180_COR3, val); 1123 1124 /* Initialize on-chip automatic flow control */ 1125 val = 0; 1126 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1127 if (cflag & CCTS_OFLOW) { 1128 rc->rc_flags |= RC_CTSFLOW; 1129 val |= COR2_CtsAE; 1130 } else 1131 rc->rc_flags |= RC_SEND_RDY; 1132 if (tp->t_state & TS_TTSTOP) 1133 rc->rc_flags |= RC_OSUSP; 1134 else 1135 rc->rc_flags &= ~RC_OSUSP; 1136 if (cflag & CRTS_IFLOW) 1137 rc->rc_flags |= RC_RTSFLOW; 1138 else 1139 rc->rc_flags &= ~RC_RTSFLOW; 1140 1141 if (inpflow) { 1142 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1143 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]); 1144 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]); 1145 val |= COR2_TxIBE; 1146 if (iflag & IXANY) 1147 val |= COR2_IXM; 1148 } 1149 1150 rcout(sc, CD180_COR2, rc->rc_cor2 = val); 1151 1152 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1153 1154 disc_optim(tp, ts, rc); 1155 1156 /* modem ctl */ 1157 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1158 if (cflag & CCTS_OFLOW) 1159 val |= MCOR1_CTSzd; 1160 rcout(sc, CD180_MCOR1, val); 1161 1162 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1163 if (cflag & CCTS_OFLOW) 1164 val |= MCOR2_CTSod; 1165 rcout(sc, CD180_MCOR2, val); 1166 1167 /* enable i/o and interrupts */ 1168 CCRCMD(sc, rc->rc_chan, 1169 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1170 WAITFORCCR(sc, rc->rc_chan); 1171 1172 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1173 if (cflag & CCTS_OFLOW) 1174 rc->rc_ier |= IER_CTS; 1175 if (cflag & CREAD) 1176 rc->rc_ier |= IER_RxData; 1177 if (tp->t_state & TS_BUSY) 1178 rc->rc_ier |= IER_TxRdy; 1179 if (ts->c_ospeed != 0) 1180 rc_modctl(rc, TIOCM_DTR, DMBIS); 1181 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1182 rc->rc_flags |= RC_SEND_RDY; 1183 rcout(sc, CD180_IER, rc->rc_ier); 1184 (void) splx(s); 1185 return 0; 1186} 1187 1188/* Re-initialize board after bogus interrupts */ 1189static void 1190rc_reinit(struct rc_softc *sc) 1191{ 1192 struct rc_chans *rc; 1193 int i; 1194 1195 rc_hwreset(sc, RC_FAKEID); 1196 rc = sc->sc_channels; 1197 for (i = 0; i < CD180_NCHAN; i++, rc++) 1198 (void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios); 1199} 1200 1201static int 1202rcioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td) 1203{ 1204 struct rc_chans *rc; 1205 struct tty *tp; 1206 int s, error; 1207 1208 rc = DEV_TO_RC(dev); 1209 tp = &rc->rc_tp; 1210 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1211 if (error != ENOIOCTL) 1212 return (error); 1213 error = ttioctl(tp, cmd, data, flag); 1214 disc_optim(tp, &tp->t_termios, rc); 1215 if (error != ENOIOCTL) 1216 return (error); 1217 s = spltty(); 1218 1219 switch (cmd) { 1220 case TIOCSBRK: 1221 rc->rc_pendcmd = CD180_C_SBRK; 1222 break; 1223 1224 case TIOCCBRK: 1225 rc->rc_pendcmd = CD180_C_EBRK; 1226 break; 1227 1228 case TIOCSDTR: 1229 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1230 break; 1231 1232 case TIOCCDTR: 1233 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1234 break; 1235 1236 case TIOCMGET: 1237 *(int *) data = rc_modctl(rc, 0, DMGET); 1238 break; 1239 1240 case TIOCMSET: 1241 (void) rc_modctl(rc, *(int *) data, DMSET); 1242 break; 1243 1244 case TIOCMBIC: 1245 (void) rc_modctl(rc, *(int *) data, DMBIC); 1246 break; 1247 1248 case TIOCMBIS: 1249 (void) rc_modctl(rc, *(int *) data, DMBIS); 1250 break; 1251 1252 case TIOCMSDTRWAIT: 1253 error = suser(td); 1254 if (error != 0) { 1255 splx(s); 1256 return (error); 1257 } 1258 rc->rc_dtrwait = *(int *)data * hz / 100; 1259 break; 1260 1261 case TIOCMGDTRWAIT: 1262 *(int *)data = rc->rc_dtrwait * 100 / hz; 1263 break; 1264 1265 default: 1266 (void) splx(s); 1267 return ENOTTY; 1268 } 1269 (void) splx(s); 1270 return 0; 1271} 1272 1273 1274/* Modem control routines */ 1275 1276static int 1277rc_modctl(struct rc_chans *rc, int bits, int cmd) 1278{ 1279 struct rc_softc *sc; 1280 u_char *dtr; 1281 u_char msvr; 1282 1283 sc = rc->rc_rcb; 1284 dtr = &sc->sc_dtr; 1285 rcout(sc, CD180_CAR, rc->rc_chan); 1286 1287 switch (cmd) { 1288 case DMSET: 1289 rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ? 1290 ~(*dtr |= 1 << rc->rc_chan) : 1291 ~(*dtr &= ~(1 << rc->rc_chan))); 1292 msvr = rcin(sc, CD180_MSVR); 1293 if (bits & TIOCM_RTS) 1294 msvr |= MSVR_RTS; 1295 else 1296 msvr &= ~MSVR_RTS; 1297 if (bits & TIOCM_DTR) 1298 msvr |= MSVR_DTR; 1299 else 1300 msvr &= ~MSVR_DTR; 1301 rcout(sc, CD180_MSVR, msvr); 1302 break; 1303 1304 case DMBIS: 1305 if (bits & TIOCM_DTR) 1306 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1307 msvr = rcin(sc, CD180_MSVR); 1308 if (bits & TIOCM_RTS) 1309 msvr |= MSVR_RTS; 1310 if (bits & TIOCM_DTR) 1311 msvr |= MSVR_DTR; 1312 rcout(sc, CD180_MSVR, msvr); 1313 break; 1314 1315 case DMGET: 1316 bits = TIOCM_LE; 1317 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR); 1318 1319 if (msvr & MSVR_RTS) 1320 bits |= TIOCM_RTS; 1321 if (msvr & MSVR_CTS) 1322 bits |= TIOCM_CTS; 1323 if (msvr & MSVR_DSR) 1324 bits |= TIOCM_DSR; 1325 if (msvr & MSVR_DTR) 1326 bits |= TIOCM_DTR; 1327 if (msvr & MSVR_CD) 1328 bits |= TIOCM_CD; 1329 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan)) 1330 bits |= TIOCM_RI; 1331 return bits; 1332 1333 case DMBIC: 1334 if (bits & TIOCM_DTR) 1335 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1336 msvr = rcin(sc, CD180_MSVR); 1337 if (bits & TIOCM_RTS) 1338 msvr &= ~MSVR_RTS; 1339 if (bits & TIOCM_DTR) 1340 msvr &= ~MSVR_DTR; 1341 rcout(sc, CD180_MSVR, msvr); 1342 break; 1343 } 1344 rc->rc_msvr = rcin(sc, CD180_MSVR); 1345 return 0; 1346} 1347 1348#define ERR(s) do { \ 1349 device_printf(sc->sc_dev, "%s", ""); \ 1350 printf s ; \ 1351 printf("\n"); \ 1352 (void) splx(old_level); \ 1353 return 1; \ 1354} while (0) 1355 1356/* Test the board. */ 1357int 1358rc_test(struct rc_softc *sc) 1359{ 1360 int chan = 0; 1361 int i = 0, rcnt, old_level; 1362 unsigned int iack, chipid; 1363 unsigned short divs; 1364 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1365#define CTLEN 8 1366 1367 struct rtest { 1368 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1369 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1370 int rxptr; /* RX pointer */ 1371 int txptr; /* TX pointer */ 1372 } tchans[CD180_NCHAN]; 1373 1374 old_level = spltty(); 1375 1376 chipid = RC_FAKEID; 1377 1378 /* First, reset board to inital state */ 1379 rc_hwreset(sc, chipid); 1380 1381 divs = RC_BRD(19200); 1382 1383 /* Initialize channels */ 1384 for (chan = 0; chan < CD180_NCHAN; chan++) { 1385 1386 /* Select and reset channel */ 1387 rcout(sc, CD180_CAR, chan); 1388 CCRCMD(sc, chan, CCR_ResetChan); 1389 WAITFORCCR(sc, chan); 1390 1391 /* Set speed */ 1392 rcout(sc, CD180_RBPRL, divs & 0xFF); 1393 rcout(sc, CD180_RBPRH, divs >> 8); 1394 rcout(sc, CD180_TBPRL, divs & 0xFF); 1395 rcout(sc, CD180_TBPRH, divs >> 8); 1396 1397 /* set timeout value */ 1398 rcout(sc, CD180_RTPR, 0); 1399 1400 /* Establish local loopback */ 1401 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1402 rcout(sc, CD180_COR2, COR2_LLM); 1403 rcout(sc, CD180_COR3, CD180_NFIFO); 1404 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1405 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN); 1406 WAITFORCCR(sc, chan); 1407 rcout(sc, CD180_MSVR, MSVR_RTS); 1408 1409 /* Fill TXBUF with test data */ 1410 for (i = 0; i < CD180_NFIFO; i++) { 1411 tchans[chan].txbuf[i] = ctest[i]; 1412 tchans[chan].rxbuf[i] = 0; 1413 } 1414 tchans[chan].txptr = tchans[chan].rxptr = 0; 1415 1416 /* Now, start transmit */ 1417 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData); 1418 } 1419 /* Pseudo-interrupt poll stuff */ 1420 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1421 i = ~(rcin(sc, RC_BSR)); 1422 if (i & RC_BSR_TOUT) 1423 ERR(("BSR timeout bit set\n")); 1424 else if (i & RC_BSR_TXINT) { 1425 iack = rcin(sc, RC_PILR_TX); 1426 if (iack != (GIVR_IT_TDI | chipid)) 1427 ERR(("Bad TX intr ack (%02x != %02x)\n", 1428 iack, GIVR_IT_TDI | chipid)); 1429 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1430 /* If no more data to transmit, disable TX intr */ 1431 if (tchans[chan].txptr >= CD180_NFIFO) { 1432 iack = rcin(sc, CD180_IER); 1433 rcout(sc, CD180_IER, iack & ~IER_TxMpty); 1434 } else { 1435 for (iack = tchans[chan].txptr; 1436 iack < CD180_NFIFO; iack++) 1437 rcout(sc, CD180_TDR, 1438 tchans[chan].txbuf[iack]); 1439 tchans[chan].txptr = iack; 1440 } 1441 rcout(sc, CD180_EOIR, 0); 1442 } else if (i & RC_BSR_RXINT) { 1443 u_char ucnt; 1444 1445 iack = rcin(sc, RC_PILR_RX); 1446 if (iack != (GIVR_IT_RGDI | chipid) && 1447 iack != (GIVR_IT_REI | chipid)) 1448 ERR(("Bad RX intr ack (%02x != %02x)\n", 1449 iack, GIVR_IT_RGDI | chipid)); 1450 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1451 ucnt = rcin(sc, CD180_RDCR) & 0xF; 1452 while (ucnt-- > 0) { 1453 iack = rcin(sc, CD180_RCSR); 1454 if (iack & RCSR_Timeout) 1455 break; 1456 if (iack & 0xF) 1457 ERR(("Bad char chan %d (RCSR = %02X)\n", 1458 chan, iack)); 1459 if (tchans[chan].rxptr > CD180_NFIFO) 1460 ERR(("Got extra chars chan %d\n", 1461 chan)); 1462 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1463 rcin(sc, CD180_RDR); 1464 } 1465 rcout(sc, CD180_EOIR, 0); 1466 } 1467 rcout(sc, RC_CTOUT, 0); 1468 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1469 if (tchans[chan].rxptr >= CD180_NFIFO) 1470 iack++; 1471 if (iack == CD180_NCHAN) 1472 break; 1473 } 1474 for (chan = 0; chan < CD180_NCHAN; chan++) { 1475 /* Select and reset channel */ 1476 rcout(sc, CD180_CAR, chan); 1477 CCRCMD(sc, chan, CCR_ResetChan); 1478 } 1479 1480 if (!rcnt) 1481 ERR(("looses characters during local loopback\n")); 1482 /* Now, check data */ 1483 for (chan = 0; chan < CD180_NCHAN; chan++) 1484 for (i = 0; i < CD180_NFIFO; i++) 1485 if (ctest[i] != tchans[chan].rxbuf[i]) 1486 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1487 chan, i, ctest[i], tchans[chan].rxbuf[i])); 1488 (void) splx(old_level); 1489 return 0; 1490} 1491 1492#ifdef RCDEBUG 1493static void 1494printrcflags(struct rc_chans *rc, char *comment) 1495{ 1496 struct rc_softc *sc; 1497 u_short f = rc->rc_flags; 1498 1499 sc = rc->rc_rcb; 1500 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1501 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1502 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1503 (f & RC_ACTOUT) ?"ACTOUT " :"", 1504 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1505 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1506 (f & RC_DORXFER)?"DORXFER " :"", 1507 (f & RC_DOXXFER)?"DOXXFER " :"", 1508 (f & RC_MODCHG) ?"MODCHG " :"", 1509 (f & RC_OSUSP) ?"OSUSP " :"", 1510 (f & RC_OSBUSY) ?"OSBUSY " :"", 1511 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1512 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1513 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1514 1515 rcout(sc, CD180_CAR, rc->rc_chan); 1516 1517 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1518 rc->rc_rcb->rcb_unit, rc->rc_chan, 1519 rcin(sc, CD180_MSVR), 1520 rcin(sc, CD180_IER), 1521 rcin(sc, CD180_CCSR)); 1522} 1523#endif /* RCDEBUG */ 1524 1525static void 1526rc_dtrwakeup(void *arg) 1527{ 1528 struct rc_chans *rc; 1529 1530 rc = (struct rc_chans *)arg; 1531 rc->rc_flags &= ~RC_DTR_OFF; 1532 wakeup(&rc->rc_dtrwait); 1533} 1534 1535static void 1536rc_discard_output(struct rc_chans *rc) 1537{ 1538 critical_enter(); 1539 if (rc->rc_flags & RC_DOXXFER) { 1540 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS; 1541 rc->rc_flags &= ~RC_DOXXFER; 1542 } 1543 rc->rc_optr = rc->rc_obufend; 1544 rc->rc_tp.t_state &= ~TS_BUSY; 1545 critical_exit(); 1546 ttwwakeup(&rc->rc_tp); 1547} 1548 1549static void 1550disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc) 1551{ 1552 1553 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1554 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1555 && (!(t->c_iflag & PARMRK) 1556 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1557 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1558 && linesw[tp->t_line].l_rint == ttyinput) 1559 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1560 else 1561 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1562 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1563} 1564 1565static void 1566rc_wait0(struct rc_softc *sc, int chan, int line) 1567{ 1568 int rcnt; 1569 1570 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--) 1571 DELAY(30); 1572 if (rcnt == 0) 1573 device_printf(sc->sc_dev, 1574 "channel %d command timeout, rc.c line: %d\n", chan, line); 1575} 1576 1577static device_method_t rc_methods[] = { 1578 /* Device interface */ 1579 DEVMETHOD(device_probe, rc_probe), 1580 DEVMETHOD(device_attach, rc_attach), 1581 DEVMETHOD(device_detach, rc_detach), 1582 { 0, 0 } 1583}; 1584 1585static driver_t rc_driver = { 1586 "rc", 1587 rc_methods, sizeof(struct rc_softc), 1588}; 1589 1590DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0); 1591