rc.c revision 12675
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#include <sys/devconf.h> 50#ifdef DEVFS 51#include <sys/devfsext.h> 52#endif /*DEVFS*/ 53 54#include <machine/clock.h> 55 56#include <i386/isa/isa.h> 57#include <i386/isa/isa_device.h> 58#include <i386/isa/sioreg.h> 59 60#include <i386/isa/ic/cd180.h> 61#include <i386/isa/rcreg.h> 62 63 64/* Prototypes */ 65int rcprobe __P((struct isa_device *)); 66int rcattach __P((struct isa_device *)); 67 68/*- 69 * This space intentionally left blank to stop __LINE__ from screwing up 70 * regression tests :-(. 71 * 72 * 73 * 74 */ 75void rcpoll __P((void)); 76 77#define rcin(port) RC_IN (nec, port) 78#define rcout(port,v) RC_OUT (nec, port, v) 79 80#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 81#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 82 83#define RC_IBUFSIZE 256 84#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 85#define RC_OBUFSIZE 512 86#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 87#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 88#define LOTS_OF_EVENTS 64 89 90#define RC_FAKEID 0x10 91 92#define RC_PROBED 1 93#define RC_ATTACHED 2 94 95#define GET_UNIT(dev) (minor(dev) & 0x3F) 96#define CALLOUT(dev) (minor(dev) & 0x80) 97 98/* For isa routines */ 99struct isa_driver rcdriver = { 100 rcprobe, rcattach, "rc" 101}; 102 103static d_open_t rcopen; 104static d_close_t rcclose; 105static d_read_t rcread; 106static d_write_t rcwrite; 107static d_ioctl_t rcioctl; 108static d_stop_t rcstop; 109static d_ttycv_t rcdevtotty; 110 111#define CDEV_MAJOR 63 112struct cdevsw rc_cdevsw = 113 { rcopen, rcclose, rcread, rcwrite, /*63*/ 114 rcioctl, rcstop, nxreset, rcdevtotty,/* rc */ 115 ttselect, nommap, NULL, "rc", NULL, -1 }; 116 117/* Per-board structure */ 118static struct rc_softc { 119 u_int rcb_probed; /* 1 - probed, 2 - attached */ 120 u_int rcb_addr; /* Base I/O addr */ 121 u_int rcb_unit; /* unit # */ 122 u_char rcb_dtr; /* DTR status */ 123 struct rc_chans *rcb_baserc; /* base rc ptr */ 124} rc_softc[NRC]; 125 126/* Per-channel structure */ 127static struct rc_chans { 128 struct rc_softc *rc_rcb; /* back ptr */ 129 u_short rc_flags; /* Misc. flags */ 130 int rc_chan; /* Channel # */ 131 u_char rc_ier; /* intr. enable reg */ 132 u_char rc_msvr; /* modem sig. status */ 133 u_char rc_cor2; /* options reg */ 134 u_char rc_pendcmd; /* special cmd pending */ 135 u_int rc_dtrwait; /* dtr timeout */ 136 u_int rc_dcdwaits; /* how many waits DCD in open */ 137 u_char rc_hotchar; /* end packed optimize */ 138 struct tty *rc_tp; /* tty struct */ 139 u_char *rc_iptr; /* Chars input buffer */ 140 u_char *rc_hiwat; /* hi-water mark */ 141 u_char *rc_bufend; /* end of buffer */ 142 u_char *rc_optr; /* ptr in output buf */ 143 u_char *rc_obufend; /* end of output buf */ 144 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 145 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 146#ifdef DEVFS 147 void *devfs_token; 148#endif 149} rc_chans[NRC * CD180_NCHAN]; 150 151static int rc_scheduled_event = 0; 152 153/* for pstat -t */ 154struct tty rc_tty[NRC * CD180_NCHAN]; 155int nrc_tty = NRC * CD180_NCHAN; 156 157/* Flags */ 158#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 159#define RC_ACTOUT 0x0002 /* Dial-out port active */ 160#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 161#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 162#define RC_DORXFER 0x0010 /* RXFER event planned */ 163#define RC_DOXXFER 0x0020 /* XXFER event planned */ 164#define RC_MODCHG 0x0040 /* Modem status changed */ 165#define RC_OSUSP 0x0080 /* Output suspended */ 166#define RC_OSBUSY 0x0100 /* start() routine in progress */ 167#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 168#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 169#define RC_SEND_RDY 0x0800 /* ready to send */ 170 171/* Table for translation of RCSR status bits to internal form */ 172static int rc_rcsrt[16] = { 173 0, TTY_OE, TTY_FE, 174 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 175 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 176 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 177 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 178 TTY_BI|TTY_PE|TTY_FE|TTY_OE 179}; 180 181/* Static prototypes */ 182static void rc_hwreset __P((int, int, unsigned int)); 183static int rc_test __P((int, int)); 184static void rc_discard_output __P((struct rc_chans *)); 185static void rc_hardclose __P((struct rc_chans *)); 186static int rc_modctl __P((struct rc_chans *, int, int)); 187static void rc_start __P((struct tty *)); 188static int rc_param __P((struct tty *, struct termios *)); 189static void rc_registerdev __P((struct isa_device *id)); 190static void rc_reinit __P((struct rc_softc *)); 191#ifdef RCDEBUG 192static void printrcflags(); 193#endif 194static timeout_t rc_dtrwakeup; 195static timeout_t rc_wakeup; 196static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 197static void rc_wait0 __P((int nec, int unit, int chan, int line)); 198 199/**********************************************/ 200 201/* Quick device probing */ 202int rcprobe(dvp) 203 struct isa_device *dvp; 204{ 205 int irq = ffs(dvp->id_irq) - 1; 206 register int nec = dvp->id_iobase; 207 208 if (dvp->id_unit > NRC) 209 return 0; 210 if (!RC_VALIDADDR(nec)) { 211 printf("rc%d: illegal base address %x\n", nec); 212 return 0; 213 } 214 if (!RC_VALIDIRQ(irq)) { 215 printf("rc%d: illegal IRQ value %d\n", irq); 216 return 0; 217 } 218 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 219 rcout(CD180_PPRH, 0x11); 220 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 221 return 0; 222 /* Now, test the board more thoroughly, with diagnostic */ 223 if (rc_test(nec, dvp->id_unit)) 224 return 0; 225 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 226 227 return 0xF; 228} 229 230static struct kern_devconf kdc_rc[NRC] = { { 231 0, 0, 0, /* filled in by dev_attach */ 232 "rc", 0, { MDDT_ISA, 0, "tty" }, 233 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 234 &kdc_isa0, /* parent */ 235 0, /* parentdata */ 236 DC_UNCONFIGURED, /* state */ 237 "RISCom/8 multiport card", 238 DC_CLS_SERIAL /* class */ 239} }; 240 241static void 242rc_registerdev(id) 243 struct isa_device *id; 244{ 245 int unit; 246 247 unit = id->id_unit; 248 if (unit != 0) 249 kdc_rc[unit] = kdc_rc[0]; 250 kdc_rc[unit].kdc_unit = unit; 251 kdc_rc[unit].kdc_isa = id; 252 kdc_rc[unit].kdc_state = DC_UNKNOWN; 253 dev_attach(&kdc_rc[unit]); 254} 255 256int rcattach(dvp) 257 struct isa_device *dvp; 258{ 259 register int i, chan, nec = dvp->id_iobase; 260 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 261 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 262 static int rc_wakeup_started = 0; 263 struct tty *tp; 264 char name[32]; 265 266 /* Thorooughly test the device */ 267 if (rcb->rcb_probed != RC_PROBED) 268 return 0; 269 rcb->rcb_addr = nec; 270 rcb->rcb_dtr = 0; 271 rcb->rcb_baserc = rc; 272 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 273 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 274 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 275 276 rc_registerdev(dvp); 277 278 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 279 rc->rc_rcb = rcb; 280 rc->rc_chan = chan; 281 rc->rc_iptr = rc->rc_ibuf; 282 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 283 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 284 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 285 rc->rc_cor2 = rc->rc_pendcmd = 0; 286 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 287 rc->rc_dtrwait = 3 * hz; 288 rc->rc_dcdwaits= 0; 289 rc->rc_hotchar = 0; 290 tp = rc->rc_tp = &rc_tty[chan]; 291 ttychars(tp); 292 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 293 tp->t_cflag = TTYDEF_CFLAG; 294 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 295#ifdef DEVFS 296/* FIX THIS to reflect real devices */ 297 sprintf(name,"rc%d.%d",dvp->id_unit,chan); 298 rc->devfs_token = devfs_add_devsw( "/", name, 299 &rc_cdevsw,(dvp->id_unit * CD180_NCHAN) + chan , 300 DV_CHR, 0, 0, 0600); 301#endif 302 } 303 rcb->rcb_probed = RC_ATTACHED; 304 if (!rc_wakeup_started) { 305 rc_wakeup((void *)NULL); 306 rc_wakeup_started = 0; 307 } 308 return 1; 309} 310 311/* RC interrupt handling */ 312void rcintr(unit) 313 int unit; 314{ 315 register struct rc_softc *rcb = &rc_softc[unit]; 316 register struct rc_chans *rc; 317 register int nec, resid; 318 register u_char val, iack, bsr, ucnt, *optr; 319 int good_data, t_state; 320 321 if (rcb->rcb_probed != RC_ATTACHED) { 322 printf("rc%d: bogus interrupt\n", unit); 323 return; 324 } 325 nec = rcb->rcb_addr; 326 327 bsr = ~(rcin(RC_BSR)); 328 329 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 330 printf("rc%d: extra interrupt\n", unit); 331 rcout(CD180_EOIR, 0); 332 return; 333 } 334 335 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 336#ifdef RCDEBUG_DETAILED 337 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 338 (bsr & RC_BSR_TOUT)?"TOUT ":"", 339 (bsr & RC_BSR_RXINT)?"RXINT ":"", 340 (bsr & RC_BSR_TXINT)?"TXINT ":"", 341 (bsr & RC_BSR_MOINT)?"MOINT":""); 342#endif 343 if (bsr & RC_BSR_TOUT) { 344 printf("rc%d: hardware failure, reset board\n", unit); 345 rcout(RC_CTOUT, 0); 346 rc_reinit(rcb); 347 return; 348 } 349 if (bsr & RC_BSR_RXINT) { 350 iack = rcin(RC_PILR_RX); 351 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 352 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 353 printf("rc%d: fake rxint: %02x\n", unit, iack); 354 goto more_intrs; 355 } 356 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 357 t_state = rc->rc_tp->t_state; 358 /* Do RTS flow control stuff */ 359 if ( (rc->rc_flags & RC_RTSFLOW) 360 || !(t_state & TS_ISOPEN) 361 ) { 362 if ( ( !(t_state & TS_ISOPEN) 363 || (t_state & TS_TBLOCK) 364 ) 365 && (rc->rc_msvr & MSVR_RTS) 366 ) 367 rcout(CD180_MSVR, 368 rc->rc_msvr &= ~MSVR_RTS); 369 else if (!(rc->rc_msvr & MSVR_RTS)) 370 rcout(CD180_MSVR, 371 rc->rc_msvr |= MSVR_RTS); 372 } 373 ucnt = rcin(CD180_RDCR) & 0xF; 374 resid = 0; 375 376 if (t_state & TS_ISOPEN) { 377 /* check for input buffer overflow */ 378 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 379 resid = ucnt; 380 ucnt = rc->rc_bufend - rc->rc_iptr; 381 resid -= ucnt; 382 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 383 rc->rc_flags |= RC_WAS_BUFOVFL; 384 rc_scheduled_event++; 385 } 386 } 387 optr = rc->rc_iptr; 388 /* check foor good data */ 389 if (good_data) { 390 while (ucnt-- > 0) { 391 val = rcin(CD180_RDR); 392 optr[0] = val; 393 optr[INPUT_FLAGS_SHIFT] = 0; 394 optr++; 395 rc_scheduled_event++; 396 if (val != 0 && val == rc->rc_hotchar) 397 setsofttty(); 398 } 399 } else { 400 /* Store also status data */ 401 while (ucnt-- > 0) { 402 iack = rcin(CD180_RCSR); 403 if (iack & RCSR_Timeout) 404 break; 405 if ( (iack & RCSR_OE) 406 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 407 rc->rc_flags |= RC_WAS_SILOVFL; 408 rc_scheduled_event++; 409 } 410 val = rcin(CD180_RDR); 411 /* 412 Don't store PE if IGNPAR and BREAK if IGNBRK, 413 this hack allows "raw" tty optimization 414 works even if IGN* is set. 415 */ 416 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 417 || (!(iack & (RCSR_PE|RCSR_FE)) 418 || !(rc->rc_tp->t_iflag & IGNPAR)) 419 && (!(iack & RCSR_Break) 420 || !(rc->rc_tp->t_iflag & IGNBRK))) { 421 if ( (iack & (RCSR_PE|RCSR_FE)) 422 && (t_state & TS_CAN_BYPASS_L_RINT) 423 && ((iack & RCSR_FE) 424 || (iack & RCSR_PE) 425 && (rc->rc_tp->t_iflag & INPCK))) 426 val = 0; 427 else if (val != 0 && val == rc->rc_hotchar) 428 setsofttty(); 429 optr[0] = val; 430 optr[INPUT_FLAGS_SHIFT] = iack; 431 optr++; 432 rc_scheduled_event++; 433 } 434 } 435 } 436 rc->rc_iptr = optr; 437 rc->rc_flags |= RC_DORXFER; 438 } else 439 resid = ucnt; 440 /* Clear FIFO if necessary */ 441 while (resid-- > 0) { 442 if (!good_data) 443 iack = rcin(CD180_RCSR); 444 else 445 iack = 0; 446 if (iack & RCSR_Timeout) 447 break; 448 (void) rcin(CD180_RDR); 449 } 450 goto more_intrs; 451 } 452 if (bsr & RC_BSR_MOINT) { 453 iack = rcin(RC_PILR_MODEM); 454 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 455 printf("rc%d: fake moint: %02x\n", unit, iack); 456 goto more_intrs; 457 } 458 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 459 iack = rcin(CD180_MCR); 460 rc->rc_msvr = rcin(CD180_MSVR); 461 rcout(CD180_MCR, 0); 462#ifdef RCDEBUG 463 printrcflags(rc, "moint"); 464#endif 465 if (rc->rc_flags & RC_CTSFLOW) { 466 if (rc->rc_msvr & MSVR_CTS) 467 rc->rc_flags |= RC_SEND_RDY; 468 else 469 rc->rc_flags &= ~RC_SEND_RDY; 470 } else 471 rc->rc_flags |= RC_SEND_RDY; 472 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 473 rc_scheduled_event += LOTS_OF_EVENTS; 474 rc->rc_flags |= RC_MODCHG; 475 setsofttty(); 476 } 477 goto more_intrs; 478 } 479 if (bsr & RC_BSR_TXINT) { 480 iack = rcin(RC_PILR_TX); 481 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 482 printf("rc%d: fake txint: %02x\n", unit, iack); 483 goto more_intrs; 484 } 485 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 486 if ( (rc->rc_flags & RC_OSUSP) 487 || !(rc->rc_flags & RC_SEND_RDY) 488 ) 489 goto more_intrs; 490 /* Handle breaks and other stuff */ 491 if (rc->rc_pendcmd) { 492 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 493 rcout(CD180_TDR, CD180_C_ESC); 494 rcout(CD180_TDR, rc->rc_pendcmd); 495 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 496 rc->rc_pendcmd = 0; 497 goto more_intrs; 498 } 499 optr = rc->rc_optr; 500 resid = rc->rc_obufend - optr; 501 if (resid > CD180_NFIFO) 502 resid = CD180_NFIFO; 503 while (resid-- > 0) 504 rcout(CD180_TDR, *optr++); 505 rc->rc_optr = optr; 506 507 /* output completed? */ 508 if (optr >= rc->rc_obufend) { 509 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 510#ifdef RCDEBUG 511 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 512#endif 513 if (!(rc->rc_flags & RC_DOXXFER)) { 514 rc_scheduled_event += LOTS_OF_EVENTS; 515 rc->rc_flags |= RC_DOXXFER; 516 setsofttty(); 517 } 518 } 519 } 520 more_intrs: 521 rcout(CD180_EOIR, 0); /* end of interrupt */ 522 rcout(RC_CTOUT, 0); 523 bsr = ~(rcin(RC_BSR)); 524 } 525} 526 527/* Feed characters to output buffer */ 528static void rc_start(tp) 529register struct tty *tp; 530{ 531 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 532 register int nec = rc->rc_rcb->rcb_addr, s; 533 534 if (rc->rc_flags & RC_OSBUSY) 535 return; 536 s = spltty(); 537 rc->rc_flags |= RC_OSBUSY; 538 disable_intr(); 539 if (tp->t_state & TS_TTSTOP) 540 rc->rc_flags |= RC_OSUSP; 541 else 542 rc->rc_flags &= ~RC_OSUSP; 543 /* Do RTS flow control stuff */ 544 if ( (rc->rc_flags & RC_RTSFLOW) 545 && (tp->t_state & TS_TBLOCK) 546 && (rc->rc_msvr & MSVR_RTS) 547 ) { 548 rcout(CD180_CAR, rc->rc_chan); 549 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 550 } else if (!(rc->rc_msvr & MSVR_RTS)) { 551 rcout(CD180_CAR, rc->rc_chan); 552 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 553 } 554 enable_intr(); 555 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 556 goto out; 557#ifdef RCDEBUG 558 printrcflags(rc, "rcstart"); 559#endif 560 ttwwakeup(tp); 561#ifdef RCDEBUG 562 printf("rcstart: outq = %d obuf = %d\n", 563 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 564#endif 565 if (tp->t_state & TS_BUSY) 566 goto out; /* output still in progress ... */ 567 568 if (tp->t_outq.c_cc > 0) { 569 u_int ocnt; 570 571 tp->t_state |= TS_BUSY; 572 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 573 disable_intr(); 574 rc->rc_optr = rc->rc_obuf; 575 rc->rc_obufend = rc->rc_optr + ocnt; 576 enable_intr(); 577 if (!(rc->rc_ier & IER_TxRdy)) { 578#ifdef RCDEBUG 579 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 580#endif 581 rcout(CD180_CAR, rc->rc_chan); 582 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 583 } 584 } 585out: 586 rc->rc_flags &= ~RC_OSBUSY; 587 (void) splx(s); 588} 589 590/* Handle delayed events. */ 591void rcpoll() 592{ 593 register struct rc_chans *rc; 594 register struct rc_softc *rcb; 595 register u_char *tptr, *eptr; 596 register int s; 597 register struct tty *tp; 598 register int chan, icnt, c, nec, unit; 599 600 if (rc_scheduled_event == 0) 601 return; 602repeat: 603 for (unit = 0; unit < NRC; unit++) { 604 rcb = &rc_softc[unit]; 605 rc = rcb->rcb_baserc; 606 nec = rc->rc_rcb->rcb_addr; 607 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 608 tp = rc->rc_tp; 609#ifdef RCDEBUG 610 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 611 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 612 printrcflags(rc, "rcevent"); 613#endif 614 if (rc->rc_flags & RC_WAS_BUFOVFL) { 615 disable_intr(); 616 rc->rc_flags &= ~RC_WAS_BUFOVFL; 617 rc_scheduled_event--; 618 enable_intr(); 619 printf("rc%d/%d: interrupt-level buffer overflow\n", 620 unit, chan); 621 } 622 if (rc->rc_flags & RC_WAS_SILOVFL) { 623 disable_intr(); 624 rc->rc_flags &= ~RC_WAS_SILOVFL; 625 rc_scheduled_event--; 626 enable_intr(); 627 printf("rc%d/%d: silo overflow\n", 628 unit, chan); 629 } 630 if (rc->rc_flags & RC_MODCHG) { 631 disable_intr(); 632 rc->rc_flags &= ~RC_MODCHG; 633 rc_scheduled_event -= LOTS_OF_EVENTS; 634 enable_intr(); 635 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 636 } 637 if (rc->rc_flags & RC_DORXFER) { 638 disable_intr(); 639 rc->rc_flags &= ~RC_DORXFER; 640 eptr = rc->rc_iptr; 641 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 642 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 643 else 644 tptr = rc->rc_ibuf; 645 icnt = eptr - tptr; 646 if (icnt > 0) { 647 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 648 rc->rc_iptr = rc->rc_ibuf; 649 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 650 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 651 } else { 652 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 653 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 654 rc->rc_hiwat = 655 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 656 } 657 if ( (rc->rc_flags & RC_RTSFLOW) 658 && (tp->t_state & TS_ISOPEN) 659 && !(tp->t_state & TS_TBLOCK) 660 && !(rc->rc_msvr & MSVR_RTS) 661 ) { 662 rcout(CD180_CAR, chan); 663 rcout(CD180_MSVR, 664 rc->rc_msvr |= MSVR_RTS); 665 } 666 rc_scheduled_event -= icnt; 667 } 668 enable_intr(); 669 670 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 671 goto done1; 672 673 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 674 && !(tp->t_state & TS_LOCAL)) { 675 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 676 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 677 && !(tp->t_state & TS_TBLOCK)) 678 ttyblock(tp); 679 tk_nin += icnt; 680 tk_rawcc += icnt; 681 tp->t_rawcc += icnt; 682 if (b_to_q(tptr, icnt, &tp->t_rawq)) 683 printf("rc%d/%d: tty-level buffer overflow\n", 684 unit, chan); 685 ttwakeup(tp); 686 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 687 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 688 tp->t_state &= ~TS_TTSTOP; 689 tp->t_lflag &= ~FLUSHO; 690 rc_start(tp); 691 } 692 } else { 693 for (; tptr < eptr; tptr++) 694 (*linesw[tp->t_line].l_rint) 695 (tptr[0] | 696 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 697 } 698done1: 699 } 700 if (rc->rc_flags & RC_DOXXFER) { 701 disable_intr(); 702 rc_scheduled_event -= LOTS_OF_EVENTS; 703 rc->rc_flags &= ~RC_DOXXFER; 704 rc->rc_tp->t_state &= ~TS_BUSY; 705 enable_intr(); 706 (*linesw[tp->t_line].l_start)(tp); 707 } 708 } 709 if (rc_scheduled_event == 0) 710 break; 711 } 712 if (rc_scheduled_event >= LOTS_OF_EVENTS) 713 goto repeat; 714} 715 716static void 717rcstop(tp, rw) 718 register struct tty *tp; 719 int rw; 720{ 721 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 722 u_char *tptr, *eptr; 723 724#ifdef RCDEBUG 725 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 726 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 727#endif 728 if (rw & FWRITE) 729 rc_discard_output(rc); 730 disable_intr(); 731 if (rw & FREAD) { 732 rc->rc_flags &= ~RC_DORXFER; 733 eptr = rc->rc_iptr; 734 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 735 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 736 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 737 } else { 738 tptr = rc->rc_ibuf; 739 rc->rc_iptr = rc->rc_ibuf; 740 } 741 rc_scheduled_event -= eptr - tptr; 742 } 743 if (tp->t_state & TS_TTSTOP) 744 rc->rc_flags |= RC_OSUSP; 745 else 746 rc->rc_flags &= ~RC_OSUSP; 747 enable_intr(); 748} 749 750static int 751rcopen(dev, flag, mode, p) 752 dev_t dev; 753 int flag, mode; 754 struct proc *p; 755{ 756 register struct rc_chans *rc; 757 register struct tty *tp; 758 int unit, nec, s, error = 0; 759 760 unit = GET_UNIT(dev); 761 if (unit >= NRC * CD180_NCHAN) 762 return ENXIO; 763 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 764 return ENXIO; 765 rc = &rc_chans[unit]; 766 tp = rc->rc_tp; 767 nec = rc->rc_rcb->rcb_addr; 768#ifdef RCDEBUG 769 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 770#endif 771 s = spltty(); 772 773again: 774 while (rc->rc_flags & RC_DTR_OFF) { 775 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 776 if (error != 0) 777 goto out; 778 } 779 if (tp->t_state & TS_ISOPEN) { 780 if (CALLOUT(dev)) { 781 if (!(rc->rc_flags & RC_ACTOUT)) { 782 error = EBUSY; 783 goto out; 784 } 785 } else { 786 if (rc->rc_flags & RC_ACTOUT) { 787 if (flag & O_NONBLOCK) { 788 error = EBUSY; 789 goto out; 790 } 791 if (error = tsleep(&rc->rc_rcb, 792 TTIPRI|PCATCH, "rcbi", 0)) 793 goto out; 794 goto again; 795 } 796 } 797 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 798 error = EBUSY; 799 goto out; 800 } 801 } else { 802 tp->t_oproc = rc_start; 803 tp->t_param = rc_param; 804 tp->t_dev = dev; 805 806 if (CALLOUT(dev)) 807 tp->t_cflag |= CLOCAL; 808 else 809 tp->t_cflag &= ~CLOCAL; 810 811 error = rc_param(tp, &tp->t_termios); 812 if (error) 813 goto out; 814 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 815 816 ttsetwater(tp); 817 818 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 819 (*linesw[tp->t_line].l_modem)(tp, 1); 820 } 821 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 822 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 823 rc->rc_dcdwaits++; 824 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 825 rc->rc_dcdwaits--; 826 if (error != 0) 827 goto out; 828 goto again; 829 } 830 error = (*linesw[tp->t_line].l_open)(dev, tp); 831 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 832 rc->rc_flags |= RC_ACTOUT; 833out: 834 (void) splx(s); 835 836 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 837 rc_hardclose(rc); 838 839 return error; 840} 841 842static int 843rcclose(dev, flag, mode, p) 844 dev_t dev; 845 int flag, mode; 846 struct proc *p; 847{ 848 register struct rc_chans *rc; 849 register struct tty *tp; 850 int s, unit = GET_UNIT(dev); 851 852 if (unit >= NRC * CD180_NCHAN) 853 return ENXIO; 854 rc = &rc_chans[unit]; 855 tp = rc->rc_tp; 856#ifdef RCDEBUG 857 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 858#endif 859 s = spltty(); 860 (*linesw[tp->t_line].l_close)(tp, flag); 861 rcstop(tp, FREAD | FWRITE); 862 rc_hardclose(rc); 863 ttyclose(tp); 864 splx(s); 865 return 0; 866} 867 868static void rc_hardclose(rc) 869register struct rc_chans *rc; 870{ 871 register int s, nec = rc->rc_rcb->rcb_addr; 872 register struct tty *tp = rc->rc_tp; 873 874 s = spltty(); 875 rcout(CD180_CAR, rc->rc_chan); 876 877 /* Disable rx/tx intrs */ 878 rcout(CD180_IER, rc->rc_ier = 0); 879 if ( (tp->t_cflag & HUPCL) 880 || !(rc->rc_flags & RC_ACTOUT) 881 && !(rc->rc_msvr & MSVR_CD) 882 && !(tp->t_cflag & CLOCAL) 883 || !(tp->t_state & TS_ISOPEN) 884 ) { 885 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 886 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 887 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 888 if (rc->rc_dtrwait) { 889 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 890 rc->rc_flags |= RC_DTR_OFF; 891 } 892 } 893 rc->rc_flags &= ~RC_ACTOUT; 894 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 895 wakeup(TSA_CARR_ON(tp)); 896 (void) splx(s); 897} 898 899/* Read from line */ 900static int 901rcread(dev, uio, flag) 902 dev_t dev; 903 struct uio *uio; 904 int flag; 905{ 906 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 907 908 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 909} 910 911/* Write to line */ 912static int 913rcwrite(dev, uio, flag) 914 dev_t dev; 915 struct uio *uio; 916 int flag; 917{ 918 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 919 920 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 921} 922 923/* Reset the bastard */ 924static void rc_hwreset(unit, nec, chipid) 925 register int unit, nec; 926 unsigned int chipid; 927{ 928 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 929 DELAY(20000); 930 WAITFORCCR(unit, -1); 931 932 rcout(RC_CTOUT, 0); /* Clear timeout */ 933 rcout(CD180_GIVR, chipid); 934 rcout(CD180_GICR, 0); 935 936 /* Set Prescaler Registers (1 msec) */ 937 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 938 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 939 940 /* Initialize Priority Interrupt Level Registers */ 941 rcout(CD180_PILR1, RC_PILR_MODEM); 942 rcout(CD180_PILR2, RC_PILR_TX); 943 rcout(CD180_PILR3, RC_PILR_RX); 944 945 /* Reset DTR */ 946 rcout(RC_DTREG, ~0); 947} 948 949/* Set channel parameters */ 950static int rc_param(tp, ts) 951 register struct tty *tp; 952 struct termios *ts; 953{ 954 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 955 register int nec = rc->rc_rcb->rcb_addr; 956 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 957 958 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 959 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 960 ) 961 return (EINVAL); 962 if (ts->c_ispeed == 0) 963 ts->c_ispeed = ts->c_ospeed; 964 odivs = RC_BRD(ts->c_ospeed); 965 idivs = RC_BRD(ts->c_ispeed); 966 967 s = spltty(); 968 969 /* Select channel */ 970 rcout(CD180_CAR, rc->rc_chan); 971 972 /* If speed == 0, hangup line */ 973 if (ts->c_ospeed == 0) { 974 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 975 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 976 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 977 } 978 979 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 980 cflag = ts->c_cflag; 981 iflag = ts->c_iflag; 982 lflag = ts->c_lflag; 983 984 if (idivs > 0) { 985 rcout(CD180_RBPRL, idivs & 0xFF); 986 rcout(CD180_RBPRH, idivs >> 8); 987 } 988 if (odivs > 0) { 989 rcout(CD180_TBPRL, odivs & 0xFF); 990 rcout(CD180_TBPRH, odivs >> 8); 991 } 992 993 /* set timeout value */ 994 if (ts->c_ispeed > 0) { 995 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 996 997 if ( !(lflag & ICANON) 998 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 999 && ts->c_cc[VTIME] * 10 > itm) 1000 itm = ts->c_cc[VTIME] * 10; 1001 1002 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 1003 } 1004 1005 switch (cflag & CSIZE) { 1006 case CS5: val = COR1_5BITS; break; 1007 case CS6: val = COR1_6BITS; break; 1008 case CS7: val = COR1_7BITS; break; 1009 default: 1010 case CS8: val = COR1_8BITS; break; 1011 } 1012 if (cflag & PARENB) { 1013 val |= COR1_NORMPAR; 1014 if (cflag & PARODD) 1015 val |= COR1_ODDP; 1016 if (!(cflag & INPCK)) 1017 val |= COR1_Ignore; 1018 } else 1019 val |= COR1_Ignore; 1020 if (cflag & CSTOPB) 1021 val |= COR1_2SB; 1022 rcout(CD180_COR1, val); 1023 1024 /* Set FIFO threshold */ 1025 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1026 inpflow = 0; 1027 if ( (iflag & IXOFF) 1028 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1029 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1030 || (iflag & IXANY) 1031 ) 1032 ) 1033 ) { 1034 inpflow = 1; 1035 val |= COR3_SCDE|COR3_FCT; 1036 } 1037 rcout(CD180_COR3, val); 1038 1039 /* Initialize on-chip automatic flow control */ 1040 val = 0; 1041 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1042 if (cflag & CCTS_OFLOW) { 1043 rc->rc_flags |= RC_CTSFLOW; 1044 val |= COR2_CtsAE; 1045 } else 1046 rc->rc_flags |= RC_SEND_RDY; 1047 if (tp->t_state & TS_TTSTOP) 1048 rc->rc_flags |= RC_OSUSP; 1049 else 1050 rc->rc_flags &= ~RC_OSUSP; 1051 if (cflag & CRTS_IFLOW) 1052 rc->rc_flags |= RC_RTSFLOW; 1053 else 1054 rc->rc_flags &= ~RC_RTSFLOW; 1055 1056 if (inpflow) { 1057 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1058 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1059 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1060 val |= COR2_TxIBE; 1061 if (iflag & IXANY) 1062 val |= COR2_IXM; 1063 } 1064 1065 rcout(CD180_COR2, rc->rc_cor2 = val); 1066 1067 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1068 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1069 1070 disc_optim(tp, ts, rc); 1071 1072 /* modem ctl */ 1073 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1074 if (cflag & CCTS_OFLOW) 1075 val |= MCOR1_CTSzd; 1076 rcout(CD180_MCOR1, val); 1077 1078 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1079 if (cflag & CCTS_OFLOW) 1080 val |= MCOR2_CTSod; 1081 rcout(CD180_MCOR2, val); 1082 1083 /* enable i/o and interrupts */ 1084 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1085 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1086 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1087 1088 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1089 if (cflag & CCTS_OFLOW) 1090 rc->rc_ier |= IER_CTS; 1091 if (cflag & CREAD) 1092 rc->rc_ier |= IER_RxData; 1093 if (tp->t_state & TS_BUSY) 1094 rc->rc_ier |= IER_TxRdy; 1095 if (ts->c_ospeed != 0) 1096 rc_modctl(rc, TIOCM_DTR, DMBIS); 1097 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1098 rc->rc_flags |= RC_SEND_RDY; 1099 rcout(CD180_IER, rc->rc_ier); 1100 (void) splx(s); 1101 return 0; 1102} 1103 1104/* Re-initialize board after bogus interrupts */ 1105static void rc_reinit(rcb) 1106struct rc_softc *rcb; 1107{ 1108 register struct rc_chans *rc, *rce; 1109 register int i, nec; 1110 1111 nec = rcb->rcb_addr; 1112 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1113 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1114 rce = rc + CD180_NCHAN; 1115 for (; rc < rce; rc++) 1116 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1117} 1118 1119static int 1120rcioctl(dev, cmd, data, flag, p) 1121dev_t dev; 1122int cmd, flag; 1123caddr_t data; 1124struct proc *p; 1125{ 1126 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1127 register int s, error; 1128 struct tty *tp = rc->rc_tp; 1129 1130 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1131 if (error >= 0) 1132 return (error); 1133 error = ttioctl(tp, cmd, data, flag); 1134 if (error >= 0) 1135 return (error); 1136 s = spltty(); 1137 1138 switch (cmd) { 1139 case TIOCSBRK: 1140 rc->rc_pendcmd = CD180_C_SBRK; 1141 break; 1142 1143 case TIOCCBRK: 1144 rc->rc_pendcmd = CD180_C_EBRK; 1145 break; 1146 1147 case TIOCSDTR: 1148 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1149 break; 1150 1151 case TIOCCDTR: 1152 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1153 break; 1154 1155 case TIOCMGET: 1156 *(int *) data = rc_modctl(rc, 0, DMGET); 1157 break; 1158 1159 case TIOCMSET: 1160 (void) rc_modctl(rc, *(int *) data, DMSET); 1161 break; 1162 1163 case TIOCMBIC: 1164 (void) rc_modctl(rc, *(int *) data, DMBIC); 1165 break; 1166 1167 case TIOCMBIS: 1168 (void) rc_modctl(rc, *(int *) data, DMBIS); 1169 break; 1170 1171 case TIOCMSDTRWAIT: 1172 error = suser(p->p_ucred, &p->p_acflag); 1173 if (error != 0) { 1174 splx(s); 1175 return (error); 1176 } 1177 rc->rc_dtrwait = *(int *)data * hz / 100; 1178 break; 1179 1180 case TIOCMGDTRWAIT: 1181 *(int *)data = rc->rc_dtrwait * 100 / hz; 1182 break; 1183 1184 default: 1185 (void) splx(s); 1186 return ENOTTY; 1187 } 1188 (void) splx(s); 1189 return 0; 1190} 1191 1192 1193/* Modem control routines */ 1194 1195static int rc_modctl(rc, bits, cmd) 1196register struct rc_chans *rc; 1197int bits, cmd; 1198{ 1199 register int nec = rc->rc_rcb->rcb_addr; 1200 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1201 1202 rcout(CD180_CAR, rc->rc_chan); 1203 1204 switch (cmd) { 1205 case DMSET: 1206 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1207 ~(*dtr |= 1 << rc->rc_chan) : 1208 ~(*dtr &= ~(1 << rc->rc_chan))); 1209 msvr = rcin(CD180_MSVR); 1210 if (bits & TIOCM_RTS) 1211 msvr |= MSVR_RTS; 1212 else 1213 msvr &= ~MSVR_RTS; 1214 if (bits & TIOCM_DTR) 1215 msvr |= MSVR_DTR; 1216 else 1217 msvr &= ~MSVR_DTR; 1218 rcout(CD180_MSVR, msvr); 1219 break; 1220 1221 case DMBIS: 1222 if (bits & TIOCM_DTR) 1223 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1224 msvr = rcin(CD180_MSVR); 1225 if (bits & TIOCM_RTS) 1226 msvr |= MSVR_RTS; 1227 if (bits & TIOCM_DTR) 1228 msvr |= MSVR_DTR; 1229 rcout(CD180_MSVR, msvr); 1230 break; 1231 1232 case DMGET: 1233 bits = TIOCM_LE; 1234 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1235 1236 if (msvr & MSVR_RTS) 1237 bits |= TIOCM_RTS; 1238 if (msvr & MSVR_CTS) 1239 bits |= TIOCM_CTS; 1240 if (msvr & MSVR_DSR) 1241 bits |= TIOCM_DSR; 1242 if (msvr & MSVR_DTR) 1243 bits |= TIOCM_DTR; 1244 if (msvr & MSVR_CD) 1245 bits |= TIOCM_CD; 1246 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1247 bits |= TIOCM_RI; 1248 return bits; 1249 1250 case DMBIC: 1251 if (bits & TIOCM_DTR) 1252 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1253 msvr = rcin(CD180_MSVR); 1254 if (bits & TIOCM_RTS) 1255 msvr &= ~MSVR_RTS; 1256 if (bits & TIOCM_DTR) 1257 msvr &= ~MSVR_DTR; 1258 rcout(CD180_MSVR, msvr); 1259 break; 1260 } 1261 rc->rc_msvr = rcin(CD180_MSVR); 1262 return 0; 1263} 1264 1265/* Test the board. */ 1266int rc_test(nec, unit) 1267 register int nec; 1268 int unit; 1269{ 1270 int chan = 0, nopt = 0; 1271 int i = 0, rcnt, old_level; 1272 unsigned int iack, chipid; 1273 unsigned short divs; 1274 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1275#define CTLEN 8 1276#define ERR(s) { \ 1277 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1278 (void) splx(old_level); return 1; } 1279 1280 struct rtest { 1281 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1282 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1283 int rxptr; /* RX pointer */ 1284 int txptr; /* TX pointer */ 1285 } tchans[CD180_NCHAN]; 1286 1287 old_level = spltty(); 1288 1289 chipid = RC_FAKEID; 1290 1291 /* First, reset board to inital state */ 1292 rc_hwreset(unit, nec, chipid); 1293 1294 divs = RC_BRD(19200); 1295 1296 /* Initialize channels */ 1297 for (chan = 0; chan < CD180_NCHAN; chan++) { 1298 1299 /* Select and reset channel */ 1300 rcout(CD180_CAR, chan); 1301 CCRCMD(unit, chan, CCR_ResetChan); 1302 WAITFORCCR(unit, chan); 1303 1304 /* Set speed */ 1305 rcout(CD180_RBPRL, divs & 0xFF); 1306 rcout(CD180_RBPRH, divs >> 8); 1307 rcout(CD180_TBPRL, divs & 0xFF); 1308 rcout(CD180_TBPRH, divs >> 8); 1309 1310 /* set timeout value */ 1311 rcout(CD180_RTPR, 0); 1312 1313 /* Establish local loopback */ 1314 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1315 rcout(CD180_COR2, COR2_LLM); 1316 rcout(CD180_COR3, CD180_NFIFO); 1317 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1318 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1319 WAITFORCCR(unit, chan); 1320 rcout(CD180_MSVR, MSVR_RTS); 1321 1322 /* Fill TXBUF with test data */ 1323 for (i = 0; i < CD180_NFIFO; i++) { 1324 tchans[chan].txbuf[i] = ctest[i]; 1325 tchans[chan].rxbuf[i] = 0; 1326 } 1327 tchans[chan].txptr = tchans[chan].rxptr = 0; 1328 1329 /* Now, start transmit */ 1330 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1331 } 1332 /* Pseudo-interrupt poll stuff */ 1333 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1334 i = ~(rcin(RC_BSR)); 1335 if (i & RC_BSR_TOUT) 1336 ERR(("BSR timeout bit set\n")) 1337 else if (i & RC_BSR_TXINT) { 1338 iack = rcin(RC_PILR_TX); 1339 if (iack != (GIVR_IT_TDI | chipid)) 1340 ERR(("Bad TX intr ack (%02x != %02x)\n", 1341 iack, GIVR_IT_TDI | chipid)); 1342 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1343 /* If no more data to transmit, disable TX intr */ 1344 if (tchans[chan].txptr >= CD180_NFIFO) { 1345 iack = rcin(CD180_IER); 1346 rcout(CD180_IER, iack & ~IER_TxMpty); 1347 } else { 1348 for (iack = tchans[chan].txptr; 1349 iack < CD180_NFIFO; iack++) 1350 rcout(CD180_TDR, 1351 tchans[chan].txbuf[iack]); 1352 tchans[chan].txptr = iack; 1353 } 1354 rcout(CD180_EOIR, 0); 1355 } else if (i & RC_BSR_RXINT) { 1356 u_char ucnt; 1357 1358 iack = rcin(RC_PILR_RX); 1359 if (iack != (GIVR_IT_RGDI | chipid) && 1360 iack != (GIVR_IT_REI | chipid)) 1361 ERR(("Bad RX intr ack (%02x != %02x)\n", 1362 iack, GIVR_IT_RGDI | chipid)) 1363 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1364 ucnt = rcin(CD180_RDCR) & 0xF; 1365 while (ucnt-- > 0) { 1366 iack = rcin(CD180_RCSR); 1367 if (iack & RCSR_Timeout) 1368 break; 1369 if (iack & 0xF) 1370 ERR(("Bad char chan %d (RCSR = %02X)\n", 1371 chan, iack)) 1372 if (tchans[chan].rxptr > CD180_NFIFO) 1373 ERR(("Got extra chars chan %d\n", 1374 chan)) 1375 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1376 rcin(CD180_RDR); 1377 } 1378 rcout(CD180_EOIR, 0); 1379 } 1380 rcout(RC_CTOUT, 0); 1381 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1382 if (tchans[chan].rxptr >= CD180_NFIFO) 1383 iack++; 1384 if (iack == CD180_NCHAN) 1385 break; 1386 } 1387 for (chan = 0; chan < CD180_NCHAN; chan++) { 1388 /* Select and reset channel */ 1389 rcout(CD180_CAR, chan); 1390 CCRCMD(unit, chan, CCR_ResetChan); 1391 } 1392 1393 if (!rcnt) 1394 ERR(("looses characters during local loopback\n")) 1395 /* Now, check data */ 1396 for (chan = 0; chan < CD180_NCHAN; chan++) 1397 for (i = 0; i < CD180_NFIFO; i++) 1398 if (ctest[i] != tchans[chan].rxbuf[i]) 1399 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1400 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1401 (void) splx(old_level); 1402 return 0; 1403} 1404 1405#ifdef RCDEBUG 1406static void printrcflags(rc, comment) 1407struct rc_chans *rc; 1408char *comment; 1409{ 1410 u_short f = rc->rc_flags; 1411 register int nec = rc->rc_rcb->rcb_addr; 1412 1413 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1414 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1415 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1416 (f & RC_ACTOUT) ?"ACTOUT " :"", 1417 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1418 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1419 (f & RC_DORXFER)?"DORXFER " :"", 1420 (f & RC_DOXXFER)?"DOXXFER " :"", 1421 (f & RC_MODCHG) ?"MODCHG " :"", 1422 (f & RC_OSUSP) ?"OSUSP " :"", 1423 (f & RC_OSBUSY) ?"OSBUSY " :"", 1424 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1425 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1426 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1427 1428 rcout(CD180_CAR, rc->rc_chan); 1429 1430 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1431 rc->rc_rcb->rcb_unit, rc->rc_chan, 1432 rcin(CD180_MSVR), 1433 rcin(CD180_IER), 1434 rcin(CD180_CCSR)); 1435} 1436#endif /* RCDEBUG */ 1437 1438static struct tty * 1439rcdevtotty(dev) 1440 dev_t dev; 1441{ 1442 int unit; 1443 1444 unit = GET_UNIT(dev); 1445 if (unit >= NRC * CD180_NCHAN) 1446 return NULL; 1447 return (&rc_tty[unit]); 1448} 1449 1450static void 1451rc_dtrwakeup(chan) 1452 void *chan; 1453{ 1454 struct rc_chans *rc; 1455 1456 rc = (struct rc_chans *)chan; 1457 rc->rc_flags &= ~RC_DTR_OFF; 1458 wakeup(&rc->rc_dtrwait); 1459} 1460 1461static void 1462rc_discard_output(rc) 1463 struct rc_chans *rc; 1464{ 1465 disable_intr(); 1466 if (rc->rc_flags & RC_DOXXFER) { 1467 rc_scheduled_event -= LOTS_OF_EVENTS; 1468 rc->rc_flags &= ~RC_DOXXFER; 1469 } 1470 rc->rc_optr = rc->rc_obufend; 1471 rc->rc_tp->t_state &= ~TS_BUSY; 1472 enable_intr(); 1473 ttwwakeup(rc->rc_tp); 1474} 1475 1476static void 1477rc_wakeup(chan) 1478 void *chan; 1479{ 1480 int unit; 1481 1482 timeout(rc_wakeup, (caddr_t)NULL, 1); 1483 1484 if (rc_scheduled_event != 0) { 1485 int s; 1486 1487 s = splsofttty(); 1488 rcpoll(); 1489 splx(s); 1490 } 1491} 1492 1493static void 1494disc_optim(tp, t, rc) 1495 struct tty *tp; 1496 struct termios *t; 1497 struct rc_chans *rc; 1498{ 1499 1500 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1501 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1502 && (!(t->c_iflag & PARMRK) 1503 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1504 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1505 && linesw[tp->t_line].l_rint == ttyinput) 1506 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1507 else 1508 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1509 if (tp->t_line == SLIPDISC) 1510 rc->rc_hotchar = 0xc0; 1511 else if (tp->t_line == PPPDISC) 1512 rc->rc_hotchar = 0x7e; 1513 else 1514 rc->rc_hotchar = 0; 1515} 1516 1517static void 1518rc_wait0(nec, unit, chan, line) 1519 int nec, unit, chan, line; 1520{ 1521 int rcnt; 1522 1523 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 1524 DELAY(15); 1525 if (rcnt == 0) 1526 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1527 unit, chan, line); 1528} 1529 1530static rc_devsw_installed = 0; 1531 1532static void rc_drvinit(void *unused) 1533{ 1534 dev_t dev; 1535 1536 if( ! rc_devsw_installed ) { 1537 dev = makedev(CDEV_MAJOR, 0); 1538 cdevsw_add(&dev,&rc_cdevsw, NULL); 1539 rc_devsw_installed = 1; 1540 } 1541} 1542 1543SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1544 1545 1546#endif /* NRC */ 1547