rc.c revision 12658
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#include <sys/devconf.h> 50 51#include <machine/clock.h> 52 53#include <i386/isa/isa.h> 54#include <i386/isa/isa_device.h> 55#include <i386/isa/sioreg.h> 56 57#include <i386/isa/ic/cd180.h> 58#include <i386/isa/rcreg.h> 59 60#ifdef JREMOD 61#include <sys/conf.h> 62#include <sys/kernel.h> 63#ifdef DEVFS 64#include <sys/devfsext.h> 65#endif /*DEVFS*/ 66#define CDEV_MAJOR 63 67#endif /*JREMOD*/ 68 69/* Prototypes */ 70int rcprobe __P((struct isa_device *)); 71int rcattach __P((struct isa_device *)); 72 73/*- 74 * This space intentionally left blank to stop __LINE__ from screwing up 75 * regression tests :-(. 76 * 77 * 78 * 79 */ 80void rcpoll __P((void)); 81 82#define rcin(port) RC_IN (nec, port) 83#define rcout(port,v) RC_OUT (nec, port, v) 84 85#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 86#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 87 88#define RC_IBUFSIZE 256 89#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 90#define RC_OBUFSIZE 512 91#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 92#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 93#define LOTS_OF_EVENTS 64 94 95#define RC_FAKEID 0x10 96 97#define RC_PROBED 1 98#define RC_ATTACHED 2 99 100#define GET_UNIT(dev) (minor(dev) & 0x3F) 101#define CALLOUT(dev) (minor(dev) & 0x80) 102 103/* For isa routines */ 104struct isa_driver rcdriver = { 105 rcprobe, rcattach, "rc" 106}; 107 108/* Per-board structure */ 109static struct rc_softc { 110 u_int rcb_probed; /* 1 - probed, 2 - attached */ 111 u_int rcb_addr; /* Base I/O addr */ 112 u_int rcb_unit; /* unit # */ 113 u_char rcb_dtr; /* DTR status */ 114 struct rc_chans *rcb_baserc; /* base rc ptr */ 115} rc_softc[NRC]; 116 117/* Per-channel structure */ 118static struct rc_chans { 119 struct rc_softc *rc_rcb; /* back ptr */ 120 u_short rc_flags; /* Misc. flags */ 121 int rc_chan; /* Channel # */ 122 u_char rc_ier; /* intr. enable reg */ 123 u_char rc_msvr; /* modem sig. status */ 124 u_char rc_cor2; /* options reg */ 125 u_char rc_pendcmd; /* special cmd pending */ 126 u_int rc_dtrwait; /* dtr timeout */ 127 u_int rc_dcdwaits; /* how many waits DCD in open */ 128 u_char rc_hotchar; /* end packed optimize */ 129 struct tty *rc_tp; /* tty struct */ 130 u_char *rc_iptr; /* Chars input buffer */ 131 u_char *rc_hiwat; /* hi-water mark */ 132 u_char *rc_bufend; /* end of buffer */ 133 u_char *rc_optr; /* ptr in output buf */ 134 u_char *rc_obufend; /* end of output buf */ 135 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 136 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 137} rc_chans[NRC * CD180_NCHAN]; 138 139static int rc_scheduled_event = 0; 140 141/* for pstat -t */ 142struct tty rc_tty[NRC * CD180_NCHAN]; 143int nrc_tty = NRC * CD180_NCHAN; 144 145/* Flags */ 146#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 147#define RC_ACTOUT 0x0002 /* Dial-out port active */ 148#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 149#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 150#define RC_DORXFER 0x0010 /* RXFER event planned */ 151#define RC_DOXXFER 0x0020 /* XXFER event planned */ 152#define RC_MODCHG 0x0040 /* Modem status changed */ 153#define RC_OSUSP 0x0080 /* Output suspended */ 154#define RC_OSBUSY 0x0100 /* start() routine in progress */ 155#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 156#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 157#define RC_SEND_RDY 0x0800 /* ready to send */ 158 159/* Table for translation of RCSR status bits to internal form */ 160static int rc_rcsrt[16] = { 161 0, TTY_OE, TTY_FE, 162 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 163 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 164 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 165 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 166 TTY_BI|TTY_PE|TTY_FE|TTY_OE 167}; 168 169/* Static prototypes */ 170static void rc_hwreset __P((int, int, unsigned int)); 171static int rc_test __P((int, int)); 172static void rc_discard_output __P((struct rc_chans *)); 173static void rc_hardclose __P((struct rc_chans *)); 174static int rc_modctl __P((struct rc_chans *, int, int)); 175static void rc_start __P((struct tty *)); 176static int rc_param __P((struct tty *, struct termios *)); 177static void rc_registerdev __P((struct isa_device *id)); 178static void rc_reinit __P((struct rc_softc *)); 179#ifdef RCDEBUG 180static void printrcflags(); 181#endif 182static timeout_t rc_dtrwakeup; 183static timeout_t rc_wakeup; 184static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 185static void rc_wait0 __P((int nec, int unit, int chan, int line)); 186 187/**********************************************/ 188 189/* Quick device probing */ 190int rcprobe(dvp) 191 struct isa_device *dvp; 192{ 193 int irq = ffs(dvp->id_irq) - 1; 194 register int nec = dvp->id_iobase; 195 196 if (dvp->id_unit > NRC) 197 return 0; 198 if (!RC_VALIDADDR(nec)) { 199 printf("rc%d: illegal base address %x\n", nec); 200 return 0; 201 } 202 if (!RC_VALIDIRQ(irq)) { 203 printf("rc%d: illegal IRQ value %d\n", irq); 204 return 0; 205 } 206 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 207 rcout(CD180_PPRH, 0x11); 208 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 209 return 0; 210 /* Now, test the board more thoroughly, with diagnostic */ 211 if (rc_test(nec, dvp->id_unit)) 212 return 0; 213 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 214 215 return 0xF; 216} 217 218static struct kern_devconf kdc_rc[NRC] = { { 219 0, 0, 0, /* filled in by dev_attach */ 220 "rc", 0, { MDDT_ISA, 0, "tty" }, 221 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 222 &kdc_isa0, /* parent */ 223 0, /* parentdata */ 224 DC_UNCONFIGURED, /* state */ 225 "RISCom/8 multiport card", 226 DC_CLS_SERIAL /* class */ 227} }; 228 229static void 230rc_registerdev(id) 231 struct isa_device *id; 232{ 233 int unit; 234 235 unit = id->id_unit; 236 if (unit != 0) 237 kdc_rc[unit] = kdc_rc[0]; 238 kdc_rc[unit].kdc_unit = unit; 239 kdc_rc[unit].kdc_isa = id; 240 kdc_rc[unit].kdc_state = DC_UNKNOWN; 241 dev_attach(&kdc_rc[unit]); 242} 243 244int rcattach(dvp) 245 struct isa_device *dvp; 246{ 247 register int i, chan, nec = dvp->id_iobase; 248 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 249 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 250 static int rc_wakeup_started = 0; 251 struct tty *tp; 252 253 /* Thorooughly test the device */ 254 if (rcb->rcb_probed != RC_PROBED) 255 return 0; 256 rcb->rcb_addr = nec; 257 rcb->rcb_dtr = 0; 258 rcb->rcb_baserc = rc; 259 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 260 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 261 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 262 263 rc_registerdev(dvp); 264 265 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 266 rc->rc_rcb = rcb; 267 rc->rc_chan = chan; 268 rc->rc_iptr = rc->rc_ibuf; 269 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 270 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 271 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 272 rc->rc_cor2 = rc->rc_pendcmd = 0; 273 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 274 rc->rc_dtrwait = 3 * hz; 275 rc->rc_dcdwaits= 0; 276 rc->rc_hotchar = 0; 277 tp = rc->rc_tp = &rc_tty[chan]; 278 ttychars(tp); 279 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 280 tp->t_cflag = TTYDEF_CFLAG; 281 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 282 } 283 rcb->rcb_probed = RC_ATTACHED; 284 if (!rc_wakeup_started) { 285 rc_wakeup((void *)NULL); 286 rc_wakeup_started = 0; 287 } 288 return 1; 289} 290 291/* RC interrupt handling */ 292void rcintr(unit) 293 int unit; 294{ 295 register struct rc_softc *rcb = &rc_softc[unit]; 296 register struct rc_chans *rc; 297 register int nec, resid; 298 register u_char val, iack, bsr, ucnt, *optr; 299 int good_data, t_state; 300 301 if (rcb->rcb_probed != RC_ATTACHED) { 302 printf("rc%d: bogus interrupt\n", unit); 303 return; 304 } 305 nec = rcb->rcb_addr; 306 307 bsr = ~(rcin(RC_BSR)); 308 309 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 310 printf("rc%d: extra interrupt\n", unit); 311 rcout(CD180_EOIR, 0); 312 return; 313 } 314 315 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 316#ifdef RCDEBUG_DETAILED 317 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 318 (bsr & RC_BSR_TOUT)?"TOUT ":"", 319 (bsr & RC_BSR_RXINT)?"RXINT ":"", 320 (bsr & RC_BSR_TXINT)?"TXINT ":"", 321 (bsr & RC_BSR_MOINT)?"MOINT":""); 322#endif 323 if (bsr & RC_BSR_TOUT) { 324 printf("rc%d: hardware failure, reset board\n", unit); 325 rcout(RC_CTOUT, 0); 326 rc_reinit(rcb); 327 return; 328 } 329 if (bsr & RC_BSR_RXINT) { 330 iack = rcin(RC_PILR_RX); 331 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 332 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 333 printf("rc%d: fake rxint: %02x\n", unit, iack); 334 goto more_intrs; 335 } 336 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 337 t_state = rc->rc_tp->t_state; 338 /* Do RTS flow control stuff */ 339 if ( (rc->rc_flags & RC_RTSFLOW) 340 || !(t_state & TS_ISOPEN) 341 ) { 342 if ( ( !(t_state & TS_ISOPEN) 343 || (t_state & TS_TBLOCK) 344 ) 345 && (rc->rc_msvr & MSVR_RTS) 346 ) 347 rcout(CD180_MSVR, 348 rc->rc_msvr &= ~MSVR_RTS); 349 else if (!(rc->rc_msvr & MSVR_RTS)) 350 rcout(CD180_MSVR, 351 rc->rc_msvr |= MSVR_RTS); 352 } 353 ucnt = rcin(CD180_RDCR) & 0xF; 354 resid = 0; 355 356 if (t_state & TS_ISOPEN) { 357 /* check for input buffer overflow */ 358 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 359 resid = ucnt; 360 ucnt = rc->rc_bufend - rc->rc_iptr; 361 resid -= ucnt; 362 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 363 rc->rc_flags |= RC_WAS_BUFOVFL; 364 rc_scheduled_event++; 365 } 366 } 367 optr = rc->rc_iptr; 368 /* check foor good data */ 369 if (good_data) { 370 while (ucnt-- > 0) { 371 val = rcin(CD180_RDR); 372 optr[0] = val; 373 optr[INPUT_FLAGS_SHIFT] = 0; 374 optr++; 375 rc_scheduled_event++; 376 if (val != 0 && val == rc->rc_hotchar) 377 setsofttty(); 378 } 379 } else { 380 /* Store also status data */ 381 while (ucnt-- > 0) { 382 iack = rcin(CD180_RCSR); 383 if (iack & RCSR_Timeout) 384 break; 385 if ( (iack & RCSR_OE) 386 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 387 rc->rc_flags |= RC_WAS_SILOVFL; 388 rc_scheduled_event++; 389 } 390 val = rcin(CD180_RDR); 391 /* 392 Don't store PE if IGNPAR and BREAK if IGNBRK, 393 this hack allows "raw" tty optimization 394 works even if IGN* is set. 395 */ 396 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 397 || (!(iack & (RCSR_PE|RCSR_FE)) 398 || !(rc->rc_tp->t_iflag & IGNPAR)) 399 && (!(iack & RCSR_Break) 400 || !(rc->rc_tp->t_iflag & IGNBRK))) { 401 if ( (iack & (RCSR_PE|RCSR_FE)) 402 && (t_state & TS_CAN_BYPASS_L_RINT) 403 && ((iack & RCSR_FE) 404 || (iack & RCSR_PE) 405 && (rc->rc_tp->t_iflag & INPCK))) 406 val = 0; 407 else if (val != 0 && val == rc->rc_hotchar) 408 setsofttty(); 409 optr[0] = val; 410 optr[INPUT_FLAGS_SHIFT] = iack; 411 optr++; 412 rc_scheduled_event++; 413 } 414 } 415 } 416 rc->rc_iptr = optr; 417 rc->rc_flags |= RC_DORXFER; 418 } else 419 resid = ucnt; 420 /* Clear FIFO if necessary */ 421 while (resid-- > 0) { 422 if (!good_data) 423 iack = rcin(CD180_RCSR); 424 else 425 iack = 0; 426 if (iack & RCSR_Timeout) 427 break; 428 (void) rcin(CD180_RDR); 429 } 430 goto more_intrs; 431 } 432 if (bsr & RC_BSR_MOINT) { 433 iack = rcin(RC_PILR_MODEM); 434 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 435 printf("rc%d: fake moint: %02x\n", unit, iack); 436 goto more_intrs; 437 } 438 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 439 iack = rcin(CD180_MCR); 440 rc->rc_msvr = rcin(CD180_MSVR); 441 rcout(CD180_MCR, 0); 442#ifdef RCDEBUG 443 printrcflags(rc, "moint"); 444#endif 445 if (rc->rc_flags & RC_CTSFLOW) { 446 if (rc->rc_msvr & MSVR_CTS) 447 rc->rc_flags |= RC_SEND_RDY; 448 else 449 rc->rc_flags &= ~RC_SEND_RDY; 450 } else 451 rc->rc_flags |= RC_SEND_RDY; 452 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 453 rc_scheduled_event += LOTS_OF_EVENTS; 454 rc->rc_flags |= RC_MODCHG; 455 setsofttty(); 456 } 457 goto more_intrs; 458 } 459 if (bsr & RC_BSR_TXINT) { 460 iack = rcin(RC_PILR_TX); 461 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 462 printf("rc%d: fake txint: %02x\n", unit, iack); 463 goto more_intrs; 464 } 465 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 466 if ( (rc->rc_flags & RC_OSUSP) 467 || !(rc->rc_flags & RC_SEND_RDY) 468 ) 469 goto more_intrs; 470 /* Handle breaks and other stuff */ 471 if (rc->rc_pendcmd) { 472 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 473 rcout(CD180_TDR, CD180_C_ESC); 474 rcout(CD180_TDR, rc->rc_pendcmd); 475 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 476 rc->rc_pendcmd = 0; 477 goto more_intrs; 478 } 479 optr = rc->rc_optr; 480 resid = rc->rc_obufend - optr; 481 if (resid > CD180_NFIFO) 482 resid = CD180_NFIFO; 483 while (resid-- > 0) 484 rcout(CD180_TDR, *optr++); 485 rc->rc_optr = optr; 486 487 /* output completed? */ 488 if (optr >= rc->rc_obufend) { 489 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 490#ifdef RCDEBUG 491 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 492#endif 493 if (!(rc->rc_flags & RC_DOXXFER)) { 494 rc_scheduled_event += LOTS_OF_EVENTS; 495 rc->rc_flags |= RC_DOXXFER; 496 setsofttty(); 497 } 498 } 499 } 500 more_intrs: 501 rcout(CD180_EOIR, 0); /* end of interrupt */ 502 rcout(RC_CTOUT, 0); 503 bsr = ~(rcin(RC_BSR)); 504 } 505} 506 507/* Feed characters to output buffer */ 508static void rc_start(tp) 509register struct tty *tp; 510{ 511 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 512 register int nec = rc->rc_rcb->rcb_addr, s; 513 514 if (rc->rc_flags & RC_OSBUSY) 515 return; 516 s = spltty(); 517 rc->rc_flags |= RC_OSBUSY; 518 disable_intr(); 519 if (tp->t_state & TS_TTSTOP) 520 rc->rc_flags |= RC_OSUSP; 521 else 522 rc->rc_flags &= ~RC_OSUSP; 523 /* Do RTS flow control stuff */ 524 if ( (rc->rc_flags & RC_RTSFLOW) 525 && (tp->t_state & TS_TBLOCK) 526 && (rc->rc_msvr & MSVR_RTS) 527 ) { 528 rcout(CD180_CAR, rc->rc_chan); 529 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 530 } else if (!(rc->rc_msvr & MSVR_RTS)) { 531 rcout(CD180_CAR, rc->rc_chan); 532 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 533 } 534 enable_intr(); 535 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 536 goto out; 537#ifdef RCDEBUG 538 printrcflags(rc, "rcstart"); 539#endif 540 ttwwakeup(tp); 541#ifdef RCDEBUG 542 printf("rcstart: outq = %d obuf = %d\n", 543 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 544#endif 545 if (tp->t_state & TS_BUSY) 546 goto out; /* output still in progress ... */ 547 548 if (tp->t_outq.c_cc > 0) { 549 u_int ocnt; 550 551 tp->t_state |= TS_BUSY; 552 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 553 disable_intr(); 554 rc->rc_optr = rc->rc_obuf; 555 rc->rc_obufend = rc->rc_optr + ocnt; 556 enable_intr(); 557 if (!(rc->rc_ier & IER_TxRdy)) { 558#ifdef RCDEBUG 559 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 560#endif 561 rcout(CD180_CAR, rc->rc_chan); 562 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 563 } 564 } 565out: 566 rc->rc_flags &= ~RC_OSBUSY; 567 (void) splx(s); 568} 569 570/* Handle delayed events. */ 571void rcpoll() 572{ 573 register struct rc_chans *rc; 574 register struct rc_softc *rcb; 575 register u_char *tptr, *eptr; 576 register int s; 577 register struct tty *tp; 578 register int chan, icnt, c, nec, unit; 579 580 if (rc_scheduled_event == 0) 581 return; 582repeat: 583 for (unit = 0; unit < NRC; unit++) { 584 rcb = &rc_softc[unit]; 585 rc = rcb->rcb_baserc; 586 nec = rc->rc_rcb->rcb_addr; 587 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 588 tp = rc->rc_tp; 589#ifdef RCDEBUG 590 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 591 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 592 printrcflags(rc, "rcevent"); 593#endif 594 if (rc->rc_flags & RC_WAS_BUFOVFL) { 595 disable_intr(); 596 rc->rc_flags &= ~RC_WAS_BUFOVFL; 597 rc_scheduled_event--; 598 enable_intr(); 599 printf("rc%d/%d: interrupt-level buffer overflow\n", 600 unit, chan); 601 } 602 if (rc->rc_flags & RC_WAS_SILOVFL) { 603 disable_intr(); 604 rc->rc_flags &= ~RC_WAS_SILOVFL; 605 rc_scheduled_event--; 606 enable_intr(); 607 printf("rc%d/%d: silo overflow\n", 608 unit, chan); 609 } 610 if (rc->rc_flags & RC_MODCHG) { 611 disable_intr(); 612 rc->rc_flags &= ~RC_MODCHG; 613 rc_scheduled_event -= LOTS_OF_EVENTS; 614 enable_intr(); 615 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 616 } 617 if (rc->rc_flags & RC_DORXFER) { 618 disable_intr(); 619 rc->rc_flags &= ~RC_DORXFER; 620 eptr = rc->rc_iptr; 621 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 622 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 623 else 624 tptr = rc->rc_ibuf; 625 icnt = eptr - tptr; 626 if (icnt > 0) { 627 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 628 rc->rc_iptr = rc->rc_ibuf; 629 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 630 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 631 } else { 632 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 633 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 634 rc->rc_hiwat = 635 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 636 } 637 if ( (rc->rc_flags & RC_RTSFLOW) 638 && (tp->t_state & TS_ISOPEN) 639 && !(tp->t_state & TS_TBLOCK) 640 && !(rc->rc_msvr & MSVR_RTS) 641 ) { 642 rcout(CD180_CAR, chan); 643 rcout(CD180_MSVR, 644 rc->rc_msvr |= MSVR_RTS); 645 } 646 rc_scheduled_event -= icnt; 647 } 648 enable_intr(); 649 650 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 651 goto done1; 652 653 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 654 && !(tp->t_state & TS_LOCAL)) { 655 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 656 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 657 && !(tp->t_state & TS_TBLOCK)) 658 ttyblock(tp); 659 tk_nin += icnt; 660 tk_rawcc += icnt; 661 tp->t_rawcc += icnt; 662 if (b_to_q(tptr, icnt, &tp->t_rawq)) 663 printf("rc%d/%d: tty-level buffer overflow\n", 664 unit, chan); 665 ttwakeup(tp); 666 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 667 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 668 tp->t_state &= ~TS_TTSTOP; 669 tp->t_lflag &= ~FLUSHO; 670 rc_start(tp); 671 } 672 } else { 673 for (; tptr < eptr; tptr++) 674 (*linesw[tp->t_line].l_rint) 675 (tptr[0] | 676 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 677 } 678done1: 679 } 680 if (rc->rc_flags & RC_DOXXFER) { 681 disable_intr(); 682 rc_scheduled_event -= LOTS_OF_EVENTS; 683 rc->rc_flags &= ~RC_DOXXFER; 684 rc->rc_tp->t_state &= ~TS_BUSY; 685 enable_intr(); 686 (*linesw[tp->t_line].l_start)(tp); 687 } 688 } 689 if (rc_scheduled_event == 0) 690 break; 691 } 692 if (rc_scheduled_event >= LOTS_OF_EVENTS) 693 goto repeat; 694} 695 696void rcstop(tp, rw) 697 register struct tty *tp; 698 int rw; 699{ 700 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 701 u_char *tptr, *eptr; 702 703#ifdef RCDEBUG 704 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 705 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 706#endif 707 if (rw & FWRITE) 708 rc_discard_output(rc); 709 disable_intr(); 710 if (rw & FREAD) { 711 rc->rc_flags &= ~RC_DORXFER; 712 eptr = rc->rc_iptr; 713 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 714 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 715 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 716 } else { 717 tptr = rc->rc_ibuf; 718 rc->rc_iptr = rc->rc_ibuf; 719 } 720 rc_scheduled_event -= eptr - tptr; 721 } 722 if (tp->t_state & TS_TTSTOP) 723 rc->rc_flags |= RC_OSUSP; 724 else 725 rc->rc_flags &= ~RC_OSUSP; 726 enable_intr(); 727} 728 729int rcopen(dev, flag, mode, p) 730 dev_t dev; 731 int flag, mode; 732 struct proc *p; 733{ 734 register struct rc_chans *rc; 735 register struct tty *tp; 736 int unit, nec, s, error = 0; 737 738 unit = GET_UNIT(dev); 739 if (unit >= NRC * CD180_NCHAN) 740 return ENXIO; 741 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 742 return ENXIO; 743 rc = &rc_chans[unit]; 744 tp = rc->rc_tp; 745 nec = rc->rc_rcb->rcb_addr; 746#ifdef RCDEBUG 747 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 748#endif 749 s = spltty(); 750 751again: 752 while (rc->rc_flags & RC_DTR_OFF) { 753 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 754 if (error != 0) 755 goto out; 756 } 757 if (tp->t_state & TS_ISOPEN) { 758 if (CALLOUT(dev)) { 759 if (!(rc->rc_flags & RC_ACTOUT)) { 760 error = EBUSY; 761 goto out; 762 } 763 } else { 764 if (rc->rc_flags & RC_ACTOUT) { 765 if (flag & O_NONBLOCK) { 766 error = EBUSY; 767 goto out; 768 } 769 if (error = tsleep(&rc->rc_rcb, 770 TTIPRI|PCATCH, "rcbi", 0)) 771 goto out; 772 goto again; 773 } 774 } 775 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 776 error = EBUSY; 777 goto out; 778 } 779 } else { 780 tp->t_oproc = rc_start; 781 tp->t_param = rc_param; 782 tp->t_dev = dev; 783 784 if (CALLOUT(dev)) 785 tp->t_cflag |= CLOCAL; 786 else 787 tp->t_cflag &= ~CLOCAL; 788 789 error = rc_param(tp, &tp->t_termios); 790 if (error) 791 goto out; 792 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 793 794 ttsetwater(tp); 795 796 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 797 (*linesw[tp->t_line].l_modem)(tp, 1); 798 } 799 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 800 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 801 rc->rc_dcdwaits++; 802 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 803 rc->rc_dcdwaits--; 804 if (error != 0) 805 goto out; 806 goto again; 807 } 808 error = (*linesw[tp->t_line].l_open)(dev, tp); 809 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 810 rc->rc_flags |= RC_ACTOUT; 811out: 812 (void) splx(s); 813 814 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 815 rc_hardclose(rc); 816 817 return error; 818} 819 820int rcclose(dev, flag, mode, p) 821 dev_t dev; 822 int flag, mode; 823 struct proc *p; 824{ 825 register struct rc_chans *rc; 826 register struct tty *tp; 827 int s, unit = GET_UNIT(dev); 828 829 if (unit >= NRC * CD180_NCHAN) 830 return ENXIO; 831 rc = &rc_chans[unit]; 832 tp = rc->rc_tp; 833#ifdef RCDEBUG 834 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 835#endif 836 s = spltty(); 837 (*linesw[tp->t_line].l_close)(tp, flag); 838 rcstop(tp, FREAD | FWRITE); 839 rc_hardclose(rc); 840 ttyclose(tp); 841 splx(s); 842 return 0; 843} 844 845static void rc_hardclose(rc) 846register struct rc_chans *rc; 847{ 848 register int s, nec = rc->rc_rcb->rcb_addr; 849 register struct tty *tp = rc->rc_tp; 850 851 s = spltty(); 852 rcout(CD180_CAR, rc->rc_chan); 853 854 /* Disable rx/tx intrs */ 855 rcout(CD180_IER, rc->rc_ier = 0); 856 if ( (tp->t_cflag & HUPCL) 857 || !(rc->rc_flags & RC_ACTOUT) 858 && !(rc->rc_msvr & MSVR_CD) 859 && !(tp->t_cflag & CLOCAL) 860 || !(tp->t_state & TS_ISOPEN) 861 ) { 862 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 863 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 864 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 865 if (rc->rc_dtrwait) { 866 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 867 rc->rc_flags |= RC_DTR_OFF; 868 } 869 } 870 rc->rc_flags &= ~RC_ACTOUT; 871 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 872 wakeup(TSA_CARR_ON(tp)); 873 (void) splx(s); 874} 875 876/* Read from line */ 877int rcread(dev, uio, flag) 878 dev_t dev; 879 struct uio *uio; 880 int flag; 881{ 882 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 883 884 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 885} 886 887/* Write to line */ 888int rcwrite(dev, uio, flag) 889 dev_t dev; 890 struct uio *uio; 891 int flag; 892{ 893 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 894 895 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 896} 897 898/* Reset the bastard */ 899static void rc_hwreset(unit, nec, chipid) 900 register int unit, nec; 901 unsigned int chipid; 902{ 903 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 904 DELAY(20000); 905 WAITFORCCR(unit, -1); 906 907 rcout(RC_CTOUT, 0); /* Clear timeout */ 908 rcout(CD180_GIVR, chipid); 909 rcout(CD180_GICR, 0); 910 911 /* Set Prescaler Registers (1 msec) */ 912 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 913 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 914 915 /* Initialize Priority Interrupt Level Registers */ 916 rcout(CD180_PILR1, RC_PILR_MODEM); 917 rcout(CD180_PILR2, RC_PILR_TX); 918 rcout(CD180_PILR3, RC_PILR_RX); 919 920 /* Reset DTR */ 921 rcout(RC_DTREG, ~0); 922} 923 924/* Set channel parameters */ 925static int rc_param(tp, ts) 926 register struct tty *tp; 927 struct termios *ts; 928{ 929 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 930 register int nec = rc->rc_rcb->rcb_addr; 931 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 932 933 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 934 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 935 ) 936 return (EINVAL); 937 if (ts->c_ispeed == 0) 938 ts->c_ispeed = ts->c_ospeed; 939 odivs = RC_BRD(ts->c_ospeed); 940 idivs = RC_BRD(ts->c_ispeed); 941 942 s = spltty(); 943 944 /* Select channel */ 945 rcout(CD180_CAR, rc->rc_chan); 946 947 /* If speed == 0, hangup line */ 948 if (ts->c_ospeed == 0) { 949 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 950 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 951 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 952 } 953 954 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 955 cflag = ts->c_cflag; 956 iflag = ts->c_iflag; 957 lflag = ts->c_lflag; 958 959 if (idivs > 0) { 960 rcout(CD180_RBPRL, idivs & 0xFF); 961 rcout(CD180_RBPRH, idivs >> 8); 962 } 963 if (odivs > 0) { 964 rcout(CD180_TBPRL, odivs & 0xFF); 965 rcout(CD180_TBPRH, odivs >> 8); 966 } 967 968 /* set timeout value */ 969 if (ts->c_ispeed > 0) { 970 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 971 972 if ( !(lflag & ICANON) 973 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 974 && ts->c_cc[VTIME] * 10 > itm) 975 itm = ts->c_cc[VTIME] * 10; 976 977 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 978 } 979 980 switch (cflag & CSIZE) { 981 case CS5: val = COR1_5BITS; break; 982 case CS6: val = COR1_6BITS; break; 983 case CS7: val = COR1_7BITS; break; 984 default: 985 case CS8: val = COR1_8BITS; break; 986 } 987 if (cflag & PARENB) { 988 val |= COR1_NORMPAR; 989 if (cflag & PARODD) 990 val |= COR1_ODDP; 991 if (!(cflag & INPCK)) 992 val |= COR1_Ignore; 993 } else 994 val |= COR1_Ignore; 995 if (cflag & CSTOPB) 996 val |= COR1_2SB; 997 rcout(CD180_COR1, val); 998 999 /* Set FIFO threshold */ 1000 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1001 inpflow = 0; 1002 if ( (iflag & IXOFF) 1003 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1004 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1005 || (iflag & IXANY) 1006 ) 1007 ) 1008 ) { 1009 inpflow = 1; 1010 val |= COR3_SCDE|COR3_FCT; 1011 } 1012 rcout(CD180_COR3, val); 1013 1014 /* Initialize on-chip automatic flow control */ 1015 val = 0; 1016 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1017 if (cflag & CCTS_OFLOW) { 1018 rc->rc_flags |= RC_CTSFLOW; 1019 val |= COR2_CtsAE; 1020 } else 1021 rc->rc_flags |= RC_SEND_RDY; 1022 if (tp->t_state & TS_TTSTOP) 1023 rc->rc_flags |= RC_OSUSP; 1024 else 1025 rc->rc_flags &= ~RC_OSUSP; 1026 if (cflag & CRTS_IFLOW) 1027 rc->rc_flags |= RC_RTSFLOW; 1028 else 1029 rc->rc_flags &= ~RC_RTSFLOW; 1030 1031 if (inpflow) { 1032 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1033 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1034 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1035 val |= COR2_TxIBE; 1036 if (iflag & IXANY) 1037 val |= COR2_IXM; 1038 } 1039 1040 rcout(CD180_COR2, rc->rc_cor2 = val); 1041 1042 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1043 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1044 1045 disc_optim(tp, ts, rc); 1046 1047 /* modem ctl */ 1048 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1049 if (cflag & CCTS_OFLOW) 1050 val |= MCOR1_CTSzd; 1051 rcout(CD180_MCOR1, val); 1052 1053 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1054 if (cflag & CCTS_OFLOW) 1055 val |= MCOR2_CTSod; 1056 rcout(CD180_MCOR2, val); 1057 1058 /* enable i/o and interrupts */ 1059 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1060 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1061 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1062 1063 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1064 if (cflag & CCTS_OFLOW) 1065 rc->rc_ier |= IER_CTS; 1066 if (cflag & CREAD) 1067 rc->rc_ier |= IER_RxData; 1068 if (tp->t_state & TS_BUSY) 1069 rc->rc_ier |= IER_TxRdy; 1070 if (ts->c_ospeed != 0) 1071 rc_modctl(rc, TIOCM_DTR, DMBIS); 1072 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1073 rc->rc_flags |= RC_SEND_RDY; 1074 rcout(CD180_IER, rc->rc_ier); 1075 (void) splx(s); 1076 return 0; 1077} 1078 1079/* Re-initialize board after bogus interrupts */ 1080static void rc_reinit(rcb) 1081struct rc_softc *rcb; 1082{ 1083 register struct rc_chans *rc, *rce; 1084 register int i, nec; 1085 1086 nec = rcb->rcb_addr; 1087 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1088 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1089 rce = rc + CD180_NCHAN; 1090 for (; rc < rce; rc++) 1091 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1092} 1093 1094int rcioctl(dev, cmd, data, flag, p) 1095dev_t dev; 1096int cmd, flag; 1097caddr_t data; 1098struct proc *p; 1099{ 1100 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1101 register int s, error; 1102 struct tty *tp = rc->rc_tp; 1103 1104 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1105 if (error >= 0) 1106 return (error); 1107 error = ttioctl(tp, cmd, data, flag); 1108 if (error >= 0) 1109 return (error); 1110 s = spltty(); 1111 1112 switch (cmd) { 1113 case TIOCSBRK: 1114 rc->rc_pendcmd = CD180_C_SBRK; 1115 break; 1116 1117 case TIOCCBRK: 1118 rc->rc_pendcmd = CD180_C_EBRK; 1119 break; 1120 1121 case TIOCSDTR: 1122 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1123 break; 1124 1125 case TIOCCDTR: 1126 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1127 break; 1128 1129 case TIOCMGET: 1130 *(int *) data = rc_modctl(rc, 0, DMGET); 1131 break; 1132 1133 case TIOCMSET: 1134 (void) rc_modctl(rc, *(int *) data, DMSET); 1135 break; 1136 1137 case TIOCMBIC: 1138 (void) rc_modctl(rc, *(int *) data, DMBIC); 1139 break; 1140 1141 case TIOCMBIS: 1142 (void) rc_modctl(rc, *(int *) data, DMBIS); 1143 break; 1144 1145 case TIOCMSDTRWAIT: 1146 error = suser(p->p_ucred, &p->p_acflag); 1147 if (error != 0) { 1148 splx(s); 1149 return (error); 1150 } 1151 rc->rc_dtrwait = *(int *)data * hz / 100; 1152 break; 1153 1154 case TIOCMGDTRWAIT: 1155 *(int *)data = rc->rc_dtrwait * 100 / hz; 1156 break; 1157 1158 default: 1159 (void) splx(s); 1160 return ENOTTY; 1161 } 1162 (void) splx(s); 1163 return 0; 1164} 1165 1166 1167/* Modem control routines */ 1168 1169static int rc_modctl(rc, bits, cmd) 1170register struct rc_chans *rc; 1171int bits, cmd; 1172{ 1173 register int nec = rc->rc_rcb->rcb_addr; 1174 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1175 1176 rcout(CD180_CAR, rc->rc_chan); 1177 1178 switch (cmd) { 1179 case DMSET: 1180 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1181 ~(*dtr |= 1 << rc->rc_chan) : 1182 ~(*dtr &= ~(1 << rc->rc_chan))); 1183 msvr = rcin(CD180_MSVR); 1184 if (bits & TIOCM_RTS) 1185 msvr |= MSVR_RTS; 1186 else 1187 msvr &= ~MSVR_RTS; 1188 if (bits & TIOCM_DTR) 1189 msvr |= MSVR_DTR; 1190 else 1191 msvr &= ~MSVR_DTR; 1192 rcout(CD180_MSVR, msvr); 1193 break; 1194 1195 case DMBIS: 1196 if (bits & TIOCM_DTR) 1197 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1198 msvr = rcin(CD180_MSVR); 1199 if (bits & TIOCM_RTS) 1200 msvr |= MSVR_RTS; 1201 if (bits & TIOCM_DTR) 1202 msvr |= MSVR_DTR; 1203 rcout(CD180_MSVR, msvr); 1204 break; 1205 1206 case DMGET: 1207 bits = TIOCM_LE; 1208 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1209 1210 if (msvr & MSVR_RTS) 1211 bits |= TIOCM_RTS; 1212 if (msvr & MSVR_CTS) 1213 bits |= TIOCM_CTS; 1214 if (msvr & MSVR_DSR) 1215 bits |= TIOCM_DSR; 1216 if (msvr & MSVR_DTR) 1217 bits |= TIOCM_DTR; 1218 if (msvr & MSVR_CD) 1219 bits |= TIOCM_CD; 1220 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1221 bits |= TIOCM_RI; 1222 return bits; 1223 1224 case DMBIC: 1225 if (bits & TIOCM_DTR) 1226 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1227 msvr = rcin(CD180_MSVR); 1228 if (bits & TIOCM_RTS) 1229 msvr &= ~MSVR_RTS; 1230 if (bits & TIOCM_DTR) 1231 msvr &= ~MSVR_DTR; 1232 rcout(CD180_MSVR, msvr); 1233 break; 1234 } 1235 rc->rc_msvr = rcin(CD180_MSVR); 1236 return 0; 1237} 1238 1239/* Test the board. */ 1240int rc_test(nec, unit) 1241 register int nec; 1242 int unit; 1243{ 1244 int chan = 0, nopt = 0; 1245 int i = 0, rcnt, old_level; 1246 unsigned int iack, chipid; 1247 unsigned short divs; 1248 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1249#define CTLEN 8 1250#define ERR(s) { \ 1251 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1252 (void) splx(old_level); return 1; } 1253 1254 struct rtest { 1255 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1256 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1257 int rxptr; /* RX pointer */ 1258 int txptr; /* TX pointer */ 1259 } tchans[CD180_NCHAN]; 1260 1261 old_level = spltty(); 1262 1263 chipid = RC_FAKEID; 1264 1265 /* First, reset board to inital state */ 1266 rc_hwreset(unit, nec, chipid); 1267 1268 divs = RC_BRD(19200); 1269 1270 /* Initialize channels */ 1271 for (chan = 0; chan < CD180_NCHAN; chan++) { 1272 1273 /* Select and reset channel */ 1274 rcout(CD180_CAR, chan); 1275 CCRCMD(unit, chan, CCR_ResetChan); 1276 WAITFORCCR(unit, chan); 1277 1278 /* Set speed */ 1279 rcout(CD180_RBPRL, divs & 0xFF); 1280 rcout(CD180_RBPRH, divs >> 8); 1281 rcout(CD180_TBPRL, divs & 0xFF); 1282 rcout(CD180_TBPRH, divs >> 8); 1283 1284 /* set timeout value */ 1285 rcout(CD180_RTPR, 0); 1286 1287 /* Establish local loopback */ 1288 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1289 rcout(CD180_COR2, COR2_LLM); 1290 rcout(CD180_COR3, CD180_NFIFO); 1291 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1292 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1293 WAITFORCCR(unit, chan); 1294 rcout(CD180_MSVR, MSVR_RTS); 1295 1296 /* Fill TXBUF with test data */ 1297 for (i = 0; i < CD180_NFIFO; i++) { 1298 tchans[chan].txbuf[i] = ctest[i]; 1299 tchans[chan].rxbuf[i] = 0; 1300 } 1301 tchans[chan].txptr = tchans[chan].rxptr = 0; 1302 1303 /* Now, start transmit */ 1304 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1305 } 1306 /* Pseudo-interrupt poll stuff */ 1307 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1308 i = ~(rcin(RC_BSR)); 1309 if (i & RC_BSR_TOUT) 1310 ERR(("BSR timeout bit set\n")) 1311 else if (i & RC_BSR_TXINT) { 1312 iack = rcin(RC_PILR_TX); 1313 if (iack != (GIVR_IT_TDI | chipid)) 1314 ERR(("Bad TX intr ack (%02x != %02x)\n", 1315 iack, GIVR_IT_TDI | chipid)); 1316 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1317 /* If no more data to transmit, disable TX intr */ 1318 if (tchans[chan].txptr >= CD180_NFIFO) { 1319 iack = rcin(CD180_IER); 1320 rcout(CD180_IER, iack & ~IER_TxMpty); 1321 } else { 1322 for (iack = tchans[chan].txptr; 1323 iack < CD180_NFIFO; iack++) 1324 rcout(CD180_TDR, 1325 tchans[chan].txbuf[iack]); 1326 tchans[chan].txptr = iack; 1327 } 1328 rcout(CD180_EOIR, 0); 1329 } else if (i & RC_BSR_RXINT) { 1330 u_char ucnt; 1331 1332 iack = rcin(RC_PILR_RX); 1333 if (iack != (GIVR_IT_RGDI | chipid) && 1334 iack != (GIVR_IT_REI | chipid)) 1335 ERR(("Bad RX intr ack (%02x != %02x)\n", 1336 iack, GIVR_IT_RGDI | chipid)) 1337 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1338 ucnt = rcin(CD180_RDCR) & 0xF; 1339 while (ucnt-- > 0) { 1340 iack = rcin(CD180_RCSR); 1341 if (iack & RCSR_Timeout) 1342 break; 1343 if (iack & 0xF) 1344 ERR(("Bad char chan %d (RCSR = %02X)\n", 1345 chan, iack)) 1346 if (tchans[chan].rxptr > CD180_NFIFO) 1347 ERR(("Got extra chars chan %d\n", 1348 chan)) 1349 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1350 rcin(CD180_RDR); 1351 } 1352 rcout(CD180_EOIR, 0); 1353 } 1354 rcout(RC_CTOUT, 0); 1355 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1356 if (tchans[chan].rxptr >= CD180_NFIFO) 1357 iack++; 1358 if (iack == CD180_NCHAN) 1359 break; 1360 } 1361 for (chan = 0; chan < CD180_NCHAN; chan++) { 1362 /* Select and reset channel */ 1363 rcout(CD180_CAR, chan); 1364 CCRCMD(unit, chan, CCR_ResetChan); 1365 } 1366 1367 if (!rcnt) 1368 ERR(("looses characters during local loopback\n")) 1369 /* Now, check data */ 1370 for (chan = 0; chan < CD180_NCHAN; chan++) 1371 for (i = 0; i < CD180_NFIFO; i++) 1372 if (ctest[i] != tchans[chan].rxbuf[i]) 1373 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1374 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1375 (void) splx(old_level); 1376 return 0; 1377} 1378 1379#ifdef RCDEBUG 1380static void printrcflags(rc, comment) 1381struct rc_chans *rc; 1382char *comment; 1383{ 1384 u_short f = rc->rc_flags; 1385 register int nec = rc->rc_rcb->rcb_addr; 1386 1387 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1388 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1389 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1390 (f & RC_ACTOUT) ?"ACTOUT " :"", 1391 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1392 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1393 (f & RC_DORXFER)?"DORXFER " :"", 1394 (f & RC_DOXXFER)?"DOXXFER " :"", 1395 (f & RC_MODCHG) ?"MODCHG " :"", 1396 (f & RC_OSUSP) ?"OSUSP " :"", 1397 (f & RC_OSBUSY) ?"OSBUSY " :"", 1398 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1399 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1400 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1401 1402 rcout(CD180_CAR, rc->rc_chan); 1403 1404 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1405 rc->rc_rcb->rcb_unit, rc->rc_chan, 1406 rcin(CD180_MSVR), 1407 rcin(CD180_IER), 1408 rcin(CD180_CCSR)); 1409} 1410#endif /* RCDEBUG */ 1411 1412struct tty * 1413rcdevtotty(dev) 1414 dev_t dev; 1415{ 1416 int unit; 1417 1418 unit = GET_UNIT(dev); 1419 if (unit >= NRC * CD180_NCHAN) 1420 return NULL; 1421 return (&rc_tty[unit]); 1422} 1423 1424static void 1425rc_dtrwakeup(chan) 1426 void *chan; 1427{ 1428 struct rc_chans *rc; 1429 1430 rc = (struct rc_chans *)chan; 1431 rc->rc_flags &= ~RC_DTR_OFF; 1432 wakeup(&rc->rc_dtrwait); 1433} 1434 1435static void 1436rc_discard_output(rc) 1437 struct rc_chans *rc; 1438{ 1439 disable_intr(); 1440 if (rc->rc_flags & RC_DOXXFER) { 1441 rc_scheduled_event -= LOTS_OF_EVENTS; 1442 rc->rc_flags &= ~RC_DOXXFER; 1443 } 1444 rc->rc_optr = rc->rc_obufend; 1445 rc->rc_tp->t_state &= ~TS_BUSY; 1446 enable_intr(); 1447 ttwwakeup(rc->rc_tp); 1448} 1449 1450static void 1451rc_wakeup(chan) 1452 void *chan; 1453{ 1454 int unit; 1455 1456 timeout(rc_wakeup, (caddr_t)NULL, 1); 1457 1458 if (rc_scheduled_event != 0) { 1459 int s; 1460 1461 s = splsofttty(); 1462 rcpoll(); 1463 splx(s); 1464 } 1465} 1466 1467static void 1468disc_optim(tp, t, rc) 1469 struct tty *tp; 1470 struct termios *t; 1471 struct rc_chans *rc; 1472{ 1473 1474 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1475 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1476 && (!(t->c_iflag & PARMRK) 1477 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1478 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1479 && linesw[tp->t_line].l_rint == ttyinput) 1480 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1481 else 1482 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1483 if (tp->t_line == SLIPDISC) 1484 rc->rc_hotchar = 0xc0; 1485 else if (tp->t_line == PPPDISC) 1486 rc->rc_hotchar = 0x7e; 1487 else 1488 rc->rc_hotchar = 0; 1489} 1490 1491static void 1492rc_wait0(nec, unit, chan, line) 1493 int nec, unit, chan, line; 1494{ 1495 int rcnt; 1496 1497 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 1498 DELAY(15); 1499 if (rcnt == 0) 1500 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1501 unit, chan, line); 1502} 1503 1504#ifdef JREMOD 1505struct cdevsw rc_cdevsw = 1506 { rcopen, rcclose, rcread, rcwrite, /*63*/ 1507 rcioctl, rcstop, nxreset, rcdevtotty,/* rc */ 1508 ttselect, nommap, NULL }; 1509 1510static rc_devsw_installed = 0; 1511 1512static void rc_drvinit(void *unused) 1513{ 1514 dev_t dev; 1515 1516 if( ! rc_devsw_installed ) { 1517 dev = makedev(CDEV_MAJOR,0); 1518 cdevsw_add(&dev,&rc_cdevsw,NULL); 1519 rc_devsw_installed = 1; 1520#ifdef DEVFS 1521 { 1522 int x; 1523/* default for a simple device with no probe routine (usually delete this) */ 1524 x=devfs_add_devsw( 1525/* path name devsw minor type uid gid perm*/ 1526 "/", "rc", major(dev), 0, DV_CHR, 0, 0, 0600); 1527 } 1528#endif 1529 } 1530} 1531 1532SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1533 1534#endif /* JREMOD */ 1535 1536#endif /* NRC */ 1537