rc.c revision 126078
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/rc/rc.c 126078 2004-02-21 20:41:11Z phk $ 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36/*#define RCDEBUG*/ 37 38#include "opt_tty.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/conf.h> 44#include <sys/fcntl.h> 45#include <sys/interrupt.h> 46#include <sys/kernel.h> 47#include <sys/malloc.h> 48#include <sys/tty.h> 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <dev/ic/cd180.h> 54#include <dev/rc/rcreg.h> 55#include <isa/isavar.h> 56 57#define IOBASE_ADDRS 14 58 59#define DEV_TO_RC(dev) (struct rc_chans *)((dev)->si_drv1) 60#define TTY_TO_RC(tty) DEV_TO_RC((tty)->t_dev) 61 62#define rcin(sc, port) RC_IN(sc, port) 63#define rcout(sc, port, v) RC_OUT(sc, port, v) 64 65#define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__) 66 67#define CCRCMD(sc, chan, cmd) do { \ 68 WAITFORCCR((sc), (chan)); \ 69 rcout((sc), CD180_CCR, (cmd)); \ 70} while (0) 71 72#define RC_IBUFSIZE 256 73#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 74#define RC_OBUFSIZE 512 75#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 76#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 77#define LOTS_OF_EVENTS 64 78 79#define RC_FAKEID 0x10 80 81#define CALLOUT(dev) (((intptr_t)(dev)->si_drv2) != 0) 82 83/* Per-channel structure */ 84struct rc_chans { 85 struct rc_softc *rc_rcb; /* back ptr */ 86 dev_t rc_dev; /* non-callout device */ 87 dev_t rc_cdev; /* callout device */ 88 u_short rc_flags; /* Misc. flags */ 89 int rc_chan; /* Channel # */ 90 u_char rc_ier; /* intr. enable reg */ 91 u_char rc_msvr; /* modem sig. status */ 92 u_char rc_cor2; /* options reg */ 93 u_char rc_pendcmd; /* special cmd pending */ 94 u_int rc_dtrwait; /* dtr timeout */ 95 u_int rc_dcdwaits; /* how many waits DCD in open */ 96 u_char rc_hotchar; /* end packed optimize */ 97 struct tty rc_tp; /* tty struct */ 98 u_char *rc_iptr; /* Chars input buffer */ 99 u_char *rc_hiwat; /* hi-water mark */ 100 u_char *rc_bufend; /* end of buffer */ 101 u_char *rc_optr; /* ptr in output buf */ 102 u_char *rc_obufend; /* end of output buf */ 103 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 104 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 105 struct callout rc_dtrcallout; 106}; 107 108/* Per-board structure */ 109struct rc_softc { 110 device_t sc_dev; 111 struct resource *sc_irq; 112 struct resource *sc_port[IOBASE_ADDRS]; 113 int sc_irqrid; 114 void *sc_hwicookie; 115 bus_space_tag_t sc_bt; 116 bus_space_handle_t sc_bh; 117 u_int sc_unit; /* unit # */ 118 u_char sc_dtr; /* DTR status */ 119 int sc_opencount; 120 int sc_scheduled_event; 121 void *sc_swicookie; 122 struct rc_chans sc_channels[CD180_NCHAN]; /* channels */ 123}; 124 125/* Static prototypes */ 126static void rc_release_resources(device_t dev); 127static void rc_intr(void *); 128static void rc_hwreset(struct rc_softc *, unsigned int); 129static int rc_test(struct rc_softc *); 130static void rc_discard_output(struct rc_chans *); 131static void rc_hardclose(struct rc_chans *); 132static int rc_modctl(struct rc_chans *, int, int); 133static void rc_start(struct tty *); 134static void rc_stop(struct tty *, int rw); 135static int rc_param(struct tty *, struct termios *); 136static void rc_pollcard(void *); 137static void rc_reinit(struct rc_softc *); 138#ifdef RCDEBUG 139static void printrcflags(); 140#endif 141static void rc_dtrwakeup(void *); 142static void disc_optim(struct tty *tp, struct termios *t, struct rc_chans *); 143static void rc_wait0(struct rc_softc *sc, int chan, int line); 144 145static d_open_t rcopen; 146static d_close_t rcclose; 147static d_ioctl_t rcioctl; 148 149static struct cdevsw rc_cdevsw = { 150 .d_open = rcopen, 151 .d_close = rcclose, 152 .d_ioctl = rcioctl, 153 .d_name = "rc", 154 .d_flags = D_TTY, 155}; 156 157static devclass_t rc_devclass; 158 159/* Flags */ 160#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 161#define RC_ACTOUT 0x0002 /* Dial-out port active */ 162#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 163#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 164#define RC_DORXFER 0x0010 /* RXFER event planned */ 165#define RC_DOXXFER 0x0020 /* XXFER event planned */ 166#define RC_MODCHG 0x0040 /* Modem status changed */ 167#define RC_OSUSP 0x0080 /* Output suspended */ 168#define RC_OSBUSY 0x0100 /* start() routine in progress */ 169#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 170#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 171#define RC_SEND_RDY 0x0800 /* ready to send */ 172 173/* Table for translation of RCSR status bits to internal form */ 174static int rc_rcsrt[16] = { 175 0, TTY_OE, TTY_FE, 176 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 177 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 178 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 179 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 180 TTY_BI|TTY_PE|TTY_FE|TTY_OE 181}; 182 183static int rc_ports[] = 184 { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 }; 185static int iobase_addrs[IOBASE_ADDRS] = 186 { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000, 187 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 }; 188 189/**********************************************/ 190 191static int 192rc_probe(device_t dev) 193{ 194 u_int port; 195 int i, found; 196 197 /* 198 * We don't know of any PnP ID's for these cards. 199 */ 200 if (isa_get_logicalid(dev) != 0) 201 return (ENXIO); 202 203 /* 204 * We have to have an IO port hint that is valid. 205 */ 206 port = isa_get_port(dev); 207 if (port == -1) 208 return (ENXIO); 209 found = 0; 210 for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++) 211 if (rc_ports[i] == port) { 212 found = 1; 213 break; 214 } 215 if (!found) 216 return (ENXIO); 217 218 /* 219 * We have to have an IRQ hint. 220 */ 221 if (isa_get_irq(dev) == -1) 222 return (ENXIO); 223 224 device_set_desc(dev, "SDL Riscom/8"); 225 return (0); 226} 227 228static int 229rc_attach(device_t dev) 230{ 231 struct rc_chans *rc; 232 struct tty *tp; 233 struct rc_softc *sc; 234 u_int port; 235 int base, chan, error, i, x; 236 dev_t cdev; 237 238 sc = device_get_softc(dev); 239 sc->sc_dev = dev; 240 241 /* 242 * We need to have IO ports. Lots of them. We need 243 * the following ranges relative to the base port: 244 * 0x0 - 0x10 245 * 0x400 - 0x410 246 * 0x800 - 0x810 247 * 0xc00 - 0xc10 248 * 0x1400 - 0x1410 249 * 0x1800 - 0x1810 250 * 0x1c00 - 0x1c10 251 * 0x2000 - 0x2010 252 * 0x3000 - 0x3010 253 * 0x3400 - 0x3410 254 * 0x3800 - 0x3810 255 * 0x3c00 - 0x3c10 256 * 0x4000 - 0x4010 257 * 0x8000 - 0x8010 258 */ 259 port = isa_get_port(dev); 260 for (i = 0; i < IOBASE_ADDRS; i++) 261 if (bus_set_resource(dev, SYS_RES_IOPORT, i, 262 port + iobase_addrs[i], 0x10) != 0) 263 return (ENXIO); 264 error = ENOMEM; 265 for (i = 0; i < IOBASE_ADDRS; i++) { 266 x = i; 267 sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x, 268 0ul, ~0ul, 0x10, RF_ACTIVE); 269 if (x != i) { 270 device_printf(dev, "ioport %d was rid %d\n", i, x); 271 goto fail; 272 } 273 if (sc->sc_port[i] == NULL) { 274 device_printf(dev, "failed to alloc ioports %x-%x\n", 275 port + iobase_addrs[i], 276 port + iobase_addrs[i] + 0x10); 277 goto fail; 278 } 279 } 280 sc->sc_bt = rman_get_bustag(sc->sc_port[0]); 281 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]); 282 283 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irqrid, 284 0ul, ~0ul, 1, RF_ACTIVE); 285 if (sc->sc_irq == NULL) { 286 device_printf(dev, "failed to alloc IRQ\n"); 287 goto fail; 288 } 289 290 /* 291 * Now do some actual tests to make sure it works. 292 */ 293 error = ENXIO; 294 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 295 rcout(sc, CD180_PPRH, 0x11); 296 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11) 297 goto fail; 298 if (rc_test(sc)) 299 goto fail; 300 301 /* 302 * Ok, start actually hooking things up. 303 */ 304 sc->sc_unit = device_get_unit(dev); 305 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/ 306 device_printf(dev, "%d chans, firmware rev. %c\n", 307 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A'); 308 rc = sc->sc_channels; 309 base = CD180_NCHAN * sc->sc_unit; 310 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 311 rc->rc_rcb = sc; 312 rc->rc_chan = chan; 313 rc->rc_iptr = rc->rc_ibuf; 314 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 315 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 316 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 317 rc->rc_dtrwait = 3 * hz; 318 callout_init(&rc->rc_dtrcallout, 0); 319 tp = &rc->rc_tp; 320 ttychars(tp); 321 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 322 tp->t_cflag = TTYDEF_CFLAG; 323 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 324 cdev = make_dev(&rc_cdevsw, chan + base, 325 UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base); 326 cdev->si_drv1 = rc; 327 cdev->si_drv2 = 0; 328 cdev->si_tty = tp; 329 rc->rc_dev = cdev; 330 cdev = make_dev(&rc_cdevsw, chan + base + 128, 331 UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base); 332 cdev->si_drv1 = rc; 333 cdev->si_drv2 = (void *)1; 334 cdev->si_tty = tp; 335 rc->rc_cdev = cdev; 336 } 337 338 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc, 339 &sc->sc_hwicookie); 340 if (error) { 341 device_printf(dev, "failed to register interrupt handler\n"); 342 goto fail; 343 } 344 345 swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0, 346 &sc->sc_swicookie); 347 return (0); 348 349fail: 350 rc_release_resources(dev); 351 return (error); 352} 353 354static int 355rc_detach(device_t dev) 356{ 357 struct rc_softc *sc; 358 struct rc_chans *rc; 359 int error, i, s; 360 361 sc = device_get_softc(dev); 362 if (sc->sc_opencount > 0) 363 return (EBUSY); 364 sc->sc_opencount = -1; 365 366 rc = sc->sc_channels; 367 for (i = 0; i < CD180_NCHAN; i++, rc++) { 368 destroy_dev(rc->rc_dev); 369 destroy_dev(rc->rc_cdev); 370 } 371 372 rc = sc->sc_channels; 373 s = splsoftclock(); 374 for (i = 0; i < CD180_NCHAN; i++) { 375 if ((rc->rc_flags & RC_DTR_OFF) && 376 !callout_stop(&rc->rc_dtrcallout)) 377 tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0); 378 } 379 380 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie); 381 if (error) 382 device_printf(dev, "failed to deregister interrupt handler\n"); 383 ithread_remove_handler(sc->sc_swicookie); 384 rc_release_resources(dev); 385 386 return (0); 387} 388 389static void 390rc_release_resources(device_t dev) 391{ 392 struct rc_softc *sc; 393 int i; 394 395 sc = device_get_softc(dev); 396 if (sc->sc_irq != NULL) { 397 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, 398 sc->sc_irq); 399 sc->sc_irq = NULL; 400 } 401 for (i = 0; i < IOBASE_ADDRS; i++) { 402 if (sc->sc_port[i] == NULL) 403 break; 404 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]); 405 sc->sc_port[i] = NULL; 406 } 407} 408 409/* RC interrupt handling */ 410static void 411rc_intr(void *arg) 412{ 413 struct rc_softc *sc; 414 struct rc_chans *rc; 415 int resid, chan; 416 u_char val, iack, bsr, ucnt, *optr; 417 int good_data, t_state; 418 419 sc = (struct rc_softc *)arg; 420 bsr = ~(rcin(sc, RC_BSR)); 421 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 422 device_printf(sc->sc_dev, "extra interrupt\n"); 423 rcout(sc, CD180_EOIR, 0); 424 return; 425 } 426 427 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 428#ifdef RCDEBUG_DETAILED 429 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr, 430 (bsr & RC_BSR_TOUT)?"TOUT ":"", 431 (bsr & RC_BSR_RXINT)?"RXINT ":"", 432 (bsr & RC_BSR_TXINT)?"TXINT ":"", 433 (bsr & RC_BSR_MOINT)?"MOINT":""); 434#endif 435 if (bsr & RC_BSR_TOUT) { 436 device_printf(sc->sc_dev, 437 "hardware failure, reset board\n"); 438 rcout(sc, RC_CTOUT, 0); 439 rc_reinit(sc); 440 return; 441 } 442 if (bsr & RC_BSR_RXINT) { 443 iack = rcin(sc, RC_PILR_RX); 444 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 445 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 446 device_printf(sc->sc_dev, 447 "fake rxint: %02x\n", iack); 448 goto more_intrs; 449 } 450 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 451 rc = &sc->sc_channels[chan]; 452 t_state = rc->rc_tp.t_state; 453 /* Do RTS flow control stuff */ 454 if ( (rc->rc_flags & RC_RTSFLOW) 455 || !(t_state & TS_ISOPEN) 456 ) { 457 if ( ( !(t_state & TS_ISOPEN) 458 || (t_state & TS_TBLOCK) 459 ) 460 && (rc->rc_msvr & MSVR_RTS) 461 ) 462 rcout(sc, CD180_MSVR, 463 rc->rc_msvr &= ~MSVR_RTS); 464 else if (!(rc->rc_msvr & MSVR_RTS)) 465 rcout(sc, CD180_MSVR, 466 rc->rc_msvr |= MSVR_RTS); 467 } 468 ucnt = rcin(sc, CD180_RDCR) & 0xF; 469 resid = 0; 470 471 if (t_state & TS_ISOPEN) { 472 /* check for input buffer overflow */ 473 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 474 resid = ucnt; 475 ucnt = rc->rc_bufend - rc->rc_iptr; 476 resid -= ucnt; 477 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 478 rc->rc_flags |= RC_WAS_BUFOVFL; 479 sc->sc_scheduled_event++; 480 } 481 } 482 optr = rc->rc_iptr; 483 /* check foor good data */ 484 if (good_data) { 485 while (ucnt-- > 0) { 486 val = rcin(sc, CD180_RDR); 487 optr[0] = val; 488 optr[INPUT_FLAGS_SHIFT] = 0; 489 optr++; 490 sc->sc_scheduled_event++; 491 if (val != 0 && val == rc->rc_hotchar) 492 swi_sched(sc->sc_swicookie, 0); 493 } 494 } else { 495 /* Store also status data */ 496 while (ucnt-- > 0) { 497 iack = rcin(sc, CD180_RCSR); 498 if (iack & RCSR_Timeout) 499 break; 500 if ( (iack & RCSR_OE) 501 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 502 rc->rc_flags |= RC_WAS_SILOVFL; 503 sc->sc_scheduled_event++; 504 } 505 val = rcin(sc, CD180_RDR); 506 /* 507 Don't store PE if IGNPAR and BREAK if IGNBRK, 508 this hack allows "raw" tty optimization 509 works even if IGN* is set. 510 */ 511 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 512 || ((!(iack & (RCSR_PE|RCSR_FE)) 513 || !(rc->rc_tp.t_iflag & IGNPAR)) 514 && (!(iack & RCSR_Break) 515 || !(rc->rc_tp.t_iflag & IGNBRK)))) { 516 if ( (iack & (RCSR_PE|RCSR_FE)) 517 && (t_state & TS_CAN_BYPASS_L_RINT) 518 && ((iack & RCSR_FE) 519 || ((iack & RCSR_PE) 520 && (rc->rc_tp.t_iflag & INPCK)))) 521 val = 0; 522 else if (val != 0 && val == rc->rc_hotchar) 523 swi_sched(sc->sc_swicookie, 0); 524 optr[0] = val; 525 optr[INPUT_FLAGS_SHIFT] = iack; 526 optr++; 527 sc->sc_scheduled_event++; 528 } 529 } 530 } 531 rc->rc_iptr = optr; 532 rc->rc_flags |= RC_DORXFER; 533 } else 534 resid = ucnt; 535 /* Clear FIFO if necessary */ 536 while (resid-- > 0) { 537 if (!good_data) 538 iack = rcin(sc, CD180_RCSR); 539 else 540 iack = 0; 541 if (iack & RCSR_Timeout) 542 break; 543 (void) rcin(sc, CD180_RDR); 544 } 545 goto more_intrs; 546 } 547 if (bsr & RC_BSR_MOINT) { 548 iack = rcin(sc, RC_PILR_MODEM); 549 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 550 device_printf(sc->sc_dev, "fake moint: %02x\n", 551 iack); 552 goto more_intrs; 553 } 554 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 555 rc = &sc->sc_channels[chan]; 556 iack = rcin(sc, CD180_MCR); 557 rc->rc_msvr = rcin(sc, CD180_MSVR); 558 rcout(sc, CD180_MCR, 0); 559#ifdef RCDEBUG 560 printrcflags(rc, "moint"); 561#endif 562 if (rc->rc_flags & RC_CTSFLOW) { 563 if (rc->rc_msvr & MSVR_CTS) 564 rc->rc_flags |= RC_SEND_RDY; 565 else 566 rc->rc_flags &= ~RC_SEND_RDY; 567 } else 568 rc->rc_flags |= RC_SEND_RDY; 569 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 570 sc->sc_scheduled_event += LOTS_OF_EVENTS; 571 rc->rc_flags |= RC_MODCHG; 572 swi_sched(sc->sc_swicookie, 0); 573 } 574 goto more_intrs; 575 } 576 if (bsr & RC_BSR_TXINT) { 577 iack = rcin(sc, RC_PILR_TX); 578 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 579 device_printf(sc->sc_dev, "fake txint: %02x\n", 580 iack); 581 goto more_intrs; 582 } 583 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 584 rc = &sc->sc_channels[chan]; 585 if ( (rc->rc_flags & RC_OSUSP) 586 || !(rc->rc_flags & RC_SEND_RDY) 587 ) 588 goto more_intrs; 589 /* Handle breaks and other stuff */ 590 if (rc->rc_pendcmd) { 591 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC); 592 rcout(sc, CD180_TDR, CD180_C_ESC); 593 rcout(sc, CD180_TDR, rc->rc_pendcmd); 594 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 595 rc->rc_pendcmd = 0; 596 goto more_intrs; 597 } 598 optr = rc->rc_optr; 599 resid = rc->rc_obufend - optr; 600 if (resid > CD180_NFIFO) 601 resid = CD180_NFIFO; 602 while (resid-- > 0) 603 rcout(sc, CD180_TDR, *optr++); 604 rc->rc_optr = optr; 605 606 /* output completed? */ 607 if (optr >= rc->rc_obufend) { 608 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy); 609#ifdef RCDEBUG 610 device_printf(sc->sc_dev, 611 "channel %d: output completed\n", 612 rc->rc_chan); 613#endif 614 if (!(rc->rc_flags & RC_DOXXFER)) { 615 sc->sc_scheduled_event += LOTS_OF_EVENTS; 616 rc->rc_flags |= RC_DOXXFER; 617 swi_sched(sc->sc_swicookie, 0); 618 } 619 } 620 } 621 more_intrs: 622 rcout(sc, CD180_EOIR, 0); /* end of interrupt */ 623 rcout(sc, RC_CTOUT, 0); 624 bsr = ~(rcin(sc, RC_BSR)); 625 } 626} 627 628/* Feed characters to output buffer */ 629static void 630rc_start(struct tty *tp) 631{ 632 struct rc_softc *sc; 633 struct rc_chans *rc; 634 int s; 635 636 rc = TTY_TO_RC(tp); 637 if (rc->rc_flags & RC_OSBUSY) 638 return; 639 sc = rc->rc_rcb; 640 s = spltty(); 641 rc->rc_flags |= RC_OSBUSY; 642 critical_enter(); 643 if (tp->t_state & TS_TTSTOP) 644 rc->rc_flags |= RC_OSUSP; 645 else 646 rc->rc_flags &= ~RC_OSUSP; 647 /* Do RTS flow control stuff */ 648 if ( (rc->rc_flags & RC_RTSFLOW) 649 && (tp->t_state & TS_TBLOCK) 650 && (rc->rc_msvr & MSVR_RTS) 651 ) { 652 rcout(sc, CD180_CAR, rc->rc_chan); 653 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 654 } else if (!(rc->rc_msvr & MSVR_RTS)) { 655 rcout(sc, CD180_CAR, rc->rc_chan); 656 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 657 } 658 critical_exit(); 659 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 660 goto out; 661#ifdef RCDEBUG 662 printrcflags(rc, "rcstart"); 663#endif 664 ttwwakeup(tp); 665#ifdef RCDEBUG 666 printf("rcstart: outq = %d obuf = %d\n", 667 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 668#endif 669 if (tp->t_state & TS_BUSY) 670 goto out; /* output still in progress ... */ 671 672 if (tp->t_outq.c_cc > 0) { 673 u_int ocnt; 674 675 tp->t_state |= TS_BUSY; 676 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 677 critical_enter(); 678 rc->rc_optr = rc->rc_obuf; 679 rc->rc_obufend = rc->rc_optr + ocnt; 680 critical_exit(); 681 if (!(rc->rc_ier & IER_TxRdy)) { 682#ifdef RCDEBUG 683 device_printf(sc->sc_dev, 684 "channel %d: rcstart enable txint\n", rc->rc_chan); 685#endif 686 rcout(sc, CD180_CAR, rc->rc_chan); 687 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy); 688 } 689 } 690out: 691 rc->rc_flags &= ~RC_OSBUSY; 692 (void) splx(s); 693} 694 695/* Handle delayed events. */ 696void 697rc_pollcard(void *arg) 698{ 699 struct rc_softc *sc; 700 struct rc_chans *rc; 701 struct tty *tp; 702 u_char *tptr, *eptr; 703 int chan, icnt; 704 705 sc = (struct rc_softc *)arg; 706 if (sc->sc_scheduled_event == 0) 707 return; 708 do { 709 rc = sc->sc_channels; 710 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 711 tp = &rc->rc_tp; 712#ifdef RCDEBUG 713 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 714 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 715 printrcflags(rc, "rcevent"); 716#endif 717 if (rc->rc_flags & RC_WAS_BUFOVFL) { 718 critical_enter(); 719 rc->rc_flags &= ~RC_WAS_BUFOVFL; 720 sc->sc_scheduled_event--; 721 critical_exit(); 722 device_printf(sc->sc_dev, 723 "channel %d: interrupt-level buffer overflow\n", 724 chan); 725 } 726 if (rc->rc_flags & RC_WAS_SILOVFL) { 727 critical_enter(); 728 rc->rc_flags &= ~RC_WAS_SILOVFL; 729 sc->sc_scheduled_event--; 730 critical_exit(); 731 device_printf(sc->sc_dev, 732 "channel %d: silo overflow\n", chan); 733 } 734 if (rc->rc_flags & RC_MODCHG) { 735 critical_enter(); 736 rc->rc_flags &= ~RC_MODCHG; 737 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 738 critical_exit(); 739 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 740 } 741 if (rc->rc_flags & RC_DORXFER) { 742 critical_enter(); 743 rc->rc_flags &= ~RC_DORXFER; 744 eptr = rc->rc_iptr; 745 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 746 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 747 else 748 tptr = rc->rc_ibuf; 749 icnt = eptr - tptr; 750 if (icnt > 0) { 751 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 752 rc->rc_iptr = rc->rc_ibuf; 753 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 754 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 755 } else { 756 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 757 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 758 rc->rc_hiwat = 759 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 760 } 761 if ( (rc->rc_flags & RC_RTSFLOW) 762 && (tp->t_state & TS_ISOPEN) 763 && !(tp->t_state & TS_TBLOCK) 764 && !(rc->rc_msvr & MSVR_RTS) 765 ) { 766 rcout(sc, CD180_CAR, chan); 767 rcout(sc, CD180_MSVR, 768 rc->rc_msvr |= MSVR_RTS); 769 } 770 sc->sc_scheduled_event -= icnt; 771 } 772 critical_exit(); 773 774 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 775 goto done1; 776 777 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 778 && !(tp->t_state & TS_LOCAL)) { 779 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 780 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 781 && !(tp->t_state & TS_TBLOCK)) 782 ttyblock(tp); 783 tk_nin += icnt; 784 tk_rawcc += icnt; 785 tp->t_rawcc += icnt; 786 if (b_to_q(tptr, icnt, &tp->t_rawq)) 787 device_printf(sc->sc_dev, 788 "channel %d: tty-level buffer overflow\n", 789 chan); 790 ttwakeup(tp); 791 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 792 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 793 tp->t_state &= ~TS_TTSTOP; 794 tp->t_lflag &= ~FLUSHO; 795 rc_start(tp); 796 } 797 } else { 798 for (; tptr < eptr; tptr++) 799 (*linesw[tp->t_line].l_rint) 800 (tptr[0] | 801 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 802 } 803done1: ; 804 } 805 if (rc->rc_flags & RC_DOXXFER) { 806 critical_enter(); 807 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 808 rc->rc_flags &= ~RC_DOXXFER; 809 rc->rc_tp.t_state &= ~TS_BUSY; 810 critical_exit(); 811 (*linesw[tp->t_line].l_start)(tp); 812 } 813 if (sc->sc_scheduled_event == 0) 814 break; 815 } 816 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS); 817} 818 819static void 820rc_stop(struct tty *tp, int rw) 821{ 822 struct rc_softc *sc; 823 struct rc_chans *rc; 824 u_char *tptr, *eptr; 825 826 rc = TTY_TO_RC(tp); 827 sc = rc->rc_rcb; 828#ifdef RCDEBUG 829 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n", 830 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 831#endif 832 if (rw & FWRITE) 833 rc_discard_output(rc); 834 critical_enter(); 835 if (rw & FREAD) { 836 rc->rc_flags &= ~RC_DORXFER; 837 eptr = rc->rc_iptr; 838 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 839 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 840 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 841 } else { 842 tptr = rc->rc_ibuf; 843 rc->rc_iptr = rc->rc_ibuf; 844 } 845 sc->sc_scheduled_event -= eptr - tptr; 846 } 847 if (tp->t_state & TS_TTSTOP) 848 rc->rc_flags |= RC_OSUSP; 849 else 850 rc->rc_flags &= ~RC_OSUSP; 851 critical_exit(); 852} 853 854static int 855rcopen(dev_t dev, int flag, int mode, d_thread_t *td) 856{ 857 struct rc_softc *sc; 858 struct rc_chans *rc; 859 struct tty *tp; 860 int s, error = 0; 861 862 rc = DEV_TO_RC(dev); 863 sc = rc->rc_rcb; 864 tp = &rc->rc_tp; 865 if (sc->sc_opencount < 0) 866 return (ENXIO); 867 sc->sc_opencount++; 868#ifdef RCDEBUG 869 device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n", 870 rc->rc_chan, dev); 871#endif 872 s = spltty(); 873 874again: 875 while (rc->rc_flags & RC_DTR_OFF) { 876 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 877 if (error != 0) 878 goto out; 879 } 880 if (tp->t_state & TS_ISOPEN) { 881 if (CALLOUT(dev)) { 882 if (!(rc->rc_flags & RC_ACTOUT)) { 883 error = EBUSY; 884 goto out; 885 } 886 } else { 887 if (rc->rc_flags & RC_ACTOUT) { 888 if (flag & O_NONBLOCK) { 889 error = EBUSY; 890 goto out; 891 } 892 error = tsleep(&rc->rc_rcb, 893 TTIPRI|PCATCH, "rcbi", 0); 894 if (error) 895 goto out; 896 goto again; 897 } 898 } 899 if (tp->t_state & TS_XCLUDE && 900 suser(td)) { 901 error = EBUSY; 902 goto out; 903 } 904 } else { 905 tp->t_oproc = rc_start; 906 tp->t_param = rc_param; 907 tp->t_stop = rc_stop; 908 tp->t_dev = dev; 909 910 if (CALLOUT(dev)) 911 tp->t_cflag |= CLOCAL; 912 else 913 tp->t_cflag &= ~CLOCAL; 914 915 error = rc_param(tp, &tp->t_termios); 916 if (error) 917 goto out; 918 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 919 920 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 921 (*linesw[tp->t_line].l_modem)(tp, 1); 922 } 923 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 924 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 925 rc->rc_dcdwaits++; 926 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 927 rc->rc_dcdwaits--; 928 if (error != 0) 929 goto out; 930 goto again; 931 } 932 error = (*linesw[tp->t_line].l_open)(dev, tp); 933 disc_optim(tp, &tp->t_termios, rc); 934 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 935 rc->rc_flags |= RC_ACTOUT; 936out: 937 (void) splx(s); 938 939 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 940 rc_hardclose(rc); 941 942 return error; 943} 944 945static int 946rcclose(dev_t dev, int flag, int mode, d_thread_t *td) 947{ 948 struct rc_softc *sc; 949 struct rc_chans *rc; 950 struct tty *tp; 951 int s; 952 953 rc = DEV_TO_RC(dev); 954 sc = rc->rc_rcb; 955 tp = &rc->rc_tp; 956#ifdef RCDEBUG 957 device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n", 958 rc->rc_chan, dev); 959#endif 960 s = spltty(); 961 (*linesw[tp->t_line].l_close)(tp, flag); 962 disc_optim(tp, &tp->t_termios, rc); 963 rc_stop(tp, FREAD | FWRITE); 964 rc_hardclose(rc); 965 ttyclose(tp); 966 splx(s); 967 KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count")); 968 sc->sc_opencount--; 969 return 0; 970} 971 972static void 973rc_hardclose(struct rc_chans *rc) 974{ 975 struct rc_softc *sc; 976 struct tty *tp; 977 int s; 978 979 tp = &rc->rc_tp; 980 sc = rc->rc_rcb; 981 s = spltty(); 982 rcout(sc, CD180_CAR, rc->rc_chan); 983 984 /* Disable rx/tx intrs */ 985 rcout(sc, CD180_IER, rc->rc_ier = 0); 986 if ( (tp->t_cflag & HUPCL) 987 || (!(rc->rc_flags & RC_ACTOUT) 988 && !(rc->rc_msvr & MSVR_CD) 989 && !(tp->t_cflag & CLOCAL)) 990 || !(tp->t_state & TS_ISOPEN) 991 ) { 992 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 993 WAITFORCCR(sc, rc->rc_chan); 994 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 995 if (rc->rc_dtrwait) { 996 callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait, 997 rc_dtrwakeup, rc); 998 rc->rc_flags |= RC_DTR_OFF; 999 } 1000 } 1001 rc->rc_flags &= ~RC_ACTOUT; 1002 wakeup( &rc->rc_rcb); /* wake bi */ 1003 wakeup(TSA_CARR_ON(tp)); 1004 (void) splx(s); 1005} 1006 1007/* Reset the bastard */ 1008static void 1009rc_hwreset(struct rc_softc *sc, u_int chipid) 1010{ 1011 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */ 1012 DELAY(20000); 1013 WAITFORCCR(sc, -1); 1014 1015 rcout(sc, RC_CTOUT, 0); /* Clear timeout */ 1016 rcout(sc, CD180_GIVR, chipid); 1017 rcout(sc, CD180_GICR, 0); 1018 1019 /* Set Prescaler Registers (1 msec) */ 1020 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 1021 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 1022 1023 /* Initialize Priority Interrupt Level Registers */ 1024 rcout(sc, CD180_PILR1, RC_PILR_MODEM); 1025 rcout(sc, CD180_PILR2, RC_PILR_TX); 1026 rcout(sc, CD180_PILR3, RC_PILR_RX); 1027 1028 /* Reset DTR */ 1029 rcout(sc, RC_DTREG, ~0); 1030} 1031 1032/* Set channel parameters */ 1033static int 1034rc_param(struct tty *tp, struct termios *ts) 1035{ 1036 struct rc_softc *sc; 1037 struct rc_chans *rc; 1038 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 1039 1040 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 1041 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 1042 ) 1043 return (EINVAL); 1044 if (ts->c_ispeed == 0) 1045 ts->c_ispeed = ts->c_ospeed; 1046 odivs = RC_BRD(ts->c_ospeed); 1047 idivs = RC_BRD(ts->c_ispeed); 1048 1049 rc = TTY_TO_RC(tp); 1050 sc = rc->rc_rcb; 1051 s = spltty(); 1052 1053 /* Select channel */ 1054 rcout(sc, CD180_CAR, rc->rc_chan); 1055 1056 /* If speed == 0, hangup line */ 1057 if (ts->c_ospeed == 0) { 1058 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 1059 WAITFORCCR(sc, rc->rc_chan); 1060 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1061 } 1062 1063 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1064 cflag = ts->c_cflag; 1065 iflag = ts->c_iflag; 1066 lflag = ts->c_lflag; 1067 1068 if (idivs > 0) { 1069 rcout(sc, CD180_RBPRL, idivs & 0xFF); 1070 rcout(sc, CD180_RBPRH, idivs >> 8); 1071 } 1072 if (odivs > 0) { 1073 rcout(sc, CD180_TBPRL, odivs & 0xFF); 1074 rcout(sc, CD180_TBPRH, odivs >> 8); 1075 } 1076 1077 /* set timeout value */ 1078 if (ts->c_ispeed > 0) { 1079 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 1080 1081 if ( !(lflag & ICANON) 1082 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1083 && ts->c_cc[VTIME] * 10 > itm) 1084 itm = ts->c_cc[VTIME] * 10; 1085 1086 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255); 1087 } 1088 1089 switch (cflag & CSIZE) { 1090 case CS5: val = COR1_5BITS; break; 1091 case CS6: val = COR1_6BITS; break; 1092 case CS7: val = COR1_7BITS; break; 1093 default: 1094 case CS8: val = COR1_8BITS; break; 1095 } 1096 if (cflag & PARENB) { 1097 val |= COR1_NORMPAR; 1098 if (cflag & PARODD) 1099 val |= COR1_ODDP; 1100 if (!(cflag & INPCK)) 1101 val |= COR1_Ignore; 1102 } else 1103 val |= COR1_Ignore; 1104 if (cflag & CSTOPB) 1105 val |= COR1_2SB; 1106 rcout(sc, CD180_COR1, val); 1107 1108 /* Set FIFO threshold */ 1109 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1110 inpflow = 0; 1111 if ( (iflag & IXOFF) 1112 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1113 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1114 || (iflag & IXANY) 1115 ) 1116 ) 1117 ) { 1118 inpflow = 1; 1119 val |= COR3_SCDE|COR3_FCT; 1120 } 1121 rcout(sc, CD180_COR3, val); 1122 1123 /* Initialize on-chip automatic flow control */ 1124 val = 0; 1125 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1126 if (cflag & CCTS_OFLOW) { 1127 rc->rc_flags |= RC_CTSFLOW; 1128 val |= COR2_CtsAE; 1129 } else 1130 rc->rc_flags |= RC_SEND_RDY; 1131 if (tp->t_state & TS_TTSTOP) 1132 rc->rc_flags |= RC_OSUSP; 1133 else 1134 rc->rc_flags &= ~RC_OSUSP; 1135 if (cflag & CRTS_IFLOW) 1136 rc->rc_flags |= RC_RTSFLOW; 1137 else 1138 rc->rc_flags &= ~RC_RTSFLOW; 1139 1140 if (inpflow) { 1141 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1142 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]); 1143 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]); 1144 val |= COR2_TxIBE; 1145 if (iflag & IXANY) 1146 val |= COR2_IXM; 1147 } 1148 1149 rcout(sc, CD180_COR2, rc->rc_cor2 = val); 1150 1151 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1152 1153 disc_optim(tp, ts, rc); 1154 1155 /* modem ctl */ 1156 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1157 if (cflag & CCTS_OFLOW) 1158 val |= MCOR1_CTSzd; 1159 rcout(sc, CD180_MCOR1, val); 1160 1161 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1162 if (cflag & CCTS_OFLOW) 1163 val |= MCOR2_CTSod; 1164 rcout(sc, CD180_MCOR2, val); 1165 1166 /* enable i/o and interrupts */ 1167 CCRCMD(sc, rc->rc_chan, 1168 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1169 WAITFORCCR(sc, rc->rc_chan); 1170 1171 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1172 if (cflag & CCTS_OFLOW) 1173 rc->rc_ier |= IER_CTS; 1174 if (cflag & CREAD) 1175 rc->rc_ier |= IER_RxData; 1176 if (tp->t_state & TS_BUSY) 1177 rc->rc_ier |= IER_TxRdy; 1178 if (ts->c_ospeed != 0) 1179 rc_modctl(rc, TIOCM_DTR, DMBIS); 1180 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1181 rc->rc_flags |= RC_SEND_RDY; 1182 rcout(sc, CD180_IER, rc->rc_ier); 1183 (void) splx(s); 1184 return 0; 1185} 1186 1187/* Re-initialize board after bogus interrupts */ 1188static void 1189rc_reinit(struct rc_softc *sc) 1190{ 1191 struct rc_chans *rc; 1192 int i; 1193 1194 rc_hwreset(sc, RC_FAKEID); 1195 rc = sc->sc_channels; 1196 for (i = 0; i < CD180_NCHAN; i++, rc++) 1197 (void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios); 1198} 1199 1200static int 1201rcioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td) 1202{ 1203 struct rc_chans *rc; 1204 struct tty *tp; 1205 int s, error; 1206 1207 rc = DEV_TO_RC(dev); 1208 tp = &rc->rc_tp; 1209 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1210 if (error != ENOIOCTL) 1211 return (error); 1212 error = ttioctl(tp, cmd, data, flag); 1213 disc_optim(tp, &tp->t_termios, rc); 1214 if (error != ENOIOCTL) 1215 return (error); 1216 s = spltty(); 1217 1218 switch (cmd) { 1219 case TIOCSBRK: 1220 rc->rc_pendcmd = CD180_C_SBRK; 1221 break; 1222 1223 case TIOCCBRK: 1224 rc->rc_pendcmd = CD180_C_EBRK; 1225 break; 1226 1227 case TIOCSDTR: 1228 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1229 break; 1230 1231 case TIOCCDTR: 1232 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1233 break; 1234 1235 case TIOCMGET: 1236 *(int *) data = rc_modctl(rc, 0, DMGET); 1237 break; 1238 1239 case TIOCMSET: 1240 (void) rc_modctl(rc, *(int *) data, DMSET); 1241 break; 1242 1243 case TIOCMBIC: 1244 (void) rc_modctl(rc, *(int *) data, DMBIC); 1245 break; 1246 1247 case TIOCMBIS: 1248 (void) rc_modctl(rc, *(int *) data, DMBIS); 1249 break; 1250 1251 case TIOCMSDTRWAIT: 1252 error = suser(td); 1253 if (error != 0) { 1254 splx(s); 1255 return (error); 1256 } 1257 rc->rc_dtrwait = *(int *)data * hz / 100; 1258 break; 1259 1260 case TIOCMGDTRWAIT: 1261 *(int *)data = rc->rc_dtrwait * 100 / hz; 1262 break; 1263 1264 default: 1265 (void) splx(s); 1266 return ENOTTY; 1267 } 1268 (void) splx(s); 1269 return 0; 1270} 1271 1272 1273/* Modem control routines */ 1274 1275static int 1276rc_modctl(struct rc_chans *rc, int bits, int cmd) 1277{ 1278 struct rc_softc *sc; 1279 u_char *dtr; 1280 u_char msvr; 1281 1282 sc = rc->rc_rcb; 1283 dtr = &sc->sc_dtr; 1284 rcout(sc, CD180_CAR, rc->rc_chan); 1285 1286 switch (cmd) { 1287 case DMSET: 1288 rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ? 1289 ~(*dtr |= 1 << rc->rc_chan) : 1290 ~(*dtr &= ~(1 << rc->rc_chan))); 1291 msvr = rcin(sc, CD180_MSVR); 1292 if (bits & TIOCM_RTS) 1293 msvr |= MSVR_RTS; 1294 else 1295 msvr &= ~MSVR_RTS; 1296 if (bits & TIOCM_DTR) 1297 msvr |= MSVR_DTR; 1298 else 1299 msvr &= ~MSVR_DTR; 1300 rcout(sc, CD180_MSVR, msvr); 1301 break; 1302 1303 case DMBIS: 1304 if (bits & TIOCM_DTR) 1305 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1306 msvr = rcin(sc, CD180_MSVR); 1307 if (bits & TIOCM_RTS) 1308 msvr |= MSVR_RTS; 1309 if (bits & TIOCM_DTR) 1310 msvr |= MSVR_DTR; 1311 rcout(sc, CD180_MSVR, msvr); 1312 break; 1313 1314 case DMGET: 1315 bits = TIOCM_LE; 1316 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR); 1317 1318 if (msvr & MSVR_RTS) 1319 bits |= TIOCM_RTS; 1320 if (msvr & MSVR_CTS) 1321 bits |= TIOCM_CTS; 1322 if (msvr & MSVR_DSR) 1323 bits |= TIOCM_DSR; 1324 if (msvr & MSVR_DTR) 1325 bits |= TIOCM_DTR; 1326 if (msvr & MSVR_CD) 1327 bits |= TIOCM_CD; 1328 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan)) 1329 bits |= TIOCM_RI; 1330 return bits; 1331 1332 case DMBIC: 1333 if (bits & TIOCM_DTR) 1334 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1335 msvr = rcin(sc, CD180_MSVR); 1336 if (bits & TIOCM_RTS) 1337 msvr &= ~MSVR_RTS; 1338 if (bits & TIOCM_DTR) 1339 msvr &= ~MSVR_DTR; 1340 rcout(sc, CD180_MSVR, msvr); 1341 break; 1342 } 1343 rc->rc_msvr = rcin(sc, CD180_MSVR); 1344 return 0; 1345} 1346 1347#define ERR(s) do { \ 1348 device_printf(sc->sc_dev, "%s", ""); \ 1349 printf s ; \ 1350 printf("\n"); \ 1351 (void) splx(old_level); \ 1352 return 1; \ 1353} while (0) 1354 1355/* Test the board. */ 1356int 1357rc_test(struct rc_softc *sc) 1358{ 1359 int chan = 0; 1360 int i = 0, rcnt, old_level; 1361 unsigned int iack, chipid; 1362 unsigned short divs; 1363 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1364#define CTLEN 8 1365 1366 struct rtest { 1367 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1368 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1369 int rxptr; /* RX pointer */ 1370 int txptr; /* TX pointer */ 1371 } tchans[CD180_NCHAN]; 1372 1373 old_level = spltty(); 1374 1375 chipid = RC_FAKEID; 1376 1377 /* First, reset board to inital state */ 1378 rc_hwreset(sc, chipid); 1379 1380 divs = RC_BRD(19200); 1381 1382 /* Initialize channels */ 1383 for (chan = 0; chan < CD180_NCHAN; chan++) { 1384 1385 /* Select and reset channel */ 1386 rcout(sc, CD180_CAR, chan); 1387 CCRCMD(sc, chan, CCR_ResetChan); 1388 WAITFORCCR(sc, chan); 1389 1390 /* Set speed */ 1391 rcout(sc, CD180_RBPRL, divs & 0xFF); 1392 rcout(sc, CD180_RBPRH, divs >> 8); 1393 rcout(sc, CD180_TBPRL, divs & 0xFF); 1394 rcout(sc, CD180_TBPRH, divs >> 8); 1395 1396 /* set timeout value */ 1397 rcout(sc, CD180_RTPR, 0); 1398 1399 /* Establish local loopback */ 1400 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1401 rcout(sc, CD180_COR2, COR2_LLM); 1402 rcout(sc, CD180_COR3, CD180_NFIFO); 1403 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1404 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN); 1405 WAITFORCCR(sc, chan); 1406 rcout(sc, CD180_MSVR, MSVR_RTS); 1407 1408 /* Fill TXBUF with test data */ 1409 for (i = 0; i < CD180_NFIFO; i++) { 1410 tchans[chan].txbuf[i] = ctest[i]; 1411 tchans[chan].rxbuf[i] = 0; 1412 } 1413 tchans[chan].txptr = tchans[chan].rxptr = 0; 1414 1415 /* Now, start transmit */ 1416 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData); 1417 } 1418 /* Pseudo-interrupt poll stuff */ 1419 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1420 i = ~(rcin(sc, RC_BSR)); 1421 if (i & RC_BSR_TOUT) 1422 ERR(("BSR timeout bit set\n")); 1423 else if (i & RC_BSR_TXINT) { 1424 iack = rcin(sc, RC_PILR_TX); 1425 if (iack != (GIVR_IT_TDI | chipid)) 1426 ERR(("Bad TX intr ack (%02x != %02x)\n", 1427 iack, GIVR_IT_TDI | chipid)); 1428 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1429 /* If no more data to transmit, disable TX intr */ 1430 if (tchans[chan].txptr >= CD180_NFIFO) { 1431 iack = rcin(sc, CD180_IER); 1432 rcout(sc, CD180_IER, iack & ~IER_TxMpty); 1433 } else { 1434 for (iack = tchans[chan].txptr; 1435 iack < CD180_NFIFO; iack++) 1436 rcout(sc, CD180_TDR, 1437 tchans[chan].txbuf[iack]); 1438 tchans[chan].txptr = iack; 1439 } 1440 rcout(sc, CD180_EOIR, 0); 1441 } else if (i & RC_BSR_RXINT) { 1442 u_char ucnt; 1443 1444 iack = rcin(sc, RC_PILR_RX); 1445 if (iack != (GIVR_IT_RGDI | chipid) && 1446 iack != (GIVR_IT_REI | chipid)) 1447 ERR(("Bad RX intr ack (%02x != %02x)\n", 1448 iack, GIVR_IT_RGDI | chipid)); 1449 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1450 ucnt = rcin(sc, CD180_RDCR) & 0xF; 1451 while (ucnt-- > 0) { 1452 iack = rcin(sc, CD180_RCSR); 1453 if (iack & RCSR_Timeout) 1454 break; 1455 if (iack & 0xF) 1456 ERR(("Bad char chan %d (RCSR = %02X)\n", 1457 chan, iack)); 1458 if (tchans[chan].rxptr > CD180_NFIFO) 1459 ERR(("Got extra chars chan %d\n", 1460 chan)); 1461 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1462 rcin(sc, CD180_RDR); 1463 } 1464 rcout(sc, CD180_EOIR, 0); 1465 } 1466 rcout(sc, RC_CTOUT, 0); 1467 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1468 if (tchans[chan].rxptr >= CD180_NFIFO) 1469 iack++; 1470 if (iack == CD180_NCHAN) 1471 break; 1472 } 1473 for (chan = 0; chan < CD180_NCHAN; chan++) { 1474 /* Select and reset channel */ 1475 rcout(sc, CD180_CAR, chan); 1476 CCRCMD(sc, chan, CCR_ResetChan); 1477 } 1478 1479 if (!rcnt) 1480 ERR(("looses characters during local loopback\n")); 1481 /* Now, check data */ 1482 for (chan = 0; chan < CD180_NCHAN; chan++) 1483 for (i = 0; i < CD180_NFIFO; i++) 1484 if (ctest[i] != tchans[chan].rxbuf[i]) 1485 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1486 chan, i, ctest[i], tchans[chan].rxbuf[i])); 1487 (void) splx(old_level); 1488 return 0; 1489} 1490 1491#ifdef RCDEBUG 1492static void 1493printrcflags(struct rc_chans *rc, char *comment) 1494{ 1495 struct rc_softc *sc; 1496 u_short f = rc->rc_flags; 1497 1498 sc = rc->rc_rcb; 1499 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1500 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1501 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1502 (f & RC_ACTOUT) ?"ACTOUT " :"", 1503 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1504 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1505 (f & RC_DORXFER)?"DORXFER " :"", 1506 (f & RC_DOXXFER)?"DOXXFER " :"", 1507 (f & RC_MODCHG) ?"MODCHG " :"", 1508 (f & RC_OSUSP) ?"OSUSP " :"", 1509 (f & RC_OSBUSY) ?"OSBUSY " :"", 1510 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1511 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1512 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1513 1514 rcout(sc, CD180_CAR, rc->rc_chan); 1515 1516 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1517 rc->rc_rcb->rcb_unit, rc->rc_chan, 1518 rcin(sc, CD180_MSVR), 1519 rcin(sc, CD180_IER), 1520 rcin(sc, CD180_CCSR)); 1521} 1522#endif /* RCDEBUG */ 1523 1524static void 1525rc_dtrwakeup(void *arg) 1526{ 1527 struct rc_chans *rc; 1528 1529 rc = (struct rc_chans *)arg; 1530 rc->rc_flags &= ~RC_DTR_OFF; 1531 wakeup(&rc->rc_dtrwait); 1532} 1533 1534static void 1535rc_discard_output(struct rc_chans *rc) 1536{ 1537 critical_enter(); 1538 if (rc->rc_flags & RC_DOXXFER) { 1539 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS; 1540 rc->rc_flags &= ~RC_DOXXFER; 1541 } 1542 rc->rc_optr = rc->rc_obufend; 1543 rc->rc_tp.t_state &= ~TS_BUSY; 1544 critical_exit(); 1545 ttwwakeup(&rc->rc_tp); 1546} 1547 1548static void 1549disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc) 1550{ 1551 1552 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1553 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1554 && (!(t->c_iflag & PARMRK) 1555 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1556 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1557 && linesw[tp->t_line].l_rint == ttyinput) 1558 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1559 else 1560 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1561 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1562} 1563 1564static void 1565rc_wait0(struct rc_softc *sc, int chan, int line) 1566{ 1567 int rcnt; 1568 1569 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--) 1570 DELAY(30); 1571 if (rcnt == 0) 1572 device_printf(sc->sc_dev, 1573 "channel %d command timeout, rc.c line: %d\n", chan, line); 1574} 1575 1576static device_method_t rc_methods[] = { 1577 /* Device interface */ 1578 DEVMETHOD(device_probe, rc_probe), 1579 DEVMETHOD(device_attach, rc_attach), 1580 DEVMETHOD(device_detach, rc_detach), 1581 { 0, 0 } 1582}; 1583 1584static driver_t rc_driver = { 1585 "rc", 1586 rc_methods, sizeof(struct rc_softc), 1587}; 1588 1589DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0); 1590