rc.c revision 118607
1180811Sstas/* 2180811Sstas * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3180811Sstas * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4180811Sstas * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org> 5180811Sstas * All rights reserved. 6180811Sstas * 7180811Sstas * Redistribution and use in source and binary forms, with or without 8180811Sstas * modification, are permitted provided that the following conditions 9180811Sstas * are met: 10180811Sstas * 1. Redistributions of source code must retain the above copyright 11180811Sstas * notice, this list of conditions and the following disclaimer. 12180811Sstas * 2. Redistributions in binary form must reproduce the above copyright 13180811Sstas * notice, this list of conditions and the following disclaimer in the 14180811Sstas * documentation and/or other materials provided with the distribution. 15180811Sstas * 16180811Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 17180811Sstas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18180811Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19180811Sstas * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20180811Sstas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21180811Sstas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22180811Sstas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23180811Sstas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24180811Sstas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25180811Sstas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26180811Sstas * SUCH DAMAGE. 27180811Sstas * 28180811Sstas * $FreeBSD: head/sys/dev/rc/rc.c 118607 2003-08-07 15:04:27Z jhb $ 29180811Sstas */ 30180811Sstas 31180811Sstas/* 32180811Sstas * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33180811Sstas * 34180811Sstas */ 35180811Sstas 36180811Sstas/*#define RCDEBUG*/ 37180811Sstas 38180811Sstas#include "opt_tty.h" 39180811Sstas 40180811Sstas#include <sys/param.h> 41180811Sstas#include <sys/systm.h> 42180811Sstas#include <sys/bus.h> 43180811Sstas#include <sys/conf.h> 44180811Sstas#include <sys/fcntl.h> 45180811Sstas#include <sys/interrupt.h> 46180811Sstas#include <sys/kernel.h> 47180811Sstas#include <sys/malloc.h> 48180811Sstas#include <sys/tty.h> 49180811Sstas#include <machine/bus.h> 50180811Sstas#include <machine/resource.h> 51180811Sstas#include <sys/rman.h> 52180811Sstas 53180811Sstas#include <dev/ic/cd180.h> 54180811Sstas#include <dev/rc/rcreg.h> 55180811Sstas#include <isa/isavar.h> 56180811Sstas 57180811Sstas#define IOBASE_ADDRS 14 58180811Sstas 59180811Sstas#define DEV_TO_RC(dev) (struct rc_chans *)((dev)->si_drv1) 60180811Sstas#define TTY_TO_RC(tty) DEV_TO_RC((tty)->t_dev) 61180811Sstas 62180811Sstas#define rcin(sc, port) RC_IN(sc, port) 63180811Sstas#define rcout(sc, port, v) RC_OUT(sc, port, v) 64180811Sstas 65180811Sstas#define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__) 66180811Sstas 67180811Sstas#define CCRCMD(sc, chan, cmd) do { \ 68180811Sstas WAITFORCCR((sc), (chan)); \ 69180811Sstas rcout((sc), CD180_CCR, (cmd)); \ 70180811Sstas} while (0) 71180811Sstas 72180811Sstas#define RC_IBUFSIZE 256 73180811Sstas#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 74180811Sstas#define RC_OBUFSIZE 512 75180811Sstas#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 76180811Sstas#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 77180811Sstas#define LOTS_OF_EVENTS 64 78180811Sstas 79180811Sstas#define RC_FAKEID 0x10 80180811Sstas 81180811Sstas#define CALLOUT(dev) (((intptr_t)(dev)->si_drv2) != 0) 82180811Sstas 83180811Sstas/* Per-channel structure */ 84180811Sstasstruct rc_chans { 85180811Sstas struct rc_softc *rc_rcb; /* back ptr */ 86180811Sstas dev_t rc_dev; /* non-callout device */ 87180811Sstas dev_t rc_cdev; /* callout device */ 88180811Sstas u_short rc_flags; /* Misc. flags */ 89180811Sstas int rc_chan; /* Channel # */ 90180811Sstas u_char rc_ier; /* intr. enable reg */ 91180811Sstas u_char rc_msvr; /* modem sig. status */ 92180811Sstas u_char rc_cor2; /* options reg */ 93180811Sstas u_char rc_pendcmd; /* special cmd pending */ 94180811Sstas u_int rc_dtrwait; /* dtr timeout */ 95180811Sstas u_int rc_dcdwaits; /* how many waits DCD in open */ 96180811Sstas u_char rc_hotchar; /* end packed optimize */ 97180811Sstas struct tty rc_tp; /* tty struct */ 98180811Sstas u_char *rc_iptr; /* Chars input buffer */ 99180811Sstas u_char *rc_hiwat; /* hi-water mark */ 100180811Sstas u_char *rc_bufend; /* end of buffer */ 101180811Sstas u_char *rc_optr; /* ptr in output buf */ 102180811Sstas u_char *rc_obufend; /* end of output buf */ 103180811Sstas u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 104180811Sstas u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 105180811Sstas struct callout rc_dtrcallout; 106180811Sstas}; 107180811Sstas 108180811Sstas/* Per-board structure */ 109180811Sstasstruct rc_softc { 110180811Sstas device_t sc_dev; 111180811Sstas struct resource *sc_irq; 112180811Sstas struct resource *sc_port[IOBASE_ADDRS]; 113180811Sstas int sc_irqrid; 114180811Sstas void *sc_hwicookie; 115180811Sstas bus_space_tag_t sc_bt; 116180811Sstas bus_space_handle_t sc_bh; 117180811Sstas u_int sc_unit; /* unit # */ 118180811Sstas u_char sc_dtr; /* DTR status */ 119180811Sstas int sc_opencount; 120180811Sstas int sc_scheduled_event; 121180811Sstas void *sc_swicookie; 122180811Sstas struct rc_chans sc_channels[CD180_NCHAN]; /* channels */ 123180811Sstas}; 124180811Sstas 125180811Sstas/* Static prototypes */ 126180811Sstasstatic void rc_release_resources(device_t dev); 127180811Sstasstatic void rc_intr(void *); 128180811Sstasstatic void rc_hwreset(struct rc_softc *, unsigned int); 129180811Sstasstatic int rc_test(struct rc_softc *); 130180811Sstasstatic void rc_discard_output(struct rc_chans *); 131180811Sstasstatic void rc_hardclose(struct rc_chans *); 132180811Sstasstatic int rc_modctl(struct rc_chans *, int, int); 133180811Sstasstatic void rc_start(struct tty *); 134180811Sstasstatic void rc_stop(struct tty *, int rw); 135180811Sstasstatic int rc_param(struct tty *, struct termios *); 136180811Sstasstatic void rc_pollcard(void *); 137180811Sstasstatic void rc_reinit(struct rc_softc *); 138180811Sstas#ifdef RCDEBUG 139180811Sstasstatic void printrcflags(); 140180811Sstas#endif 141180811Sstasstatic void rc_dtrwakeup(void *); 142180811Sstasstatic void disc_optim(struct tty *tp, struct termios *t, struct rc_chans *); 143180811Sstasstatic void rc_wait0(struct rc_softc *sc, int chan, int line); 144180811Sstas 145180811Sstasstatic d_open_t rcopen; 146180811Sstasstatic d_close_t rcclose; 147180811Sstasstatic d_ioctl_t rcioctl; 148180811Sstas 149180811Sstas#define CDEV_MAJOR 63 150180811Sstasstatic struct cdevsw rc_cdevsw = { 151180811Sstas .d_open = rcopen, 152180811Sstas .d_close = rcclose, 153180811Sstas .d_read = ttyread, 154180811Sstas .d_write = ttywrite, 155180811Sstas .d_ioctl = rcioctl, 156180811Sstas .d_poll = ttypoll, 157180811Sstas .d_name = "rc", 158180811Sstas .d_maj = CDEV_MAJOR, 159180811Sstas .d_flags = D_TTY, 160180811Sstas .d_kqfilter = ttykqfilter, 161180811Sstas}; 162180811Sstas 163180811Sstasstatic devclass_t rc_devclass; 164180811Sstas 165180811Sstas/* Flags */ 166180811Sstas#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 167180811Sstas#define RC_ACTOUT 0x0002 /* Dial-out port active */ 168180811Sstas#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 169180811Sstas#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 170180811Sstas#define RC_DORXFER 0x0010 /* RXFER event planned */ 171180811Sstas#define RC_DOXXFER 0x0020 /* XXFER event planned */ 172180811Sstas#define RC_MODCHG 0x0040 /* Modem status changed */ 173180811Sstas#define RC_OSUSP 0x0080 /* Output suspended */ 174180811Sstas#define RC_OSBUSY 0x0100 /* start() routine in progress */ 175180811Sstas#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 176180811Sstas#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 177180811Sstas#define RC_SEND_RDY 0x0800 /* ready to send */ 178180811Sstas 179180811Sstas/* Table for translation of RCSR status bits to internal form */ 180180811Sstasstatic int rc_rcsrt[16] = { 181180811Sstas 0, TTY_OE, TTY_FE, 182180811Sstas TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 183180811Sstas TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 184180811Sstas TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 185180811Sstas TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 186180811Sstas TTY_BI|TTY_PE|TTY_FE|TTY_OE 187180811Sstas}; 188180811Sstas 189180811Sstasstatic int rc_ports[] = 190180811Sstas { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 }; 191180811Sstasstatic int iobase_addrs[IOBASE_ADDRS] = 192180811Sstas { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000, 193180811Sstas 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 }; 194180811Sstas 195180811Sstas/**********************************************/ 196180811Sstas 197180811Sstasstatic int 198180811Sstasrc_probe(device_t dev) 199180811Sstas{ 200180811Sstas u_int port; 201180811Sstas int i, found; 202180811Sstas 203180811Sstas /* 204180811Sstas * We don't know of any PnP ID's for these cards. 205180811Sstas */ 206180811Sstas if (isa_get_logicalid(dev) != 0) 207180811Sstas return (ENXIO); 208180811Sstas 209180811Sstas /* 210180811Sstas * We have to have an IO port hint that is valid. 211180811Sstas */ 212180811Sstas port = isa_get_port(dev); 213180811Sstas if (port == -1) 214180811Sstas return (ENXIO); 215180811Sstas found = 0; 216180811Sstas for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++) 217180811Sstas if (rc_ports[i] == port) { 218180811Sstas found = 1; 219180811Sstas break; 220180811Sstas } 221180811Sstas if (!found) 222180811Sstas return (ENXIO); 223180811Sstas 224180811Sstas /* 225180811Sstas * We have to have an IRQ hint. 226180811Sstas */ 227180811Sstas if (isa_get_irq(dev) == -1) 228180811Sstas return (ENXIO); 229180811Sstas 230180811Sstas device_set_desc(dev, "SDL Riscom/8"); 231180811Sstas return (0); 232180811Sstas} 233 234static int 235rc_attach(device_t dev) 236{ 237 struct rc_chans *rc; 238 struct tty *tp; 239 struct rc_softc *sc; 240 u_int port; 241 int base, chan, error, i, x; 242 dev_t cdev; 243 244 sc = device_get_softc(dev); 245 sc->sc_dev = dev; 246 247 /* 248 * We need to have IO ports. Lots of them. We need 249 * the following ranges relative to the base port: 250 * 0x0 - 0x10 251 * 0x400 - 0x410 252 * 0x800 - 0x810 253 * 0xc00 - 0xc10 254 * 0x1400 - 0x1410 255 * 0x1800 - 0x1810 256 * 0x1c00 - 0x1c10 257 * 0x2000 - 0x2010 258 * 0x3000 - 0x3010 259 * 0x3400 - 0x3410 260 * 0x3800 - 0x3810 261 * 0x3c00 - 0x3c10 262 * 0x4000 - 0x4010 263 * 0x8000 - 0x8010 264 */ 265 port = isa_get_port(dev); 266 for (i = 0; i < IOBASE_ADDRS; i++) 267 if (bus_set_resource(dev, SYS_RES_IOPORT, i, 268 port + iobase_addrs[i], 0x10) != 0) 269 return (ENXIO); 270 error = ENOMEM; 271 for (i = 0; i < IOBASE_ADDRS; i++) { 272 x = i; 273 sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x, 274 0ul, ~0ul, 0x10, RF_ACTIVE); 275 if (x != i) { 276 device_printf(dev, "ioport %d was rid %d\n", i, x); 277 goto fail; 278 } 279 if (sc->sc_port[i] == NULL) { 280 device_printf(dev, "failed to alloc ioports %x-%x\n", 281 port + iobase_addrs[i], 282 port + iobase_addrs[i] + 0x10); 283 goto fail; 284 } 285 } 286 sc->sc_bt = rman_get_bustag(sc->sc_port[0]); 287 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]); 288 289 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irqrid, 290 0ul, ~0ul, 1, RF_ACTIVE); 291 if (sc->sc_irq == NULL) { 292 device_printf(dev, "failed to alloc IRQ\n"); 293 goto fail; 294 } 295 296 /* 297 * Now do some actual tests to make sure it works. 298 */ 299 error = ENXIO; 300 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 301 rcout(sc, CD180_PPRH, 0x11); 302 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11) 303 goto fail; 304 if (rc_test(sc)) 305 goto fail; 306 307 /* 308 * Ok, start actually hooking things up. 309 */ 310 sc->sc_unit = device_get_unit(dev); 311 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/ 312 device_printf(dev, "%d chans, firmware rev. %c\n", 313 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A'); 314 rc = sc->sc_channels; 315 base = CD180_NCHAN * sc->sc_unit; 316 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 317 rc->rc_rcb = sc; 318 rc->rc_chan = chan; 319 rc->rc_iptr = rc->rc_ibuf; 320 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 321 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 322 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 323 rc->rc_dtrwait = 3 * hz; 324 callout_init(&rc->rc_dtrcallout, 0); 325 tp = &rc->rc_tp; 326 ttychars(tp); 327 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 328 tp->t_cflag = TTYDEF_CFLAG; 329 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 330 cdev = make_dev(&rc_cdevsw, chan + base, 331 UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base); 332 cdev->si_drv1 = rc; 333 cdev->si_drv2 = 0; 334 cdev->si_tty = tp; 335 rc->rc_dev = cdev; 336 cdev = make_dev(&rc_cdevsw, chan + base + 128, 337 UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base); 338 cdev->si_drv1 = rc; 339 cdev->si_drv2 = (void *)1; 340 cdev->si_tty = tp; 341 rc->rc_cdev = cdev; 342 } 343 344 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc, 345 &sc->sc_hwicookie); 346 if (error) { 347 device_printf(dev, "failed to register interrupt handler\n"); 348 goto fail; 349 } 350 351 swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0, 352 &sc->sc_swicookie); 353 return (0); 354 355fail: 356 rc_release_resources(dev); 357 return (error); 358} 359 360static int 361rc_detach(device_t dev) 362{ 363 struct rc_softc *sc; 364 struct rc_chans *rc; 365 int error, i, s; 366 367 sc = device_get_softc(dev); 368 if (sc->sc_opencount > 0) 369 return (EBUSY); 370 sc->sc_opencount = -1; 371 372 rc = sc->sc_channels; 373 for (i = 0; i < CD180_NCHAN; i++, rc++) { 374 destroy_dev(rc->rc_dev); 375 destroy_dev(rc->rc_cdev); 376 } 377 378 rc = sc->sc_channels; 379 s = splsoftclock(); 380 for (i = 0; i < CD180_NCHAN; i++) { 381 if ((rc->rc_flags & RC_DTR_OFF) && 382 !callout_stop(&rc->rc_dtrcallout)) 383 tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0); 384 } 385 386 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie); 387 if (error) 388 device_printf(dev, "failed to deregister interrupt handler\n"); 389 ithread_remove_handler(sc->sc_swicookie); 390 rc_release_resources(dev); 391 392 return (0); 393} 394 395static void 396rc_release_resources(device_t dev) 397{ 398 struct rc_softc *sc; 399 int i; 400 401 sc = device_get_softc(dev); 402 if (sc->sc_irq != NULL) { 403 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, 404 sc->sc_irq); 405 sc->sc_irq = NULL; 406 } 407 for (i = 0; i < IOBASE_ADDRS; i++) { 408 if (sc->sc_port[i] == NULL) 409 break; 410 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]); 411 sc->sc_port[i] = NULL; 412 } 413} 414 415/* RC interrupt handling */ 416static void 417rc_intr(void *arg) 418{ 419 struct rc_softc *sc; 420 struct rc_chans *rc; 421 int resid, chan; 422 u_char val, iack, bsr, ucnt, *optr; 423 int good_data, t_state; 424 425 sc = (struct rc_softc *)arg; 426 bsr = ~(rcin(sc, RC_BSR)); 427 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 428 device_printf(sc->sc_dev, "extra interrupt\n"); 429 rcout(sc, CD180_EOIR, 0); 430 return; 431 } 432 433 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 434#ifdef RCDEBUG_DETAILED 435 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr, 436 (bsr & RC_BSR_TOUT)?"TOUT ":"", 437 (bsr & RC_BSR_RXINT)?"RXINT ":"", 438 (bsr & RC_BSR_TXINT)?"TXINT ":"", 439 (bsr & RC_BSR_MOINT)?"MOINT":""); 440#endif 441 if (bsr & RC_BSR_TOUT) { 442 device_printf(sc->sc_dev, 443 "hardware failure, reset board\n"); 444 rcout(sc, RC_CTOUT, 0); 445 rc_reinit(sc); 446 return; 447 } 448 if (bsr & RC_BSR_RXINT) { 449 iack = rcin(sc, RC_PILR_RX); 450 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 451 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 452 device_printf(sc->sc_dev, 453 "fake rxint: %02x\n", iack); 454 goto more_intrs; 455 } 456 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 457 rc = &sc->sc_channels[chan]; 458 t_state = rc->rc_tp.t_state; 459 /* Do RTS flow control stuff */ 460 if ( (rc->rc_flags & RC_RTSFLOW) 461 || !(t_state & TS_ISOPEN) 462 ) { 463 if ( ( !(t_state & TS_ISOPEN) 464 || (t_state & TS_TBLOCK) 465 ) 466 && (rc->rc_msvr & MSVR_RTS) 467 ) 468 rcout(sc, CD180_MSVR, 469 rc->rc_msvr &= ~MSVR_RTS); 470 else if (!(rc->rc_msvr & MSVR_RTS)) 471 rcout(sc, CD180_MSVR, 472 rc->rc_msvr |= MSVR_RTS); 473 } 474 ucnt = rcin(sc, CD180_RDCR) & 0xF; 475 resid = 0; 476 477 if (t_state & TS_ISOPEN) { 478 /* check for input buffer overflow */ 479 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 480 resid = ucnt; 481 ucnt = rc->rc_bufend - rc->rc_iptr; 482 resid -= ucnt; 483 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 484 rc->rc_flags |= RC_WAS_BUFOVFL; 485 sc->sc_scheduled_event++; 486 } 487 } 488 optr = rc->rc_iptr; 489 /* check foor good data */ 490 if (good_data) { 491 while (ucnt-- > 0) { 492 val = rcin(sc, CD180_RDR); 493 optr[0] = val; 494 optr[INPUT_FLAGS_SHIFT] = 0; 495 optr++; 496 sc->sc_scheduled_event++; 497 if (val != 0 && val == rc->rc_hotchar) 498 swi_sched(sc->sc_swicookie, 0); 499 } 500 } else { 501 /* Store also status data */ 502 while (ucnt-- > 0) { 503 iack = rcin(sc, CD180_RCSR); 504 if (iack & RCSR_Timeout) 505 break; 506 if ( (iack & RCSR_OE) 507 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 508 rc->rc_flags |= RC_WAS_SILOVFL; 509 sc->sc_scheduled_event++; 510 } 511 val = rcin(sc, CD180_RDR); 512 /* 513 Don't store PE if IGNPAR and BREAK if IGNBRK, 514 this hack allows "raw" tty optimization 515 works even if IGN* is set. 516 */ 517 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 518 || ((!(iack & (RCSR_PE|RCSR_FE)) 519 || !(rc->rc_tp.t_iflag & IGNPAR)) 520 && (!(iack & RCSR_Break) 521 || !(rc->rc_tp.t_iflag & IGNBRK)))) { 522 if ( (iack & (RCSR_PE|RCSR_FE)) 523 && (t_state & TS_CAN_BYPASS_L_RINT) 524 && ((iack & RCSR_FE) 525 || ((iack & RCSR_PE) 526 && (rc->rc_tp.t_iflag & INPCK)))) 527 val = 0; 528 else if (val != 0 && val == rc->rc_hotchar) 529 swi_sched(sc->sc_swicookie, 0); 530 optr[0] = val; 531 optr[INPUT_FLAGS_SHIFT] = iack; 532 optr++; 533 sc->sc_scheduled_event++; 534 } 535 } 536 } 537 rc->rc_iptr = optr; 538 rc->rc_flags |= RC_DORXFER; 539 } else 540 resid = ucnt; 541 /* Clear FIFO if necessary */ 542 while (resid-- > 0) { 543 if (!good_data) 544 iack = rcin(sc, CD180_RCSR); 545 else 546 iack = 0; 547 if (iack & RCSR_Timeout) 548 break; 549 (void) rcin(sc, CD180_RDR); 550 } 551 goto more_intrs; 552 } 553 if (bsr & RC_BSR_MOINT) { 554 iack = rcin(sc, RC_PILR_MODEM); 555 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 556 device_printf(sc->sc_dev, "fake moint: %02x\n", 557 iack); 558 goto more_intrs; 559 } 560 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 561 rc = &sc->sc_channels[chan]; 562 iack = rcin(sc, CD180_MCR); 563 rc->rc_msvr = rcin(sc, CD180_MSVR); 564 rcout(sc, CD180_MCR, 0); 565#ifdef RCDEBUG 566 printrcflags(rc, "moint"); 567#endif 568 if (rc->rc_flags & RC_CTSFLOW) { 569 if (rc->rc_msvr & MSVR_CTS) 570 rc->rc_flags |= RC_SEND_RDY; 571 else 572 rc->rc_flags &= ~RC_SEND_RDY; 573 } else 574 rc->rc_flags |= RC_SEND_RDY; 575 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 576 sc->sc_scheduled_event += LOTS_OF_EVENTS; 577 rc->rc_flags |= RC_MODCHG; 578 swi_sched(sc->sc_swicookie, 0); 579 } 580 goto more_intrs; 581 } 582 if (bsr & RC_BSR_TXINT) { 583 iack = rcin(sc, RC_PILR_TX); 584 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 585 device_printf(sc->sc_dev, "fake txint: %02x\n", 586 iack); 587 goto more_intrs; 588 } 589 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 590 rc = &sc->sc_channels[chan]; 591 if ( (rc->rc_flags & RC_OSUSP) 592 || !(rc->rc_flags & RC_SEND_RDY) 593 ) 594 goto more_intrs; 595 /* Handle breaks and other stuff */ 596 if (rc->rc_pendcmd) { 597 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC); 598 rcout(sc, CD180_TDR, CD180_C_ESC); 599 rcout(sc, CD180_TDR, rc->rc_pendcmd); 600 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 601 rc->rc_pendcmd = 0; 602 goto more_intrs; 603 } 604 optr = rc->rc_optr; 605 resid = rc->rc_obufend - optr; 606 if (resid > CD180_NFIFO) 607 resid = CD180_NFIFO; 608 while (resid-- > 0) 609 rcout(sc, CD180_TDR, *optr++); 610 rc->rc_optr = optr; 611 612 /* output completed? */ 613 if (optr >= rc->rc_obufend) { 614 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy); 615#ifdef RCDEBUG 616 device_printf(sc->sc_dev, 617 "channel %d: output completed\n", 618 rc->rc_chan); 619#endif 620 if (!(rc->rc_flags & RC_DOXXFER)) { 621 sc->sc_scheduled_event += LOTS_OF_EVENTS; 622 rc->rc_flags |= RC_DOXXFER; 623 swi_sched(sc->sc_swicookie, 0); 624 } 625 } 626 } 627 more_intrs: 628 rcout(sc, CD180_EOIR, 0); /* end of interrupt */ 629 rcout(sc, RC_CTOUT, 0); 630 bsr = ~(rcin(sc, RC_BSR)); 631 } 632} 633 634/* Feed characters to output buffer */ 635static void 636rc_start(struct tty *tp) 637{ 638 struct rc_softc *sc; 639 struct rc_chans *rc; 640 int s; 641 642 rc = TTY_TO_RC(tp); 643 if (rc->rc_flags & RC_OSBUSY) 644 return; 645 sc = rc->rc_rcb; 646 s = spltty(); 647 rc->rc_flags |= RC_OSBUSY; 648 critical_enter(); 649 if (tp->t_state & TS_TTSTOP) 650 rc->rc_flags |= RC_OSUSP; 651 else 652 rc->rc_flags &= ~RC_OSUSP; 653 /* Do RTS flow control stuff */ 654 if ( (rc->rc_flags & RC_RTSFLOW) 655 && (tp->t_state & TS_TBLOCK) 656 && (rc->rc_msvr & MSVR_RTS) 657 ) { 658 rcout(sc, CD180_CAR, rc->rc_chan); 659 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 660 } else if (!(rc->rc_msvr & MSVR_RTS)) { 661 rcout(sc, CD180_CAR, rc->rc_chan); 662 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 663 } 664 critical_exit(); 665 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 666 goto out; 667#ifdef RCDEBUG 668 printrcflags(rc, "rcstart"); 669#endif 670 ttwwakeup(tp); 671#ifdef RCDEBUG 672 printf("rcstart: outq = %d obuf = %d\n", 673 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 674#endif 675 if (tp->t_state & TS_BUSY) 676 goto out; /* output still in progress ... */ 677 678 if (tp->t_outq.c_cc > 0) { 679 u_int ocnt; 680 681 tp->t_state |= TS_BUSY; 682 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 683 critical_enter(); 684 rc->rc_optr = rc->rc_obuf; 685 rc->rc_obufend = rc->rc_optr + ocnt; 686 critical_exit(); 687 if (!(rc->rc_ier & IER_TxRdy)) { 688#ifdef RCDEBUG 689 device_printf(sc->sc_dev, 690 "channel %d: rcstart enable txint\n", rc->rc_chan); 691#endif 692 rcout(sc, CD180_CAR, rc->rc_chan); 693 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy); 694 } 695 } 696out: 697 rc->rc_flags &= ~RC_OSBUSY; 698 (void) splx(s); 699} 700 701/* Handle delayed events. */ 702void 703rc_pollcard(void *arg) 704{ 705 struct rc_softc *sc; 706 struct rc_chans *rc; 707 struct tty *tp; 708 u_char *tptr, *eptr; 709 int chan, icnt; 710 711 sc = (struct rc_softc *)arg; 712 if (sc->sc_scheduled_event == 0) 713 return; 714 do { 715 rc = sc->sc_channels; 716 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 717 tp = &rc->rc_tp; 718#ifdef RCDEBUG 719 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 720 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 721 printrcflags(rc, "rcevent"); 722#endif 723 if (rc->rc_flags & RC_WAS_BUFOVFL) { 724 critical_enter(); 725 rc->rc_flags &= ~RC_WAS_BUFOVFL; 726 sc->sc_scheduled_event--; 727 critical_exit(); 728 device_printf(sc->sc_dev, 729 "channel %d: interrupt-level buffer overflow\n", 730 chan); 731 } 732 if (rc->rc_flags & RC_WAS_SILOVFL) { 733 critical_enter(); 734 rc->rc_flags &= ~RC_WAS_SILOVFL; 735 sc->sc_scheduled_event--; 736 critical_exit(); 737 device_printf(sc->sc_dev, 738 "channel %d: silo overflow\n", chan); 739 } 740 if (rc->rc_flags & RC_MODCHG) { 741 critical_enter(); 742 rc->rc_flags &= ~RC_MODCHG; 743 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 744 critical_exit(); 745 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 746 } 747 if (rc->rc_flags & RC_DORXFER) { 748 critical_enter(); 749 rc->rc_flags &= ~RC_DORXFER; 750 eptr = rc->rc_iptr; 751 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 752 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 753 else 754 tptr = rc->rc_ibuf; 755 icnt = eptr - tptr; 756 if (icnt > 0) { 757 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 758 rc->rc_iptr = rc->rc_ibuf; 759 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 760 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 761 } else { 762 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 763 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 764 rc->rc_hiwat = 765 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 766 } 767 if ( (rc->rc_flags & RC_RTSFLOW) 768 && (tp->t_state & TS_ISOPEN) 769 && !(tp->t_state & TS_TBLOCK) 770 && !(rc->rc_msvr & MSVR_RTS) 771 ) { 772 rcout(sc, CD180_CAR, chan); 773 rcout(sc, CD180_MSVR, 774 rc->rc_msvr |= MSVR_RTS); 775 } 776 sc->sc_scheduled_event -= icnt; 777 } 778 critical_exit(); 779 780 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 781 goto done1; 782 783 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 784 && !(tp->t_state & TS_LOCAL)) { 785 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 786 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 787 && !(tp->t_state & TS_TBLOCK)) 788 ttyblock(tp); 789 tk_nin += icnt; 790 tk_rawcc += icnt; 791 tp->t_rawcc += icnt; 792 if (b_to_q(tptr, icnt, &tp->t_rawq)) 793 device_printf(sc->sc_dev, 794 "channel %d: tty-level buffer overflow\n", 795 chan); 796 ttwakeup(tp); 797 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 798 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 799 tp->t_state &= ~TS_TTSTOP; 800 tp->t_lflag &= ~FLUSHO; 801 rc_start(tp); 802 } 803 } else { 804 for (; tptr < eptr; tptr++) 805 (*linesw[tp->t_line].l_rint) 806 (tptr[0] | 807 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 808 } 809done1: ; 810 } 811 if (rc->rc_flags & RC_DOXXFER) { 812 critical_enter(); 813 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 814 rc->rc_flags &= ~RC_DOXXFER; 815 rc->rc_tp.t_state &= ~TS_BUSY; 816 critical_exit(); 817 (*linesw[tp->t_line].l_start)(tp); 818 } 819 if (sc->sc_scheduled_event == 0) 820 break; 821 } 822 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS); 823} 824 825static void 826rc_stop(struct tty *tp, int rw) 827{ 828 struct rc_softc *sc; 829 struct rc_chans *rc; 830 u_char *tptr, *eptr; 831 832 rc = TTY_TO_RC(tp); 833 sc = rc->rc_rcb; 834#ifdef RCDEBUG 835 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n", 836 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 837#endif 838 if (rw & FWRITE) 839 rc_discard_output(rc); 840 critical_enter(); 841 if (rw & FREAD) { 842 rc->rc_flags &= ~RC_DORXFER; 843 eptr = rc->rc_iptr; 844 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 845 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 846 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 847 } else { 848 tptr = rc->rc_ibuf; 849 rc->rc_iptr = rc->rc_ibuf; 850 } 851 sc->sc_scheduled_event -= eptr - tptr; 852 } 853 if (tp->t_state & TS_TTSTOP) 854 rc->rc_flags |= RC_OSUSP; 855 else 856 rc->rc_flags &= ~RC_OSUSP; 857 critical_exit(); 858} 859 860static int 861rcopen(dev_t dev, int flag, int mode, d_thread_t *td) 862{ 863 struct rc_softc *sc; 864 struct rc_chans *rc; 865 struct tty *tp; 866 int s, error = 0; 867 868 rc = DEV_TO_RC(dev); 869 sc = rc->rc_rcb; 870 tp = &rc->rc_tp; 871 if (sc->sc_opencount < 0) 872 return (ENXIO); 873 sc->sc_opencount++; 874#ifdef RCDEBUG 875 device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n", 876 rc->rc_chan, dev); 877#endif 878 s = spltty(); 879 880again: 881 while (rc->rc_flags & RC_DTR_OFF) { 882 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 883 if (error != 0) 884 goto out; 885 } 886 if (tp->t_state & TS_ISOPEN) { 887 if (CALLOUT(dev)) { 888 if (!(rc->rc_flags & RC_ACTOUT)) { 889 error = EBUSY; 890 goto out; 891 } 892 } else { 893 if (rc->rc_flags & RC_ACTOUT) { 894 if (flag & O_NONBLOCK) { 895 error = EBUSY; 896 goto out; 897 } 898 error = tsleep(&rc->rc_rcb, 899 TTIPRI|PCATCH, "rcbi", 0); 900 if (error) 901 goto out; 902 goto again; 903 } 904 } 905 if (tp->t_state & TS_XCLUDE && 906 suser(td)) { 907 error = EBUSY; 908 goto out; 909 } 910 } else { 911 tp->t_oproc = rc_start; 912 tp->t_param = rc_param; 913 tp->t_stop = rc_stop; 914 tp->t_dev = dev; 915 916 if (CALLOUT(dev)) 917 tp->t_cflag |= CLOCAL; 918 else 919 tp->t_cflag &= ~CLOCAL; 920 921 error = rc_param(tp, &tp->t_termios); 922 if (error) 923 goto out; 924 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 925 926 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 927 (*linesw[tp->t_line].l_modem)(tp, 1); 928 } 929 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 930 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 931 rc->rc_dcdwaits++; 932 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 933 rc->rc_dcdwaits--; 934 if (error != 0) 935 goto out; 936 goto again; 937 } 938 error = (*linesw[tp->t_line].l_open)(dev, tp); 939 disc_optim(tp, &tp->t_termios, rc); 940 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 941 rc->rc_flags |= RC_ACTOUT; 942out: 943 (void) splx(s); 944 945 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 946 rc_hardclose(rc); 947 948 return error; 949} 950 951static int 952rcclose(dev_t dev, int flag, int mode, d_thread_t *td) 953{ 954 struct rc_softc *sc; 955 struct rc_chans *rc; 956 struct tty *tp; 957 int s; 958 959 rc = DEV_TO_RC(dev); 960 sc = rc->rc_rcb; 961 tp = &rc->rc_tp; 962#ifdef RCDEBUG 963 device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n", 964 rc->rc_chan, dev); 965#endif 966 s = spltty(); 967 (*linesw[tp->t_line].l_close)(tp, flag); 968 disc_optim(tp, &tp->t_termios, rc); 969 rc_stop(tp, FREAD | FWRITE); 970 rc_hardclose(rc); 971 ttyclose(tp); 972 splx(s); 973 KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count")); 974 sc->sc_opencount--; 975 return 0; 976} 977 978static void 979rc_hardclose(struct rc_chans *rc) 980{ 981 struct rc_softc *sc; 982 struct tty *tp; 983 int s; 984 985 tp = &rc->rc_tp; 986 sc = rc->rc_rcb; 987 s = spltty(); 988 rcout(sc, CD180_CAR, rc->rc_chan); 989 990 /* Disable rx/tx intrs */ 991 rcout(sc, CD180_IER, rc->rc_ier = 0); 992 if ( (tp->t_cflag & HUPCL) 993 || (!(rc->rc_flags & RC_ACTOUT) 994 && !(rc->rc_msvr & MSVR_CD) 995 && !(tp->t_cflag & CLOCAL)) 996 || !(tp->t_state & TS_ISOPEN) 997 ) { 998 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 999 WAITFORCCR(sc, rc->rc_chan); 1000 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 1001 if (rc->rc_dtrwait) { 1002 callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait, 1003 rc_dtrwakeup, rc); 1004 rc->rc_flags |= RC_DTR_OFF; 1005 } 1006 } 1007 rc->rc_flags &= ~RC_ACTOUT; 1008 wakeup( &rc->rc_rcb); /* wake bi */ 1009 wakeup(TSA_CARR_ON(tp)); 1010 (void) splx(s); 1011} 1012 1013/* Reset the bastard */ 1014static void 1015rc_hwreset(struct rc_softc *sc, u_int chipid) 1016{ 1017 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */ 1018 DELAY(20000); 1019 WAITFORCCR(sc, -1); 1020 1021 rcout(sc, RC_CTOUT, 0); /* Clear timeout */ 1022 rcout(sc, CD180_GIVR, chipid); 1023 rcout(sc, CD180_GICR, 0); 1024 1025 /* Set Prescaler Registers (1 msec) */ 1026 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 1027 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 1028 1029 /* Initialize Priority Interrupt Level Registers */ 1030 rcout(sc, CD180_PILR1, RC_PILR_MODEM); 1031 rcout(sc, CD180_PILR2, RC_PILR_TX); 1032 rcout(sc, CD180_PILR3, RC_PILR_RX); 1033 1034 /* Reset DTR */ 1035 rcout(sc, RC_DTREG, ~0); 1036} 1037 1038/* Set channel parameters */ 1039static int 1040rc_param(struct tty *tp, struct termios *ts) 1041{ 1042 struct rc_softc *sc; 1043 struct rc_chans *rc; 1044 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 1045 1046 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 1047 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 1048 ) 1049 return (EINVAL); 1050 if (ts->c_ispeed == 0) 1051 ts->c_ispeed = ts->c_ospeed; 1052 odivs = RC_BRD(ts->c_ospeed); 1053 idivs = RC_BRD(ts->c_ispeed); 1054 1055 rc = TTY_TO_RC(tp); 1056 sc = rc->rc_rcb; 1057 s = spltty(); 1058 1059 /* Select channel */ 1060 rcout(sc, CD180_CAR, rc->rc_chan); 1061 1062 /* If speed == 0, hangup line */ 1063 if (ts->c_ospeed == 0) { 1064 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 1065 WAITFORCCR(sc, rc->rc_chan); 1066 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1067 } 1068 1069 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1070 cflag = ts->c_cflag; 1071 iflag = ts->c_iflag; 1072 lflag = ts->c_lflag; 1073 1074 if (idivs > 0) { 1075 rcout(sc, CD180_RBPRL, idivs & 0xFF); 1076 rcout(sc, CD180_RBPRH, idivs >> 8); 1077 } 1078 if (odivs > 0) { 1079 rcout(sc, CD180_TBPRL, odivs & 0xFF); 1080 rcout(sc, CD180_TBPRH, odivs >> 8); 1081 } 1082 1083 /* set timeout value */ 1084 if (ts->c_ispeed > 0) { 1085 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 1086 1087 if ( !(lflag & ICANON) 1088 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1089 && ts->c_cc[VTIME] * 10 > itm) 1090 itm = ts->c_cc[VTIME] * 10; 1091 1092 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255); 1093 } 1094 1095 switch (cflag & CSIZE) { 1096 case CS5: val = COR1_5BITS; break; 1097 case CS6: val = COR1_6BITS; break; 1098 case CS7: val = COR1_7BITS; break; 1099 default: 1100 case CS8: val = COR1_8BITS; break; 1101 } 1102 if (cflag & PARENB) { 1103 val |= COR1_NORMPAR; 1104 if (cflag & PARODD) 1105 val |= COR1_ODDP; 1106 if (!(cflag & INPCK)) 1107 val |= COR1_Ignore; 1108 } else 1109 val |= COR1_Ignore; 1110 if (cflag & CSTOPB) 1111 val |= COR1_2SB; 1112 rcout(sc, CD180_COR1, val); 1113 1114 /* Set FIFO threshold */ 1115 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1116 inpflow = 0; 1117 if ( (iflag & IXOFF) 1118 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1119 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1120 || (iflag & IXANY) 1121 ) 1122 ) 1123 ) { 1124 inpflow = 1; 1125 val |= COR3_SCDE|COR3_FCT; 1126 } 1127 rcout(sc, CD180_COR3, val); 1128 1129 /* Initialize on-chip automatic flow control */ 1130 val = 0; 1131 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1132 if (cflag & CCTS_OFLOW) { 1133 rc->rc_flags |= RC_CTSFLOW; 1134 val |= COR2_CtsAE; 1135 } else 1136 rc->rc_flags |= RC_SEND_RDY; 1137 if (tp->t_state & TS_TTSTOP) 1138 rc->rc_flags |= RC_OSUSP; 1139 else 1140 rc->rc_flags &= ~RC_OSUSP; 1141 if (cflag & CRTS_IFLOW) 1142 rc->rc_flags |= RC_RTSFLOW; 1143 else 1144 rc->rc_flags &= ~RC_RTSFLOW; 1145 1146 if (inpflow) { 1147 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1148 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]); 1149 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]); 1150 val |= COR2_TxIBE; 1151 if (iflag & IXANY) 1152 val |= COR2_IXM; 1153 } 1154 1155 rcout(sc, CD180_COR2, rc->rc_cor2 = val); 1156 1157 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1158 1159 disc_optim(tp, ts, rc); 1160 1161 /* modem ctl */ 1162 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1163 if (cflag & CCTS_OFLOW) 1164 val |= MCOR1_CTSzd; 1165 rcout(sc, CD180_MCOR1, val); 1166 1167 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1168 if (cflag & CCTS_OFLOW) 1169 val |= MCOR2_CTSod; 1170 rcout(sc, CD180_MCOR2, val); 1171 1172 /* enable i/o and interrupts */ 1173 CCRCMD(sc, rc->rc_chan, 1174 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1175 WAITFORCCR(sc, rc->rc_chan); 1176 1177 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1178 if (cflag & CCTS_OFLOW) 1179 rc->rc_ier |= IER_CTS; 1180 if (cflag & CREAD) 1181 rc->rc_ier |= IER_RxData; 1182 if (tp->t_state & TS_BUSY) 1183 rc->rc_ier |= IER_TxRdy; 1184 if (ts->c_ospeed != 0) 1185 rc_modctl(rc, TIOCM_DTR, DMBIS); 1186 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1187 rc->rc_flags |= RC_SEND_RDY; 1188 rcout(sc, CD180_IER, rc->rc_ier); 1189 (void) splx(s); 1190 return 0; 1191} 1192 1193/* Re-initialize board after bogus interrupts */ 1194static void 1195rc_reinit(struct rc_softc *sc) 1196{ 1197 struct rc_chans *rc; 1198 int i; 1199 1200 rc_hwreset(sc, RC_FAKEID); 1201 rc = sc->sc_channels; 1202 for (i = 0; i < CD180_NCHAN; i++, rc++) 1203 (void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios); 1204} 1205 1206static int 1207rcioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td) 1208{ 1209 struct rc_chans *rc; 1210 struct tty *tp; 1211 int s, error; 1212 1213 rc = DEV_TO_RC(dev); 1214 tp = &rc->rc_tp; 1215 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1216 if (error != ENOIOCTL) 1217 return (error); 1218 error = ttioctl(tp, cmd, data, flag); 1219 disc_optim(tp, &tp->t_termios, rc); 1220 if (error != ENOIOCTL) 1221 return (error); 1222 s = spltty(); 1223 1224 switch (cmd) { 1225 case TIOCSBRK: 1226 rc->rc_pendcmd = CD180_C_SBRK; 1227 break; 1228 1229 case TIOCCBRK: 1230 rc->rc_pendcmd = CD180_C_EBRK; 1231 break; 1232 1233 case TIOCSDTR: 1234 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1235 break; 1236 1237 case TIOCCDTR: 1238 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1239 break; 1240 1241 case TIOCMGET: 1242 *(int *) data = rc_modctl(rc, 0, DMGET); 1243 break; 1244 1245 case TIOCMSET: 1246 (void) rc_modctl(rc, *(int *) data, DMSET); 1247 break; 1248 1249 case TIOCMBIC: 1250 (void) rc_modctl(rc, *(int *) data, DMBIC); 1251 break; 1252 1253 case TIOCMBIS: 1254 (void) rc_modctl(rc, *(int *) data, DMBIS); 1255 break; 1256 1257 case TIOCMSDTRWAIT: 1258 error = suser(td); 1259 if (error != 0) { 1260 splx(s); 1261 return (error); 1262 } 1263 rc->rc_dtrwait = *(int *)data * hz / 100; 1264 break; 1265 1266 case TIOCMGDTRWAIT: 1267 *(int *)data = rc->rc_dtrwait * 100 / hz; 1268 break; 1269 1270 default: 1271 (void) splx(s); 1272 return ENOTTY; 1273 } 1274 (void) splx(s); 1275 return 0; 1276} 1277 1278 1279/* Modem control routines */ 1280 1281static int 1282rc_modctl(struct rc_chans *rc, int bits, int cmd) 1283{ 1284 struct rc_softc *sc; 1285 u_char *dtr; 1286 u_char msvr; 1287 1288 sc = rc->rc_rcb; 1289 dtr = &sc->sc_dtr; 1290 rcout(sc, CD180_CAR, rc->rc_chan); 1291 1292 switch (cmd) { 1293 case DMSET: 1294 rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ? 1295 ~(*dtr |= 1 << rc->rc_chan) : 1296 ~(*dtr &= ~(1 << rc->rc_chan))); 1297 msvr = rcin(sc, CD180_MSVR); 1298 if (bits & TIOCM_RTS) 1299 msvr |= MSVR_RTS; 1300 else 1301 msvr &= ~MSVR_RTS; 1302 if (bits & TIOCM_DTR) 1303 msvr |= MSVR_DTR; 1304 else 1305 msvr &= ~MSVR_DTR; 1306 rcout(sc, CD180_MSVR, msvr); 1307 break; 1308 1309 case DMBIS: 1310 if (bits & TIOCM_DTR) 1311 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1312 msvr = rcin(sc, CD180_MSVR); 1313 if (bits & TIOCM_RTS) 1314 msvr |= MSVR_RTS; 1315 if (bits & TIOCM_DTR) 1316 msvr |= MSVR_DTR; 1317 rcout(sc, CD180_MSVR, msvr); 1318 break; 1319 1320 case DMGET: 1321 bits = TIOCM_LE; 1322 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR); 1323 1324 if (msvr & MSVR_RTS) 1325 bits |= TIOCM_RTS; 1326 if (msvr & MSVR_CTS) 1327 bits |= TIOCM_CTS; 1328 if (msvr & MSVR_DSR) 1329 bits |= TIOCM_DSR; 1330 if (msvr & MSVR_DTR) 1331 bits |= TIOCM_DTR; 1332 if (msvr & MSVR_CD) 1333 bits |= TIOCM_CD; 1334 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan)) 1335 bits |= TIOCM_RI; 1336 return bits; 1337 1338 case DMBIC: 1339 if (bits & TIOCM_DTR) 1340 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1341 msvr = rcin(sc, CD180_MSVR); 1342 if (bits & TIOCM_RTS) 1343 msvr &= ~MSVR_RTS; 1344 if (bits & TIOCM_DTR) 1345 msvr &= ~MSVR_DTR; 1346 rcout(sc, CD180_MSVR, msvr); 1347 break; 1348 } 1349 rc->rc_msvr = rcin(sc, CD180_MSVR); 1350 return 0; 1351} 1352 1353#define ERR(s) do { \ 1354 device_printf(sc->sc_dev, "%s", ""); \ 1355 printf s ; \ 1356 printf("\n"); \ 1357 (void) splx(old_level); \ 1358 return 1; \ 1359} while (0) 1360 1361/* Test the board. */ 1362int 1363rc_test(struct rc_softc *sc) 1364{ 1365 int chan = 0; 1366 int i = 0, rcnt, old_level; 1367 unsigned int iack, chipid; 1368 unsigned short divs; 1369 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1370#define CTLEN 8 1371 1372 struct rtest { 1373 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1374 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1375 int rxptr; /* RX pointer */ 1376 int txptr; /* TX pointer */ 1377 } tchans[CD180_NCHAN]; 1378 1379 old_level = spltty(); 1380 1381 chipid = RC_FAKEID; 1382 1383 /* First, reset board to inital state */ 1384 rc_hwreset(sc, chipid); 1385 1386 divs = RC_BRD(19200); 1387 1388 /* Initialize channels */ 1389 for (chan = 0; chan < CD180_NCHAN; chan++) { 1390 1391 /* Select and reset channel */ 1392 rcout(sc, CD180_CAR, chan); 1393 CCRCMD(sc, chan, CCR_ResetChan); 1394 WAITFORCCR(sc, chan); 1395 1396 /* Set speed */ 1397 rcout(sc, CD180_RBPRL, divs & 0xFF); 1398 rcout(sc, CD180_RBPRH, divs >> 8); 1399 rcout(sc, CD180_TBPRL, divs & 0xFF); 1400 rcout(sc, CD180_TBPRH, divs >> 8); 1401 1402 /* set timeout value */ 1403 rcout(sc, CD180_RTPR, 0); 1404 1405 /* Establish local loopback */ 1406 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1407 rcout(sc, CD180_COR2, COR2_LLM); 1408 rcout(sc, CD180_COR3, CD180_NFIFO); 1409 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1410 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN); 1411 WAITFORCCR(sc, chan); 1412 rcout(sc, CD180_MSVR, MSVR_RTS); 1413 1414 /* Fill TXBUF with test data */ 1415 for (i = 0; i < CD180_NFIFO; i++) { 1416 tchans[chan].txbuf[i] = ctest[i]; 1417 tchans[chan].rxbuf[i] = 0; 1418 } 1419 tchans[chan].txptr = tchans[chan].rxptr = 0; 1420 1421 /* Now, start transmit */ 1422 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData); 1423 } 1424 /* Pseudo-interrupt poll stuff */ 1425 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1426 i = ~(rcin(sc, RC_BSR)); 1427 if (i & RC_BSR_TOUT) 1428 ERR(("BSR timeout bit set\n")); 1429 else if (i & RC_BSR_TXINT) { 1430 iack = rcin(sc, RC_PILR_TX); 1431 if (iack != (GIVR_IT_TDI | chipid)) 1432 ERR(("Bad TX intr ack (%02x != %02x)\n", 1433 iack, GIVR_IT_TDI | chipid)); 1434 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1435 /* If no more data to transmit, disable TX intr */ 1436 if (tchans[chan].txptr >= CD180_NFIFO) { 1437 iack = rcin(sc, CD180_IER); 1438 rcout(sc, CD180_IER, iack & ~IER_TxMpty); 1439 } else { 1440 for (iack = tchans[chan].txptr; 1441 iack < CD180_NFIFO; iack++) 1442 rcout(sc, CD180_TDR, 1443 tchans[chan].txbuf[iack]); 1444 tchans[chan].txptr = iack; 1445 } 1446 rcout(sc, CD180_EOIR, 0); 1447 } else if (i & RC_BSR_RXINT) { 1448 u_char ucnt; 1449 1450 iack = rcin(sc, RC_PILR_RX); 1451 if (iack != (GIVR_IT_RGDI | chipid) && 1452 iack != (GIVR_IT_REI | chipid)) 1453 ERR(("Bad RX intr ack (%02x != %02x)\n", 1454 iack, GIVR_IT_RGDI | chipid)); 1455 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1456 ucnt = rcin(sc, CD180_RDCR) & 0xF; 1457 while (ucnt-- > 0) { 1458 iack = rcin(sc, CD180_RCSR); 1459 if (iack & RCSR_Timeout) 1460 break; 1461 if (iack & 0xF) 1462 ERR(("Bad char chan %d (RCSR = %02X)\n", 1463 chan, iack)); 1464 if (tchans[chan].rxptr > CD180_NFIFO) 1465 ERR(("Got extra chars chan %d\n", 1466 chan)); 1467 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1468 rcin(sc, CD180_RDR); 1469 } 1470 rcout(sc, CD180_EOIR, 0); 1471 } 1472 rcout(sc, RC_CTOUT, 0); 1473 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1474 if (tchans[chan].rxptr >= CD180_NFIFO) 1475 iack++; 1476 if (iack == CD180_NCHAN) 1477 break; 1478 } 1479 for (chan = 0; chan < CD180_NCHAN; chan++) { 1480 /* Select and reset channel */ 1481 rcout(sc, CD180_CAR, chan); 1482 CCRCMD(sc, chan, CCR_ResetChan); 1483 } 1484 1485 if (!rcnt) 1486 ERR(("looses characters during local loopback\n")); 1487 /* Now, check data */ 1488 for (chan = 0; chan < CD180_NCHAN; chan++) 1489 for (i = 0; i < CD180_NFIFO; i++) 1490 if (ctest[i] != tchans[chan].rxbuf[i]) 1491 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1492 chan, i, ctest[i], tchans[chan].rxbuf[i])); 1493 (void) splx(old_level); 1494 return 0; 1495} 1496 1497#ifdef RCDEBUG 1498static void 1499printrcflags(struct rc_chans *rc, char *comment) 1500{ 1501 struct rc_softc *sc; 1502 u_short f = rc->rc_flags; 1503 1504 sc = rc->rc_rcb; 1505 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1506 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1507 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1508 (f & RC_ACTOUT) ?"ACTOUT " :"", 1509 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1510 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1511 (f & RC_DORXFER)?"DORXFER " :"", 1512 (f & RC_DOXXFER)?"DOXXFER " :"", 1513 (f & RC_MODCHG) ?"MODCHG " :"", 1514 (f & RC_OSUSP) ?"OSUSP " :"", 1515 (f & RC_OSBUSY) ?"OSBUSY " :"", 1516 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1517 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1518 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1519 1520 rcout(sc, CD180_CAR, rc->rc_chan); 1521 1522 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1523 rc->rc_rcb->rcb_unit, rc->rc_chan, 1524 rcin(sc, CD180_MSVR), 1525 rcin(sc, CD180_IER), 1526 rcin(sc, CD180_CCSR)); 1527} 1528#endif /* RCDEBUG */ 1529 1530static void 1531rc_dtrwakeup(void *arg) 1532{ 1533 struct rc_chans *rc; 1534 1535 rc = (struct rc_chans *)arg; 1536 rc->rc_flags &= ~RC_DTR_OFF; 1537 wakeup(&rc->rc_dtrwait); 1538} 1539 1540static void 1541rc_discard_output(struct rc_chans *rc) 1542{ 1543 critical_enter(); 1544 if (rc->rc_flags & RC_DOXXFER) { 1545 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS; 1546 rc->rc_flags &= ~RC_DOXXFER; 1547 } 1548 rc->rc_optr = rc->rc_obufend; 1549 rc->rc_tp.t_state &= ~TS_BUSY; 1550 critical_exit(); 1551 ttwwakeup(&rc->rc_tp); 1552} 1553 1554static void 1555disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc) 1556{ 1557 1558 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1559 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1560 && (!(t->c_iflag & PARMRK) 1561 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1562 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1563 && linesw[tp->t_line].l_rint == ttyinput) 1564 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1565 else 1566 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1567 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1568} 1569 1570static void 1571rc_wait0(struct rc_softc *sc, int chan, int line) 1572{ 1573 int rcnt; 1574 1575 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--) 1576 DELAY(30); 1577 if (rcnt == 0) 1578 device_printf(sc->sc_dev, 1579 "channel %d command timeout, rc.c line: %d\n", chan, line); 1580} 1581 1582static device_method_t rc_methods[] = { 1583 /* Device interface */ 1584 DEVMETHOD(device_probe, rc_probe), 1585 DEVMETHOD(device_attach, rc_attach), 1586 DEVMETHOD(device_detach, rc_detach), 1587 { 0, 0 } 1588}; 1589 1590static driver_t rc_driver = { 1591 "rc", 1592 rc_methods, sizeof(struct rc_softc), 1593}; 1594 1595DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0); 1596