rc.c revision 111821
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/rc/rc.c 111821 2003-03-03 16:24:47Z phk $ 29 */ 30 31/* 32 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 33 * 34 */ 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/conf.h> 42#include <sys/fcntl.h> 43#include <sys/interrupt.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/tty.h> 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/rman.h> 50 51#include <dev/ic/cd180.h> 52#include <dev/rc/rcreg.h> 53#include <isa/isavar.h> 54 55#define IOBASE_ADDRS 14 56 57#define DEV_TO_RC(dev) (struct rc_chans *)((dev)->si_drv1) 58#define TTY_TO_RC(tty) DEV_TO_RC((tty)->t_dev) 59 60#define rcin(sc, port) RC_IN(sc, port) 61#define rcout(sc, port, v) RC_OUT(sc, port, v) 62 63#define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__) 64 65#define CCRCMD(sc, chan, cmd) do { \ 66 WAITFORCCR((sc), (chan)); \ 67 rcout((sc), CD180_CCR, (cmd)); \ 68} while (0) 69 70#define RC_IBUFSIZE 256 71#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 72#define RC_OBUFSIZE 512 73#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 74#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 75#define LOTS_OF_EVENTS 64 76 77#define RC_FAKEID 0x10 78 79#define CALLOUT(dev) (((intptr_t)(dev)->si_drv2) != 0) 80 81/* Per-channel structure */ 82struct rc_chans { 83 struct rc_softc *rc_rcb; /* back ptr */ 84 dev_t rc_dev; /* non-callout device */ 85 dev_t rc_cdev; /* callout device */ 86 u_short rc_flags; /* Misc. flags */ 87 int rc_chan; /* Channel # */ 88 u_char rc_ier; /* intr. enable reg */ 89 u_char rc_msvr; /* modem sig. status */ 90 u_char rc_cor2; /* options reg */ 91 u_char rc_pendcmd; /* special cmd pending */ 92 u_int rc_dtrwait; /* dtr timeout */ 93 u_int rc_dcdwaits; /* how many waits DCD in open */ 94 u_char rc_hotchar; /* end packed optimize */ 95 struct tty rc_tp; /* tty struct */ 96 u_char *rc_iptr; /* Chars input buffer */ 97 u_char *rc_hiwat; /* hi-water mark */ 98 u_char *rc_bufend; /* end of buffer */ 99 u_char *rc_optr; /* ptr in output buf */ 100 u_char *rc_obufend; /* end of output buf */ 101 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 102 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 103 struct callout rc_dtrcallout; 104}; 105 106/* Per-board structure */ 107struct rc_softc { 108 device_t sc_dev; 109 struct resource *sc_irq; 110 struct resource *sc_port[IOBASE_ADDRS]; 111 int sc_irqrid; 112 void *sc_hwicookie; 113 bus_space_tag_t sc_bt; 114 bus_space_handle_t sc_bh; 115 u_int sc_unit; /* unit # */ 116 u_char sc_dtr; /* DTR status */ 117 int sc_opencount; 118 int sc_scheduled_event; 119 void *sc_swicookie; 120 struct rc_chans sc_channels[CD180_NCHAN]; /* channels */ 121}; 122 123/* Static prototypes */ 124static void rc_release_resources(device_t dev); 125static void rc_intr(void *); 126static void rc_hwreset(struct rc_softc *, unsigned int); 127static int rc_test(struct rc_softc *); 128static void rc_discard_output(struct rc_chans *); 129static void rc_hardclose(struct rc_chans *); 130static int rc_modctl(struct rc_chans *, int, int); 131static void rc_start(struct tty *); 132static void rc_stop(struct tty *, int rw); 133static int rc_param(struct tty *, struct termios *); 134static void rc_pollcard(void *); 135static void rc_reinit(struct rc_softc *); 136#ifdef RCDEBUG 137static void printrcflags(); 138#endif 139static void rc_dtrwakeup(void *); 140static void disc_optim(struct tty *tp, struct termios *t, struct rc_chans *); 141static void rc_wait0(struct rc_softc *sc, int chan, int line); 142 143static d_open_t rcopen; 144static d_close_t rcclose; 145static d_ioctl_t rcioctl; 146 147#define CDEV_MAJOR 63 148static struct cdevsw rc_cdevsw = { 149 .d_open = rcopen, 150 .d_close = rcclose, 151 .d_read = ttyread, 152 .d_write = ttywrite, 153 .d_ioctl = rcioctl, 154 .d_poll = ttypoll, 155 .d_name = "rc", 156 .d_maj = CDEV_MAJOR, 157 .d_flags = D_TTY, 158 .d_kqfilter = ttykqfilter, 159}; 160 161static devclass_t rc_devclass; 162 163/* Flags */ 164#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 165#define RC_ACTOUT 0x0002 /* Dial-out port active */ 166#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 167#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 168#define RC_DORXFER 0x0010 /* RXFER event planned */ 169#define RC_DOXXFER 0x0020 /* XXFER event planned */ 170#define RC_MODCHG 0x0040 /* Modem status changed */ 171#define RC_OSUSP 0x0080 /* Output suspended */ 172#define RC_OSBUSY 0x0100 /* start() routine in progress */ 173#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 174#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 175#define RC_SEND_RDY 0x0800 /* ready to send */ 176 177/* Table for translation of RCSR status bits to internal form */ 178static int rc_rcsrt[16] = { 179 0, TTY_OE, TTY_FE, 180 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 181 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 182 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 183 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 184 TTY_BI|TTY_PE|TTY_FE|TTY_OE 185}; 186 187static int rc_ports[] = 188 { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 }; 189static int iobase_addrs[IOBASE_ADDRS] = 190 { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000, 191 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 }; 192 193/**********************************************/ 194 195static int 196rc_probe(device_t dev) 197{ 198 u_int port; 199 int i, found; 200 201 /* 202 * We don't know of any PnP ID's for these cards. 203 */ 204 if (isa_get_logicalid(dev) != 0) 205 return (ENXIO); 206 207 /* 208 * We have to have an IO port hint that is valid. 209 */ 210 port = isa_get_port(dev); 211 if (port == -1) 212 return (ENXIO); 213 found = 0; 214 for (i = 0; i < sizeof(rc_ports) / sizeof(int); i++) 215 if (rc_ports[i] == port) { 216 found = 1; 217 break; 218 } 219 if (!found) 220 return (ENXIO); 221 222 /* 223 * We have to have an IRQ hint. 224 */ 225 if (isa_get_irq(dev) == -1) 226 return (ENXIO); 227 228 device_set_desc(dev, "SDL Riscom/8"); 229 return (0); 230} 231 232static int 233rc_attach(device_t dev) 234{ 235 struct rc_chans *rc; 236 struct tty *tp; 237 struct rc_softc *sc; 238 u_int port; 239 int base, chan, error, i, x; 240 dev_t cdev; 241 242 sc = device_get_softc(dev); 243 sc->sc_dev = dev; 244 245 /* 246 * We need to have IO ports. Lots of them. We need 247 * the following ranges relative to the base port: 248 * 0x0 - 0x10 249 * 0x400 - 0x410 250 * 0x800 - 0x810 251 * 0xc00 - 0xc10 252 * 0x1400 - 0x1410 253 * 0x1800 - 0x1810 254 * 0x1c00 - 0x1c10 255 * 0x2000 - 0x2010 256 * 0x3000 - 0x3010 257 * 0x3400 - 0x3410 258 * 0x3800 - 0x3810 259 * 0x3c00 - 0x3c10 260 * 0x4000 - 0x4010 261 * 0x8000 - 0x8010 262 */ 263 port = isa_get_port(dev); 264 for (i = 0; i < IOBASE_ADDRS; i++) 265 if (bus_set_resource(dev, SYS_RES_IOPORT, i, 266 port + iobase_addrs[i], 0x10) != 0) 267 return (ENXIO); 268 error = ENOMEM; 269 for (i = 0; i < IOBASE_ADDRS; i++) { 270 x = i; 271 sc->sc_port[i] = bus_alloc_resource(dev, SYS_RES_IOPORT, &x, 272 0ul, ~0ul, 0x10, RF_ACTIVE); 273 if (x != i) { 274 device_printf(dev, "ioport %d was rid %d\n", i, x); 275 goto fail; 276 } 277 if (sc->sc_port[i] == NULL) { 278 device_printf(dev, "failed to alloc ioports %x-%x\n", 279 port + iobase_addrs[i], 280 port + iobase_addrs[i] + 0x10); 281 goto fail; 282 } 283 } 284 sc->sc_bt = rman_get_bustag(sc->sc_port[0]); 285 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]); 286 287 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irqrid, 288 0ul, ~0ul, 1, RF_ACTIVE); 289 if (sc->sc_irq == NULL) { 290 device_printf(dev, "failed to alloc IRQ\n"); 291 goto fail; 292 } 293 294 /* 295 * Now do some actual tests to make sure it works. 296 */ 297 error = ENXIO; 298 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 299 rcout(sc, CD180_PPRH, 0x11); 300 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11) 301 goto fail; 302 if (rc_test(sc)) 303 goto fail; 304 305 /* 306 * Ok, start actually hooking things up. 307 */ 308 sc->sc_unit = device_get_unit(dev); 309 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/ 310 device_printf(dev, "%d chans, firmware rev. %c\n", 311 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A'); 312 rc = sc->sc_channels; 313 base = CD180_NCHAN * sc->sc_unit; 314 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 315 rc->rc_rcb = sc; 316 rc->rc_chan = chan; 317 rc->rc_iptr = rc->rc_ibuf; 318 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 319 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 320 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 321 rc->rc_dtrwait = 3 * hz; 322 callout_init(&rc->rc_dtrcallout, 0); 323 tp = &rc->rc_tp; 324 ttychars(tp); 325 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 326 tp->t_cflag = TTYDEF_CFLAG; 327 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 328 cdev = make_dev(&rc_cdevsw, chan + base, 329 UID_ROOT, GID_WHEEL, 0600, "ttym%d", chan + base); 330 cdev->si_drv1 = rc; 331 cdev->si_drv2 = 0; 332 cdev->si_tty = tp; 333 rc->rc_dev = cdev; 334 cdev = make_dev(&rc_cdevsw, chan + base + 128, 335 UID_UUCP, GID_DIALER, 0660, "cuam%d", chan + base); 336 cdev->si_drv1 = rc; 337 cdev->si_drv2 = (void *)1; 338 cdev->si_tty = tp; 339 rc->rc_cdev = cdev; 340 } 341 342 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, rc_intr, sc, 343 &sc->sc_hwicookie); 344 if (error) { 345 device_printf(dev, "failed to register interrupt handler\n"); 346 goto fail; 347 } 348 349 swi_add(&tty_ithd, "tty:rc", rc_pollcard, sc, SWI_TTY, 0, 350 &sc->sc_swicookie); 351 return (0); 352 353fail: 354 rc_release_resources(dev); 355 return (error); 356} 357 358static int 359rc_detach(device_t dev) 360{ 361 struct rc_softc *sc; 362 struct rc_chans *rc; 363 int error, i, s; 364 365 sc = device_get_softc(dev); 366 if (sc->sc_opencount > 0) 367 return (EBUSY); 368 sc->sc_opencount = -1; 369 370 rc = sc->sc_channels; 371 for (i = 0; i < CD180_NCHAN; i++, rc++) { 372 destroy_dev(rc->rc_dev); 373 destroy_dev(rc->rc_cdev); 374 } 375 376 rc = sc->sc_channels; 377 s = splsoftclock(); 378 for (i = 0; i < CD180_NCHAN; i++) { 379 if ((rc->rc_flags & RC_DTR_OFF) && 380 !callout_stop(&rc->rc_dtrcallout)) 381 tsleep(&rc->rc_dtrwait, TTIPRI, "rcdtrdet", 0); 382 } 383 384 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie); 385 if (error) 386 device_printf(dev, "failed to deregister interrupt handler\n"); 387 ithread_remove_handler(sc->sc_swicookie); 388 rc_release_resources(dev); 389 390 return (0); 391} 392 393static void 394rc_release_resources(device_t dev) 395{ 396 struct rc_softc *sc; 397 int i; 398 399 sc = device_get_softc(dev); 400 if (sc->sc_irq != NULL) { 401 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, 402 sc->sc_irq); 403 sc->sc_irq = NULL; 404 } 405 for (i = 0; i < IOBASE_ADDRS; i++) { 406 if (sc->sc_port[i] == NULL) 407 break; 408 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]); 409 sc->sc_port[i] = NULL; 410 } 411} 412 413/* RC interrupt handling */ 414static void 415rc_intr(void *arg) 416{ 417 struct rc_softc *sc; 418 struct rc_chans *rc; 419 int resid, chan; 420 u_char val, iack, bsr, ucnt, *optr; 421 int good_data, t_state; 422 423 sc = (struct rc_softc *)arg; 424 bsr = ~(rcin(sc, RC_BSR)); 425 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 426 device_printf(sc->sc_dev, "extra interrupt\n"); 427 rcout(sc, CD180_EOIR, 0); 428 return; 429 } 430 431 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 432#ifdef RCDEBUG_DETAILED 433 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr, 434 (bsr & RC_BSR_TOUT)?"TOUT ":"", 435 (bsr & RC_BSR_RXINT)?"RXINT ":"", 436 (bsr & RC_BSR_TXINT)?"TXINT ":"", 437 (bsr & RC_BSR_MOINT)?"MOINT":""); 438#endif 439 if (bsr & RC_BSR_TOUT) { 440 device_printf(sc->sc_dev, 441 "hardware failure, reset board\n"); 442 rcout(sc, RC_CTOUT, 0); 443 rc_reinit(sc); 444 return; 445 } 446 if (bsr & RC_BSR_RXINT) { 447 iack = rcin(sc, RC_PILR_RX); 448 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 449 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 450 device_printf(sc->sc_dev, 451 "fake rxint: %02x\n", iack); 452 goto more_intrs; 453 } 454 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 455 rc = &sc->sc_channels[chan]; 456 t_state = rc->rc_tp.t_state; 457 /* Do RTS flow control stuff */ 458 if ( (rc->rc_flags & RC_RTSFLOW) 459 || !(t_state & TS_ISOPEN) 460 ) { 461 if ( ( !(t_state & TS_ISOPEN) 462 || (t_state & TS_TBLOCK) 463 ) 464 && (rc->rc_msvr & MSVR_RTS) 465 ) 466 rcout(sc, CD180_MSVR, 467 rc->rc_msvr &= ~MSVR_RTS); 468 else if (!(rc->rc_msvr & MSVR_RTS)) 469 rcout(sc, CD180_MSVR, 470 rc->rc_msvr |= MSVR_RTS); 471 } 472 ucnt = rcin(sc, CD180_RDCR) & 0xF; 473 resid = 0; 474 475 if (t_state & TS_ISOPEN) { 476 /* check for input buffer overflow */ 477 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 478 resid = ucnt; 479 ucnt = rc->rc_bufend - rc->rc_iptr; 480 resid -= ucnt; 481 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 482 rc->rc_flags |= RC_WAS_BUFOVFL; 483 sc->sc_scheduled_event++; 484 } 485 } 486 optr = rc->rc_iptr; 487 /* check foor good data */ 488 if (good_data) { 489 while (ucnt-- > 0) { 490 val = rcin(sc, CD180_RDR); 491 optr[0] = val; 492 optr[INPUT_FLAGS_SHIFT] = 0; 493 optr++; 494 sc->sc_scheduled_event++; 495 if (val != 0 && val == rc->rc_hotchar) 496 swi_sched(sc->sc_swicookie, 0); 497 } 498 } else { 499 /* Store also status data */ 500 while (ucnt-- > 0) { 501 iack = rcin(sc, CD180_RCSR); 502 if (iack & RCSR_Timeout) 503 break; 504 if ( (iack & RCSR_OE) 505 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 506 rc->rc_flags |= RC_WAS_SILOVFL; 507 sc->sc_scheduled_event++; 508 } 509 val = rcin(sc, CD180_RDR); 510 /* 511 Don't store PE if IGNPAR and BREAK if IGNBRK, 512 this hack allows "raw" tty optimization 513 works even if IGN* is set. 514 */ 515 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 516 || ((!(iack & (RCSR_PE|RCSR_FE)) 517 || !(rc->rc_tp.t_iflag & IGNPAR)) 518 && (!(iack & RCSR_Break) 519 || !(rc->rc_tp.t_iflag & IGNBRK)))) { 520 if ( (iack & (RCSR_PE|RCSR_FE)) 521 && (t_state & TS_CAN_BYPASS_L_RINT) 522 && ((iack & RCSR_FE) 523 || ((iack & RCSR_PE) 524 && (rc->rc_tp.t_iflag & INPCK)))) 525 val = 0; 526 else if (val != 0 && val == rc->rc_hotchar) 527 swi_sched(sc->sc_swicookie, 0); 528 optr[0] = val; 529 optr[INPUT_FLAGS_SHIFT] = iack; 530 optr++; 531 sc->sc_scheduled_event++; 532 } 533 } 534 } 535 rc->rc_iptr = optr; 536 rc->rc_flags |= RC_DORXFER; 537 } else 538 resid = ucnt; 539 /* Clear FIFO if necessary */ 540 while (resid-- > 0) { 541 if (!good_data) 542 iack = rcin(sc, CD180_RCSR); 543 else 544 iack = 0; 545 if (iack & RCSR_Timeout) 546 break; 547 (void) rcin(sc, CD180_RDR); 548 } 549 goto more_intrs; 550 } 551 if (bsr & RC_BSR_MOINT) { 552 iack = rcin(sc, RC_PILR_MODEM); 553 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 554 device_printf(sc->sc_dev, "fake moint: %02x\n", 555 iack); 556 goto more_intrs; 557 } 558 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 559 rc = &sc->sc_channels[chan]; 560 iack = rcin(sc, CD180_MCR); 561 rc->rc_msvr = rcin(sc, CD180_MSVR); 562 rcout(sc, CD180_MCR, 0); 563#ifdef RCDEBUG 564 printrcflags(rc, "moint"); 565#endif 566 if (rc->rc_flags & RC_CTSFLOW) { 567 if (rc->rc_msvr & MSVR_CTS) 568 rc->rc_flags |= RC_SEND_RDY; 569 else 570 rc->rc_flags &= ~RC_SEND_RDY; 571 } else 572 rc->rc_flags |= RC_SEND_RDY; 573 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 574 sc->sc_scheduled_event += LOTS_OF_EVENTS; 575 rc->rc_flags |= RC_MODCHG; 576 swi_sched(sc->sc_swicookie, 0); 577 } 578 goto more_intrs; 579 } 580 if (bsr & RC_BSR_TXINT) { 581 iack = rcin(sc, RC_PILR_TX); 582 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 583 device_printf(sc->sc_dev, "fake txint: %02x\n", 584 iack); 585 goto more_intrs; 586 } 587 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH); 588 rc = &sc->sc_channels[chan]; 589 if ( (rc->rc_flags & RC_OSUSP) 590 || !(rc->rc_flags & RC_SEND_RDY) 591 ) 592 goto more_intrs; 593 /* Handle breaks and other stuff */ 594 if (rc->rc_pendcmd) { 595 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC); 596 rcout(sc, CD180_TDR, CD180_C_ESC); 597 rcout(sc, CD180_TDR, rc->rc_pendcmd); 598 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 599 rc->rc_pendcmd = 0; 600 goto more_intrs; 601 } 602 optr = rc->rc_optr; 603 resid = rc->rc_obufend - optr; 604 if (resid > CD180_NFIFO) 605 resid = CD180_NFIFO; 606 while (resid-- > 0) 607 rcout(sc, CD180_TDR, *optr++); 608 rc->rc_optr = optr; 609 610 /* output completed? */ 611 if (optr >= rc->rc_obufend) { 612 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy); 613#ifdef RCDEBUG 614 device_printf(sc->sc_dev, 615 "channel %d: output completed\n", 616 rc->rc_chan); 617#endif 618 if (!(rc->rc_flags & RC_DOXXFER)) { 619 sc->sc_scheduled_event += LOTS_OF_EVENTS; 620 rc->rc_flags |= RC_DOXXFER; 621 swi_sched(sc->sc_swicookie, 0); 622 } 623 } 624 } 625 more_intrs: 626 rcout(sc, CD180_EOIR, 0); /* end of interrupt */ 627 rcout(sc, RC_CTOUT, 0); 628 bsr = ~(rcin(sc, RC_BSR)); 629 } 630} 631 632/* Feed characters to output buffer */ 633static void 634rc_start(struct tty *tp) 635{ 636 struct rc_softc *sc; 637 struct rc_chans *rc; 638 int s; 639 640 rc = TTY_TO_RC(tp); 641 if (rc->rc_flags & RC_OSBUSY) 642 return; 643 sc = rc->rc_rcb; 644 s = spltty(); 645 rc->rc_flags |= RC_OSBUSY; 646 critical_enter(); 647 if (tp->t_state & TS_TTSTOP) 648 rc->rc_flags |= RC_OSUSP; 649 else 650 rc->rc_flags &= ~RC_OSUSP; 651 /* Do RTS flow control stuff */ 652 if ( (rc->rc_flags & RC_RTSFLOW) 653 && (tp->t_state & TS_TBLOCK) 654 && (rc->rc_msvr & MSVR_RTS) 655 ) { 656 rcout(sc, CD180_CAR, rc->rc_chan); 657 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 658 } else if (!(rc->rc_msvr & MSVR_RTS)) { 659 rcout(sc, CD180_CAR, rc->rc_chan); 660 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 661 } 662 critical_exit(); 663 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 664 goto out; 665#ifdef RCDEBUG 666 printrcflags(rc, "rcstart"); 667#endif 668 ttwwakeup(tp); 669#ifdef RCDEBUG 670 printf("rcstart: outq = %d obuf = %d\n", 671 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 672#endif 673 if (tp->t_state & TS_BUSY) 674 goto out; /* output still in progress ... */ 675 676 if (tp->t_outq.c_cc > 0) { 677 u_int ocnt; 678 679 tp->t_state |= TS_BUSY; 680 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 681 critical_enter(); 682 rc->rc_optr = rc->rc_obuf; 683 rc->rc_obufend = rc->rc_optr + ocnt; 684 critical_exit(); 685 if (!(rc->rc_ier & IER_TxRdy)) { 686#ifdef RCDEBUG 687 device_printf(sc->sc_dev, 688 "channel %d: rcstart enable txint\n", rc->rc_chan); 689#endif 690 rcout(sc, CD180_CAR, rc->rc_chan); 691 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy); 692 } 693 } 694out: 695 rc->rc_flags &= ~RC_OSBUSY; 696 (void) splx(s); 697} 698 699/* Handle delayed events. */ 700void 701rc_pollcard(void *arg) 702{ 703 struct rc_softc *sc; 704 struct rc_chans *rc; 705 struct tty *tp; 706 u_char *tptr, *eptr; 707 int chan, icnt; 708 709 sc = (struct rc_softc *)arg; 710 if (sc->sc_scheduled_event == 0) 711 return; 712 do { 713 rc = sc->sc_channels; 714 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 715 tp = &rc->rc_tp; 716#ifdef RCDEBUG 717 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 718 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 719 printrcflags(rc, "rcevent"); 720#endif 721 if (rc->rc_flags & RC_WAS_BUFOVFL) { 722 critical_enter(); 723 rc->rc_flags &= ~RC_WAS_BUFOVFL; 724 sc->sc_scheduled_event--; 725 critical_exit(); 726 device_printf(sc->sc_dev, 727 "channel %d: interrupt-level buffer overflow\n", 728 chan); 729 } 730 if (rc->rc_flags & RC_WAS_SILOVFL) { 731 critical_enter(); 732 rc->rc_flags &= ~RC_WAS_SILOVFL; 733 sc->sc_scheduled_event--; 734 critical_exit(); 735 device_printf(sc->sc_dev, 736 "channel %d: silo overflow\n", chan); 737 } 738 if (rc->rc_flags & RC_MODCHG) { 739 critical_enter(); 740 rc->rc_flags &= ~RC_MODCHG; 741 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 742 critical_exit(); 743 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 744 } 745 if (rc->rc_flags & RC_DORXFER) { 746 critical_enter(); 747 rc->rc_flags &= ~RC_DORXFER; 748 eptr = rc->rc_iptr; 749 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 750 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 751 else 752 tptr = rc->rc_ibuf; 753 icnt = eptr - tptr; 754 if (icnt > 0) { 755 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 756 rc->rc_iptr = rc->rc_ibuf; 757 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 758 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 759 } else { 760 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 761 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 762 rc->rc_hiwat = 763 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 764 } 765 if ( (rc->rc_flags & RC_RTSFLOW) 766 && (tp->t_state & TS_ISOPEN) 767 && !(tp->t_state & TS_TBLOCK) 768 && !(rc->rc_msvr & MSVR_RTS) 769 ) { 770 rcout(sc, CD180_CAR, chan); 771 rcout(sc, CD180_MSVR, 772 rc->rc_msvr |= MSVR_RTS); 773 } 774 sc->sc_scheduled_event -= icnt; 775 } 776 critical_exit(); 777 778 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 779 goto done1; 780 781 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 782 && !(tp->t_state & TS_LOCAL)) { 783 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 784 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 785 && !(tp->t_state & TS_TBLOCK)) 786 ttyblock(tp); 787 tk_nin += icnt; 788 tk_rawcc += icnt; 789 tp->t_rawcc += icnt; 790 if (b_to_q(tptr, icnt, &tp->t_rawq)) 791 device_printf(sc->sc_dev, 792 "channel %d: tty-level buffer overflow\n", 793 chan); 794 ttwakeup(tp); 795 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 796 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 797 tp->t_state &= ~TS_TTSTOP; 798 tp->t_lflag &= ~FLUSHO; 799 rc_start(tp); 800 } 801 } else { 802 for (; tptr < eptr; tptr++) 803 (*linesw[tp->t_line].l_rint) 804 (tptr[0] | 805 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 806 } 807done1: ; 808 } 809 if (rc->rc_flags & RC_DOXXFER) { 810 critical_enter(); 811 sc->sc_scheduled_event -= LOTS_OF_EVENTS; 812 rc->rc_flags &= ~RC_DOXXFER; 813 rc->rc_tp.t_state &= ~TS_BUSY; 814 critical_exit(); 815 (*linesw[tp->t_line].l_start)(tp); 816 } 817 if (sc->sc_scheduled_event == 0) 818 break; 819 } 820 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS); 821} 822 823static void 824rc_stop(struct tty *tp, int rw) 825{ 826 struct rc_softc *sc; 827 struct rc_chans *rc; 828 u_char *tptr, *eptr; 829 830 rc = TTY_TO_RC(tp); 831 sc = rc->rc_rcb; 832#ifdef RCDEBUG 833 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n", 834 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 835#endif 836 if (rw & FWRITE) 837 rc_discard_output(rc); 838 critical_enter(); 839 if (rw & FREAD) { 840 rc->rc_flags &= ~RC_DORXFER; 841 eptr = rc->rc_iptr; 842 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 843 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 844 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 845 } else { 846 tptr = rc->rc_ibuf; 847 rc->rc_iptr = rc->rc_ibuf; 848 } 849 sc->sc_scheduled_event -= eptr - tptr; 850 } 851 if (tp->t_state & TS_TTSTOP) 852 rc->rc_flags |= RC_OSUSP; 853 else 854 rc->rc_flags &= ~RC_OSUSP; 855 critical_exit(); 856} 857 858static int 859rcopen(dev_t dev, int flag, int mode, d_thread_t *td) 860{ 861 struct rc_softc *sc; 862 struct rc_chans *rc; 863 struct tty *tp; 864 int s, error = 0; 865 866 rc = DEV_TO_RC(dev); 867 sc = rc->rc_rcb; 868 tp = &rc->rc_tp; 869 if (sc->sc_opencount < 0) 870 return (ENXIO); 871 sc->sc_opencount++; 872#ifdef RCDEBUG 873 device_printf(sc->sc_dev, "channel %d: rcopen: dev %p\n", 874 rc->rc_chan, dev); 875#endif 876 s = spltty(); 877 878again: 879 while (rc->rc_flags & RC_DTR_OFF) { 880 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 881 if (error != 0) 882 goto out; 883 } 884 if (tp->t_state & TS_ISOPEN) { 885 if (CALLOUT(dev)) { 886 if (!(rc->rc_flags & RC_ACTOUT)) { 887 error = EBUSY; 888 goto out; 889 } 890 } else { 891 if (rc->rc_flags & RC_ACTOUT) { 892 if (flag & O_NONBLOCK) { 893 error = EBUSY; 894 goto out; 895 } 896 error = tsleep(&rc->rc_rcb, 897 TTIPRI|PCATCH, "rcbi", 0); 898 if (error) 899 goto out; 900 goto again; 901 } 902 } 903 if (tp->t_state & TS_XCLUDE && 904 suser(td)) { 905 error = EBUSY; 906 goto out; 907 } 908 } else { 909 tp->t_oproc = rc_start; 910 tp->t_param = rc_param; 911 tp->t_stop = rc_stop; 912 tp->t_dev = dev; 913 914 if (CALLOUT(dev)) 915 tp->t_cflag |= CLOCAL; 916 else 917 tp->t_cflag &= ~CLOCAL; 918 919 error = rc_param(tp, &tp->t_termios); 920 if (error) 921 goto out; 922 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 923 924 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 925 (*linesw[tp->t_line].l_modem)(tp, 1); 926 } 927 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 928 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 929 rc->rc_dcdwaits++; 930 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 931 rc->rc_dcdwaits--; 932 if (error != 0) 933 goto out; 934 goto again; 935 } 936 error = (*linesw[tp->t_line].l_open)(dev, tp); 937 disc_optim(tp, &tp->t_termios, rc); 938 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 939 rc->rc_flags |= RC_ACTOUT; 940out: 941 (void) splx(s); 942 943 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 944 rc_hardclose(rc); 945 946 return error; 947} 948 949static int 950rcclose(dev_t dev, int flag, int mode, d_thread_t *td) 951{ 952 struct rc_softc *sc; 953 struct rc_chans *rc; 954 struct tty *tp; 955 int s; 956 957 rc = DEV_TO_RC(dev); 958 sc = rc->rc_rcb; 959 tp = &rc->rc_tp; 960#ifdef RCDEBUG 961 device_printf(sc->sc_dev, "channel %d: rcclose dev %p\n", 962 rc->rc_chan, dev); 963#endif 964 s = spltty(); 965 (*linesw[tp->t_line].l_close)(tp, flag); 966 disc_optim(tp, &tp->t_termios, rc); 967 rc_stop(tp, FREAD | FWRITE); 968 rc_hardclose(rc); 969 ttyclose(tp); 970 splx(s); 971 KASSERT(sc->sc_opencount > 0, ("rcclose: non-positive open count")); 972 sc->sc_opencount--; 973 return 0; 974} 975 976static void 977rc_hardclose(struct rc_chans *rc) 978{ 979 struct rc_softc *sc; 980 struct tty *tp; 981 int s; 982 983 tp = &rc->rc_tp; 984 sc = rc->rc_rcb; 985 s = spltty(); 986 rcout(sc, CD180_CAR, rc->rc_chan); 987 988 /* Disable rx/tx intrs */ 989 rcout(sc, CD180_IER, rc->rc_ier = 0); 990 if ( (tp->t_cflag & HUPCL) 991 || (!(rc->rc_flags & RC_ACTOUT) 992 && !(rc->rc_msvr & MSVR_CD) 993 && !(tp->t_cflag & CLOCAL)) 994 || !(tp->t_state & TS_ISOPEN) 995 ) { 996 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 997 WAITFORCCR(sc, rc->rc_chan); 998 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 999 if (rc->rc_dtrwait) { 1000 callout_reset(&rc->rc_dtrcallout, rc->rc_dtrwait, 1001 rc_dtrwakeup, rc); 1002 rc->rc_flags |= RC_DTR_OFF; 1003 } 1004 } 1005 rc->rc_flags &= ~RC_ACTOUT; 1006 wakeup( &rc->rc_rcb); /* wake bi */ 1007 wakeup(TSA_CARR_ON(tp)); 1008 (void) splx(s); 1009} 1010 1011/* Reset the bastard */ 1012static void 1013rc_hwreset(struct rc_softc *sc, uint chipid) 1014{ 1015 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */ 1016 DELAY(20000); 1017 WAITFORCCR(sc, -1); 1018 1019 rcout(sc, RC_CTOUT, 0); /* Clear timeout */ 1020 rcout(sc, CD180_GIVR, chipid); 1021 rcout(sc, CD180_GICR, 0); 1022 1023 /* Set Prescaler Registers (1 msec) */ 1024 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 1025 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 1026 1027 /* Initialize Priority Interrupt Level Registers */ 1028 rcout(sc, CD180_PILR1, RC_PILR_MODEM); 1029 rcout(sc, CD180_PILR2, RC_PILR_TX); 1030 rcout(sc, CD180_PILR3, RC_PILR_RX); 1031 1032 /* Reset DTR */ 1033 rcout(sc, RC_DTREG, ~0); 1034} 1035 1036/* Set channel parameters */ 1037static int 1038rc_param(struct tty *tp, struct termios *ts) 1039{ 1040 struct rc_softc *sc; 1041 struct rc_chans *rc; 1042 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 1043 1044 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 1045 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 1046 ) 1047 return (EINVAL); 1048 if (ts->c_ispeed == 0) 1049 ts->c_ispeed = ts->c_ospeed; 1050 odivs = RC_BRD(ts->c_ospeed); 1051 idivs = RC_BRD(ts->c_ispeed); 1052 1053 rc = TTY_TO_RC(tp); 1054 sc = rc->rc_rcb; 1055 s = spltty(); 1056 1057 /* Select channel */ 1058 rcout(sc, CD180_CAR, rc->rc_chan); 1059 1060 /* If speed == 0, hangup line */ 1061 if (ts->c_ospeed == 0) { 1062 CCRCMD(sc, rc->rc_chan, CCR_ResetChan); 1063 WAITFORCCR(sc, rc->rc_chan); 1064 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1065 } 1066 1067 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1068 cflag = ts->c_cflag; 1069 iflag = ts->c_iflag; 1070 lflag = ts->c_lflag; 1071 1072 if (idivs > 0) { 1073 rcout(sc, CD180_RBPRL, idivs & 0xFF); 1074 rcout(sc, CD180_RBPRH, idivs >> 8); 1075 } 1076 if (odivs > 0) { 1077 rcout(sc, CD180_TBPRL, odivs & 0xFF); 1078 rcout(sc, CD180_TBPRH, odivs >> 8); 1079 } 1080 1081 /* set timeout value */ 1082 if (ts->c_ispeed > 0) { 1083 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 1084 1085 if ( !(lflag & ICANON) 1086 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1087 && ts->c_cc[VTIME] * 10 > itm) 1088 itm = ts->c_cc[VTIME] * 10; 1089 1090 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255); 1091 } 1092 1093 switch (cflag & CSIZE) { 1094 case CS5: val = COR1_5BITS; break; 1095 case CS6: val = COR1_6BITS; break; 1096 case CS7: val = COR1_7BITS; break; 1097 default: 1098 case CS8: val = COR1_8BITS; break; 1099 } 1100 if (cflag & PARENB) { 1101 val |= COR1_NORMPAR; 1102 if (cflag & PARODD) 1103 val |= COR1_ODDP; 1104 if (!(cflag & INPCK)) 1105 val |= COR1_Ignore; 1106 } else 1107 val |= COR1_Ignore; 1108 if (cflag & CSTOPB) 1109 val |= COR1_2SB; 1110 rcout(sc, CD180_COR1, val); 1111 1112 /* Set FIFO threshold */ 1113 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1114 inpflow = 0; 1115 if ( (iflag & IXOFF) 1116 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1117 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1118 || (iflag & IXANY) 1119 ) 1120 ) 1121 ) { 1122 inpflow = 1; 1123 val |= COR3_SCDE|COR3_FCT; 1124 } 1125 rcout(sc, CD180_COR3, val); 1126 1127 /* Initialize on-chip automatic flow control */ 1128 val = 0; 1129 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1130 if (cflag & CCTS_OFLOW) { 1131 rc->rc_flags |= RC_CTSFLOW; 1132 val |= COR2_CtsAE; 1133 } else 1134 rc->rc_flags |= RC_SEND_RDY; 1135 if (tp->t_state & TS_TTSTOP) 1136 rc->rc_flags |= RC_OSUSP; 1137 else 1138 rc->rc_flags &= ~RC_OSUSP; 1139 if (cflag & CRTS_IFLOW) 1140 rc->rc_flags |= RC_RTSFLOW; 1141 else 1142 rc->rc_flags &= ~RC_RTSFLOW; 1143 1144 if (inpflow) { 1145 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1146 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]); 1147 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]); 1148 val |= COR2_TxIBE; 1149 if (iflag & IXANY) 1150 val |= COR2_IXM; 1151 } 1152 1153 rcout(sc, CD180_COR2, rc->rc_cor2 = val); 1154 1155 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1156 1157 disc_optim(tp, ts, rc); 1158 1159 /* modem ctl */ 1160 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1161 if (cflag & CCTS_OFLOW) 1162 val |= MCOR1_CTSzd; 1163 rcout(sc, CD180_MCOR1, val); 1164 1165 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1166 if (cflag & CCTS_OFLOW) 1167 val |= MCOR2_CTSod; 1168 rcout(sc, CD180_MCOR2, val); 1169 1170 /* enable i/o and interrupts */ 1171 CCRCMD(sc, rc->rc_chan, 1172 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1173 WAITFORCCR(sc, rc->rc_chan); 1174 1175 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1176 if (cflag & CCTS_OFLOW) 1177 rc->rc_ier |= IER_CTS; 1178 if (cflag & CREAD) 1179 rc->rc_ier |= IER_RxData; 1180 if (tp->t_state & TS_BUSY) 1181 rc->rc_ier |= IER_TxRdy; 1182 if (ts->c_ospeed != 0) 1183 rc_modctl(rc, TIOCM_DTR, DMBIS); 1184 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1185 rc->rc_flags |= RC_SEND_RDY; 1186 rcout(sc, CD180_IER, rc->rc_ier); 1187 (void) splx(s); 1188 return 0; 1189} 1190 1191/* Re-initialize board after bogus interrupts */ 1192static void 1193rc_reinit(struct rc_softc *sc) 1194{ 1195 struct rc_chans *rc; 1196 int i; 1197 1198 rc_hwreset(sc, RC_FAKEID); 1199 rc = sc->sc_channels; 1200 for (i = 0; i < CD180_NCHAN; i++, rc++) 1201 (void) rc_param(&rc->rc_tp, &rc->rc_tp.t_termios); 1202} 1203 1204static int 1205rcioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td) 1206{ 1207 struct rc_chans *rc; 1208 struct tty *tp; 1209 int s, error; 1210 1211 rc = DEV_TO_RC(dev); 1212 tp = &rc->rc_tp; 1213 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1214 if (error != ENOIOCTL) 1215 return (error); 1216 error = ttioctl(tp, cmd, data, flag); 1217 disc_optim(tp, &tp->t_termios, rc); 1218 if (error != ENOIOCTL) 1219 return (error); 1220 s = spltty(); 1221 1222 switch (cmd) { 1223 case TIOCSBRK: 1224 rc->rc_pendcmd = CD180_C_SBRK; 1225 break; 1226 1227 case TIOCCBRK: 1228 rc->rc_pendcmd = CD180_C_EBRK; 1229 break; 1230 1231 case TIOCSDTR: 1232 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1233 break; 1234 1235 case TIOCCDTR: 1236 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1237 break; 1238 1239 case TIOCMGET: 1240 *(int *) data = rc_modctl(rc, 0, DMGET); 1241 break; 1242 1243 case TIOCMSET: 1244 (void) rc_modctl(rc, *(int *) data, DMSET); 1245 break; 1246 1247 case TIOCMBIC: 1248 (void) rc_modctl(rc, *(int *) data, DMBIC); 1249 break; 1250 1251 case TIOCMBIS: 1252 (void) rc_modctl(rc, *(int *) data, DMBIS); 1253 break; 1254 1255 case TIOCMSDTRWAIT: 1256 error = suser(td); 1257 if (error != 0) { 1258 splx(s); 1259 return (error); 1260 } 1261 rc->rc_dtrwait = *(int *)data * hz / 100; 1262 break; 1263 1264 case TIOCMGDTRWAIT: 1265 *(int *)data = rc->rc_dtrwait * 100 / hz; 1266 break; 1267 1268 default: 1269 (void) splx(s); 1270 return ENOTTY; 1271 } 1272 (void) splx(s); 1273 return 0; 1274} 1275 1276 1277/* Modem control routines */ 1278 1279static int 1280rc_modctl(struct rc_chans *rc, int bits, int cmd) 1281{ 1282 struct rc_softc *sc; 1283 u_char *dtr; 1284 u_char msvr; 1285 1286 sc = rc->rc_rcb; 1287 dtr = &sc->sc_dtr; 1288 rcout(sc, CD180_CAR, rc->rc_chan); 1289 1290 switch (cmd) { 1291 case DMSET: 1292 rcout(sc, RC_DTREG, (bits & TIOCM_DTR) ? 1293 ~(*dtr |= 1 << rc->rc_chan) : 1294 ~(*dtr &= ~(1 << rc->rc_chan))); 1295 msvr = rcin(sc, CD180_MSVR); 1296 if (bits & TIOCM_RTS) 1297 msvr |= MSVR_RTS; 1298 else 1299 msvr &= ~MSVR_RTS; 1300 if (bits & TIOCM_DTR) 1301 msvr |= MSVR_DTR; 1302 else 1303 msvr &= ~MSVR_DTR; 1304 rcout(sc, CD180_MSVR, msvr); 1305 break; 1306 1307 case DMBIS: 1308 if (bits & TIOCM_DTR) 1309 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1310 msvr = rcin(sc, CD180_MSVR); 1311 if (bits & TIOCM_RTS) 1312 msvr |= MSVR_RTS; 1313 if (bits & TIOCM_DTR) 1314 msvr |= MSVR_DTR; 1315 rcout(sc, CD180_MSVR, msvr); 1316 break; 1317 1318 case DMGET: 1319 bits = TIOCM_LE; 1320 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR); 1321 1322 if (msvr & MSVR_RTS) 1323 bits |= TIOCM_RTS; 1324 if (msvr & MSVR_CTS) 1325 bits |= TIOCM_CTS; 1326 if (msvr & MSVR_DSR) 1327 bits |= TIOCM_DSR; 1328 if (msvr & MSVR_DTR) 1329 bits |= TIOCM_DTR; 1330 if (msvr & MSVR_CD) 1331 bits |= TIOCM_CD; 1332 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan)) 1333 bits |= TIOCM_RI; 1334 return bits; 1335 1336 case DMBIC: 1337 if (bits & TIOCM_DTR) 1338 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1339 msvr = rcin(sc, CD180_MSVR); 1340 if (bits & TIOCM_RTS) 1341 msvr &= ~MSVR_RTS; 1342 if (bits & TIOCM_DTR) 1343 msvr &= ~MSVR_DTR; 1344 rcout(sc, CD180_MSVR, msvr); 1345 break; 1346 } 1347 rc->rc_msvr = rcin(sc, CD180_MSVR); 1348 return 0; 1349} 1350 1351#define ERR(s) do { \ 1352 device_printf(sc->sc_dev, "%s", ""); \ 1353 printf s ; \ 1354 printf("\n"); \ 1355 (void) splx(old_level); \ 1356 return 1; \ 1357} while (0) 1358 1359/* Test the board. */ 1360int 1361rc_test(struct rc_softc *sc) 1362{ 1363 int chan = 0; 1364 int i = 0, rcnt, old_level; 1365 unsigned int iack, chipid; 1366 unsigned short divs; 1367 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1368#define CTLEN 8 1369 1370 struct rtest { 1371 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1372 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1373 int rxptr; /* RX pointer */ 1374 int txptr; /* TX pointer */ 1375 } tchans[CD180_NCHAN]; 1376 1377 old_level = spltty(); 1378 1379 chipid = RC_FAKEID; 1380 1381 /* First, reset board to inital state */ 1382 rc_hwreset(sc, chipid); 1383 1384 divs = RC_BRD(19200); 1385 1386 /* Initialize channels */ 1387 for (chan = 0; chan < CD180_NCHAN; chan++) { 1388 1389 /* Select and reset channel */ 1390 rcout(sc, CD180_CAR, chan); 1391 CCRCMD(sc, chan, CCR_ResetChan); 1392 WAITFORCCR(sc, chan); 1393 1394 /* Set speed */ 1395 rcout(sc, CD180_RBPRL, divs & 0xFF); 1396 rcout(sc, CD180_RBPRH, divs >> 8); 1397 rcout(sc, CD180_TBPRL, divs & 0xFF); 1398 rcout(sc, CD180_TBPRH, divs >> 8); 1399 1400 /* set timeout value */ 1401 rcout(sc, CD180_RTPR, 0); 1402 1403 /* Establish local loopback */ 1404 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1405 rcout(sc, CD180_COR2, COR2_LLM); 1406 rcout(sc, CD180_COR3, CD180_NFIFO); 1407 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1408 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN); 1409 WAITFORCCR(sc, chan); 1410 rcout(sc, CD180_MSVR, MSVR_RTS); 1411 1412 /* Fill TXBUF with test data */ 1413 for (i = 0; i < CD180_NFIFO; i++) { 1414 tchans[chan].txbuf[i] = ctest[i]; 1415 tchans[chan].rxbuf[i] = 0; 1416 } 1417 tchans[chan].txptr = tchans[chan].rxptr = 0; 1418 1419 /* Now, start transmit */ 1420 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData); 1421 } 1422 /* Pseudo-interrupt poll stuff */ 1423 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1424 i = ~(rcin(sc, RC_BSR)); 1425 if (i & RC_BSR_TOUT) 1426 ERR(("BSR timeout bit set\n")); 1427 else if (i & RC_BSR_TXINT) { 1428 iack = rcin(sc, RC_PILR_TX); 1429 if (iack != (GIVR_IT_TDI | chipid)) 1430 ERR(("Bad TX intr ack (%02x != %02x)\n", 1431 iack, GIVR_IT_TDI | chipid)); 1432 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1433 /* If no more data to transmit, disable TX intr */ 1434 if (tchans[chan].txptr >= CD180_NFIFO) { 1435 iack = rcin(sc, CD180_IER); 1436 rcout(sc, CD180_IER, iack & ~IER_TxMpty); 1437 } else { 1438 for (iack = tchans[chan].txptr; 1439 iack < CD180_NFIFO; iack++) 1440 rcout(sc, CD180_TDR, 1441 tchans[chan].txbuf[iack]); 1442 tchans[chan].txptr = iack; 1443 } 1444 rcout(sc, CD180_EOIR, 0); 1445 } else if (i & RC_BSR_RXINT) { 1446 u_char ucnt; 1447 1448 iack = rcin(sc, RC_PILR_RX); 1449 if (iack != (GIVR_IT_RGDI | chipid) && 1450 iack != (GIVR_IT_REI | chipid)) 1451 ERR(("Bad RX intr ack (%02x != %02x)\n", 1452 iack, GIVR_IT_RGDI | chipid)); 1453 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1454 ucnt = rcin(sc, CD180_RDCR) & 0xF; 1455 while (ucnt-- > 0) { 1456 iack = rcin(sc, CD180_RCSR); 1457 if (iack & RCSR_Timeout) 1458 break; 1459 if (iack & 0xF) 1460 ERR(("Bad char chan %d (RCSR = %02X)\n", 1461 chan, iack)); 1462 if (tchans[chan].rxptr > CD180_NFIFO) 1463 ERR(("Got extra chars chan %d\n", 1464 chan)); 1465 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1466 rcin(sc, CD180_RDR); 1467 } 1468 rcout(sc, CD180_EOIR, 0); 1469 } 1470 rcout(sc, RC_CTOUT, 0); 1471 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1472 if (tchans[chan].rxptr >= CD180_NFIFO) 1473 iack++; 1474 if (iack == CD180_NCHAN) 1475 break; 1476 } 1477 for (chan = 0; chan < CD180_NCHAN; chan++) { 1478 /* Select and reset channel */ 1479 rcout(sc, CD180_CAR, chan); 1480 CCRCMD(sc, chan, CCR_ResetChan); 1481 } 1482 1483 if (!rcnt) 1484 ERR(("looses characters during local loopback\n")); 1485 /* Now, check data */ 1486 for (chan = 0; chan < CD180_NCHAN; chan++) 1487 for (i = 0; i < CD180_NFIFO; i++) 1488 if (ctest[i] != tchans[chan].rxbuf[i]) 1489 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1490 chan, i, ctest[i], tchans[chan].rxbuf[i])); 1491 (void) splx(old_level); 1492 return 0; 1493} 1494 1495#ifdef RCDEBUG 1496static void 1497printrcflags(struct rc_chans *rc, char *comment) 1498{ 1499 struct rc_softc *sc; 1500 u_short f = rc->rc_flags; 1501 1502 sc = rc->rc_rcb; 1503 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1504 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1505 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1506 (f & RC_ACTOUT) ?"ACTOUT " :"", 1507 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1508 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1509 (f & RC_DORXFER)?"DORXFER " :"", 1510 (f & RC_DOXXFER)?"DOXXFER " :"", 1511 (f & RC_MODCHG) ?"MODCHG " :"", 1512 (f & RC_OSUSP) ?"OSUSP " :"", 1513 (f & RC_OSBUSY) ?"OSBUSY " :"", 1514 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1515 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1516 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1517 1518 rcout(sc, CD180_CAR, rc->rc_chan); 1519 1520 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1521 rc->rc_rcb->rcb_unit, rc->rc_chan, 1522 rcin(sc, CD180_MSVR), 1523 rcin(sc, CD180_IER), 1524 rcin(sc, CD180_CCSR)); 1525} 1526#endif /* RCDEBUG */ 1527 1528static void 1529rc_dtrwakeup(void *arg) 1530{ 1531 struct rc_chans *rc; 1532 1533 rc = (struct rc_chans *)arg; 1534 rc->rc_flags &= ~RC_DTR_OFF; 1535 wakeup(&rc->rc_dtrwait); 1536} 1537 1538static void 1539rc_discard_output(struct rc_chans *rc) 1540{ 1541 critical_enter(); 1542 if (rc->rc_flags & RC_DOXXFER) { 1543 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS; 1544 rc->rc_flags &= ~RC_DOXXFER; 1545 } 1546 rc->rc_optr = rc->rc_obufend; 1547 rc->rc_tp.t_state &= ~TS_BUSY; 1548 critical_exit(); 1549 ttwwakeup(&rc->rc_tp); 1550} 1551 1552static void 1553disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc) 1554{ 1555 1556 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1557 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1558 && (!(t->c_iflag & PARMRK) 1559 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1560 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1561 && linesw[tp->t_line].l_rint == ttyinput) 1562 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1563 else 1564 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1565 rc->rc_hotchar = linesw[tp->t_line].l_hotchar; 1566} 1567 1568static void 1569rc_wait0(struct rc_softc *sc, int chan, int line) 1570{ 1571 int rcnt; 1572 1573 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--) 1574 DELAY(30); 1575 if (rcnt == 0) 1576 device_printf(sc->sc_dev, 1577 "channel %d command timeout, rc.c line: %d\n", chan, line); 1578} 1579 1580static device_method_t rc_methods[] = { 1581 /* Device interface */ 1582 DEVMETHOD(device_probe, rc_probe), 1583 DEVMETHOD(device_attach, rc_attach), 1584 DEVMETHOD(device_detach, rc_detach), 1585 { 0, 0 } 1586}; 1587 1588static driver_t rc_driver = { 1589 "rc", 1590 rc_methods, sizeof(struct rc_softc), 1591}; 1592 1593DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0); 1594