rc.c revision 8471
18471Sache/* 28471Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 38471Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 48471Sache * All rights reserved. 58471Sache * 68471Sache * Redistribution and use in source and binary forms, with or without 78471Sache * modification, are permitted provided that the following conditions 88471Sache * are met: 98471Sache * 1. Redistributions of source code must retain the above copyright 108471Sache * notice, this list of conditions and the following disclaimer. 118471Sache * 2. Redistributions in binary form must reproduce the above copyright 128471Sache * notice, this list of conditions and the following disclaimer in the 138471Sache * documentation and/or other materials provided with the distribution. 148471Sache * 158471Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 168471Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178471Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 188471Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 198471Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 208471Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 218471Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228471Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 238471Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 248471Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 258471Sache * SUCH DAMAGE. 268471Sache */ 278471Sache 288471Sache/* 298471Sache * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 308471Sache * 318471Sache */ 328471Sache 338471Sache#include "rc.h" 348471Sache#if NRC > 0 358471Sache 368471Sache/*#define RCDEBUG */ 378471Sache 388471Sache#include <sys/param.h> 398471Sache#include <sys/systm.h> 408471Sache#include <sys/ioctl.h> 418471Sache#include <sys/tty.h> 428471Sache#include <sys/proc.h> 438471Sache#include <sys/user.h> 448471Sache#include <sys/conf.h> 458471Sache#include <sys/dkstat.h> 468471Sache#include <sys/file.h> 478471Sache#include <sys/uio.h> 488471Sache#include <sys/kernel.h> 498471Sache#include <sys/syslog.h> 508471Sache#include <sys/devconf.h> 518471Sache 528471Sache#include <machine/clock.h> 538471Sache 548471Sache#include <i386/isa/isa.h> 558471Sache#include <i386/isa/isa_device.h> 568471Sache#include <i386/isa/sioreg.h> 578471Sache 588471Sache#include <i386/isa/ic/cd180.h> 598471Sache#include <i386/isa/rcreg.h> 608471Sache 618471Sache/* Prototypes */ 628471Sacheint rcprobe __P((struct isa_device *)); 638471Sacheint rcattach __P((struct isa_device *)); 648471Sache 658471Sacheint rcopen __P((dev_t, int, int, struct proc *)); 668471Sacheint rcclose __P((dev_t, int, int, struct proc *)); 678471Sacheint rcread __P((dev_t, struct uio *, int)); 688471Sacheint rcwrite __P((dev_t, struct uio *, int)); 698471Sachevoid rcintr __P((int)); 708471Sachevoid rcpoll __P((void)); 718471Sachevoid rcstop __P((struct tty *, int)); 728471Sacheint rcioctl __P((dev_t, int, caddr_t, int, struct proc *)); 738471Sache 748471Sache#define rcin(port) RC_IN (nec, port) 758471Sache#define rcout(port,v) RC_OUT (nec, port, v) 768471Sache 778471Sache/* Counter short for timeouts */ 788471Sachestatic volatile int rcnt; 798471Sache 808471Sache#define WAITFORCCR { for (rcnt = 100000; rcin(CD180_CCR) && rcnt; rcnt--) ; } 818471Sache#define CCRCMD(cmd) WAITFORCCR; rcout(CD180_CCR, cmd) 828471Sache 838471Sache#define RC_IBUFSIZE 512 848471Sache#define RC_OBUFSIZE 1024 858471Sache#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 868471Sache#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 878471Sache#define LOTS_OF_EVENTS 64 888471Sache 898471Sache#define RC_TXTIMEO 30 /* 30 seconds wait if intr loss */ 908471Sache#define RC_FAKEID 0x10 918471Sache 928471Sache#define GET_UNIT(dev) (minor(dev) & 0x3F) 938471Sache#define CALLOUT(dev) (minor(dev) & 0x80) 948471Sache 958471Sache/* For isa routines */ 968471Sachestruct isa_driver rcdriver = { 978471Sache rcprobe, rcattach, "rc" 988471Sache}; 998471Sache 1008471Sache/* Per-board structure */ 1018471Sachestatic struct rc_softc { 1028471Sache u_int rcb_probed; /* 1 if device probed */ 1038471Sache u_int rcb_addr; /* Base I/O addr */ 1048471Sache u_int rcb_unit; /* unit # */ 1058471Sache u_char rcb_dtr; /* DTR status */ 1068471Sache struct rc_chans *rcb_baserc; /* base rc ptr */ 1078471Sache} rc_softc[NRC]; 1088471Sache 1098471Sache/* Per-channel structure */ 1108471Sachestatic struct rc_chans { 1118471Sache struct rc_softc *rc_rcb; /* back ptr */ 1128471Sache u_short rc_flags; /* Misc. flags */ 1138471Sache int rc_chan; /* Channel # */ 1148471Sache u_char rc_ier; /* intr. enable reg */ 1158471Sache u_char rc_msvr; /* modem sig. status */ 1168471Sache u_char rc_cor2; /* options reg */ 1178471Sache u_char rc_pendcmd; /* special cmd pending */ 1188471Sache u_int rc_dtrwait; /* dtr timeout */ 1198471Sache long rc_txitime; /* time of last TX intr */ 1208471Sache u_int rc_dcdwaits; /* how many waits DCD in open */ 1218471Sache u_char rc_hotchar; /* end packed optimize */ 1228471Sache struct tty *rc_tp; /* tty struct */ 1238471Sache u_char *rc_iptr; /* Chars input buffer */ 1248471Sache u_char *rc_hiwat; /* hi-water mark */ 1258471Sache u_char *rc_bufend; /* end of buffer */ 1268471Sache u_char *rc_optr; /* ptr in output buf */ 1278471Sache u_char rc_ocnt; 1288471Sache u_char *rc_obufend; /* end of output buf */ 1298471Sache u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1308471Sache u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 1318471Sache} rc_chans[NRC * CD180_NCHAN]; 1328471Sache 1338471Sachestatic int rc_scheduled_event = 0; 1348471Sache 1358471Sache/* for pstat -t */ 1368471Sachestruct tty rc_tty[NRC * CD180_NCHAN]; 1378471Sacheint nrc_tty = NRC * CD180_NCHAN; 1388471Sache 1398471Sache/* Flags */ 1408471Sache#define RC_DTR_OFF 000001 /* DTR wait, for close/open */ 1418471Sache#define RC_ACTOUT 000002 /* Dial-out port active */ 1428471Sache#define RC_RTSFLOW 000004 /* RTS flow ctl enabled */ 1438471Sache#define RC_CTSFLOW 000010 /* CTS flow ctl enabled */ 1448471Sache#define RC_DORXFER 000020 /* RXFER event planned */ 1458471Sache#define RC_DOXXFER 000040 /* RXFER event planned */ 1468471Sache#define RC_MODCHG 000100 /* Modem status changed */ 1478471Sache#define RC_OSUSP 000200 /* Output suspended */ 1488471Sache#define RC_OSBUSY 000400 /* start() routine in progress */ 1498471Sache#define RC_WAS_BUFOVFL 001000 /* low-level buffer ovferflow */ 1508471Sache#define RC_WAS_SILOVFL 002000 /* silo buffer overflow */ 1518471Sache#define RC_SEND_RDY 004000 /* ready to send */ 1528471Sache 1538471Sachestatic struct speedtab rc_speedtab[] = { 1548471Sache 0, 0, 1558471Sache 50, RC_BRD(50), 1568471Sache 75, RC_BRD(75), 1578471Sache 110, RC_BRD(110), 1588471Sache 134, RC_BRD(134), 1598471Sache 150, RC_BRD(150), 1608471Sache 200, RC_BRD(200), 1618471Sache 300, RC_BRD(300), 1628471Sache 600, RC_BRD(600), 1638471Sache 1200, RC_BRD(1200), 1648471Sache 1800, RC_BRD(1800), 1658471Sache 2400, RC_BRD(2400), 1668471Sache 4800, RC_BRD(4800), 1678471Sache 9600, RC_BRD(9600), 1688471Sache 19200, RC_BRD(19200), 1698471Sache 38400, RC_BRD(38400), 1708471Sache 57600, RC_BRD(57600), 1718471Sache /* real max value is 76800 with 9.8304 MHz clock */ 1728471Sache -1, -1 1738471Sache}; 1748471Sache 1758471Sache/* Table for translation of RCSR status bits to internal form */ 1768471Sachestatic int rc_rcsrt[16] = { 1778471Sache 0, TTY_OE, TTY_FE, 1788471Sache TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1798471Sache TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1808471Sache TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1818471Sache TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1828471Sache TTY_BI|TTY_PE|TTY_FE|TTY_OE 1838471Sache}; 1848471Sache 1858471Sache/* Static prototypes */ 1868471Sachestatic void rc_hwreset __P((int, unsigned int)); 1878471Sachestatic int rc_test __P((int, int)); 1888471Sachestatic void rc_discard_output __P((struct rc_chans *)); 1898471Sachestatic void rc_hardclose __P((struct rc_chans *)); 1908471Sachestatic int rc_modctl __P((struct rc_chans *, int, int)); 1918471Sachestatic void rc_start __P((struct tty *)); 1928471Sachestatic int rc_param __P((struct tty *, struct termios *)); 1938471Sachestatic void rc_registerdev __P((struct isa_device *id)); 1948471Sachestatic timeout_t rc_dtrwakeup; 1958471Sachestatic timeout_t rc_wakeup; 1968471Sachestatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 1978471Sache 1988471Sache/**********************************************/ 1998471Sache 2008471Sache/* Quick device probing */ 2018471Sacheint rcprobe(dvp) 2028471Sache struct isa_device *dvp; 2038471Sache{ 2048471Sache int irq = ffs(dvp->id_irq) - 1; 2058471Sache register int nec = dvp->id_iobase; 2068471Sache 2078471Sache if (dvp->id_unit > NRC) 2088471Sache return 0; 2098471Sache rc_softc[dvp->id_unit].rcb_probed = 0; 2108471Sache if (!RC_VALIDADDR(nec)) { 2118471Sache printf("rc%d: illegal base address %x\n", nec); 2128471Sache return 0; 2138471Sache } 2148471Sache if (!RC_VALIDIRQ(irq)) { 2158471Sache printf("rc%d: illegal IRQ value %d\n", irq); 2168471Sache return 0; 2178471Sache } 2188471Sache rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2198471Sache rcout(CD180_PPRH, 0x11); 2208471Sache if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2218471Sache return 0; 2228471Sache /* Now, test the board more thoroughly, with diagnostic */ 2238471Sache if (rc_test(nec, dvp->id_unit)) 2248471Sache return 0; 2258471Sache rc_softc[dvp->id_unit].rcb_probed = 1; 2268471Sache return 1; 2278471Sache} 2288471Sache 2298471Sachestatic struct kern_devconf kdc_rc[NRC] = { { 2308471Sache 0, 0, 0, /* filled in by dev_attach */ 2318471Sache "rc", 0, { MDDT_ISA, 0, "tty" }, 2328471Sache isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 2338471Sache &kdc_isa0, /* parent */ 2348471Sache 0, /* parentdata */ 2358471Sache DC_UNCONFIGURED, /* state */ 2368471Sache "RISCom/8 multiport card", 2378471Sache DC_CLS_SERIAL /* class */ 2388471Sache} }; 2398471Sache 2408471Sachestatic void 2418471Sacherc_registerdev(id) 2428471Sache struct isa_device *id; 2438471Sache{ 2448471Sache int unit; 2458471Sache 2468471Sache unit = id->id_unit; 2478471Sache if (unit != 0) 2488471Sache kdc_rc[unit] = kdc_rc[0]; 2498471Sache kdc_rc[unit].kdc_unit = unit; 2508471Sache kdc_rc[unit].kdc_isa = id; 2518471Sache kdc_rc[unit].kdc_state = DC_UNKNOWN; 2528471Sache dev_attach(&kdc_rc[unit]); 2538471Sache} 2548471Sache 2558471Sache/* Test device, then attach */ 2568471Sacheint rcattach(dvp) 2578471Sache struct isa_device *dvp; 2588471Sache{ 2598471Sache register int i, chan, nec = dvp->id_iobase; 2608471Sache struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 2618471Sache struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2628471Sache static int rc_wakeup_started = 0; 2638471Sache 2648471Sache /* Thorooughly test the device */ 2658471Sache if (!rcb->rcb_probed) 2668471Sache return 0; 2678471Sache rcb->rcb_addr = nec; 2688471Sache rcb->rcb_dtr = 0; 2698471Sache rcb->rcb_baserc = rc; 2708471Sache /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2718471Sache printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2728471Sache CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2738471Sache 2748471Sache rc_registerdev(dvp); 2758471Sache 2768471Sache for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 2778471Sache rc->rc_rcb = rcb; 2788471Sache rc->rc_chan = chan; 2798471Sache rc->rc_iptr = rc->rc_ibuf; 2808471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2818471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2828471Sache rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 2838471Sache rc->rc_cor2 = rc->rc_pendcmd = 0; 2848471Sache rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2858471Sache rc->rc_txitime = (~0UL >> 1); 2868471Sache rc->rc_dtrwait = 3 * hz; 2878471Sache rc->rc_ocnt = 0; 2888471Sache rc->rc_dcdwaits= 0; 2898471Sache rc->rc_hotchar = 0; 2908471Sache } 2918471Sache if (!rc_wakeup_started) { 2928471Sache rc_wakeup((void *)NULL); 2938471Sache rc_wakeup_started = 0; 2948471Sache } 2958471Sache return 1; 2968471Sache} 2978471Sache 2988471Sache/* RC interrupt handling */ 2998471Sachevoid rcintr(unit) 3008471Sache int unit; 3018471Sache{ 3028471Sache register struct rc_softc *rcb = &rc_softc[unit]; 3038471Sache register struct rc_chans *rc; 3048471Sache register u_char val; 3058471Sache register u_int nec, bsr, iack, ucnt; 3068471Sache int good_data, resid; 3078471Sache 3088471Sache nec = rcb->rcb_addr; 3098471Sache 3108471Sachepossibly_more_intrs: 3118471Sache bsr = ~(rcin(RC_BSR)); 3128471Sache 3138471Sache#ifdef RCDEBUG 3148471Sache printf("rcintr: %d (%02x) %s %s %s %s\n", unit, bsr, 3158471Sache (bsr & RC_BSR_TOUT)?"TOUT":"", 3168471Sache (bsr & RC_BSR_RXINT)?"RXINT":"", 3178471Sache (bsr & RC_BSR_TXINT)?"TXINT":"", 3188471Sache (bsr & RC_BSR_MOINT)?"MOINT":""); 3198471Sache#endif 3208471Sache if (bsr & RC_BSR_RXINT) { 3218471Sache iack = rcin(RC_PILR_RX); 3228471Sache#ifdef RCDEBUG 3238471Sache printf("rxint iack = %02x\n", iack); 3248471Sache#endif 3258471Sache rc = rcb->rcb_baserc + (rcin(CD180_GICR) >> GICR_LSH); 3268471Sache ucnt = rcin(CD180_RDCR); 3278471Sache resid = 0; 3288471Sache good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3298471Sache#ifdef RCDEBUG 3308471Sache printrcflags(rc, "rxint"); 3318471Sache#endif 3328471Sache /* Do RTS flow control stuff */ 3338471Sache if ( (rc->rc_flags & RC_RTSFLOW) 3348471Sache || !rc->rc_tp 3358471Sache || !(rc->rc_tp->t_state & TS_ISOPEN)) { 3368471Sache if ( (!rc->rc_tp 3378471Sache || !(rc->rc_tp->t_state & TS_ISOPEN) 3388471Sache || (rc->rc_tp->t_state & TS_TBLOCK)) 3398471Sache && (rc->rc_msvr & MSVR_RTS)) 3408471Sache rcout(CD180_MSVR, 3418471Sache rc->rc_msvr &= ~MSVR_RTS); 3428471Sache else if (!(rc->rc_msvr & MSVR_RTS)) 3438471Sache rcout(CD180_MSVR, 3448471Sache rc->rc_msvr |= MSVR_RTS); 3458471Sache } 3468471Sache 3478471Sache if (rc->rc_tp && (rc->rc_tp->t_state & TS_ISOPEN)) { 3488471Sache /* check for input buffer overflow */ 3498471Sache if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3508471Sache resid = ucnt; 3518471Sache ucnt = rc->rc_bufend - rc->rc_iptr; 3528471Sache resid -= ucnt; 3538471Sache if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3548471Sache rc->rc_flags |= RC_WAS_BUFOVFL; 3558471Sache rc_scheduled_event++; 3568471Sache } 3578471Sache } 3588471Sache /* check foor good data */ 3598471Sache if (good_data) { 3608471Sache while (ucnt-- > 0) { 3618471Sache val = rcin(CD180_RDR); 3628471Sache rc->rc_iptr[0] = val; 3638471Sache rc->rc_iptr[INPUT_FLAGS_SHIFT] = 0; 3648471Sache rc->rc_iptr++; 3658471Sache rc_scheduled_event++; 3668471Sache if (rc->rc_hotchar != 0 && val == rc->rc_hotchar) 3678471Sache setsofttty(); 3688471Sache } 3698471Sache } else { 3708471Sache /* Store also status data */ 3718471Sache while (ucnt-- > 0) { 3728471Sache iack = rcin(CD180_RCSR); 3738471Sache if (iack & RCSR_TOUT) { 3748471Sache (void) rcin(CD180_RDR); 3758471Sache break; 3768471Sache } 3778471Sache if ( (iack & RCSR_OE) 3788471Sache && !(rc->rc_flags & RC_WAS_SILOVFL)) { 3798471Sache rc->rc_flags |= RC_WAS_SILOVFL; 3808471Sache rc_scheduled_event++; 3818471Sache } 3828471Sache val = rcin(CD180_RDR); 3838471Sache /* 3848471Sache Don't store PE if IGNPAR and BREAK if IGNBRK, 3858471Sache this hack allows "raw" tty optimization 3868471Sache works even if IGN* is set. 3878471Sache */ 3888471Sache if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_BREAK)) 3898471Sache || (!(iack & (RCSR_PE|RCSR_FE)) 3908471Sache || !(rc->rc_tp->t_iflag & IGNPAR)) 3918471Sache && (!(iack & RCSR_BREAK) 3928471Sache || !(rc->rc_tp->t_iflag & IGNBRK))) { 3938471Sache if ( (iack & (RCSR_PE|RCSR_FE)) 3948471Sache && (rc->rc_tp->t_state & TS_CAN_BYPASS_L_RINT) 3958471Sache && ((iack & RCSR_FE) 3968471Sache || (iack & RCSR_PE) 3978471Sache && (rc->rc_tp->t_iflag & INPCK))) 3988471Sache val = 0; 3998471Sache else if (rc->rc_hotchar != 0 && val == rc->rc_hotchar) 4008471Sache setsofttty(); 4018471Sache rc->rc_iptr[0] = val; 4028471Sache rc->rc_iptr[INPUT_FLAGS_SHIFT] = iack; 4038471Sache rc->rc_iptr++; 4048471Sache rc_scheduled_event++; 4058471Sache } 4068471Sache } 4078471Sache } 4088471Sache rc->rc_flags |= RC_DORXFER; 4098471Sache } else 4108471Sache resid = ucnt; 4118471Sache /* Clear FIFO if necessary */ 4128471Sache while (resid-- > 0) { 4138471Sache if (!good_data) 4148471Sache iack = rcin(CD180_RCSR); 4158471Sache else 4168471Sache iack = 0; 4178471Sache (void) rcin(CD180_RDR); 4188471Sache if (iack & RCSR_TOUT) 4198471Sache break; 4208471Sache } 4218471Sache rcout(CD180_EOIR, 0); 4228471Sache goto possibly_more_intrs; 4238471Sache } 4248471Sache if (bsr & RC_BSR_MOINT) { 4258471Sache iack = rcin(CD180_MCR); 4268471Sache rc = rcb->rcb_baserc + (rcin(CD180_GICR) >> GICR_LSH); 4278471Sache#ifdef RCDEBUG 4288471Sache printrcflags(rc, "moint"); 4298471Sache#endif 4308471Sache rc->rc_msvr = rcin(CD180_MSVR); 4318471Sache if (rc->rc_flags & RC_CTSFLOW) { 4328471Sache if (rc->rc_msvr & MSVR_CTS) 4338471Sache rc->rc_flags |= RC_SEND_RDY; 4348471Sache else 4358471Sache rc->rc_flags &= ~RC_SEND_RDY; 4368471Sache } 4378471Sache if (iack & MCR_CDCHG) { 4388471Sache rc->rc_flags |= RC_MODCHG; 4398471Sache rc_scheduled_event += LOTS_OF_EVENTS; 4408471Sache setsofttty(); 4418471Sache } 4428471Sache rcout(CD180_EOIR, 0); 4438471Sache goto possibly_more_intrs; 4448471Sache } 4458471Sache if (bsr & RC_BSR_TXINT) { 4468471Sache rc = rcb->rcb_baserc + (rcin(CD180_GICR) >> GICR_LSH); 4478471Sache rc->rc_txitime = time.tv_sec; 4488471Sache#ifdef RCDEBUG 4498471Sache printrcflags(rc, "txint"); 4508471Sache#endif 4518471Sache if ( (rc->rc_flags & RC_OSUSP) 4528471Sache || !(rc->rc_flags & RC_SEND_RDY)) 4538471Sache goto skip; 4548471Sache ucnt = rc->rc_obufend - rc->rc_optr; 4558471Sache if (ucnt > CD180_NFIFO) 4568471Sache ucnt = CD180_NFIFO; 4578471Sache /* Handle breaks and other stuff */ 4588471Sache if (rc->rc_pendcmd) { 4598471Sache rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4608471Sache rcout(CD180_TDR, CD180_C_ESC); 4618471Sache rcout(CD180_TDR, rc->rc_pendcmd); 4628471Sache rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4638471Sache rc->rc_pendcmd = 0; 4648471Sache rcout(CD180_EOIR, 0); 4658471Sache goto possibly_more_intrs; 4668471Sache } 4678471Sache while (ucnt-- > 0) 4688471Sache rcout(CD180_TDR, *rc->rc_optr++); 4698471Sache 4708471Sache /* output completed? */ 4718471Sache if (rc->rc_optr >= rc->rc_obufend) { 4728471Sache rcout(CD180_IER, rc->rc_ier &= 4738471Sache ~(IER_TXRDY|IER_TXMPTY)); 4748471Sache#ifdef RCDEBUG 4758471Sache printf("tx intr disabled\n"); 4768471Sache#endif 4778471Sache rc->rc_flags |= RC_DOXXFER; 4788471Sache rc_scheduled_event += LOTS_OF_EVENTS; 4798471Sache setsofttty(); 4808471Sache } 4818471Sache skip: 4828471Sache rcout(CD180_EOIR, 0); 4838471Sache goto possibly_more_intrs; 4848471Sache } 4858471Sache rcout(RC_BSR, 0); /* -/- */ 4868471Sache#ifdef RCDEBUG 4878471Sache if (rc_scheduled_event) 4888471Sache printf("event scheduled unit %d\n", unit); 4898471Sache#endif 4908471Sache} 4918471Sache 4928471Sache/* Feed characters to output buffer */ 4938471Sachestatic void rc_start(tp) 4948471Sacheregister struct tty *tp; 4958471Sache{ 4968471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 4978471Sache register int nec = rc->rc_rcb->rcb_addr, s; 4988471Sache 4998471Sache if (rc->rc_flags & RC_OSBUSY) 5008471Sache return; 5018471Sache s = spltty(); 5028471Sache rc->rc_flags |= RC_OSBUSY; 5038471Sache disable_intr(); 5048471Sache if (tp->t_state & TS_TTSTOP) 5058471Sache rc->rc_flags |= RC_OSUSP; 5068471Sache else 5078471Sache rc->rc_flags &= ~RC_OSUSP; 5088471Sache /* Do RTS flow control stuff */ 5098471Sache if (rc->rc_flags & RC_RTSFLOW) { 5108471Sache if ((tp->t_state & TS_TBLOCK) && 5118471Sache (rc->rc_msvr & MSVR_RTS)) { 5128471Sache rcout(CD180_CAR, rc->rc_chan); 5138471Sache rcout(CD180_MSVR, 5148471Sache rc->rc_msvr &= ~MSVR_RTS); 5158471Sache } else if (!(rc->rc_msvr & MSVR_RTS)) { 5168471Sache rcout(CD180_CAR, rc->rc_chan); 5178471Sache rcout(CD180_MSVR, 5188471Sache rc->rc_msvr |= MSVR_RTS); 5198471Sache } 5208471Sache } 5218471Sache enable_intr(); 5228471Sache if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5238471Sache goto out; 5248471Sache#ifdef RCDEBUG 5258471Sache printrcflags(rc, "rcstart"); 5268471Sache#endif 5278471Sache /* Checking for stale tx intrs */ 5288471Sache if ((rc->rc_ier & IER_TXRDY) && 5298471Sache (rc->rc_txitime - time.tv_sec) > RC_TXTIMEO) { 5308471Sache rc->rc_txitime = time.tv_sec; 5318471Sache printf("rc%d: chan %d: lost TX intr, reinit\n", 5328471Sache rc->rc_rcb->rcb_unit, rc->rc_chan); 5338471Sache /* try to re-initialize channel */ 5348471Sache rcout(CD180_CAR, rc->rc_chan); 5358471Sache CCRCMD(CCR_RESETCHAN); 5368471Sache (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 5378471Sache } 5388471Sache if (tp->t_outq.c_cc <= tp->t_lowat) { 5398471Sache if (tp->t_state & TS_ASLEEP) { 5408471Sache tp->t_state &= ~TS_ASLEEP; 5418471Sache wakeup((caddr_t)&tp->t_outq); 5428471Sache } 5438471Sache selwakeup(&tp->t_wsel); 5448471Sache } 5458471Sache#ifdef RCDEBUG 5468471Sache printf("rcstart: q = %d olen = %d\n", 5478471Sache tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5488471Sache#endif 5498471Sache /* maybe we need to check for lost intrs here */ 5508471Sache if (rc->rc_optr < rc->rc_obufend) 5518471Sache goto out; /* output still in progress ... */ 5528471Sache 5538471Sache if (tp->t_outq.c_cc > 0) { 5548471Sache u_int ocnt; 5558471Sache 5568471Sache tp->t_state |= TS_BUSY; 5578471Sache ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 5588471Sache disable_intr(); 5598471Sache rc->rc_ocnt = ocnt; 5608471Sache rc->rc_optr = rc->rc_obuf; 5618471Sache rc->rc_obufend = rc->rc_optr + rc->rc_ocnt; 5628471Sache enable_intr(); 5638471Sache if ((rc->rc_ier & IER_TXRDY) == 0) { 5648471Sache#ifdef RCDEBUG 5658471Sache printf("rcstart: enable txint\n"); 5668471Sache#endif 5678471Sache rcout(CD180_CAR, rc->rc_chan); 5688471Sache rcout(CD180_IER, rc->rc_ier |= IER_TXRDY); 5698471Sache } 5708471Sache } else { 5718471Sache rc->rc_ocnt = 0; 5728471Sache tp->t_flags &= ~TS_BUSY; 5738471Sache } 5748471Sacheout: 5758471Sache rc->rc_flags &= ~RC_OSBUSY; 5768471Sache (void) splx(s); 5778471Sache} 5788471Sache 5798471Sache/* Handle delayed events. */ 5808471Sachevoid rcpoll() 5818471Sache{ 5828471Sache register struct rc_chans *rc; 5838471Sache register struct rc_softc *rcb; 5848471Sache register u_char *tptr, *eptr; 5858471Sache register int s; 5868471Sache register struct tty *tp; 5878471Sache register int chan, icnt, c, nec, unit; 5888471Sache 5898471Sache if (rc_scheduled_event == 0) 5908471Sache return; 5918471Sacherepeat: 5928471Sache for (unit = 0; unit < NRC; unit++) { 5938471Sache rcb = &rc_softc[unit]; 5948471Sache rc = rcb->rcb_baserc; 5958471Sache nec = rc->rc_rcb->rcb_addr; 5968471Sache for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 5978471Sache tp = rc->rc_tp; 5988471Sache#ifdef RCDEBUG 5998471Sache if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 6008471Sache RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 6018471Sache printrcflags(rc, "rcevent"); 6028471Sache#endif 6038471Sache if (rc->rc_flags & RC_WAS_BUFOVFL) { 6048471Sache rc->rc_flags &= ~RC_WAS_BUFOVFL; 6058471Sache rc_scheduled_event--; 6068471Sache printf("rc%d/%d: interrupt-level buffer overflow\n", 6078471Sache unit, chan); 6088471Sache } 6098471Sache if (rc->rc_flags & RC_WAS_SILOVFL) { 6108471Sache rc->rc_flags &= ~RC_WAS_SILOVFL; 6118471Sache rc_scheduled_event--; 6128471Sache printf("rc%d/%d: silo overflow\n", 6138471Sache unit, chan); 6148471Sache } 6158471Sache if (rc->rc_flags & RC_MODCHG) { 6168471Sache rc->rc_flags &= ~RC_MODCHG; 6178471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6188471Sache if (tp) 6198471Sache (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 6208471Sache } 6218471Sache if (rc->rc_flags & RC_DORXFER) { 6228471Sache rc->rc_flags &= ~RC_DORXFER; 6238471Sache 6248471Sache disable_intr(); 6258471Sache eptr = rc->rc_iptr; 6268471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 6278471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6288471Sache else 6298471Sache tptr = rc->rc_ibuf; 6308471Sache icnt = eptr - tptr; 6318471Sache if (icnt > 0) { 6328471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 6338471Sache rc->rc_iptr = rc->rc_ibuf; 6348471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 6358471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 6368471Sache } else { 6378471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6388471Sache rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 6398471Sache rc->rc_hiwat = 6408471Sache &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 6418471Sache } 6428471Sache if ((rc->rc_flags & RC_RTSFLOW) 6438471Sache && !(rc->rc_msvr & MSVR_RTS) 6448471Sache && tp != NULL 6458471Sache && (tp->t_state & TS_ISOPEN) 6468471Sache && !(tp->t_state & TS_TBLOCK)) { 6478471Sache rcout(CD180_CAR, chan); 6488471Sache rcout(CD180_MSVR, 6498471Sache rc->rc_msvr |= MSVR_RTS); 6508471Sache } 6518471Sache rc_scheduled_event -= icnt; 6528471Sache } 6538471Sache enable_intr(); 6548471Sache 6558471Sache if (icnt <= 0 || !tp || !(tp->t_state & TS_ISOPEN)) 6568471Sache goto done1; 6578471Sache 6588471Sache if ( linesw[tp->t_line].l_rint == ttyinput 6598471Sache && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 6608471Sache && !(tp->t_state & TS_TBLOCK) 6618471Sache && (tp->t_rawq.c_cc + icnt) > RC_IHIGHWATER) { 6628471Sache int queue_full = 0; 6638471Sache 6648471Sache if ((tp->t_iflag & IXOFF) && 6658471Sache tp->t_cc[VSTOP] != _POSIX_VDISABLE && 6668471Sache (queue_full = putc(tp->t_cc[VSTOP], &tp->t_outq)) == 0 || 6678471Sache (rc->rc_flags & RC_RTSFLOW)) { 6688471Sache tp->t_state |= TS_TBLOCK; 6698471Sache ttstart(tp); 6708471Sache if (queue_full) /* try again */ 6718471Sache tp->t_state &= ~TS_TBLOCK; 6728471Sache } 6738471Sache } 6748471Sache if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 6758471Sache && !(tp->t_state & TS_LOCAL)) { 6768471Sache tk_nin += icnt; 6778471Sache tk_rawcc += icnt; 6788471Sache tp->t_rawcc += icnt; 6798471Sache if (b_to_q(tptr, icnt, &tp->t_rawq)) 6808471Sache printf("rc%d/%d: tty-level buffer overflow\n", 6818471Sache unit, chan); 6828471Sache ttwakeup(tp); 6838471Sache if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 6848471Sache || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 6858471Sache tp->t_state &= ~TS_TTSTOP; 6868471Sache tp->t_lflag &= ~FLUSHO; 6878471Sache ttstart(tp); 6888471Sache } 6898471Sache } else { 6908471Sache for (; tptr < eptr; tptr++) 6918471Sache (*linesw[tp->t_line].l_rint) 6928471Sache (tptr[0] | 6938471Sache rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 6948471Sache } 6958471Sachedone1: 6968471Sache } 6978471Sache if (rc->rc_flags & RC_DOXXFER) { 6988471Sache rc_discard_output(rc); 6998471Sache (*linesw[tp->t_line].l_start)(tp); 7008471Sache } 7018471Sache } 7028471Sache if (rc_scheduled_event == 0) 7038471Sache break; 7048471Sache } 7058471Sache if (rc_scheduled_event >= LOTS_OF_EVENTS) 7068471Sache goto repeat; 7078471Sache} 7088471Sache 7098471Sachevoid rcstop(tp, rw) 7108471Sache register struct tty *tp; 7118471Sache int rw; 7128471Sache{ 7138471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 7148471Sache u_char *tptr, *eptr; 7158471Sache 7168471Sache#ifdef RCDEBUG 7178471Sache printf("rcstop %d/%d: %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 7188471Sache (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 7198471Sache#endif 7208471Sache if (rw & FWRITE) 7218471Sache rc_discard_output(rc); 7228471Sache disable_intr(); 7238471Sache if (rw & FREAD) { 7248471Sache eptr = rc->rc_iptr; 7258471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 7268471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7278471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7288471Sache } else { 7298471Sache tptr = rc->rc_ibuf; 7308471Sache rc->rc_iptr = rc->rc_ibuf; 7318471Sache } 7328471Sache rc_scheduled_event -= eptr - tptr; 7338471Sache } 7348471Sache if (tp->t_state & TS_TTSTOP) 7358471Sache rc->rc_flags |= RC_OSUSP; 7368471Sache else 7378471Sache rc->rc_flags &= ~RC_OSUSP; 7388471Sache enable_intr(); 7398471Sache} 7408471Sache 7418471Sacheint rcopen(dev, flag, mode, p) 7428471Sache dev_t dev; 7438471Sache int flag, mode; 7448471Sache struct proc *p; 7458471Sache{ 7468471Sache register struct rc_chans *rc; 7478471Sache register struct tty *tp; 7488471Sache int unit, nec, s, error = 0; 7498471Sache 7508471Sache unit = GET_UNIT(dev); 7518471Sache if (unit >= NRC * CD180_NCHAN) 7528471Sache return ENXIO; 7538471Sache rc = &rc_chans[unit]; 7548471Sache tp = rc->rc_tp = &rc_tty[unit]; 7558471Sache nec = rc->rc_rcb->rcb_addr; 7568471Sache#ifdef RCDEBUG 7578471Sache printf("rcopen: dev %02x\n", dev); 7588471Sache#endif 7598471Sache s = spltty(); 7608471Sache 7618471Sacheagain: 7628471Sache while (rc->rc_flags & RC_DTR_OFF) { 7638471Sache error = tsleep(&rc->rc_dtrwait, TTIPRI | PCATCH, "rcdtr", 0); 7648471Sache if (error != 0) 7658471Sache goto out; 7668471Sache } 7678471Sache if (tp->t_state & TS_ISOPEN) { 7688471Sache if (CALLOUT(dev)) { 7698471Sache if (!(rc->rc_flags & RC_ACTOUT)) { 7708471Sache error = EBUSY; 7718471Sache goto out; 7728471Sache } 7738471Sache } else { 7748471Sache if (rc->rc_flags & RC_ACTOUT) { 7758471Sache if (flag & O_NONBLOCK) { 7768471Sache error = EBUSY; 7778471Sache goto out; 7788471Sache } 7798471Sache if (error = tsleep(&rc->rc_rcb, 7808471Sache TTIPRI|PCATCH, "rcbi", 0)) 7818471Sache goto out; 7828471Sache goto again; 7838471Sache } 7848471Sache } 7858471Sache if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 7868471Sache error = EBUSY; 7878471Sache goto out; 7888471Sache } 7898471Sache } else { 7908471Sache tp->t_oproc = rc_start; 7918471Sache tp->t_param = rc_param; 7928471Sache tp->t_dev = dev; 7938471Sache 7948471Sache if (tp->t_ispeed == 0) { 7958471Sache ttychars(tp); 7968471Sache tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 7978471Sache tp->t_cflag = TTYDEF_CFLAG; 7988471Sache tp->t_ispeed = tp->t_ospeed = 9600; 7998471Sache } 8008471Sache if (CALLOUT(dev)) 8018471Sache tp->t_cflag |= CLOCAL; 8028471Sache else 8038471Sache tp->t_cflag &= ~CLOCAL; 8048471Sache 8058471Sache (void) rc_modctl(rc, TIOCM_DTR|TIOCM_RTS, DMSET); 8068471Sache 8078471Sache error = rc_param(tp, &tp->t_termios); 8088471Sache if (error) 8098471Sache goto out; 8108471Sache 8118471Sache ttsetwater(tp); 8128471Sache 8138471Sache disable_intr(); 8148471Sache rcout(CD180_CAR, rc->rc_chan); 8158471Sache rc->rc_msvr = rcin(CD180_MSVR); 8168471Sache rcout(CD180_IER, rc->rc_ier |= IER_CD | IER_TXRDY | IER_RXD); 8178471Sache enable_intr(); 8188471Sache 8198471Sache if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 8208471Sache (*linesw[tp->t_line].l_modem)(tp, 1); 8218471Sache } 8228471Sache if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 8238471Sache && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 8248471Sache rc->rc_dcdwaits++; 8258471Sache error = tsleep(&tp->t_rawq, TTIPRI | PCATCH, "rcdcd", 0); 8268471Sache rc->rc_dcdwaits--; 8278471Sache if (error != 0) 8288471Sache goto out; 8298471Sache goto again; 8308471Sache } 8318471Sache error = (*linesw[tp->t_line].l_open)(dev, tp); 8328471Sache if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 8338471Sache rc->rc_flags |= RC_ACTOUT; 8348471Sacheout: 8358471Sache (void) splx(s); 8368471Sache 8378471Sache if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 8388471Sache rc_hardclose(rc); 8398471Sache 8408471Sache return error; 8418471Sache} 8428471Sache 8438471Sacheint rcclose(dev, flag, mode, p) 8448471Sache dev_t dev; 8458471Sache int flag, mode; 8468471Sache struct proc *p; 8478471Sache{ 8488471Sache register struct rc_chans *rc; 8498471Sache register struct tty *tp; 8508471Sache int s, unit = GET_UNIT(dev); 8518471Sache 8528471Sache if (unit >= NRC * CD180_NCHAN) 8538471Sache return ENXIO; 8548471Sache rc = &rc_chans[unit]; 8558471Sache tp = rc->rc_tp; 8568471Sache s = spltty(); 8578471Sache (*linesw[tp->t_line].l_close)(tp, flag); 8588471Sache rcstop(tp, FREAD | FWRITE); 8598471Sache rc_hardclose(rc); 8608471Sache ttyclose(tp); 8618471Sache splx(s); 8628471Sache return 0; 8638471Sache} 8648471Sache 8658471Sachestatic void rc_hardclose(rc) 8668471Sacheregister struct rc_chans *rc; 8678471Sache{ 8688471Sache register int s, nec = rc->rc_rcb->rcb_addr; 8698471Sache register struct tty *tp = rc->rc_tp; 8708471Sache 8718471Sache s = spltty(); 8728471Sache rcout(CD180_CAR, rc->rc_chan); 8738471Sache 8748471Sache /* Disable all intrs */ 8758471Sache rcout(CD180_IER, rc->rc_ier = 0); 8768471Sache if ( tp->t_cflag & HUPCL 8778471Sache || !(rc->rc_flags & RC_ACTOUT) 8788471Sache && !(rc->rc_msvr & MSVR_CD) 8798471Sache && !(tp->t_cflag & CLOCAL) 8808471Sache || !(tp->t_state & TS_ISOPEN)) { 8818471Sache (void) rc_modctl(rc, TIOCM_RTS, DMSET); 8828471Sache if (rc->rc_dtrwait) { 8838471Sache timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 8848471Sache rc->rc_flags |= RC_DTR_OFF; 8858471Sache } 8868471Sache } 8878471Sache rc->rc_flags &= ~RC_ACTOUT; 8888471Sache wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 8898471Sache wakeup((caddr_t) &tp->t_rawq); /* wake dcd */ 8908471Sache (void) splx(s); 8918471Sache} 8928471Sache 8938471Sache/* Read from line */ 8948471Sacheint rcread(dev, uio, flag) 8958471Sache dev_t dev; 8968471Sache struct uio *uio; 8978471Sache int flag; 8988471Sache{ 8998471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9008471Sache return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 9018471Sache} 9028471Sache 9038471Sache/* Write to line */ 9048471Sacheint rcwrite(dev, uio, flag) 9058471Sache dev_t dev; 9068471Sache struct uio *uio; 9078471Sache int flag; 9088471Sache{ 9098471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9108471Sache return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 9118471Sache} 9128471Sache 9138471Sache/* Reset the bastard */ 9148471Sachestatic void rc_hwreset(nec, chipid) 9158471Sache register int nec; 9168471Sache unsigned int chipid; 9178471Sache{ 9188471Sache CCRCMD(CCR_HWRESET); /* Hardware reset */ 9198471Sache DELAY(20000); 9208471Sache rcout(RC_BSR_TOUT, 0); /* Clear timeout */ 9218471Sache rcout(CD180_GIVR, chipid); 9228471Sache rcout(CD180_GICR, 0); 9238471Sache 9248471Sache /* Set Prescaler Registers (1 msec) */ 9258471Sache rcout(CD180_PPRL, (RC_OSCFREQ / 1000) & 0xFF); 9268471Sache rcout(CD180_PPRH, (RC_OSCFREQ / 1000) >> 8); 9278471Sache 9288471Sache /* Initialize Priority Interrupt Level Registers */ 9298471Sache rcout(CD180_PILR1, RC_PILR_MODEM); 9308471Sache rcout(CD180_PILR2, RC_PILR_TX); 9318471Sache rcout(CD180_PILR3, RC_PILR_RX); 9328471Sache 9338471Sache /* Reset DTR */ 9348471Sache rcout(RC_DTR, ~0); 9358471Sache} 9368471Sache 9378471Sache/* Set channel parameters */ 9388471Sachestatic int rc_param(tp, ts) 9398471Sache register struct tty *tp; 9408471Sache struct termios *ts; 9418471Sache{ 9428471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 9438471Sache register int nec = rc->rc_rcb->rcb_addr; 9448471Sache int idivs, odivs, s, val, cflag, iflag, lflag; 9458471Sache 9468471Sache odivs = ttspeedtab(ts->c_ospeed, rc_speedtab); 9478471Sache if (ts->c_ispeed == 0) 9488471Sache ts->c_ispeed = ts->c_ospeed; 9498471Sache idivs = ttspeedtab(ts->c_ispeed, rc_speedtab); 9508471Sache if (idivs < 0 || odivs < 0) 9518471Sache return (EINVAL); 9528471Sache 9538471Sache s = spltty(); 9548471Sache 9558471Sache /* If speed == 0, hangup line */ 9568471Sache if (ts->c_ospeed == 0) 9578471Sache rc_modctl(rc, TIOCM_DTR, DMBIC); 9588471Sache else 9598471Sache rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMBIS); 9608471Sache 9618471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 9628471Sache cflag = ts->c_cflag; 9638471Sache iflag = ts->c_iflag; 9648471Sache lflag = ts->c_lflag; 9658471Sache 9668471Sache /* Select channel */ 9678471Sache rcout(CD180_CAR, rc->rc_chan); 9688471Sache 9698471Sache if (idivs > 0) { 9708471Sache rcout(CD180_RBPRL, idivs & 0xFF); 9718471Sache rcout(CD180_RBPRH, idivs >> 8); 9728471Sache } 9738471Sache if (odivs > 0) { 9748471Sache rcout(CD180_TBPRL, odivs & 0xFF); 9758471Sache rcout(CD180_TBPRH, odivs >> 8); 9768471Sache } 9778471Sache 9788471Sache /* set timeout value */ 9798471Sache rcout(CD180_RTPR, 0); 9808471Sache 9818471Sache switch (cflag & CSIZE) { 9828471Sache case CS5: val = COR1_5BITS; break; 9838471Sache case CS6: val = COR1_6BITS; break; 9848471Sache case CS7: val = COR1_7BITS; break; 9858471Sache default: 9868471Sache case CS8: val = COR1_8BITS; break; 9878471Sache } 9888471Sache if (cflag & PARENB) { 9898471Sache val |= COR1_NORMPAR; 9908471Sache if (cflag & PARODD) 9918471Sache val |= COR1_ODDP; 9928471Sache } else 9938471Sache val |= COR1_IGNORE; 9948471Sache if (cflag & CSTOPB) 9958471Sache val |= COR1_2SB; 9968471Sache rcout(CD180_COR1, val); 9978471Sache 9988471Sache /* Set FIFO threshold */ 9998471Sache rcout(CD180_COR3, ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2); 10008471Sache CCRCMD(CCR_CORCHG1 | CCR_CORCHG3); 10018471Sache 10028471Sache /* Initialize on-chip automatic flow control */ 10038471Sache val = 0; 10048471Sache 10058471Sache if (cflag & CCTS_OFLOW) { 10068471Sache rc->rc_flags |= RC_CTSFLOW; 10078471Sache val |= COR2_CTSAE; 10088471Sache rc->rc_msvr = rcin(CD180_MSVR); 10098471Sache if (rc->rc_msvr & MSVR_CTS) 10108471Sache rc->rc_flags |= RC_SEND_RDY; 10118471Sache else 10128471Sache rc->rc_flags &= ~RC_SEND_RDY; 10138471Sache } 10148471Sache else 10158471Sache rc->rc_flags |= RC_SEND_RDY; 10168471Sache 10178471Sache if (cflag & CRTS_IFLOW) 10188471Sache rc->rc_flags |= RC_RTSFLOW; 10198471Sache 10208471Sache if (iflag & (IXON|IXOFF)) { 10218471Sache /* Initailize xon/xoff characters */ 10228471Sache rcout(CD180_SCHR1, ts->c_cc[CSTART]); 10238471Sache rcout(CD180_SCHR2, ts->c_cc[CSTOP]); 10248471Sache if (iflag & IXON) { 10258471Sache val |= COR2_TXIBE; 10268471Sache if (iflag & IXANY) 10278471Sache val |= COR2_IXM; 10288471Sache } 10298471Sache } 10308471Sache 10318471Sache rcout(CD180_COR2, val); 10328471Sache CCRCMD(CCR_CORCHG2); 10338471Sache 10348471Sache disc_optim(tp, ts, rc); 10358471Sache 10368471Sache /* modem ctl */ 10378471Sache rcout(CD180_MCOR1, MCOR1_CDZD); 10388471Sache rcout(CD180_MCOR2, MCOR2_CDOD); 10398471Sache 10408471Sache /* enable i/o and interrupts */ 10418471Sache CCRCMD(CCR_TXEN|CCR_RXEN); 10428471Sache rcout(CD180_IER, rc->rc_ier |= IER_CD | IER_RXD); 10438471Sache 10448471Sache (void) splx(s); 10458471Sache return 0; 10468471Sache} 10478471Sache 10488471Sacheint rcioctl(dev, cmd, data, flag, p) 10498471Sachedev_t dev; 10508471Sacheint cmd, flag; 10518471Sachecaddr_t data; 10528471Sachestruct proc *p; 10538471Sache{ 10548471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 10558471Sache register int s, error; 10568471Sache struct tty *tp = rc->rc_tp; 10578471Sache 10588471Sache error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 10598471Sache if (error >= 0) 10608471Sache return (error); 10618471Sache error = ttioctl(tp, cmd, data, flag); 10628471Sache if (error >= 0) 10638471Sache return (error); 10648471Sache s = spltty(); 10658471Sache 10668471Sache switch (cmd) { 10678471Sache case TIOCSBRK: 10688471Sache rc->rc_pendcmd = CD180_C_SBRK; 10698471Sache break; 10708471Sache 10718471Sache case TIOCCBRK: 10728471Sache rc->rc_pendcmd = CD180_C_EBRK; 10738471Sache break; 10748471Sache 10758471Sache case TIOCSDTR: 10768471Sache (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMBIS); 10778471Sache break; 10788471Sache 10798471Sache case TIOCCDTR: 10808471Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 10818471Sache break; 10828471Sache 10838471Sache case TIOCMGET: 10848471Sache *(int *) data = rc_modctl(rc, 0, DMGET); 10858471Sache break; 10868471Sache 10878471Sache case TIOCMSET: 10888471Sache (void) rc_modctl(rc, *(int *) data, DMSET); 10898471Sache break; 10908471Sache 10918471Sache case TIOCMBIC: 10928471Sache (void) rc_modctl(rc, *(int *) data, DMBIC); 10938471Sache break; 10948471Sache 10958471Sache case TIOCMBIS: 10968471Sache (void) rc_modctl(rc, *(int *) data, DMBIS); 10978471Sache break; 10988471Sache 10998471Sache case TIOCMSDTRWAIT: 11008471Sache error = suser(p->p_ucred, &p->p_acflag); 11018471Sache if (error != 0) { 11028471Sache splx(s); 11038471Sache return (error); 11048471Sache } 11058471Sache rc->rc_dtrwait = *(int *)data * hz / 100; 11068471Sache break; 11078471Sache 11088471Sache case TIOCMGDTRWAIT: 11098471Sache *(int *)data = rc->rc_dtrwait * 100 / hz; 11108471Sache break; 11118471Sache 11128471Sache default: 11138471Sache (void) splx(s); 11148471Sache return ENOTTY; 11158471Sache } 11168471Sache (void) splx(s); 11178471Sache return 0; 11188471Sache} 11198471Sache 11208471Sache 11218471Sache/* Modem control routines */ 11228471Sache 11238471Sachestatic int rc_modctl(rc, bits, cmd) 11248471Sacheregister struct rc_chans *rc; 11258471Sacheint bits, cmd; 11268471Sache{ 11278471Sache register int nec = rc->rc_rcb->rcb_addr; 11288471Sache u_char *dtr = &rc->rc_rcb->rcb_dtr; 11298471Sache unsigned int msvr; 11308471Sache 11318471Sache rcout(CD180_CAR, rc->rc_chan); 11328471Sache 11338471Sache switch (cmd) { 11348471Sache case DMSET: 11358471Sache rcout(CD180_MSVR, 0); 11368471Sache *dtr &= ~(1 << rc->rc_chan); 11378471Sache /* falltrough */ 11388471Sache 11398471Sache case DMBIS: 11408471Sache if (bits & TIOCM_RTS) 11418471Sache rcout(CD180_MSVR, MSVR_RTS); 11428471Sache if (bits & TIOCM_DTR) 11438471Sache rcout(RC_DTR, ~(*dtr |= (1 << rc->rc_chan))); 11448471Sache break; 11458471Sache 11468471Sache case DMGET: 11478471Sache msvr = rcin(CD180_MSVR); 11488471Sache bits = TIOCM_LE; 11498471Sache 11508471Sache if (msvr & MSVR_RTS) 11518471Sache bits |= TIOCM_RTS; 11528471Sache if (msvr & MSVR_CTS) 11538471Sache bits |= TIOCM_CTS; 11548471Sache if (msvr & MSVR_DSR) 11558471Sache bits |= TIOCM_DSR; 11568471Sache if (msvr & MSVR_DTR) 11578471Sache bits |= TIOCM_DTR; 11588471Sache return bits; 11598471Sache 11608471Sache case DMBIC: 11618471Sache if (bits & TIOCM_DTR) 11628471Sache rcout(RC_DTR, ~(*dtr &= ~(1 << rc->rc_chan))); 11638471Sache if (bits & TIOCM_RTS) 11648471Sache rcout(CD180_MSVR, 0); 11658471Sache break; 11668471Sache } 11678471Sache return 0; 11688471Sache} 11698471Sache 11708471Sache/* Test the board. */ 11718471Sacheint rc_test(nec, unit) 11728471Sache register int nec; 11738471Sache int unit; 11748471Sache{ 11758471Sache int chan = 0, nopt = 0; 11768471Sache int i = 0, rcnt, old_level; 11778471Sache unsigned int iack, chipid; 11788471Sache unsigned short divs; 11798471Sache static u_char ctest[] = "\377\125\252\045\244\0\377"; 11808471Sache#define CTLEN 8 11818471Sache#define ERR(s) { \ 11828471Sache printf("rc%d: ", unit); printf s ; printf("\n"); \ 11838471Sache (void) splx(old_level); return 1; } 11848471Sache#define TWAITFORCCR \ 11858471Sache for (rcnt = 100000; rcin(CD180_CCR) && rcnt; rcnt--) ; \ 11868471Sache if (!rcnt) ERR(("Timeout waiting for zero CCR")) 11878471Sache 11888471Sache struct rtest { 11898471Sache u_char txbuf[CD180_NFIFO]; /* TX buffer */ 11908471Sache u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 11918471Sache int rxptr; /* RX pointer */ 11928471Sache int txptr; /* TX pointer */ 11938471Sache } tchans[CD180_NCHAN]; 11948471Sache 11958471Sache old_level = splhigh(); 11968471Sache 11978471Sache chipid = RC_FAKEID; 11988471Sache 11998471Sache /* First, reset board to inital state */ 12008471Sache rc_hwreset(nec, chipid); 12018471Sache 12028471Sache /* Initialize channels */ 12038471Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 12048471Sache 12058471Sache divs = RC_BRD(19200); 12068471Sache 12078471Sache TWAITFORCCR; 12088471Sache 12098471Sache /* Select and reset channel */ 12108471Sache rcout(CD180_CAR, chan); 12118471Sache rcout(CD180_CCR, CCR_RESETCHAN); 12128471Sache TWAITFORCCR; 12138471Sache 12148471Sache /* Set speed */ 12158471Sache rcout(CD180_RBPRL, divs & 0xFF); 12168471Sache rcout(CD180_RBPRH, divs >> 8); 12178471Sache rcout(CD180_TBPRL, divs & 0xFF); 12188471Sache rcout(CD180_TBPRH, divs >> 8); 12198471Sache 12208471Sache /* set timeout value */ 12218471Sache rcout(CD180_RTPR, 0); 12228471Sache 12238471Sache /* Establish local loopback */ 12248471Sache rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 12258471Sache rcout(CD180_COR2, COR2_LLM); 12268471Sache rcout(CD180_COR3, CD180_NFIFO); 12278471Sache TWAITFORCCR; 12288471Sache rcout(CD180_CCR, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 12298471Sache TWAITFORCCR; 12308471Sache rcout(CD180_CCR, CCR_RXEN | CCR_TXEN); 12318471Sache rcout(CD180_MSVR, MSVR_RTS); 12328471Sache 12338471Sache /* Fill TXBUF with test data */ 12348471Sache for (i = 0; i < CD180_NFIFO; i++) { 12358471Sache tchans[chan].txbuf[i] = ctest[i]; 12368471Sache tchans[chan].rxbuf[i] = 0; 12378471Sache } 12388471Sache tchans[chan].txptr = tchans[chan].rxptr = 0; 12398471Sache 12408471Sache /* Now, start transmit */ 12418471Sache rcout(CD180_IER, IER_TXMPTY | IER_RXD); 12428471Sache } 12438471Sache /* Pseudo-interrupt poll stuff */ 12448471Sache for (rcnt = 10000; rcnt-- > 0; rcnt--) { 12458471Sache i = ~(rcin(RC_BSR)) & 0xF; 12468471Sache if (i & RC_BSR_TOUT) 12478471Sache ERR(("BSR timeout bit set\n")) 12488471Sache if (i & RC_BSR_TXINT) { 12498471Sache iack = rcin(RC_PILR_TX); 12508471Sache if (iack != (GIVR_IT_TDI | chipid)) 12518471Sache ERR(("Bad TX intr ack (%02x != %02x)\n", 12528471Sache iack, GIVR_IT_TDI | chipid)); 12538471Sache chan = (rcin(CD180_GICR) >> 2) & 07; 12548471Sache /* If no more data to transmit, disable TX intr */ 12558471Sache if (tchans[chan].txptr >= CD180_NFIFO) { 12568471Sache iack = rcin(CD180_IER); 12578471Sache rcout(CD180_IER, iack & ~IER_TXMPTY); 12588471Sache } else { 12598471Sache for (iack = tchans[chan].txptr; 12608471Sache iack < CD180_NFIFO; iack++) 12618471Sache rcout(CD180_TDR, 12628471Sache tchans[chan].txbuf[iack]); 12638471Sache tchans[chan].txptr = iack; 12648471Sache rcout(CD180_EOIR, 0); 12658471Sache } 12668471Sache 12678471Sache } 12688471Sache if (i & RC_BSR_RXINT) { 12698471Sache unsigned int ucnt; 12708471Sache 12718471Sache iack = rcin(RC_PILR_RX); 12728471Sache if (iack != (GIVR_IT_RGDI | chipid) && 12738471Sache iack != (GIVR_IT_REI | chipid)) 12748471Sache ERR(("Bad RX intr ack (%02x != %02x)\n", 12758471Sache iack, GIVR_IT_RGDI | chipid)) 12768471Sache chan = (rcin(CD180_GICR) >> 2) & 07; 12778471Sache ucnt = rcin(CD180_RDCR) & 0xF; 12788471Sache while (ucnt-- > 0) { 12798471Sache iack = rcin(CD180_RCSR); 12808471Sache if (iack & RCSR_TOUT) 12818471Sache break; 12828471Sache if (iack & 0xF) 12838471Sache ERR(("Bad char chan %d (RCSR = %02X)\n", 12848471Sache chan, iack)) 12858471Sache if (tchans[chan].rxptr > CD180_NFIFO) 12868471Sache ERR(("Got extra chars chan %d\n", 12878471Sache chan)) 12888471Sache tchans[chan].rxbuf[tchans[chan].rxptr++] = 12898471Sache rcin(CD180_RDR); 12908471Sache } 12918471Sache rcout(CD180_EOIR, 0); 12928471Sache } 12938471Sache rcout(RC_BSR, 0); 12948471Sache for (iack = chan = 0; chan < CD180_NCHAN; chan++) 12958471Sache if (tchans[chan].rxptr >= CD180_NFIFO) 12968471Sache iack++; 12978471Sache if (iack == CD180_NCHAN) 12988471Sache break; 12998471Sache } 13008471Sache if (!rcnt) 13018471Sache ERR(("looses characters during local loopback\n")) 13028471Sache /* Now, check data */ 13038471Sache for (chan = 0; chan < CD180_NCHAN; chan++) 13048471Sache for (i = 0; i < CD180_NFIFO; i++) 13058471Sache if (ctest[i] != tchans[chan].rxbuf[i]) 13068471Sache ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 13078471Sache chan, i, ctest[i], tchans[chan].rxbuf[i])) 13088471Sache (void) splx(old_level); 13098471Sache return 0; 13108471Sache} 13118471Sache 13128471Sache#ifdef RCDEBUG 13138471Sache 13148471Sacheint printrcflags(rc, comment) 13158471Sachestruct rc_chans *rc; 13168471Sachechar *comment; 13178471Sache{ 13188471Sache u_short f = rc->rc_flags; 13198471Sache 13208471Sache printf("rc %d/%d %s flags: %s%s%s%s%s%s%s%s%s\n", 13218471Sache rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 13228471Sache (f & RC_DTR_OFF)?"DTR_OFF " :"", 13238471Sache (f & RC_ACTOUT) ?"ACTOUT ":"", 13248471Sache (f & RC_RTSFLOW)?"RTSFL " :"", 13258471Sache (f & RC_CTSFLOW)?"CTSFL " :"", 13268471Sache (f & RC_DORXFER)?"DORXF " :"", 13278471Sache (f & RC_DOXXFER)?"DOXXF " :"", 13288471Sache (f & RC_MODCHG) ?"MODC " :"", 13298471Sache (f & RC_OSUSP) ?"OSUSP " :""); 13308471Sache return 0; 13318471Sache} 13328471Sache#endif /* RCDEBUG */ 13338471Sache 13348471Sachestruct tty * 13358471Sachercdevtotty(dev) 13368471Sache dev_t dev; 13378471Sache{ 13388471Sache int unit; 13398471Sache 13408471Sache unit = GET_UNIT(dev); 13418471Sache if (unit >= NRC * CD180_NCHAN) 13428471Sache return NULL; 13438471Sache return (&rc_tty[unit]); 13448471Sache} 13458471Sache 13468471Sachestatic void 13478471Sacherc_dtrwakeup(chan) 13488471Sache void *chan; 13498471Sache{ 13508471Sache struct rc_chans *rc; 13518471Sache 13528471Sache rc = (struct rc_chans *)chan; 13538471Sache rc->rc_flags &= ~RC_DTR_OFF; 13548471Sache wakeup(&rc->rc_dtrwait); 13558471Sache} 13568471Sache 13578471Sachestatic void 13588471Sacherc_discard_output(rc) 13598471Sache struct rc_chans *rc; 13608471Sache{ 13618471Sache disable_intr(); 13628471Sache if (rc->rc_flags & RC_DOXXFER) { 13638471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 13648471Sache rc->rc_flags &= ~RC_DOXXFER; 13658471Sache } 13668471Sache rc->rc_optr = rc->rc_obufend; 13678471Sache enable_intr(); 13688471Sache rc->rc_tp->t_state &= ~TS_BUSY; 13698471Sache} 13708471Sache 13718471Sachestatic void 13728471Sacherc_wakeup(chan) 13738471Sache void *chan; 13748471Sache{ 13758471Sache int unit; 13768471Sache 13778471Sache timeout(rc_wakeup, (caddr_t)NULL, 1); 13788471Sache 13798471Sache if (rc_scheduled_event != 0) { 13808471Sache int s; 13818471Sache 13828471Sache s = splsofttty(); 13838471Sache rcpoll(); 13848471Sache splx(s); 13858471Sache } 13868471Sache} 13878471Sache 13888471Sachestatic void 13898471Sachedisc_optim(tp, t, rc) 13908471Sache struct tty *tp; 13918471Sache struct termios *t; 13928471Sache struct rc_chans *rc; 13938471Sache{ 13948471Sache 13958471Sache if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP 13968471Sache | IXOFF | IXON)) 13978471Sache && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 13988471Sache && (!(t->c_iflag & PARMRK) || 13998471Sache (t->c_iflag & (IGNPAR|IGNBRK)) == (IGNPAR|IGNBRK)) 14008471Sache && !(t->c_lflag & (ECHO | ECHONL | ICANON | IEXTEN | ISIG 14018471Sache | PENDIN)) 14028471Sache && linesw[tp->t_line].l_rint == ttyinput) 14038471Sache tp->t_state |= TS_CAN_BYPASS_L_RINT; 14048471Sache else 14058471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 14068471Sache if (tp->t_line == SLIPDISC) 14078471Sache rc->rc_hotchar = 0xc0; 14088471Sache else if (tp->t_line == PPPDISC) 14098471Sache rc->rc_hotchar = 0x7e; 14108471Sache else 14118471Sache rc->rc_hotchar = 0; 14128471Sache} 14138471Sache#endif /* NRC */ 1414