1156321Sdamien/* $FreeBSD$ */ 2156321Sdamien 3156321Sdamien/*- 4156321Sdamien * Copyright (c) 2006 5156321Sdamien * Damien Bergamini <damien.bergamini@free.fr> 6156321Sdamien * 7156321Sdamien * Permission to use, copy, modify, and distribute this software for any 8156321Sdamien * purpose with or without fee is hereby granted, provided that the above 9156321Sdamien * copyright notice and this permission notice appear in all copies. 10156321Sdamien * 11156321Sdamien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12156321Sdamien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13156321Sdamien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14156321Sdamien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15156321Sdamien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16156321Sdamien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17156321Sdamien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18156321Sdamien */ 19156321Sdamien 20170530Ssam#define RT2661_NOISE_FLOOR -95 21170530Ssam 22156321Sdamien#define RT2661_TX_RING_COUNT 32 23156321Sdamien#define RT2661_MGT_RING_COUNT 32 24156321Sdamien#define RT2661_RX_RING_COUNT 64 25156321Sdamien 26156321Sdamien#define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) 27156321Sdamien#define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) 28156321Sdamien#define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) 29156321Sdamien#define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) 30156321Sdamien 31156321Sdamien#define RT2661_MAX_SCATTER 5 32156321Sdamien 33156321Sdamien/* 34156321Sdamien * Control and status registers. 35156321Sdamien */ 36156321Sdamien#define RT2661_HOST_CMD_CSR 0x0008 37156321Sdamien#define RT2661_MCU_CNTL_CSR 0x000c 38156321Sdamien#define RT2661_SOFT_RESET_CSR 0x0010 39156321Sdamien#define RT2661_MCU_INT_SOURCE_CSR 0x0014 40156321Sdamien#define RT2661_MCU_INT_MASK_CSR 0x0018 41156321Sdamien#define RT2661_PCI_USEC_CSR 0x001c 42156321Sdamien#define RT2661_H2M_MAILBOX_CSR 0x2100 43156321Sdamien#define RT2661_M2H_CMD_DONE_CSR 0x2104 44156321Sdamien#define RT2661_HW_BEACON_BASE0 0x2c00 45156321Sdamien#define RT2661_MAC_CSR0 0x3000 46156321Sdamien#define RT2661_MAC_CSR1 0x3004 47156321Sdamien#define RT2661_MAC_CSR2 0x3008 48156321Sdamien#define RT2661_MAC_CSR3 0x300c 49156321Sdamien#define RT2661_MAC_CSR4 0x3010 50156321Sdamien#define RT2661_MAC_CSR5 0x3014 51156321Sdamien#define RT2661_MAC_CSR6 0x3018 52156321Sdamien#define RT2661_MAC_CSR7 0x301c 53156321Sdamien#define RT2661_MAC_CSR8 0x3020 54156321Sdamien#define RT2661_MAC_CSR9 0x3024 55156321Sdamien#define RT2661_MAC_CSR10 0x3028 56156321Sdamien#define RT2661_MAC_CSR11 0x302c 57156321Sdamien#define RT2661_MAC_CSR12 0x3030 58156321Sdamien#define RT2661_MAC_CSR13 0x3034 59156321Sdamien#define RT2661_MAC_CSR14 0x3038 60156321Sdamien#define RT2661_MAC_CSR15 0x303c 61156321Sdamien#define RT2661_TXRX_CSR0 0x3040 62156321Sdamien#define RT2661_TXRX_CSR1 0x3044 63156321Sdamien#define RT2661_TXRX_CSR2 0x3048 64156321Sdamien#define RT2661_TXRX_CSR3 0x304c 65156321Sdamien#define RT2661_TXRX_CSR4 0x3050 66156321Sdamien#define RT2661_TXRX_CSR5 0x3054 67156321Sdamien#define RT2661_TXRX_CSR6 0x3058 68156321Sdamien#define RT2661_TXRX_CSR7 0x305c 69156321Sdamien#define RT2661_TXRX_CSR8 0x3060 70156321Sdamien#define RT2661_TXRX_CSR9 0x3064 71156321Sdamien#define RT2661_TXRX_CSR10 0x3068 72156321Sdamien#define RT2661_TXRX_CSR11 0x306c 73156321Sdamien#define RT2661_TXRX_CSR12 0x3070 74156321Sdamien#define RT2661_TXRX_CSR13 0x3074 75156321Sdamien#define RT2661_TXRX_CSR14 0x3078 76156321Sdamien#define RT2661_TXRX_CSR15 0x307c 77156321Sdamien#define RT2661_PHY_CSR0 0x3080 78156321Sdamien#define RT2661_PHY_CSR1 0x3084 79156321Sdamien#define RT2661_PHY_CSR2 0x3088 80156321Sdamien#define RT2661_PHY_CSR3 0x308c 81156321Sdamien#define RT2661_PHY_CSR4 0x3090 82156321Sdamien#define RT2661_PHY_CSR5 0x3094 83156321Sdamien#define RT2661_PHY_CSR6 0x3098 84156321Sdamien#define RT2661_PHY_CSR7 0x309c 85156321Sdamien#define RT2661_SEC_CSR0 0x30a0 86156321Sdamien#define RT2661_SEC_CSR1 0x30a4 87156321Sdamien#define RT2661_SEC_CSR2 0x30a8 88156321Sdamien#define RT2661_SEC_CSR3 0x30ac 89156321Sdamien#define RT2661_SEC_CSR4 0x30b0 90156321Sdamien#define RT2661_SEC_CSR5 0x30b4 91156321Sdamien#define RT2661_STA_CSR0 0x30c0 92156321Sdamien#define RT2661_STA_CSR1 0x30c4 93156321Sdamien#define RT2661_STA_CSR2 0x30c8 94156321Sdamien#define RT2661_STA_CSR3 0x30cc 95156321Sdamien#define RT2661_STA_CSR4 0x30d0 96156321Sdamien#define RT2661_AC0_BASE_CSR 0x3400 97156321Sdamien#define RT2661_AC1_BASE_CSR 0x3404 98156321Sdamien#define RT2661_AC2_BASE_CSR 0x3408 99156321Sdamien#define RT2661_AC3_BASE_CSR 0x340c 100156321Sdamien#define RT2661_MGT_BASE_CSR 0x3410 101156321Sdamien#define RT2661_TX_RING_CSR0 0x3418 102156321Sdamien#define RT2661_TX_RING_CSR1 0x341c 103156321Sdamien#define RT2661_AIFSN_CSR 0x3420 104156321Sdamien#define RT2661_CWMIN_CSR 0x3424 105156321Sdamien#define RT2661_CWMAX_CSR 0x3428 106156321Sdamien#define RT2661_TX_DMA_DST_CSR 0x342c 107156321Sdamien#define RT2661_TX_CNTL_CSR 0x3430 108156321Sdamien#define RT2661_LOAD_TX_RING_CSR 0x3434 109156321Sdamien#define RT2661_RX_BASE_CSR 0x3450 110156321Sdamien#define RT2661_RX_RING_CSR 0x3454 111156321Sdamien#define RT2661_RX_CNTL_CSR 0x3458 112156321Sdamien#define RT2661_PCI_CFG_CSR 0x3460 113156321Sdamien#define RT2661_INT_SOURCE_CSR 0x3468 114156321Sdamien#define RT2661_INT_MASK_CSR 0x346c 115156321Sdamien#define RT2661_E2PROM_CSR 0x3470 116156321Sdamien#define RT2661_AC_TXOP_CSR0 0x3474 117156321Sdamien#define RT2661_AC_TXOP_CSR1 0x3478 118156321Sdamien#define RT2661_TEST_MODE_CSR 0x3484 119156321Sdamien#define RT2661_IO_CNTL_CSR 0x3498 120156321Sdamien#define RT2661_MCU_CODE_BASE 0x4000 121156321Sdamien 122156321Sdamien 123156321Sdamien/* possible flags for register HOST_CMD_CSR */ 124156321Sdamien#define RT2661_KICK_CMD (1 << 7) 125156321Sdamien/* Host to MCU (8051) command identifiers */ 126156321Sdamien#define RT2661_MCU_CMD_SLEEP 0x30 127156321Sdamien#define RT2661_MCU_CMD_WAKEUP 0x31 128156321Sdamien#define RT2661_MCU_SET_LED 0x50 129156321Sdamien#define RT2661_MCU_SET_RSSI_LED 0x52 130156321Sdamien 131156321Sdamien/* possible flags for register MCU_CNTL_CSR */ 132156321Sdamien#define RT2661_MCU_SEL (1 << 0) 133156321Sdamien#define RT2661_MCU_RESET (1 << 1) 134156321Sdamien#define RT2661_MCU_READY (1 << 2) 135156321Sdamien 136156321Sdamien/* possible flags for register MCU_INT_SOURCE_CSR */ 137156321Sdamien#define RT2661_MCU_CMD_DONE 0xff 138156321Sdamien#define RT2661_MCU_WAKEUP (1 << 8) 139156321Sdamien#define RT2661_MCU_BEACON_EXPIRE (1 << 9) 140156321Sdamien 141156321Sdamien/* possible flags for register H2M_MAILBOX_CSR */ 142156321Sdamien#define RT2661_H2M_BUSY (1 << 24) 143156321Sdamien#define RT2661_TOKEN_NO_INTR 0xff 144156321Sdamien 145156321Sdamien/* possible flags for register MAC_CSR5 */ 146156321Sdamien#define RT2661_ONE_BSSID 3 147156321Sdamien 148156321Sdamien/* possible flags for register TXRX_CSR0 */ 149156321Sdamien/* Tx filter flags are in the low 16 bits */ 150156321Sdamien#define RT2661_AUTO_TX_SEQ (1 << 15) 151156321Sdamien/* Rx filter flags are in the high 16 bits */ 152156321Sdamien#define RT2661_DISABLE_RX (1 << 16) 153156321Sdamien#define RT2661_DROP_CRC_ERROR (1 << 17) 154156321Sdamien#define RT2661_DROP_PHY_ERROR (1 << 18) 155156321Sdamien#define RT2661_DROP_CTL (1 << 19) 156156321Sdamien#define RT2661_DROP_NOT_TO_ME (1 << 20) 157156321Sdamien#define RT2661_DROP_TODS (1 << 21) 158156321Sdamien#define RT2661_DROP_VER_ERROR (1 << 22) 159156321Sdamien#define RT2661_DROP_MULTICAST (1 << 23) 160156321Sdamien#define RT2661_DROP_BROADCAST (1 << 24) 161156321Sdamien#define RT2661_DROP_ACKCTS (1 << 25) 162156321Sdamien 163156321Sdamien/* possible flags for register TXRX_CSR4 */ 164156321Sdamien#define RT2661_SHORT_PREAMBLE (1 << 19) 165156321Sdamien#define RT2661_MRR_ENABLED (1 << 20) 166156321Sdamien#define RT2661_MRR_CCK_FALLBACK (1 << 23) 167156321Sdamien 168156321Sdamien/* possible flags for register TXRX_CSR9 */ 169156321Sdamien#define RT2661_TSF_TICKING (1 << 16) 170156321Sdamien#define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) 171156321Sdamien/* TBTT stands for Target Beacon Transmission Time */ 172156321Sdamien#define RT2661_ENABLE_TBTT (1 << 19) 173156321Sdamien#define RT2661_GENERATE_BEACON (1 << 20) 174156321Sdamien 175156321Sdamien/* possible flags for register PHY_CSR0 */ 176156321Sdamien#define RT2661_PA_PE_2GHZ (1 << 16) 177156321Sdamien#define RT2661_PA_PE_5GHZ (1 << 17) 178156321Sdamien 179156321Sdamien/* possible flags for register PHY_CSR3 */ 180156321Sdamien#define RT2661_BBP_READ (1 << 15) 181156321Sdamien#define RT2661_BBP_BUSY (1 << 16) 182156321Sdamien 183156321Sdamien/* possible flags for register PHY_CSR4 */ 184156321Sdamien#define RT2661_RF_21BIT (21 << 24) 185258780Seadler#define RT2661_RF_BUSY (1U << 31) 186156321Sdamien 187156321Sdamien/* possible values for register STA_CSR4 */ 188156321Sdamien#define RT2661_TX_STAT_VALID (1 << 0) 189156321Sdamien#define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) 190156321Sdamien#define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) 191156321Sdamien#define RT2661_TX_QID(v) (((v) >> 8) & 0xf) 192156321Sdamien#define RT2661_TX_SUCCESS 0 193156321Sdamien#define RT2661_TX_RETRY_FAIL 6 194156321Sdamien 195156321Sdamien/* possible flags for register TX_CNTL_CSR */ 196156321Sdamien#define RT2661_KICK_MGT (1 << 4) 197156321Sdamien 198156321Sdamien/* possible flags for register INT_SOURCE_CSR */ 199156321Sdamien#define RT2661_TX_DONE (1 << 0) 200156321Sdamien#define RT2661_RX_DONE (1 << 1) 201156321Sdamien#define RT2661_TX0_DMA_DONE (1 << 16) 202156321Sdamien#define RT2661_TX1_DMA_DONE (1 << 17) 203156321Sdamien#define RT2661_TX2_DMA_DONE (1 << 18) 204156321Sdamien#define RT2661_TX3_DMA_DONE (1 << 19) 205156321Sdamien#define RT2661_MGT_DONE (1 << 20) 206156321Sdamien 207156321Sdamien/* possible flags for register E2PROM_CSR */ 208156321Sdamien#define RT2661_C (1 << 1) 209156321Sdamien#define RT2661_S (1 << 2) 210156321Sdamien#define RT2661_D (1 << 3) 211156321Sdamien#define RT2661_Q (1 << 4) 212156321Sdamien#define RT2661_93C46 (1 << 5) 213156321Sdamien 214156321Sdamien/* Tx descriptor */ 215156321Sdamienstruct rt2661_tx_desc { 216156321Sdamien uint32_t flags; 217156321Sdamien#define RT2661_TX_BUSY (1 << 0) 218156321Sdamien#define RT2661_TX_VALID (1 << 1) 219156321Sdamien#define RT2661_TX_MORE_FRAG (1 << 2) 220156321Sdamien#define RT2661_TX_NEED_ACK (1 << 3) 221156321Sdamien#define RT2661_TX_TIMESTAMP (1 << 4) 222156321Sdamien#define RT2661_TX_OFDM (1 << 5) 223156321Sdamien#define RT2661_TX_IFS (1 << 6) 224156321Sdamien#define RT2661_TX_LONG_RETRY (1 << 7) 225156321Sdamien#define RT2661_TX_BURST (1 << 28) 226156321Sdamien 227156321Sdamien uint16_t wme; 228156321Sdamien#define RT2661_QID(v) (v) 229156321Sdamien#define RT2661_AIFSN(v) ((v) << 4) 230156321Sdamien#define RT2661_LOGCWMIN(v) ((v) << 8) 231156321Sdamien#define RT2661_LOGCWMAX(v) ((v) << 12) 232156321Sdamien 233156321Sdamien uint16_t xflags; 234156321Sdamien#define RT2661_TX_HWSEQ (1 << 12) 235156321Sdamien 236156321Sdamien uint8_t plcp_signal; 237156321Sdamien uint8_t plcp_service; 238156321Sdamien#define RT2661_PLCP_LENGEXT 0x80 239156321Sdamien 240156321Sdamien uint8_t plcp_length_lo; 241156321Sdamien uint8_t plcp_length_hi; 242156321Sdamien 243156321Sdamien uint32_t iv; 244156321Sdamien uint32_t eiv; 245156321Sdamien 246156321Sdamien uint8_t offset; 247156321Sdamien uint8_t qid; 248156321Sdamien#define RT2661_QID_MGT 13 249156321Sdamien 250156321Sdamien uint8_t txpower; 251156321Sdamien#define RT2661_DEFAULT_TXPOWER 0 252156321Sdamien 253156321Sdamien uint8_t reserved1; 254156321Sdamien 255156321Sdamien uint32_t addr[RT2661_MAX_SCATTER]; 256156321Sdamien uint16_t len[RT2661_MAX_SCATTER]; 257156321Sdamien 258156321Sdamien uint16_t reserved2; 259156321Sdamien} __packed; 260156321Sdamien 261156321Sdamien/* Rx descriptor */ 262156321Sdamienstruct rt2661_rx_desc { 263156321Sdamien uint32_t flags; 264156321Sdamien#define RT2661_RX_BUSY (1 << 0) 265156321Sdamien#define RT2661_RX_DROP (1 << 1) 266156321Sdamien#define RT2661_RX_CRC_ERROR (1 << 6) 267156321Sdamien#define RT2661_RX_OFDM (1 << 7) 268156321Sdamien#define RT2661_RX_PHY_ERROR (1 << 8) 269156321Sdamien#define RT2661_RX_CIPHER_MASK 0x00000600 270156321Sdamien 271156321Sdamien uint8_t rate; 272156321Sdamien uint8_t rssi; 273156321Sdamien uint8_t reserved1; 274156321Sdamien uint8_t offset; 275156321Sdamien uint32_t iv; 276156321Sdamien uint32_t eiv; 277156321Sdamien uint32_t reserved2; 278156321Sdamien uint32_t physaddr; 279156321Sdamien uint32_t reserved3[10]; 280156321Sdamien} __packed; 281156321Sdamien 282156321Sdamien#define RAL_RF1 0 283156321Sdamien#define RAL_RF2 2 284156321Sdamien#define RAL_RF3 1 285156321Sdamien#define RAL_RF4 3 286156321Sdamien 287156321Sdamien/* dual-band RF */ 288156321Sdamien#define RT2661_RF_5225 1 289156321Sdamien#define RT2661_RF_5325 2 290156321Sdamien/* single-band RF */ 291156321Sdamien#define RT2661_RF_2527 3 292156321Sdamien#define RT2661_RF_2529 4 293156321Sdamien 294156321Sdamien#define RT2661_RX_DESC_BACK 4 295156321Sdamien 296156321Sdamien#define RT2661_SMART_MODE (1 << 0) 297156321Sdamien 298156321Sdamien#define RT2661_BBPR94_DEFAULT 6 299156321Sdamien 300156321Sdamien#define RT2661_SHIFT_D 3 301156321Sdamien#define RT2661_SHIFT_Q 4 302156321Sdamien 303156321Sdamien#define RT2661_EEPROM_MAC01 0x02 304156321Sdamien#define RT2661_EEPROM_MAC23 0x03 305156321Sdamien#define RT2661_EEPROM_MAC45 0x04 306156321Sdamien#define RT2661_EEPROM_ANTENNA 0x10 307156321Sdamien#define RT2661_EEPROM_CONFIG2 0x11 308156321Sdamien#define RT2661_EEPROM_BBP_BASE 0x13 309156321Sdamien#define RT2661_EEPROM_TXPOWER 0x23 310156321Sdamien#define RT2661_EEPROM_FREQ_OFFSET 0x2f 311156321Sdamien#define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d 312156321Sdamien#define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e 313156321Sdamien 314156321Sdamien#define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 315156321Sdamien 316156321Sdamien/* 317156321Sdamien * control and status registers access macros 318156321Sdamien */ 319156321Sdamien#define RAL_READ(sc, reg) \ 320156321Sdamien bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 321156321Sdamien 322156321Sdamien#define RAL_READ_REGION_4(sc, offset, datap, count) \ 323156321Sdamien bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 324156321Sdamien (datap), (count)) 325156321Sdamien 326156321Sdamien#define RAL_WRITE(sc, reg, val) \ 327156321Sdamien bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 328156321Sdamien 329156321Sdamien#define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 330156321Sdamien bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 331156321Sdamien (datap), (count)) 332156321Sdamien 333156321Sdamien/* 334156321Sdamien * EEPROM access macro 335156321Sdamien */ 336156321Sdamien#define RT2661_EEPROM_CTL(sc, val) do { \ 337156321Sdamien RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ 338156321Sdamien DELAY(RT2661_EEPROM_DELAY); \ 339156321Sdamien} while (/* CONSTCOND */0) 340156321Sdamien 341156321Sdamien/* 342156321Sdamien * Default values for MAC registers; values taken from the reference driver. 343156321Sdamien */ 344156321Sdamien#define RT2661_DEF_MAC \ 345156321Sdamien { RT2661_TXRX_CSR0, 0x0000b032 }, \ 346156321Sdamien { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ 347156321Sdamien { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ 348156321Sdamien { RT2661_TXRX_CSR3, 0x00858687 }, \ 349156321Sdamien { RT2661_TXRX_CSR7, 0x2e31353b }, \ 350156321Sdamien { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ 351156321Sdamien { RT2661_TXRX_CSR15, 0x0000000f }, \ 352156321Sdamien { RT2661_MAC_CSR6, 0x00000fff }, \ 353156321Sdamien { RT2661_MAC_CSR8, 0x016c030a }, \ 354156321Sdamien { RT2661_MAC_CSR10, 0x00000718 }, \ 355156321Sdamien { RT2661_MAC_CSR12, 0x00000004 }, \ 356156321Sdamien { RT2661_MAC_CSR13, 0x0000e000 }, \ 357156321Sdamien { RT2661_SEC_CSR0, 0x00000000 }, \ 358156321Sdamien { RT2661_SEC_CSR1, 0x00000000 }, \ 359156321Sdamien { RT2661_SEC_CSR5, 0x00000000 }, \ 360156321Sdamien { RT2661_PHY_CSR1, 0x000023b0 }, \ 361156321Sdamien { RT2661_PHY_CSR5, 0x060a100c }, \ 362156321Sdamien { RT2661_PHY_CSR6, 0x00080606 }, \ 363156321Sdamien { RT2661_PHY_CSR7, 0x00000a08 }, \ 364156321Sdamien { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ 365156321Sdamien { RT2661_AIFSN_CSR, 0x00002273 }, \ 366156321Sdamien { RT2661_CWMIN_CSR, 0x00002344 }, \ 367156321Sdamien { RT2661_CWMAX_CSR, 0x000034aa }, \ 368156321Sdamien { RT2661_TEST_MODE_CSR, 0x00000200 }, \ 369156321Sdamien { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } 370156321Sdamien 371156321Sdamien/* 372156321Sdamien * Default values for BBP registers; values taken from the reference driver. 373156321Sdamien */ 374156321Sdamien#define RT2661_DEF_BBP \ 375156321Sdamien { 3, 0x00 }, \ 376156321Sdamien { 15, 0x30 }, \ 377156321Sdamien { 17, 0x20 }, \ 378156321Sdamien { 21, 0xc8 }, \ 379156321Sdamien { 22, 0x38 }, \ 380156321Sdamien { 23, 0x06 }, \ 381156321Sdamien { 24, 0xfe }, \ 382156321Sdamien { 25, 0x0a }, \ 383156321Sdamien { 26, 0x0d }, \ 384156321Sdamien { 34, 0x12 }, \ 385156321Sdamien { 37, 0x07 }, \ 386156321Sdamien { 39, 0xf8 }, \ 387156321Sdamien { 41, 0x60 }, \ 388156321Sdamien { 53, 0x10 }, \ 389156321Sdamien { 54, 0x18 }, \ 390156321Sdamien { 60, 0x10 }, \ 391156321Sdamien { 61, 0x04 }, \ 392156321Sdamien { 62, 0x04 }, \ 393156321Sdamien { 75, 0xfe }, \ 394156321Sdamien { 86, 0xfe }, \ 395156321Sdamien { 88, 0xfe }, \ 396156321Sdamien { 90, 0x0f }, \ 397156321Sdamien { 99, 0x00 }, \ 398156321Sdamien { 102, 0x16 }, \ 399156321Sdamien { 107, 0x04 } 400156321Sdamien 401156321Sdamien/* 402156321Sdamien * Default settings for RF registers; values taken from the reference driver. 403156321Sdamien */ 404156321Sdamien#define RT2661_RF5225_1 \ 405156321Sdamien { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 406156321Sdamien { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 407156321Sdamien { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 408156321Sdamien { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 409156321Sdamien { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 410156321Sdamien { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 411156321Sdamien { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 412156321Sdamien { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 413156321Sdamien { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 414156321Sdamien { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 415156321Sdamien { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 416156321Sdamien { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 417156321Sdamien { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 418156321Sdamien { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 419156321Sdamien \ 420156321Sdamien { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 421156321Sdamien { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 422156321Sdamien { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 423156321Sdamien { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 424156321Sdamien { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 425156321Sdamien { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 426156321Sdamien { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 427156321Sdamien { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 428156321Sdamien \ 429156321Sdamien { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 430156321Sdamien { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 431156321Sdamien { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 432156321Sdamien { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 433156321Sdamien { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 434156321Sdamien { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 435156321Sdamien { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 436156321Sdamien { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 437156321Sdamien { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 438156321Sdamien { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 439156321Sdamien { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 440156321Sdamien \ 441156321Sdamien { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 442156321Sdamien { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 443156321Sdamien { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 444156321Sdamien { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 445156321Sdamien { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } 446156321Sdamien 447156321Sdamien#define RT2661_RF5225_2 \ 448156321Sdamien { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 449156321Sdamien { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 450156321Sdamien { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 451156321Sdamien { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 452156321Sdamien { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 453156321Sdamien { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 454156321Sdamien { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 455156321Sdamien { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 456156321Sdamien { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 457156321Sdamien { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 458156321Sdamien { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 459156321Sdamien { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 460156321Sdamien { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 461156321Sdamien { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 462156321Sdamien \ 463156321Sdamien { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ 464156321Sdamien { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ 465156321Sdamien { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ 466156321Sdamien { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ 467156321Sdamien { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ 468156321Sdamien { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ 469156321Sdamien { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ 470156321Sdamien { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ 471156321Sdamien \ 472156321Sdamien { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ 473156321Sdamien { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ 474156321Sdamien { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ 475156321Sdamien { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ 476156321Sdamien { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ 477156321Sdamien { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ 478156321Sdamien { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ 479156321Sdamien { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ 480156321Sdamien { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ 481156321Sdamien { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ 482156321Sdamien { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ 483156321Sdamien \ 484156321Sdamien { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ 485156321Sdamien { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ 486156321Sdamien { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ 487156321Sdamien { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ 488156321Sdamien { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } 489