ql_hw.h revision 305488
1/* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/qlxgbe/ql_hw.h 305488 2016-09-06 19:18:50Z davidcs $ 28 */ 29/* 30 * File: ql_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33#ifndef _QL_HW_H_ 34#define _QL_HW_H_ 35 36/* 37 * PCIe Registers; Direct Mapped; Offsets from BAR0 38 */ 39 40/* 41 * Register offsets for QLE8030 42 */ 43 44/* 45 * Firmware Mailbox Registers 46 * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each 47 */ 48#define Q8_FW_MBOX0 0x00000800 49#define Q8_FW_MBOX511 0x00000FFC 50 51/* 52 * Host Mailbox Registers 53 * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each 54 */ 55#define Q8_HOST_MBOX0 0x00000000 56#define Q8_HOST_MBOX511 0x000007FC 57 58#define Q8_MBOX_INT_ENABLE 0x00001000 59#define Q8_MBOX_INT_MASK_MSIX 0x00001200 60#define Q8_MBOX_INT_LEGACY 0x00003010 61 62#define Q8_HOST_MBOX_CNTRL 0x00003038 63#define Q8_FW_MBOX_CNTRL 0x0000303C 64 65#define Q8_PEG_HALT_STATUS1 0x000034A8 66#define Q8_PEG_HALT_STATUS2 0x000034AC 67#define Q8_FIRMWARE_HEARTBEAT 0x000034B0 68 69#define Q8_FLASH_LOCK_ID 0x00003500 70#define Q8_DRIVER_LOCK_ID 0x00003504 71#define Q8_FW_CAPABILITIES 0x00003528 72 73#define Q8_FW_VER_MAJOR 0x00003550 74#define Q8_FW_VER_MINOR 0x00003554 75#define Q8_FW_VER_SUB 0x00003558 76 77#define Q8_BOOTLD_ADDR 0x0000355C 78#define Q8_BOOTLD_SIZE 0x00003560 79 80#define Q8_FW_IMAGE_ADDR 0x00003564 81#define Q8_FW_BUILD_NUMBER 0x00003568 82#define Q8_FW_IMAGE_VALID 0x000035FC 83 84#define Q8_CMDPEG_STATE 0x00003650 85 86#define Q8_LINK_STATE 0x00003698 87#define Q8_LINK_STATE_2 0x0000369C 88 89#define Q8_LINK_SPEED_0 0x000036E0 90#define Q8_LINK_SPEED_1 0x000036E4 91#define Q8_LINK_SPEED_2 0x000036E8 92#define Q8_LINK_SPEED_3 0x000036EC 93 94#define Q8_MAX_LINK_SPEED_0 0x000036F0 95#define Q8_MAX_LINK_SPEED_1 0x000036F4 96#define Q8_MAX_LINK_SPEED_2 0x000036F8 97#define Q8_MAX_LINK_SPEED_3 0x000036FC 98 99#define Q8_ASIC_TEMPERATURE 0x000037B4 100 101/* 102 * CRB Window Registers 103 * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each 104 */ 105#define Q8_CRB_WINDOW_PF0 0x00003800 106#define Q8_CRB_WINDOW_PF15 0x0000383C 107 108#define Q8_FLASH_LOCK 0x00003850 109#define Q8_FLASH_UNLOCK 0x00003854 110 111#define Q8_DRIVER_LOCK 0x00003868 112#define Q8_DRIVER_UNLOCK 0x0000386C 113 114#define Q8_LEGACY_INT_PTR 0x000038C0 115#define Q8_LEGACY_INT_TRIG 0x000038C4 116#define Q8_LEGACY_INT_MASK 0x000038C8 117 118#define Q8_WILD_CARD 0x000038F0 119#define Q8_INFORMANT 0x000038FC 120 121/* 122 * Ethernet Interface Specific Registers 123 */ 124#define Q8_DRIVER_OP_MODE 0x00003570 125#define Q8_API_VERSION 0x0000356C 126#define Q8_NPAR_STATE 0x0000359C 127 128/* 129 * End of PCIe Registers; Direct Mapped; Offsets from BAR0 130 */ 131 132/* 133 * Indirect Registers 134 */ 135#define Q8_LED_DUAL_0 0x28084C80 136#define Q8_LED_SINGLE_0 0x28084C90 137 138#define Q8_LED_DUAL_1 0x28084CA0 139#define Q8_LED_SINGLE_1 0x28084CB0 140 141#define Q8_LED_DUAL_2 0x28084CC0 142#define Q8_LED_SINGLE_2 0x28084CD0 143 144#define Q8_LED_DUAL_3 0x28084CE0 145#define Q8_LED_SINGLE_3 0x28084CF0 146 147#define Q8_GPIO_1 0x28084D00 148#define Q8_GPIO_2 0x28084D10 149#define Q8_GPIO_3 0x28084D20 150#define Q8_GPIO_4 0x28084D40 151#define Q8_GPIO_5 0x28084D50 152#define Q8_GPIO_6 0x28084D60 153#define Q8_GPIO_7 0x42100060 154#define Q8_GPIO_8 0x42100064 155 156#define Q8_FLASH_SPI_STATUS 0x2808E010 157#define Q8_FLASH_SPI_CONTROL 0x2808E014 158 159#define Q8_FLASH_STATUS 0x42100004 160#define Q8_FLASH_CONTROL 0x42110004 161#define Q8_FLASH_ADDRESS 0x42110008 162#define Q8_FLASH_WR_DATA 0x4211000C 163#define Q8_FLASH_RD_DATA 0x42110018 164 165#define Q8_FLASH_DIRECT_WINDOW 0x42110030 166#define Q8_FLASH_DIRECT_DATA 0x42150000 167 168#define Q8_MS_CNTRL 0x41000090 169 170#define Q8_MS_ADDR_LO 0x41000094 171#define Q8_MS_ADDR_HI 0x41000098 172 173#define Q8_MS_WR_DATA_0_31 0x410000A0 174#define Q8_MS_WR_DATA_32_63 0x410000A4 175#define Q8_MS_WR_DATA_64_95 0x410000B0 176#define Q8_MS_WR_DATA_96_127 0x410000B4 177 178#define Q8_MS_RD_DATA_0_31 0x410000A8 179#define Q8_MS_RD_DATA_32_63 0x410000AC 180#define Q8_MS_RD_DATA_64_95 0x410000B8 181#define Q8_MS_RD_DATA_96_127 0x410000BC 182 183#define Q8_CRB_PEG_0 0x3400003c 184#define Q8_CRB_PEG_1 0x3410003c 185#define Q8_CRB_PEG_2 0x3420003c 186#define Q8_CRB_PEG_3 0x3430003c 187#define Q8_CRB_PEG_4 0x34B0003c 188 189/* 190 * Macros for reading and writing registers 191 */ 192 193#if defined(__i386__) || defined(__amd64__) 194#define Q8_MB() __asm volatile("mfence" ::: "memory") 195#define Q8_WMB() __asm volatile("sfence" ::: "memory") 196#define Q8_RMB() __asm volatile("lfence" ::: "memory") 197#else 198#define Q8_MB() 199#define Q8_WMB() 200#define Q8_RMB() 201#endif 202 203#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 204 205#define WRITE_REG32(ha, reg, val) \ 206 {\ 207 bus_write_4((ha->pci_reg), reg, val);\ 208 bus_read_4((ha->pci_reg), reg);\ 209 } 210 211#define Q8_NUM_MBOX 512 212 213#define Q8_MAX_NUM_MULTICAST_ADDRS 1023 214#define Q8_MAC_ADDR_LEN 6 215 216/* 217 * Firmware Interface 218 */ 219 220/* 221 * Command Response Interface - Commands 222 */ 223 224#define Q8_MBX_CONFIG_IP_ADDRESS 0x0001 225#define Q8_MBX_CONFIG_INTR 0x0002 226#define Q8_MBX_MAP_INTR_SRC 0x0003 227#define Q8_MBX_MAP_SDS_TO_RDS 0x0006 228#define Q8_MBX_CREATE_RX_CNTXT 0x0007 229#define Q8_MBX_DESTROY_RX_CNTXT 0x0008 230#define Q8_MBX_CREATE_TX_CNTXT 0x0009 231#define Q8_MBX_DESTROY_TX_CNTXT 0x000A 232#define Q8_MBX_ADD_RX_RINGS 0x000B 233#define Q8_MBX_CONFIG_LRO_FLOW 0x000C 234#define Q8_MBX_CONFIG_MAC_LEARNING 0x000D 235#define Q8_MBX_GET_STATS 0x000F 236#define Q8_MBX_GENERATE_INTR 0x0011 237#define Q8_MBX_SET_MAX_MTU 0x0012 238#define Q8_MBX_MAC_ADDR_CNTRL 0x001F 239#define Q8_MBX_GET_PCI_CONFIG 0x0020 240#define Q8_MBX_GET_NIC_PARTITION 0x0021 241#define Q8_MBX_SET_NIC_PARTITION 0x0022 242#define Q8_MBX_QUERY_WOL_CAP 0x002C 243#define Q8_MBX_SET_WOL_CONFIG 0x002D 244#define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F 245#define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030 246#define Q8_MBX_GET_FW_DCBX_CAPS 0x0034 247#define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035 248#define Q8_MBX_CONFIG_RSS 0x0041 249#define Q8_MBX_CONFIG_RSS_TABLE 0x0042 250#define Q8_MBX_CONFIG_INTR_COALESCE 0x0043 251#define Q8_MBX_CONFIG_LED 0x0044 252#define Q8_MBX_CONFIG_MAC_ADDR 0x0045 253#define Q8_MBX_CONFIG_STATISTICS 0x0046 254#define Q8_MBX_CONFIG_LOOPBACK 0x0047 255#define Q8_MBX_LINK_EVENT_REQ 0x0048 256#define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 257#define Q8_MBX_CONFIG_FW_LRO 0x004A 258#define Q8_MBX_HW_CONFIG 0x004C 259#define Q8_MBX_INIT_NIC_FUNC 0x0060 260#define Q8_MBX_STOP_NIC_FUNC 0x0061 261#define Q8_MBX_IDC_REQ 0x0062 262#define Q8_MBX_IDC_ACK 0x0063 263#define Q8_MBX_SET_PORT_CONFIG 0x0066 264#define Q8_MBX_GET_PORT_CONFIG 0x0067 265#define Q8_MBX_GET_LINK_STATUS 0x0068 266 267 268 269/* 270 * Mailbox Command Response 271 */ 272#define Q8_MBX_RSP_SUCCESS 0x0001 273#define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002 274#define Q8_MBX_RSP_NO_CARD_CRB 0x0003 275#define Q8_MBX_RSP_NO_CARD_MEM 0x0004 276#define Q8_MBX_RSP_NO_CARD_RSRC 0x0005 277#define Q8_MBX_RSP_INVALID_ARGS 0x0006 278#define Q8_MBX_RSP_INVALID_ACTION 0x0007 279#define Q8_MBX_RSP_INVALID_STATE 0x0008 280#define Q8_MBX_RSP_NOT_SUPPORTED 0x0009 281#define Q8_MBX_RSP_NOT_PERMITTED 0x000A 282#define Q8_MBX_RSP_NOT_READY 0x000B 283#define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C 284#define Q8_MBX_RSP_ALREADY_EXISTS 0x000D 285#define Q8_MBX_RSP_BAD_SIGNATURE 0x000E 286#define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F 287#define Q8_MBX_RSP_CMD_INVALID 0x0010 288#define Q8_MBX_RSP_TIMEOUT 0x0011 289#define Q8_MBX_RSP_CMD_FAILED 0x0012 290#define Q8_MBX_RSP_FATAL_TEMP 0x0013 291#define Q8_MBX_RSP_MAX_EXCEEDED 0x0014 292#define Q8_MBX_RSP_UNSPECIFIED 0x0015 293#define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017 294#define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018 295#define Q8_MBX_RSP_INTR_INVALID_OP 0x0019 296#define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A 297 298#define Q8_MBX_CMD_VERSION (0x2 << 13) 299#define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9)) 300/* 301 * Configure IP Address 302 */ 303typedef struct _q80_config_ip_addr { 304 uint16_t opcode; 305 uint16_t count_version; 306 307 uint8_t cmd; 308#define Q8_MBX_CONFIG_IP_ADD_IP 0x1 309#define Q8_MBX_CONFIG_IP_DEL_IP 0x2 310 311 uint8_t ip_type; 312#define Q8_MBX_CONFIG_IP_V4 0x0 313#define Q8_MBX_CONFIG_IP_V6 0x1 314 315 uint16_t rsrvd; 316 union { 317 struct { 318 uint32_t addr; 319 uint32_t rsrvd[3]; 320 } ipv4; 321 uint8_t ipv6_addr[16]; 322 } u; 323} __packed q80_config_ip_addr_t; 324 325typedef struct _q80_config_ip_addr_rsp { 326 uint16_t opcode; 327 uint16_t regcnt_status; 328} __packed q80_config_ip_addr_rsp_t; 329 330/* 331 * Configure Interrupt Command 332 */ 333typedef struct _q80_intr { 334 uint8_t cmd_type; 335#define Q8_MBX_CONFIG_INTR_CREATE 0x1 336#define Q8_MBX_CONFIG_INTR_DELETE 0x2 337#define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4) 338#define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4) 339 340 uint8_t rsrvd; 341 uint16_t msix_index; 342} __packed q80_intr_t; 343 344#define Q8_MAX_INTR_VECTORS 16 345typedef struct _q80_config_intr { 346 uint16_t opcode; 347 uint16_t count_version; 348 uint8_t nentries; 349 uint8_t rsrvd[3]; 350 q80_intr_t intr[Q8_MAX_INTR_VECTORS]; 351} __packed q80_config_intr_t; 352 353typedef struct _q80_intr_rsp { 354 uint8_t status; 355 uint8_t cmd; 356 uint16_t intr_id; 357 uint32_t intr_src; 358} q80_intr_rsp_t; 359 360typedef struct _q80_config_intr_rsp { 361 uint16_t opcode; 362 uint16_t regcnt_status; 363 uint8_t nentries; 364 uint8_t rsrvd[3]; 365 q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS]; 366} __packed q80_config_intr_rsp_t; 367 368/* 369 * Configure LRO Flow Command 370 */ 371typedef struct _q80_config_lro_flow { 372 uint16_t opcode; 373 uint16_t count_version; 374 375 uint8_t cmd; 376#define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01 377#define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02 378 379 uint8_t type_ts; 380#define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00 381#define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01 382#define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00 383#define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02 384 385 uint16_t rsrvd; 386 union { 387 struct { 388 uint32_t addr; 389 uint32_t rsrvd[3]; 390 } ipv4; 391 uint8_t ipv6_addr[16]; 392 } dst; 393 union { 394 struct { 395 uint32_t addr; 396 uint32_t rsrvd[3]; 397 } ipv4; 398 uint8_t ipv6_addr[16]; 399 } src; 400 uint16_t dst_port; 401 uint16_t src_port; 402} __packed q80_config_lro_flow_t; 403 404typedef struct _q80_config_lro_flow_rsp { 405 uint16_t opcode; 406 uint16_t regcnt_status; 407} __packed q80_config_lro_flow_rsp_t; 408 409typedef struct _q80_set_max_mtu { 410 uint16_t opcode; 411 uint16_t count_version; 412 uint32_t cntxt_id; 413 uint32_t mtu; 414} __packed q80_set_max_mtu_t; 415 416typedef struct _q80_set_max_mtu_rsp { 417 uint16_t opcode; 418 uint16_t regcnt_status; 419} __packed q80_set_max_mtu_rsp_t; 420 421/* 422 * Configure RSS 423 */ 424typedef struct _q80_config_rss { 425 uint16_t opcode; 426 uint16_t count_version; 427 428 uint16_t cntxt_id; 429 uint16_t rsrvd; 430 431 uint8_t hash_type; 432#define Q8_MBX_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 433#define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 434#define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 435#define Q8_MBX_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 436#define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 437#define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 438 439 uint8_t flags; 440#define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1) 441#define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2) 442#define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4) 443 444 uint16_t indtbl_mask; 445#define Q8_MBX_RSS_INDTBL_MASK 0x7F 446#define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000 447 448 uint32_t multi_rss; 449#define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30 450#define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31 451 452 uint64_t rss_key[5]; 453} __packed q80_config_rss_t; 454 455typedef struct _q80_config_rss_rsp { 456 uint16_t opcode; 457 uint16_t regcnt_status; 458} __packed q80_config_rss_rsp_t; 459 460/* 461 * Configure RSS Indirection Table 462 */ 463#define Q8_RSS_IND_TBL_SIZE 40 464#define Q8_RSS_IND_TBL_MIN_IDX 0 465#define Q8_RSS_IND_TBL_MAX_IDX 127 466 467typedef struct _q80_config_rss_ind_table { 468 uint16_t opcode; 469 uint16_t count_version; 470 uint8_t start_idx; 471 uint8_t end_idx; 472 uint16_t cntxt_id; 473 uint8_t ind_table[Q8_RSS_IND_TBL_SIZE]; 474} __packed q80_config_rss_ind_table_t; 475 476typedef struct _q80_config_rss_ind_table_rsp { 477 uint16_t opcode; 478 uint16_t regcnt_status; 479} __packed q80_config_rss_ind_table_rsp_t; 480 481/* 482 * Configure Interrupt Coalescing and Generation 483 */ 484typedef struct _q80_config_intr_coalesc { 485 uint16_t opcode; 486 uint16_t count_version; 487 uint16_t flags; 488#define Q8_MBX_INTRC_FLAGS_RCV 1 489#define Q8_MBX_INTRC_FLAGS_XMT 2 490#define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3) 491 492 uint16_t cntxt_id; 493 uint16_t max_pkts; 494 uint16_t max_mswait; 495 uint8_t timer_type; 496#define Q8_MBX_INTRC_TIMER_NONE 0 497#define Q8_MBX_INTRC_TIMER_SINGLE 1 498#define Q8_MBX_INTRC_TIMER_PERIODIC 2 499 500 uint16_t sds_ring_mask; 501 502 uint8_t rsrvd; 503 uint32_t ms_timeout; 504} __packed q80_config_intr_coalesc_t; 505 506typedef struct _q80_config_intr_coalesc_rsp { 507 uint16_t opcode; 508 uint16_t regcnt_status; 509} __packed q80_config_intr_coalesc_rsp_t; 510 511/* 512 * Configure MAC Address 513 */ 514typedef struct _q80_mac_addr { 515 uint8_t addr[6]; 516 uint16_t vlan_tci; 517} __packed q80_mac_addr_t; 518 519#define Q8_MAX_MAC_ADDRS 64 520 521typedef struct _q80_config_mac_addr { 522 uint16_t opcode; 523 uint16_t count_version; 524 uint8_t cmd; 525#define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1 526#define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2 527 528#define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6) 529#define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6) 530#define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6) 531 532 uint8_t nmac_entries; 533 uint16_t cntxt_id; 534 q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS]; 535} __packed q80_config_mac_addr_t; 536 537typedef struct _q80_config_mac_addr_rsp { 538 uint16_t opcode; 539 uint16_t regcnt_status; 540 uint8_t cmd; 541 uint8_t nmac_entries; 542 uint16_t cntxt_id; 543 uint32_t status[Q8_MAX_MAC_ADDRS]; 544} __packed q80_config_mac_addr_rsp_t; 545 546/* 547 * Configure MAC Receive Mode 548 */ 549typedef struct _q80_config_mac_rcv_mode { 550 uint16_t opcode; 551 uint16_t count_version; 552 553 uint8_t mode; 554#define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1 555#define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2 556 557 uint8_t rsrvd; 558 uint16_t cntxt_id; 559} __packed q80_config_mac_rcv_mode_t; 560 561typedef struct _q80_config_mac_rcv_mode_rsp { 562 uint16_t opcode; 563 uint16_t regcnt_status; 564} __packed q80_config_mac_rcv_mode_rsp_t; 565 566/* 567 * Configure Firmware Controlled LRO 568 */ 569typedef struct _q80_config_fw_lro { 570 uint16_t opcode; 571 uint16_t count_version; 572 573 uint8_t flags; 574#define Q8_MBX_FW_LRO_IPV4 0x1 575#define Q8_MBX_FW_LRO_IPV6 0x2 576#define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4 577#define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8 578#define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10 579 580 uint8_t rsrvd; 581 uint16_t cntxt_id; 582 583 uint16_t low_threshold; 584 uint16_t rsrvd0; 585} __packed q80_config_fw_lro_t; 586 587typedef struct _q80_config_fw_lro_rsp { 588 uint16_t opcode; 589 uint16_t regcnt_status; 590} __packed q80_config_fw_lro_rsp_t; 591 592/* 593 * Minidump mailbox commands 594 */ 595typedef struct _q80_config_md_templ_size { 596 uint16_t opcode; 597 uint16_t count_version; 598} __packed q80_config_md_templ_size_t; 599 600typedef struct _q80_config_md_templ_size_rsp { 601 uint16_t opcode; 602 uint16_t regcnt_status; 603 uint32_t rsrvd; 604 uint32_t templ_size; 605 uint32_t templ_version; 606} __packed q80_config_md_templ_size_rsp_t; 607 608typedef struct _q80_config_md_templ_cmd { 609 uint16_t opcode; 610 uint16_t count_version; 611 uint64_t buf_addr; /* physical address of buffer */ 612 uint32_t buff_size; 613 uint32_t offset; 614} __packed q80_config_md_templ_cmd_t; 615 616typedef struct _q80_config_md_templ_cmd_rsp { 617 uint16_t opcode; 618 uint16_t regcnt_status; 619 uint32_t rsrvd; 620 uint32_t templ_size; 621 uint32_t buff_size; 622 uint32_t offset; 623} __packed q80_config_md_templ_cmd_rsp_t; 624 625/* 626 * Hardware Configuration Commands 627 */ 628 629typedef struct _q80_hw_config { 630 uint16_t opcode; 631 uint16_t count_version; 632#define Q8_HW_CONFIG_SET_MDIO_REG_COUNT 0x06 633#define Q8_HW_CONFIG_GET_MDIO_REG_COUNT 0x05 634#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03 635#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02 636#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT 0x03 637#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT 0x02 638#define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT 0x02 639 640 uint32_t cmd; 641#define Q8_HW_CONFIG_SET_MDIO_REG 0x01 642#define Q8_HW_CONFIG_GET_MDIO_REG 0x02 643#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE 0x03 644#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE 0x04 645#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD 0x07 646#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD 0x08 647#define Q8_HW_CONFIG_GET_ECC_COUNTS 0x0A 648 649 union { 650 struct { 651 uint32_t phys_port_number; 652 uint32_t phy_dev_addr; 653 uint32_t reg_addr; 654 uint32_t data; 655 } set_mdio; 656 657 struct { 658 uint32_t phys_port_number; 659 uint32_t phy_dev_addr; 660 uint32_t reg_addr; 661 } get_mdio; 662 663 struct { 664 uint32_t mode; 665#define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL 0x1 666#define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO 0x2 667 668 } set_cam_search_mode; 669 670 struct { 671 uint32_t value; 672 } set_temp_threshold; 673 } u; 674} __packed q80_hw_config_t; 675 676typedef struct _q80_hw_config_rsp { 677 uint16_t opcode; 678 uint16_t regcnt_status; 679 680 union { 681 struct { 682 uint32_t value; 683 } get_mdio; 684 685 struct { 686 uint32_t mode; 687 } get_cam_search_mode; 688 689 struct { 690 uint32_t temp_warn; 691 uint32_t curr_temp; 692 uint32_t osc_ring_rate; 693 uint32_t core_voltage; 694 } get_temp_threshold; 695 696 struct { 697 uint32_t ddr_ecc_error_count; 698 uint32_t ocm_ecc_error_count; 699 uint32_t l2_dcache_ecc_error_count; 700 uint32_t l2_icache_ecc_error_count; 701 uint32_t eport_ecc_error_count; 702 } get_ecc_counts; 703 } u; 704} __packed q80_hw_config_rsp_t; 705 706/* 707 * Link Event Request Command 708 */ 709typedef struct _q80_link_event { 710 uint16_t opcode; 711 uint16_t count_version; 712 uint8_t cmd; 713#define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0 714#define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1 715 716 uint8_t flags; 717#define Q8_LINK_EVENT_FLAGS_SEND_RSP 1 718 719 uint16_t cntxt_id; 720} __packed q80_link_event_t; 721 722typedef struct _q80_link_event_rsp { 723 uint16_t opcode; 724 uint16_t regcnt_status; 725} __packed q80_link_event_rsp_t; 726 727/* 728 * Get Statistics Command 729 */ 730typedef struct _q80_rcv_stats { 731 uint64_t total_bytes; 732 uint64_t total_pkts; 733 uint64_t lro_pkt_count; 734 uint64_t sw_pkt_count; 735 uint64_t ip_chksum_err; 736 uint64_t pkts_wo_acntxts; 737 uint64_t pkts_dropped_no_sds_card; 738 uint64_t pkts_dropped_no_sds_host; 739 uint64_t oversized_pkts; 740 uint64_t pkts_dropped_no_rds; 741 uint64_t unxpctd_mcast_pkts; 742 uint64_t re1_fbq_error; 743 uint64_t invalid_mac_addr; 744 uint64_t rds_prime_trys; 745 uint64_t rds_prime_success; 746 uint64_t lro_flows_added; 747 uint64_t lro_flows_deleted; 748 uint64_t lro_flows_active; 749 uint64_t pkts_droped_unknown; 750} __packed q80_rcv_stats_t; 751 752typedef struct _q80_xmt_stats { 753 uint64_t total_bytes; 754 uint64_t total_pkts; 755 uint64_t errors; 756 uint64_t pkts_dropped; 757 uint64_t switch_pkts; 758 uint64_t num_buffers; 759} __packed q80_xmt_stats_t; 760 761typedef struct _q80_mac_stats { 762 uint64_t xmt_frames; 763 uint64_t xmt_bytes; 764 uint64_t xmt_mcast_pkts; 765 uint64_t xmt_bcast_pkts; 766 uint64_t xmt_pause_frames; 767 uint64_t xmt_cntrl_pkts; 768 uint64_t xmt_pkt_lt_64bytes; 769 uint64_t xmt_pkt_lt_127bytes; 770 uint64_t xmt_pkt_lt_255bytes; 771 uint64_t xmt_pkt_lt_511bytes; 772 uint64_t xmt_pkt_lt_1023bytes; 773 uint64_t xmt_pkt_lt_1518bytes; 774 uint64_t xmt_pkt_gt_1518bytes; 775 uint64_t rsrvd0[3]; 776 uint64_t rcv_frames; 777 uint64_t rcv_bytes; 778 uint64_t rcv_mcast_pkts; 779 uint64_t rcv_bcast_pkts; 780 uint64_t rcv_pause_frames; 781 uint64_t rcv_cntrl_pkts; 782 uint64_t rcv_pkt_lt_64bytes; 783 uint64_t rcv_pkt_lt_127bytes; 784 uint64_t rcv_pkt_lt_255bytes; 785 uint64_t rcv_pkt_lt_511bytes; 786 uint64_t rcv_pkt_lt_1023bytes; 787 uint64_t rcv_pkt_lt_1518bytes; 788 uint64_t rcv_pkt_gt_1518bytes; 789 uint64_t rsrvd1[3]; 790 uint64_t rcv_len_error; 791 uint64_t rcv_len_small; 792 uint64_t rcv_len_large; 793 uint64_t rcv_jabber; 794 uint64_t rcv_dropped; 795 uint64_t fcs_error; 796 uint64_t align_error; 797 uint64_t eswitched_frames; 798 uint64_t eswitched_bytes; 799 uint64_t eswitched_mcast_frames; 800 uint64_t eswitched_bcast_frames; 801 uint64_t eswitched_ucast_frames; 802 uint64_t eswitched_err_free_frames; 803 uint64_t eswitched_err_free_bytes; 804} __packed q80_mac_stats_t; 805 806typedef struct _q80_get_stats { 807 uint16_t opcode; 808 uint16_t count_version; 809 810 uint32_t cmd; 811#define Q8_GET_STATS_CMD_CLEAR 0x01 812#define Q8_GET_STATS_CMD_RCV 0x00 813#define Q8_GET_STATS_CMD_XMT 0x02 814#define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00 815#define Q8_GET_STATS_CMD_TYPE_MAC 0x04 816#define Q8_GET_STATS_CMD_TYPE_FUNC 0x08 817#define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C 818#define Q8_GET_STATS_CMD_TYPE_ALL (0x7 << 2) 819 820} __packed q80_get_stats_t; 821 822typedef struct _q80_get_stats_rsp { 823 uint16_t opcode; 824 uint16_t regcnt_status; 825 uint32_t cmd; 826 union { 827 q80_rcv_stats_t rcv; 828 q80_xmt_stats_t xmt; 829 q80_mac_stats_t mac; 830 } u; 831} __packed q80_get_stats_rsp_t; 832 833typedef struct _q80_get_mac_rcv_xmt_stats_rsp { 834 uint16_t opcode; 835 uint16_t regcnt_status; 836 uint32_t cmd; 837 q80_mac_stats_t mac; 838 q80_rcv_stats_t rcv; 839 q80_xmt_stats_t xmt; 840} __packed q80_get_mac_rcv_xmt_stats_rsp_t; 841 842/* 843 * Init NIC Function 844 * Used to Register DCBX Configuration Change AEN 845 */ 846typedef struct _q80_init_nic_func { 847 uint16_t opcode; 848 uint16_t count_version; 849 850 uint32_t options; 851#define Q8_INIT_NIC_REG_IDC_AEN 0x01 852#define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02 853#define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04 854 855} __packed q80_init_nic_func_t; 856 857typedef struct _q80_init_nic_func_rsp { 858 uint16_t opcode; 859 uint16_t regcnt_status; 860} __packed q80_init_nic_func_rsp_t; 861 862/* 863 * Stop NIC Function 864 * Used to DeRegister DCBX Configuration Change AEN 865 */ 866typedef struct _q80_stop_nic_func { 867 uint16_t opcode; 868 uint16_t count_version; 869 870 uint32_t options; 871#define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02 872#define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04 873 874} __packed q80_stop_nic_func_t; 875 876typedef struct _q80_stop_nic_func_rsp { 877 uint16_t opcode; 878 uint16_t regcnt_status; 879} __packed q80_stop_nic_func_rsp_t; 880 881/* 882 * Query Firmware DCBX Capabilities 883 */ 884typedef struct _q80_query_fw_dcbx_caps { 885 uint16_t opcode; 886 uint16_t count_version; 887} __packed q80_query_fw_dcbx_caps_t; 888 889typedef struct _q80_query_fw_dcbx_caps_rsp { 890 uint16_t opcode; 891 uint16_t regcnt_status; 892 893 uint32_t dcbx_caps; 894#define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001 895#define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002 896#define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004 897#define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008 898#define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000 899#define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000 900#define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000 901 902} __packed q80_query_fw_dcbx_caps_rsp_t; 903 904/* 905 * IDC Ack Cmd 906 */ 907 908typedef struct _q80_idc_ack { 909 uint16_t opcode; 910 uint16_t count_version; 911 912 uint32_t aen_mb1; 913 uint32_t aen_mb2; 914 uint32_t aen_mb3; 915 uint32_t aen_mb4; 916 917} __packed q80_idc_ack_t; 918 919typedef struct _q80_idc_ack_rsp { 920 uint16_t opcode; 921 uint16_t regcnt_status; 922} __packed q80_idc_ack_rsp_t; 923 924 925/* 926 * Set Port Configuration command 927 * Used to set Ethernet Standard Pause values 928 */ 929 930typedef struct _q80_set_port_cfg { 931 uint16_t opcode; 932 uint16_t count_version; 933 934 uint32_t cfg_bits; 935 936#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1) 937#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1) 938#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1) 939#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1) 940#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1) 941 942#define Q8_VALID_LOOPBACK_MODE(mode) \ 943 (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \ 944 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \ 945 ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT))) 946 947#define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4 948 949#define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5) 950#define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5) 951#define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5) 952#define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5) 953 954#define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8 955#define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9 956#define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10 957#define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11 958 959#define Q8_PORT_CFG_BITS_AUTONEG BIT_15 960#define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17 961#define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18 962#define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19 963 964#define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 965#define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20) 966#define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 967#define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 968 969} __packed q80_set_port_cfg_t; 970 971typedef struct _q80_set_port_cfg_rsp { 972 uint16_t opcode; 973 uint16_t regcnt_status; 974} __packed q80_set_port_cfg_rsp_t; 975 976/* 977 * Get Port Configuration Command 978 */ 979 980typedef struct _q80_get_port_cfg { 981 uint16_t opcode; 982 uint16_t count_version; 983} __packed q80_get_port_cfg_t; 984 985typedef struct _q80_get_port_cfg_rsp { 986 uint16_t opcode; 987 uint16_t regcnt_status; 988 989 uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */ 990 991 uint8_t phys_port_type; 992 uint8_t rsvd[3]; 993} __packed q80_get_port_cfg_rsp_t; 994 995/* 996 * Get Link Status Command 997 * Used to get current PAUSE values for the port 998 */ 999 1000typedef struct _q80_get_link_status { 1001 uint16_t opcode; 1002 uint16_t count_version; 1003} __packed q80_get_link_status_t; 1004 1005typedef struct _q80_get_link_status_rsp { 1006 uint16_t opcode; 1007 uint16_t regcnt_status; 1008 1009 uint32_t cfg_bits; 1010#define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0 1011 1012#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3) 1013#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3) 1014#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3) 1015#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3) 1016#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3) 1017#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3) 1018 1019#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6) 1020#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6) 1021#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6) 1022#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6) 1023 1024#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8) 1025#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6) 1026#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6) 1027#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6) 1028 1029#define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12 1030#define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13 1031 1032#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 1033#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20) 1034#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 1035#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 1036#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20) 1037 1038 uint32_t link_state; 1039#define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0 1040#define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3 1041#define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4 1042#define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5 1043#define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6 1044#define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7 1045#define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9 1046#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 1047 1048 uint32_t sfp_info; 1049#define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3 1050#define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0 1051#define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1 1052#define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2 1053#define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3 1054 1055#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2) 1056#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2) 1057#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2) 1058#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2) 1059#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2) 1060 1061#define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4) 1062#define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4) 1063#define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4) 1064#define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4) 1065#define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4) 1066#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4) 1067#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4) 1068#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4) 1069#define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4) 1070#define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4) 1071#define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4) 1072#define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4) 1073#define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4) 1074#define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4) 1075 1076#define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9 1077#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 1078#define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16) 1079 1080} __packed q80_get_link_status_rsp_t; 1081 1082 1083/* 1084 * Transmit Related Definitions 1085 */ 1086/* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/ 1087#define MAX_TCNTXT_RINGS 8 1088 1089/* 1090 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 1091 */ 1092 1093typedef struct _q80_rq_tx_ring { 1094 uint64_t paddr; 1095 uint64_t tx_consumer; 1096 uint16_t nentries; 1097 uint16_t intr_id; 1098 uint8_t intr_src_bit; 1099 uint8_t rsrvd[3]; 1100} __packed q80_rq_tx_ring_t; 1101 1102typedef struct _q80_rq_tx_cntxt { 1103 uint16_t opcode; 1104 uint16_t count_version; 1105 1106 uint32_t cap0; 1107#define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0) 1108#define Q8_TX_CNTXT_CAP0_LSO (1 << 6) 1109#define Q8_TX_CNTXT_CAP0_TC (1 << 25) 1110 1111 uint32_t cap1; 1112 uint32_t cap2; 1113 uint32_t cap3; 1114 uint8_t ntx_rings; 1115 uint8_t traffic_class; /* bits 8-10; others reserved */ 1116 uint16_t tx_vpid; 1117 q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1118} __packed q80_rq_tx_cntxt_t; 1119 1120typedef struct _q80_rsp_tx_ring { 1121 uint32_t prod_index; 1122 uint16_t cntxt_id; 1123 uint8_t state; 1124 uint8_t rsrvd; 1125} q80_rsp_tx_ring_t; 1126 1127typedef struct _q80_rsp_tx_cntxt { 1128 uint16_t opcode; 1129 uint16_t regcnt_status; 1130 uint8_t ntx_rings; 1131 uint8_t phy_port; 1132 uint8_t virt_port; 1133 uint8_t rsrvd; 1134 q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1135} __packed q80_rsp_tx_cntxt_t; 1136 1137typedef struct _q80_tx_cntxt_destroy { 1138 uint16_t opcode; 1139 uint16_t count_version; 1140 uint32_t cntxt_id; 1141} __packed q80_tx_cntxt_destroy_t; 1142 1143typedef struct _q80_tx_cntxt_destroy_rsp { 1144 uint16_t opcode; 1145 uint16_t regcnt_status; 1146} __packed q80_tx_cntxt_destroy_rsp_t; 1147 1148/* 1149 * Transmit Command Descriptor 1150 * These commands are issued on the Transmit Ring associated with a Transmit 1151 * context 1152 */ 1153typedef struct _q80_tx_cmd { 1154 uint8_t tcp_hdr_off; /* TCP Header Offset */ 1155 uint8_t ip_hdr_off; /* IP Header Offset */ 1156 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 1157 1158 /* flags field */ 1159#define Q8_TX_CMD_FLAGS_MULTICAST 0x01 1160#define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 1161#define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 1162#define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 1163 1164 /* opcode field */ 1165#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 1166#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 1167#define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 1168#define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 1169#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 1170#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 1171#define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 1172 1173 uint8_t n_bufs; /* # of data segs in data buffer */ 1174 uint8_t data_len_lo; /* data length lower 8 bits */ 1175 uint16_t data_len_hi; /* data length upper 16 bits */ 1176 1177 uint64_t buf2_addr; /* buffer 2 address */ 1178 1179 uint16_t rsrvd0; 1180 uint16_t mss; /* MSS for this packet */ 1181 uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 1182 1183#define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 1184 1185 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 1186 uint16_t rsrvd1; 1187 1188 uint64_t buf3_addr; /* buffer 3 address */ 1189 uint64_t buf1_addr; /* buffer 1 address */ 1190 1191 uint16_t buf1_len; /* length of buffer 1 */ 1192 uint16_t buf2_len; /* length of buffer 2 */ 1193 uint16_t buf3_len; /* length of buffer 3 */ 1194 uint16_t buf4_len; /* length of buffer 4 */ 1195 1196 uint64_t buf4_addr; /* buffer 4 address */ 1197 1198 uint32_t rsrvd2; 1199 uint16_t rsrvd3; 1200 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 1201 1202} __packed q80_tx_cmd_t; /* 64 bytes */ 1203 1204#define Q8_TX_CMD_MAX_SEGMENTS 4 1205#define Q8_TX_CMD_TSO_ALIGN 2 1206#define Q8_TX_MAX_NON_TSO_SEGS 62 1207 1208 1209/* 1210 * Receive Related Definitions 1211 */ 1212#define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */ 1213 1214#ifdef QL_ENABLE_ISCSI_TLV 1215#define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ 1216#define NUM_TX_RINGS (MAX_SDS_RINGS * 2) 1217#else 1218#define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 1219#define NUM_TX_RINGS MAX_SDS_RINGS 1220#endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 1221#define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */ 1222 1223 1224typedef struct _q80_rq_sds_ring { 1225 uint64_t paddr; /* physical addr of status ring in system memory */ 1226 uint64_t hdr_split1; 1227 uint64_t hdr_split2; 1228 uint16_t size; /* number of entries in status ring */ 1229 uint16_t hdr_split1_size; 1230 uint16_t hdr_split2_size; 1231 uint16_t hdr_split_count; 1232 uint16_t intr_id; 1233 uint8_t intr_src_bit; 1234 uint8_t rsrvd[5]; 1235} __packed q80_rq_sds_ring_t; /* 10 32bit words */ 1236 1237typedef struct _q80_rq_rds_ring { 1238 uint64_t paddr_std; /* physical addr of rcv ring in system memory */ 1239 uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */ 1240 uint16_t std_bsize; 1241 uint16_t std_nentries; 1242 uint16_t jumbo_bsize; 1243 uint16_t jumbo_nentries; 1244} __packed q80_rq_rds_ring_t; /* 6 32bit words */ 1245 1246#define MAX_RCNTXT_SDS_RINGS 8 1247 1248typedef struct _q80_rq_rcv_cntxt { 1249 uint16_t opcode; 1250 uint16_t count_version; 1251 uint32_t cap0; 1252#define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0) 1253#define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1) 1254#define Q8_RCV_CNTXT_CAP0_LRO (1 << 5) 1255#define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10) 1256#define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14) 1257#define Q8_RCV_CNTXT_CAP0_RSS (1 << 15) 1258#define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16) 1259#define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18) 1260#define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19) 1261#define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO (1 << 26) 1262 1263 uint32_t cap1; 1264 uint32_t cap2; 1265 uint32_t cap3; 1266 uint8_t nrds_sets_rings; 1267 uint8_t nsds_rings; 1268 uint16_t rds_producer_mode; 1269#define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0 1270#define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1 1271 1272 uint16_t rcv_vpid; 1273 uint16_t rsrvd0; 1274 uint32_t rsrvd1; 1275 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1276 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1277} __packed q80_rq_rcv_cntxt_t; 1278 1279typedef struct _q80_rsp_rds_ring { 1280 uint32_t prod_std; 1281 uint32_t prod_jumbo; 1282} __packed q80_rsp_rds_ring_t; /* 8 bytes */ 1283 1284typedef struct _q80_rsp_rcv_cntxt { 1285 uint16_t opcode; 1286 uint16_t regcnt_status; 1287 uint8_t nrds_sets_rings; 1288 uint8_t nsds_rings; 1289 uint16_t cntxt_id; 1290 uint8_t state; 1291 uint8_t num_funcs; 1292 uint8_t phy_port; 1293 uint8_t virt_port; 1294 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1295 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1296} __packed q80_rsp_rcv_cntxt_t; 1297 1298typedef struct _q80_rcv_cntxt_destroy { 1299 uint16_t opcode; 1300 uint16_t count_version; 1301 uint32_t cntxt_id; 1302} __packed q80_rcv_cntxt_destroy_t; 1303 1304typedef struct _q80_rcv_cntxt_destroy_rsp { 1305 uint16_t opcode; 1306 uint16_t regcnt_status; 1307} __packed q80_rcv_cntxt_destroy_rsp_t; 1308 1309 1310/* 1311 * Add Receive Rings 1312 */ 1313typedef struct _q80_rq_add_rcv_rings { 1314 uint16_t opcode; 1315 uint16_t count_version; 1316 uint8_t nrds_sets_rings; 1317 uint8_t nsds_rings; 1318 uint16_t cntxt_id; 1319 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1320 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1321} __packed q80_rq_add_rcv_rings_t; 1322 1323typedef struct _q80_rsp_add_rcv_rings { 1324 uint16_t opcode; 1325 uint16_t regcnt_status; 1326 uint8_t nrds_sets_rings; 1327 uint8_t nsds_rings; 1328 uint16_t cntxt_id; 1329 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1330 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1331} __packed q80_rsp_add_rcv_rings_t; 1332 1333/* 1334 * Map Status Ring to Receive Descriptor Set 1335 */ 1336 1337#define MAX_SDS_TO_RDS_MAP 16 1338 1339typedef struct _q80_sds_rds_map_e { 1340 uint8_t sds_ring; 1341 uint8_t rsrvd0; 1342 uint8_t rds_ring; 1343 uint8_t rsrvd1; 1344} __packed q80_sds_rds_map_e_t; 1345 1346typedef struct _q80_rq_map_sds_to_rds { 1347 uint16_t opcode; 1348 uint16_t count_version; 1349 uint16_t cntxt_id; 1350 uint16_t num_rings; 1351 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1352} __packed q80_rq_map_sds_to_rds_t; 1353 1354 1355typedef struct _q80_rsp_map_sds_to_rds { 1356 uint16_t opcode; 1357 uint16_t regcnt_status; 1358 uint16_t cntxt_id; 1359 uint16_t num_rings; 1360 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1361} __packed q80_rsp_map_sds_to_rds_t; 1362 1363 1364/* 1365 * Receive Descriptor corresponding to each entry in the receive ring 1366 */ 1367typedef struct _q80_rcv_desc { 1368 uint16_t handle; 1369 uint16_t rsrvd; 1370 uint32_t buf_size; /* buffer size in bytes */ 1371 uint64_t buf_addr; /* physical address of buffer */ 1372} __packed q80_recv_desc_t; 1373 1374/* 1375 * Status Descriptor corresponding to each entry in the Status ring 1376 */ 1377typedef struct _q80_stat_desc { 1378 uint64_t data[2]; 1379} __packed q80_stat_desc_t; 1380 1381/* 1382 * definitions for data[0] field of Status Descriptor 1383 */ 1384#define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF) 1385#define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF) 1386#define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF) 1387#define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF) 1388/* 1389 * definitions for data[1] field of Status Descriptor 1390 */ 1391 1392#define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF) 1393#define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01 1394#define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02 1395#define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04 1396#define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05 1397#define Q8_STAT_DESC_OPCODE_CONT 0x06 1398 1399/* 1400 * definitions for data[1] field of Status Descriptor for standard frames 1401 * status descriptor opcode equals 0x04 1402 */ 1403#define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007) 1404#define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00 1405#define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 1406#define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 1407#define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 1408 1409#define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1) 1410#define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF) 1411 1412#define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 1413#define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 1414#define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007) 1415 1416/* 1417 * definitions for data[0-1] fields of Status Descriptor for LRO 1418 * status descriptor opcode equals 0x04 1419 */ 1420 1421/* definitions for data[1] field */ 1422#define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 1423 1424/* 1425 * definitions specific to opcode 0x04 data[1] 1426 */ 1427#define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007) 1428#define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF) 1429#define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF) 1430#define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1) 1431#define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1) 1432 1433 1434/* 1435 * definitions specific to opcode 0x05 data[1] 1436 */ 1437#define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003) 1438 1439/* 1440 * definitions for opcode 0x06 1441 */ 1442/* definitions for data[0] field */ 1443#define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF) 1444#define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF) 1445#define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF) 1446#define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF) 1447 1448/* definitions for data[1] field */ 1449#define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF) 1450#define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF) 1451#define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7) 1452#define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF) 1453 1454/** Driver Related Definitions Begin **/ 1455 1456#define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 1457 1458/* The number of descriptors should be a power of 2 */ 1459#define NUM_TX_DESCRIPTORS 1024 1460#define NUM_STATUS_DESCRIPTORS 1024 1461 1462 1463#define NUM_RX_DESCRIPTORS 2048 1464 1465/* 1466 * structure describing various dma buffers 1467 */ 1468 1469typedef struct qla_dmabuf { 1470 volatile struct { 1471 uint32_t tx_ring :1, 1472 rds_ring :1, 1473 sds_ring :1, 1474 minidump :1; 1475 } flags; 1476 1477 qla_dma_t tx_ring; 1478 qla_dma_t rds_ring[MAX_RDS_RINGS]; 1479 qla_dma_t sds_ring[MAX_SDS_RINGS]; 1480 qla_dma_t minidump; 1481} qla_dmabuf_t; 1482 1483typedef struct _qla_sds { 1484 q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 1485 uint32_t sdsr_next; /* next entry in SDS ring to process */ 1486 struct lro_ctrl lro; 1487 void *rxb_free; 1488 uint32_t rx_free; 1489 volatile uint32_t rcv_active; 1490 uint32_t sds_consumer; 1491 uint64_t intr_count; 1492 uint64_t spurious_intr_count; 1493} qla_sds_t; 1494 1495#define Q8_MAX_LRO_CONT_DESC 7 1496#define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7)) 1497#define Q8_MAX_HANDLES_NON_LRO 8 1498 1499typedef struct _qla_sgl_rcv { 1500 uint16_t pkt_length; 1501 uint16_t num_handles; 1502 uint16_t chksum_status; 1503 uint32_t rss_hash; 1504 uint16_t rss_hash_flags; 1505 uint16_t vlan_tag; 1506 uint16_t handle[Q8_MAX_HANDLES_NON_LRO]; 1507} qla_sgl_rcv_t; 1508 1509typedef struct _qla_sgl_lro { 1510 uint16_t flags; 1511#define Q8_LRO_COMP_TS 0x1 1512#define Q8_LRO_COMP_PUSH_BIT 0x2 1513 uint16_t l2_offset; 1514 uint16_t l4_offset; 1515 1516 uint16_t payload_length; 1517 uint16_t num_handles; 1518 uint32_t rss_hash; 1519 uint16_t rss_hash_flags; 1520 uint16_t vlan_tag; 1521 uint16_t handle[Q8_MAX_HANDLES_LRO]; 1522} qla_sgl_lro_t; 1523 1524typedef union { 1525 qla_sgl_rcv_t rcv; 1526 qla_sgl_lro_t lro; 1527} qla_sgl_comp_t; 1528 1529#define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 1530 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16) 1531 1532typedef struct _qla_hw_tx_cntxt { 1533 q80_tx_cmd_t *tx_ring_base; 1534 bus_addr_t tx_ring_paddr; 1535 1536 volatile uint32_t *tx_cons; /* tx consumer shadow reg */ 1537 bus_addr_t tx_cons_paddr; 1538 1539 volatile uint32_t txr_free; /* # of free entries in tx ring */ 1540 volatile uint32_t txr_next; /* # next available tx ring entry */ 1541 volatile uint32_t txr_comp; /* index of last tx entry completed */ 1542 1543 uint32_t tx_prod_reg; 1544 uint16_t tx_cntxt_id; 1545 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 1546 1547} qla_hw_tx_cntxt_t; 1548 1549typedef struct _qla_mcast { 1550 uint16_t rsrvd; 1551 uint8_t addr[6]; 1552} __packed qla_mcast_t; 1553 1554typedef struct _qla_rdesc { 1555 volatile uint32_t prod_std; 1556 volatile uint32_t prod_jumbo; 1557 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 1558 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 1559 volatile uint64_t count; 1560} qla_rdesc_t; 1561 1562typedef struct _qla_flash_desc_table { 1563 uint32_t flash_valid; 1564 uint16_t flash_ver; 1565 uint16_t flash_len; 1566 uint16_t flash_cksum; 1567 uint16_t flash_unused; 1568 uint8_t flash_model[16]; 1569 uint16_t flash_manuf; 1570 uint16_t flash_id; 1571 uint8_t flash_flag; 1572 uint8_t erase_cmd; 1573 uint8_t alt_erase_cmd; 1574 uint8_t write_enable_cmd; 1575 uint8_t write_enable_bits; 1576 uint8_t write_statusreg_cmd; 1577 uint8_t unprotected_sec_cmd; 1578 uint8_t read_manuf_cmd; 1579 uint32_t block_size; 1580 uint32_t alt_block_size; 1581 uint32_t flash_size; 1582 uint32_t write_enable_data; 1583 uint8_t readid_addr_len; 1584 uint8_t write_disable_bits; 1585 uint8_t read_dev_id_len; 1586 uint8_t chip_erase_cmd; 1587 uint16_t read_timeo; 1588 uint8_t protected_sec_cmd; 1589 uint8_t resvd[65]; 1590} __packed qla_flash_desc_table_t; 1591 1592/* 1593 * struct for storing hardware specific information for a given interface 1594 */ 1595typedef struct _qla_hw { 1596 struct { 1597 uint32_t 1598 unicast_mac :1, 1599 bcast_mac :1, 1600 loopback_mode :2, 1601 init_tx_cnxt :1, 1602 init_rx_cnxt :1, 1603 init_intr_cnxt :1, 1604 fduplex :1, 1605 autoneg :1, 1606 fdt_valid :1; 1607 } flags; 1608 1609 1610 uint16_t link_speed; 1611 uint16_t cable_length; 1612 uint32_t cable_oui; 1613 uint8_t link_up; 1614 uint8_t module_type; 1615 uint8_t link_faults; 1616 1617 uint8_t mac_rcv_mode; 1618 1619 uint32_t max_mtu; 1620 1621 uint8_t mac_addr[ETHER_ADDR_LEN]; 1622 1623 uint32_t num_sds_rings; 1624 uint32_t num_rds_rings; 1625 uint32_t num_tx_rings; 1626 1627 qla_dmabuf_t dma_buf; 1628 1629 /* Transmit Side */ 1630 1631 qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS]; 1632 1633 /* Receive Side */ 1634 1635 uint16_t rcv_cntxt_id; 1636 1637 uint32_t mbx_intr_mask_offset; 1638 1639 uint16_t intr_id[MAX_SDS_RINGS]; 1640 uint32_t intr_src[MAX_SDS_RINGS]; 1641 1642 qla_sds_t sds[MAX_SDS_RINGS]; 1643 uint32_t mbox[Q8_NUM_MBOX]; 1644 qla_rdesc_t rds[MAX_RDS_RINGS]; 1645 1646 uint32_t rds_pidx_thres; 1647 uint32_t sds_cidx_thres; 1648 1649 uint32_t rcv_intr_coalesce; 1650 uint32_t xmt_intr_coalesce; 1651 1652 /* Immediate Completion */ 1653 volatile uint32_t imd_compl; 1654 volatile uint32_t aen_mb0; 1655 volatile uint32_t aen_mb1; 1656 volatile uint32_t aen_mb2; 1657 volatile uint32_t aen_mb3; 1658 volatile uint32_t aen_mb4; 1659 1660 /* multicast address list */ 1661 uint32_t nmcast; 1662 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; 1663 1664 /* reset sequence */ 1665#define Q8_MAX_RESET_SEQ_IDX 16 1666 uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX]; 1667 uint32_t rst_seq_idx; 1668 1669 /* heart beat register value */ 1670 uint32_t hbeat_value; 1671 uint32_t health_count; 1672 1673 uint32_t max_tx_segs; 1674 uint32_t min_lro_pkt_size; 1675 1676 uint32_t enable_9kb; 1677 1678 uint32_t user_pri_nic; 1679 uint32_t user_pri_iscsi; 1680 uint64_t iscsi_pkt_count; 1681 1682 /* Flash Descriptor Table */ 1683 qla_flash_desc_table_t fdt; 1684 1685 /* Minidump Related */ 1686 uint32_t mdump_init; 1687 uint32_t mdump_done; 1688 uint32_t mdump_active; 1689 uint32_t mdump_capture_mask; 1690 uint32_t mdump_start_seq_index; 1691 void *mdump_buffer; 1692 uint32_t mdump_buffer_size; 1693 void *mdump_template; 1694 uint32_t mdump_template_size; 1695} qla_hw_t; 1696 1697#define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \ 1698 bus_write_4((ha->pci_reg), prod_reg, val); 1699 1700#define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \ 1701 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val) 1702 1703#define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 1704 bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val); 1705 1706#define QL_ENABLE_INTERRUPTS(ha, i) \ 1707 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0); 1708 1709#define QL_BUFFER_ALIGN 16 1710 1711 1712/* 1713 * Flash Configuration 1714 */ 1715#define Q8_BOARD_CONFIG_OFFSET 0x370000 1716#define Q8_BOARD_CONFIG_LENGTH 0x2000 1717 1718#define Q8_BOARD_CONFIG_MAC0_LO 0x400 1719 1720#define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD 1721#define Q8_FDT_FLASH_ADDR_VAL 0xFD009F 1722#define Q8_FDT_FLASH_CTRL_VAL 0x3F 1723#define Q8_FDT_MASK_VAL 0xFF 1724 1725#define Q8_WR_ENABLE_FL_ADDR 0xFD0100 1726#define Q8_WR_ENABLE_FL_CTRL 0x5 1727 1728#define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF 1729#define Q8_ERASE_FL_ADDR_MASK 0xFD0300 1730#define Q8_ERASE_FL_CTRL_MASK 0x3D 1731 1732#define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD 1733#define Q8_WR_FL_ADDR_MASK 0x800000 1734#define Q8_WR_FL_CTRL_MASK 0x3D 1735 1736#define QL_FDT_OFFSET 0x3F0000 1737#define Q8_FLASH_SECTOR_SIZE 0x10000 1738 1739/* 1740 * Off Chip Memory Access 1741 */ 1742 1743typedef struct _q80_offchip_mem_val { 1744 uint32_t data_lo; 1745 uint32_t data_hi; 1746 uint32_t data_ulo; 1747 uint32_t data_uhi; 1748} q80_offchip_mem_val_t; 1749 1750#endif /* #ifndef _QL_HW_H_ */ 1751