ql_hw.c revision 324761
1250661Sdavidcs/* 2284741Sdavidcs * Copyright (c) 2013-2016 Qlogic Corporation 3250661Sdavidcs * All rights reserved. 4250661Sdavidcs * 5250661Sdavidcs * Redistribution and use in source and binary forms, with or without 6250661Sdavidcs * modification, are permitted provided that the following conditions 7250661Sdavidcs * are met: 8250661Sdavidcs * 9250661Sdavidcs * 1. Redistributions of source code must retain the above copyright 10250661Sdavidcs * notice, this list of conditions and the following disclaimer. 11250661Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12250661Sdavidcs * notice, this list of conditions and the following disclaimer in the 13250661Sdavidcs * documentation and/or other materials provided with the distribution. 14250661Sdavidcs * 15250661Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16250661Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250661Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250661Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19250661Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20250661Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21250661Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22250661Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23250661Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24250661Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25250661Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26250661Sdavidcs */ 27250661Sdavidcs 28250661Sdavidcs/* 29250661Sdavidcs * File: ql_hw.c 30250661Sdavidcs * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 31298955Spfg * Content: Contains Hardware dependent functions 32250661Sdavidcs */ 33250661Sdavidcs 34250661Sdavidcs#include <sys/cdefs.h> 35250661Sdavidcs__FBSDID("$FreeBSD: stable/11/sys/dev/qlxgbe/ql_hw.c 324761 2017-10-19 17:28:09Z davidcs $"); 36250661Sdavidcs 37250661Sdavidcs#include "ql_os.h" 38250661Sdavidcs#include "ql_hw.h" 39250661Sdavidcs#include "ql_def.h" 40250661Sdavidcs#include "ql_inline.h" 41250661Sdavidcs#include "ql_ver.h" 42250661Sdavidcs#include "ql_glbl.h" 43250661Sdavidcs#include "ql_dbg.h" 44305487Sdavidcs#include "ql_minidump.h" 45250661Sdavidcs 46250661Sdavidcs/* 47250661Sdavidcs * Static Functions 48250661Sdavidcs */ 49250661Sdavidcs 50250661Sdavidcsstatic void qla_del_rcv_cntxt(qla_host_t *ha); 51250661Sdavidcsstatic int qla_init_rcv_cntxt(qla_host_t *ha); 52250661Sdavidcsstatic void qla_del_xmt_cntxt(qla_host_t *ha); 53250661Sdavidcsstatic int qla_init_xmt_cntxt(qla_host_t *ha); 54250661Sdavidcsstatic int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 55250661Sdavidcs uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause); 56284741Sdavidcsstatic int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, 57284741Sdavidcs uint32_t num_intrs, uint32_t create); 58250661Sdavidcsstatic int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id); 59250661Sdavidcsstatic int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, 60284741Sdavidcs int tenable, int rcv); 61250661Sdavidcsstatic int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode); 62250661Sdavidcsstatic int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id); 63250661Sdavidcs 64250661Sdavidcsstatic int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, 65250661Sdavidcs uint8_t *hdr); 66250661Sdavidcsstatic int qla_hw_add_all_mcast(qla_host_t *ha); 67284741Sdavidcsstatic int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds); 68250661Sdavidcs 69284741Sdavidcsstatic int qla_init_nic_func(qla_host_t *ha); 70284741Sdavidcsstatic int qla_stop_nic_func(qla_host_t *ha); 71284741Sdavidcsstatic int qla_query_fw_dcbx_caps(qla_host_t *ha); 72284741Sdavidcsstatic int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits); 73284741Sdavidcsstatic int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits); 74305488Sdavidcsstatic int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode); 75305488Sdavidcsstatic int qla_get_cam_search_mode(qla_host_t *ha); 76284741Sdavidcs 77305487Sdavidcsstatic void ql_minidump_free(qla_host_t *ha); 78250661Sdavidcs 79250661Sdavidcs#ifdef QL_DBG 80250661Sdavidcs 81250661Sdavidcsstatic void 82250661Sdavidcsqla_stop_pegs(qla_host_t *ha) 83250661Sdavidcs{ 84250661Sdavidcs uint32_t val = 1; 85250661Sdavidcs 86250661Sdavidcs ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0); 87250661Sdavidcs ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0); 88250661Sdavidcs ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0); 89250661Sdavidcs ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0); 90250661Sdavidcs ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0); 91250661Sdavidcs device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__); 92250661Sdavidcs} 93250661Sdavidcs 94250661Sdavidcsstatic int 95250661Sdavidcsqla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS) 96250661Sdavidcs{ 97250661Sdavidcs int err, ret = 0; 98250661Sdavidcs qla_host_t *ha; 99250661Sdavidcs 100250661Sdavidcs err = sysctl_handle_int(oidp, &ret, 0, req); 101250661Sdavidcs 102250661Sdavidcs 103250661Sdavidcs if (err || !req->newptr) 104250661Sdavidcs return (err); 105250661Sdavidcs 106250661Sdavidcs if (ret == 1) { 107250661Sdavidcs ha = (qla_host_t *)arg1; 108322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 109322972Sdavidcs qla_stop_pegs(ha); 110322972Sdavidcs QLA_UNLOCK(ha, __func__); 111322972Sdavidcs } 112250661Sdavidcs } 113250661Sdavidcs 114250661Sdavidcs return err; 115250661Sdavidcs} 116250661Sdavidcs#endif /* #ifdef QL_DBG */ 117250661Sdavidcs 118284741Sdavidcsstatic int 119284741Sdavidcsqla_validate_set_port_cfg_bit(uint32_t bits) 120284741Sdavidcs{ 121284741Sdavidcs if ((bits & 0xF) > 1) 122284741Sdavidcs return (-1); 123284741Sdavidcs 124284741Sdavidcs if (((bits >> 4) & 0xF) > 2) 125284741Sdavidcs return (-1); 126284741Sdavidcs 127284741Sdavidcs if (((bits >> 8) & 0xF) > 2) 128284741Sdavidcs return (-1); 129284741Sdavidcs 130284741Sdavidcs return (0); 131284741Sdavidcs} 132284741Sdavidcs 133284741Sdavidcsstatic int 134284741Sdavidcsqla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS) 135284741Sdavidcs{ 136284741Sdavidcs int err, ret = 0; 137284741Sdavidcs qla_host_t *ha; 138284741Sdavidcs uint32_t cfg_bits; 139284741Sdavidcs 140284741Sdavidcs err = sysctl_handle_int(oidp, &ret, 0, req); 141284741Sdavidcs 142284741Sdavidcs if (err || !req->newptr) 143284741Sdavidcs return (err); 144284741Sdavidcs 145322972Sdavidcs ha = (qla_host_t *)arg1; 146322972Sdavidcs 147284741Sdavidcs if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) { 148284741Sdavidcs 149284741Sdavidcs err = qla_get_port_config(ha, &cfg_bits); 150284741Sdavidcs 151284741Sdavidcs if (err) 152284741Sdavidcs goto qla_sysctl_set_port_cfg_exit; 153284741Sdavidcs 154284741Sdavidcs if (ret & 0x1) { 155284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE; 156284741Sdavidcs } else { 157284741Sdavidcs cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE; 158284741Sdavidcs } 159284741Sdavidcs 160284741Sdavidcs ret = ret >> 4; 161284741Sdavidcs cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK; 162284741Sdavidcs 163284741Sdavidcs if ((ret & 0xF) == 0) { 164284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED; 165284741Sdavidcs } else if ((ret & 0xF) == 1){ 166284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD; 167284741Sdavidcs } else { 168284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM; 169284741Sdavidcs } 170284741Sdavidcs 171284741Sdavidcs ret = ret >> 4; 172284741Sdavidcs cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK; 173284741Sdavidcs 174284741Sdavidcs if (ret == 0) { 175284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV; 176284741Sdavidcs } else if (ret == 1){ 177284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT; 178284741Sdavidcs } else { 179284741Sdavidcs cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV; 180284741Sdavidcs } 181284741Sdavidcs 182322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 183322972Sdavidcs err = qla_set_port_config(ha, cfg_bits); 184322972Sdavidcs QLA_UNLOCK(ha, __func__); 185322972Sdavidcs } else { 186322972Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 187322972Sdavidcs } 188284741Sdavidcs } else { 189322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 190322972Sdavidcs err = qla_get_port_config(ha, &cfg_bits); 191322972Sdavidcs QLA_UNLOCK(ha, __func__); 192322972Sdavidcs } else { 193322972Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 194322972Sdavidcs } 195284741Sdavidcs } 196284741Sdavidcs 197284741Sdavidcsqla_sysctl_set_port_cfg_exit: 198284741Sdavidcs return err; 199284741Sdavidcs} 200284741Sdavidcs 201305488Sdavidcsstatic int 202305488Sdavidcsqla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS) 203305488Sdavidcs{ 204305488Sdavidcs int err, ret = 0; 205305488Sdavidcs qla_host_t *ha; 206305488Sdavidcs 207305488Sdavidcs err = sysctl_handle_int(oidp, &ret, 0, req); 208305488Sdavidcs 209305488Sdavidcs if (err || !req->newptr) 210305488Sdavidcs return (err); 211305488Sdavidcs 212305488Sdavidcs ha = (qla_host_t *)arg1; 213305488Sdavidcs 214305488Sdavidcs if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) || 215305488Sdavidcs (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) { 216322972Sdavidcs 217322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 218322972Sdavidcs err = qla_set_cam_search_mode(ha, (uint32_t)ret); 219322972Sdavidcs QLA_UNLOCK(ha, __func__); 220322972Sdavidcs } else { 221322972Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 222322972Sdavidcs } 223322972Sdavidcs 224305488Sdavidcs } else { 225305488Sdavidcs device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret); 226305488Sdavidcs } 227305488Sdavidcs 228305488Sdavidcs return (err); 229305488Sdavidcs} 230305488Sdavidcs 231305488Sdavidcsstatic int 232305488Sdavidcsqla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS) 233305488Sdavidcs{ 234305488Sdavidcs int err, ret = 0; 235305488Sdavidcs qla_host_t *ha; 236305488Sdavidcs 237305488Sdavidcs err = sysctl_handle_int(oidp, &ret, 0, req); 238305488Sdavidcs 239305488Sdavidcs if (err || !req->newptr) 240305488Sdavidcs return (err); 241305488Sdavidcs 242305488Sdavidcs ha = (qla_host_t *)arg1; 243322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 244322972Sdavidcs err = qla_get_cam_search_mode(ha); 245322972Sdavidcs QLA_UNLOCK(ha, __func__); 246322972Sdavidcs } else { 247322972Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 248322972Sdavidcs } 249305488Sdavidcs 250305488Sdavidcs return (err); 251305488Sdavidcs} 252305488Sdavidcs 253322972Sdavidcsstatic void 254322972Sdavidcsqlnx_add_hw_mac_stats_sysctls(qla_host_t *ha) 255322972Sdavidcs{ 256322972Sdavidcs struct sysctl_ctx_list *ctx; 257322972Sdavidcs struct sysctl_oid_list *children; 258322972Sdavidcs struct sysctl_oid *ctx_oid; 259305488Sdavidcs 260322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 261322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 262322972Sdavidcs 263322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_mac", 264322972Sdavidcs CTLFLAG_RD, NULL, "stats_hw_mac"); 265322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 266322972Sdavidcs 267322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 268322972Sdavidcs OID_AUTO, "xmt_frames", 269322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_frames, 270322972Sdavidcs "xmt_frames"); 271322972Sdavidcs 272322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 273322972Sdavidcs OID_AUTO, "xmt_bytes", 274322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_bytes, 275322972Sdavidcs "xmt_frames"); 276322972Sdavidcs 277322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 278322972Sdavidcs OID_AUTO, "xmt_mcast_pkts", 279322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts, 280322972Sdavidcs "xmt_mcast_pkts"); 281322972Sdavidcs 282322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 283322972Sdavidcs OID_AUTO, "xmt_bcast_pkts", 284322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts, 285322972Sdavidcs "xmt_bcast_pkts"); 286322972Sdavidcs 287322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 288322972Sdavidcs OID_AUTO, "xmt_pause_frames", 289322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames, 290322972Sdavidcs "xmt_pause_frames"); 291322972Sdavidcs 292322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 293322972Sdavidcs OID_AUTO, "xmt_cntrl_pkts", 294322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts, 295322972Sdavidcs "xmt_cntrl_pkts"); 296322972Sdavidcs 297322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 298322972Sdavidcs OID_AUTO, "xmt_pkt_lt_64bytes", 299322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes, 300322972Sdavidcs "xmt_pkt_lt_64bytes"); 301322972Sdavidcs 302322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 303322972Sdavidcs OID_AUTO, "xmt_pkt_lt_127bytes", 304322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes, 305322972Sdavidcs "xmt_pkt_lt_127bytes"); 306322972Sdavidcs 307322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 308322972Sdavidcs OID_AUTO, "xmt_pkt_lt_255bytes", 309322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes, 310322972Sdavidcs "xmt_pkt_lt_255bytes"); 311322972Sdavidcs 312322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 313322972Sdavidcs OID_AUTO, "xmt_pkt_lt_511bytes", 314322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes, 315322972Sdavidcs "xmt_pkt_lt_511bytes"); 316322972Sdavidcs 317322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 318322972Sdavidcs OID_AUTO, "xmt_pkt_lt_1023bytes", 319322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes, 320322972Sdavidcs "xmt_pkt_lt_1023bytes"); 321322972Sdavidcs 322322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 323322972Sdavidcs OID_AUTO, "xmt_pkt_lt_1518bytes", 324322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes, 325322972Sdavidcs "xmt_pkt_lt_1518bytes"); 326322972Sdavidcs 327322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 328322972Sdavidcs OID_AUTO, "xmt_pkt_gt_1518bytes", 329322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes, 330322972Sdavidcs "xmt_pkt_gt_1518bytes"); 331322972Sdavidcs 332322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 333322972Sdavidcs OID_AUTO, "rcv_frames", 334322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_frames, 335322972Sdavidcs "rcv_frames"); 336322972Sdavidcs 337322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 338322972Sdavidcs OID_AUTO, "rcv_bytes", 339322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_bytes, 340322972Sdavidcs "rcv_bytes"); 341322972Sdavidcs 342322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 343322972Sdavidcs OID_AUTO, "rcv_mcast_pkts", 344322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts, 345322972Sdavidcs "rcv_mcast_pkts"); 346322972Sdavidcs 347322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 348322972Sdavidcs OID_AUTO, "rcv_bcast_pkts", 349322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts, 350322972Sdavidcs "rcv_bcast_pkts"); 351322972Sdavidcs 352322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 353322972Sdavidcs OID_AUTO, "rcv_pause_frames", 354322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames, 355322972Sdavidcs "rcv_pause_frames"); 356322972Sdavidcs 357322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 358322972Sdavidcs OID_AUTO, "rcv_cntrl_pkts", 359322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts, 360322972Sdavidcs "rcv_cntrl_pkts"); 361322972Sdavidcs 362322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 363322972Sdavidcs OID_AUTO, "rcv_pkt_lt_64bytes", 364322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes, 365322972Sdavidcs "rcv_pkt_lt_64bytes"); 366322972Sdavidcs 367322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 368322972Sdavidcs OID_AUTO, "rcv_pkt_lt_127bytes", 369322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes, 370322972Sdavidcs "rcv_pkt_lt_127bytes"); 371322972Sdavidcs 372322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 373322972Sdavidcs OID_AUTO, "rcv_pkt_lt_255bytes", 374322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes, 375322972Sdavidcs "rcv_pkt_lt_255bytes"); 376322972Sdavidcs 377322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 378322972Sdavidcs OID_AUTO, "rcv_pkt_lt_511bytes", 379322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes, 380322972Sdavidcs "rcv_pkt_lt_511bytes"); 381322972Sdavidcs 382322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 383322972Sdavidcs OID_AUTO, "rcv_pkt_lt_1023bytes", 384322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes, 385322972Sdavidcs "rcv_pkt_lt_1023bytes"); 386322972Sdavidcs 387322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 388322972Sdavidcs OID_AUTO, "rcv_pkt_lt_1518bytes", 389322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes, 390322972Sdavidcs "rcv_pkt_lt_1518bytes"); 391322972Sdavidcs 392322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 393322972Sdavidcs OID_AUTO, "rcv_pkt_gt_1518bytes", 394322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes, 395322972Sdavidcs "rcv_pkt_gt_1518bytes"); 396322972Sdavidcs 397322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 398322972Sdavidcs OID_AUTO, "rcv_len_error", 399322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_len_error, 400322972Sdavidcs "rcv_len_error"); 401322972Sdavidcs 402322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 403322972Sdavidcs OID_AUTO, "rcv_len_small", 404322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_len_small, 405322972Sdavidcs "rcv_len_small"); 406322972Sdavidcs 407322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 408322972Sdavidcs OID_AUTO, "rcv_len_large", 409322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_len_large, 410322972Sdavidcs "rcv_len_large"); 411322972Sdavidcs 412322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 413322972Sdavidcs OID_AUTO, "rcv_jabber", 414322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_jabber, 415322972Sdavidcs "rcv_jabber"); 416322972Sdavidcs 417322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 418322972Sdavidcs OID_AUTO, "rcv_dropped", 419322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.rcv_dropped, 420322972Sdavidcs "rcv_dropped"); 421322972Sdavidcs 422322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 423322972Sdavidcs OID_AUTO, "fcs_error", 424322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.fcs_error, 425322972Sdavidcs "fcs_error"); 426322972Sdavidcs 427322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 428322972Sdavidcs OID_AUTO, "align_error", 429322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.align_error, 430322972Sdavidcs "align_error"); 431322972Sdavidcs 432322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 433322972Sdavidcs OID_AUTO, "eswitched_frames", 434322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_frames, 435322972Sdavidcs "eswitched_frames"); 436322972Sdavidcs 437322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 438322972Sdavidcs OID_AUTO, "eswitched_bytes", 439322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_bytes, 440322972Sdavidcs "eswitched_bytes"); 441322972Sdavidcs 442322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 443322972Sdavidcs OID_AUTO, "eswitched_mcast_frames", 444322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames, 445322972Sdavidcs "eswitched_mcast_frames"); 446322972Sdavidcs 447322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 448322972Sdavidcs OID_AUTO, "eswitched_bcast_frames", 449322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames, 450322972Sdavidcs "eswitched_bcast_frames"); 451322972Sdavidcs 452322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 453322972Sdavidcs OID_AUTO, "eswitched_ucast_frames", 454322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames, 455322972Sdavidcs "eswitched_ucast_frames"); 456322972Sdavidcs 457322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 458322972Sdavidcs OID_AUTO, "eswitched_err_free_frames", 459322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames, 460322972Sdavidcs "eswitched_err_free_frames"); 461322972Sdavidcs 462322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 463322972Sdavidcs OID_AUTO, "eswitched_err_free_bytes", 464322972Sdavidcs CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes, 465322972Sdavidcs "eswitched_err_free_bytes"); 466322972Sdavidcs 467322972Sdavidcs return; 468322972Sdavidcs} 469322972Sdavidcs 470322972Sdavidcsstatic void 471322972Sdavidcsqlnx_add_hw_rcv_stats_sysctls(qla_host_t *ha) 472322972Sdavidcs{ 473322972Sdavidcs struct sysctl_ctx_list *ctx; 474322972Sdavidcs struct sysctl_oid_list *children; 475322972Sdavidcs struct sysctl_oid *ctx_oid; 476322972Sdavidcs 477322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 478322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 479322972Sdavidcs 480322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_rcv", 481322972Sdavidcs CTLFLAG_RD, NULL, "stats_hw_rcv"); 482322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 483322972Sdavidcs 484322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 485322972Sdavidcs OID_AUTO, "total_bytes", 486322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.total_bytes, 487322972Sdavidcs "total_bytes"); 488322972Sdavidcs 489322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 490322972Sdavidcs OID_AUTO, "total_pkts", 491322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.total_pkts, 492322972Sdavidcs "total_pkts"); 493322972Sdavidcs 494322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 495322972Sdavidcs OID_AUTO, "lro_pkt_count", 496322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count, 497322972Sdavidcs "lro_pkt_count"); 498322972Sdavidcs 499322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 500322972Sdavidcs OID_AUTO, "sw_pkt_count", 501322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count, 502322972Sdavidcs "sw_pkt_count"); 503322972Sdavidcs 504322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 505322972Sdavidcs OID_AUTO, "ip_chksum_err", 506322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err, 507322972Sdavidcs "ip_chksum_err"); 508322972Sdavidcs 509322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 510322972Sdavidcs OID_AUTO, "pkts_wo_acntxts", 511322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts, 512322972Sdavidcs "pkts_wo_acntxts"); 513322972Sdavidcs 514322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 515322972Sdavidcs OID_AUTO, "pkts_dropped_no_sds_card", 516322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card, 517322972Sdavidcs "pkts_dropped_no_sds_card"); 518322972Sdavidcs 519322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 520322972Sdavidcs OID_AUTO, "pkts_dropped_no_sds_host", 521322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host, 522322972Sdavidcs "pkts_dropped_no_sds_host"); 523322972Sdavidcs 524322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 525322972Sdavidcs OID_AUTO, "oversized_pkts", 526322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.oversized_pkts, 527322972Sdavidcs "oversized_pkts"); 528322972Sdavidcs 529322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 530322972Sdavidcs OID_AUTO, "pkts_dropped_no_rds", 531322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds, 532322972Sdavidcs "pkts_dropped_no_rds"); 533322972Sdavidcs 534322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 535322972Sdavidcs OID_AUTO, "unxpctd_mcast_pkts", 536322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts, 537322972Sdavidcs "unxpctd_mcast_pkts"); 538322972Sdavidcs 539322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 540322972Sdavidcs OID_AUTO, "re1_fbq_error", 541322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error, 542322972Sdavidcs "re1_fbq_error"); 543322972Sdavidcs 544322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 545322972Sdavidcs OID_AUTO, "invalid_mac_addr", 546322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr, 547322972Sdavidcs "invalid_mac_addr"); 548322972Sdavidcs 549322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 550322972Sdavidcs OID_AUTO, "rds_prime_trys", 551322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys, 552322972Sdavidcs "rds_prime_trys"); 553322972Sdavidcs 554322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 555322972Sdavidcs OID_AUTO, "rds_prime_success", 556322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.rds_prime_success, 557322972Sdavidcs "rds_prime_success"); 558322972Sdavidcs 559322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 560322972Sdavidcs OID_AUTO, "lro_flows_added", 561322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.lro_flows_added, 562322972Sdavidcs "lro_flows_added"); 563322972Sdavidcs 564322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 565322972Sdavidcs OID_AUTO, "lro_flows_deleted", 566322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted, 567322972Sdavidcs "lro_flows_deleted"); 568322972Sdavidcs 569322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 570322972Sdavidcs OID_AUTO, "lro_flows_active", 571322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.lro_flows_active, 572322972Sdavidcs "lro_flows_active"); 573322972Sdavidcs 574322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 575322972Sdavidcs OID_AUTO, "pkts_droped_unknown", 576322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown, 577322972Sdavidcs "pkts_droped_unknown"); 578322972Sdavidcs 579322972Sdavidcs SYSCTL_ADD_QUAD(ctx, children, 580322972Sdavidcs OID_AUTO, "pkts_cnt_oversized", 581322972Sdavidcs CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized, 582322972Sdavidcs "pkts_cnt_oversized"); 583322972Sdavidcs 584322972Sdavidcs return; 585322972Sdavidcs} 586322972Sdavidcs 587322972Sdavidcsstatic void 588322972Sdavidcsqlnx_add_hw_xmt_stats_sysctls(qla_host_t *ha) 589322972Sdavidcs{ 590322972Sdavidcs struct sysctl_ctx_list *ctx; 591322972Sdavidcs struct sysctl_oid_list *children; 592322972Sdavidcs struct sysctl_oid_list *node_children; 593322972Sdavidcs struct sysctl_oid *ctx_oid; 594322972Sdavidcs int i; 595322972Sdavidcs uint8_t name_str[16]; 596322972Sdavidcs 597322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 598322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 599322972Sdavidcs 600322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_xmt", 601322972Sdavidcs CTLFLAG_RD, NULL, "stats_hw_xmt"); 602322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 603322972Sdavidcs 604322972Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 605322972Sdavidcs 606322972Sdavidcs bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 607322972Sdavidcs snprintf(name_str, sizeof(name_str), "%d", i); 608322972Sdavidcs 609322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 610322972Sdavidcs CTLFLAG_RD, NULL, name_str); 611322972Sdavidcs node_children = SYSCTL_CHILDREN(ctx_oid); 612322972Sdavidcs 613322972Sdavidcs /* Tx Related */ 614322972Sdavidcs 615322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 616322972Sdavidcs OID_AUTO, "total_bytes", 617322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].total_bytes, 618322972Sdavidcs "total_bytes"); 619322972Sdavidcs 620322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 621322972Sdavidcs OID_AUTO, "total_pkts", 622322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].total_pkts, 623322972Sdavidcs "total_pkts"); 624322972Sdavidcs 625322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 626322972Sdavidcs OID_AUTO, "errors", 627322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].errors, 628322972Sdavidcs "errors"); 629322972Sdavidcs 630322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 631322972Sdavidcs OID_AUTO, "pkts_dropped", 632322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped, 633322972Sdavidcs "pkts_dropped"); 634322972Sdavidcs 635322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 636322972Sdavidcs OID_AUTO, "switch_pkts", 637322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts, 638322972Sdavidcs "switch_pkts"); 639322972Sdavidcs 640322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 641322972Sdavidcs OID_AUTO, "num_buffers", 642322972Sdavidcs CTLFLAG_RD, &ha->hw.xmt[i].num_buffers, 643322972Sdavidcs "num_buffers"); 644322972Sdavidcs } 645322972Sdavidcs 646322972Sdavidcs return; 647322972Sdavidcs} 648322972Sdavidcs 649322972Sdavidcsstatic void 650322972Sdavidcsqlnx_add_hw_stats_sysctls(qla_host_t *ha) 651322972Sdavidcs{ 652322972Sdavidcs qlnx_add_hw_mac_stats_sysctls(ha); 653322972Sdavidcs qlnx_add_hw_rcv_stats_sysctls(ha); 654322972Sdavidcs qlnx_add_hw_xmt_stats_sysctls(ha); 655322972Sdavidcs 656322972Sdavidcs return; 657322972Sdavidcs} 658322972Sdavidcs 659322972Sdavidcsstatic void 660322972Sdavidcsqlnx_add_drvr_sds_stats(qla_host_t *ha) 661322972Sdavidcs{ 662322972Sdavidcs struct sysctl_ctx_list *ctx; 663322972Sdavidcs struct sysctl_oid_list *children; 664322972Sdavidcs struct sysctl_oid_list *node_children; 665322972Sdavidcs struct sysctl_oid *ctx_oid; 666322972Sdavidcs int i; 667322972Sdavidcs uint8_t name_str[16]; 668322972Sdavidcs 669322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 670322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 671322972Sdavidcs 672322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_sds", 673322972Sdavidcs CTLFLAG_RD, NULL, "stats_drvr_sds"); 674322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 675322972Sdavidcs 676322972Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; i++) { 677322972Sdavidcs 678322972Sdavidcs bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 679322972Sdavidcs snprintf(name_str, sizeof(name_str), "%d", i); 680322972Sdavidcs 681322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 682322972Sdavidcs CTLFLAG_RD, NULL, name_str); 683322972Sdavidcs node_children = SYSCTL_CHILDREN(ctx_oid); 684322972Sdavidcs 685322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 686322972Sdavidcs OID_AUTO, "intr_count", 687322972Sdavidcs CTLFLAG_RD, &ha->hw.sds[i].intr_count, 688322972Sdavidcs "intr_count"); 689322972Sdavidcs 690322972Sdavidcs SYSCTL_ADD_UINT(ctx, node_children, 691322972Sdavidcs OID_AUTO, "rx_free", 692322972Sdavidcs CTLFLAG_RD, &ha->hw.sds[i].rx_free, 693322972Sdavidcs ha->hw.sds[i].rx_free, "rx_free"); 694322972Sdavidcs } 695322972Sdavidcs 696322972Sdavidcs return; 697322972Sdavidcs} 698322972Sdavidcsstatic void 699322972Sdavidcsqlnx_add_drvr_rds_stats(qla_host_t *ha) 700322972Sdavidcs{ 701322972Sdavidcs struct sysctl_ctx_list *ctx; 702322972Sdavidcs struct sysctl_oid_list *children; 703322972Sdavidcs struct sysctl_oid_list *node_children; 704322972Sdavidcs struct sysctl_oid *ctx_oid; 705322972Sdavidcs int i; 706322972Sdavidcs uint8_t name_str[16]; 707322972Sdavidcs 708322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 709322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 710322972Sdavidcs 711322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_rds", 712322972Sdavidcs CTLFLAG_RD, NULL, "stats_drvr_rds"); 713322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 714322972Sdavidcs 715322972Sdavidcs for (i = 0; i < ha->hw.num_rds_rings; i++) { 716322972Sdavidcs 717322972Sdavidcs bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 718322972Sdavidcs snprintf(name_str, sizeof(name_str), "%d", i); 719322972Sdavidcs 720322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 721322972Sdavidcs CTLFLAG_RD, NULL, name_str); 722322972Sdavidcs node_children = SYSCTL_CHILDREN(ctx_oid); 723322972Sdavidcs 724322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 725322972Sdavidcs OID_AUTO, "count", 726322972Sdavidcs CTLFLAG_RD, &ha->hw.rds[i].count, 727322972Sdavidcs "count"); 728322972Sdavidcs 729322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 730322972Sdavidcs OID_AUTO, "lro_pkt_count", 731322972Sdavidcs CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count, 732322972Sdavidcs "lro_pkt_count"); 733322972Sdavidcs 734322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 735322972Sdavidcs OID_AUTO, "lro_bytes", 736322972Sdavidcs CTLFLAG_RD, &ha->hw.rds[i].lro_bytes, 737322972Sdavidcs "lro_bytes"); 738322972Sdavidcs } 739322972Sdavidcs 740322972Sdavidcs return; 741322972Sdavidcs} 742322972Sdavidcs 743322972Sdavidcsstatic void 744322972Sdavidcsqlnx_add_drvr_tx_stats(qla_host_t *ha) 745322972Sdavidcs{ 746322972Sdavidcs struct sysctl_ctx_list *ctx; 747322972Sdavidcs struct sysctl_oid_list *children; 748322972Sdavidcs struct sysctl_oid_list *node_children; 749322972Sdavidcs struct sysctl_oid *ctx_oid; 750322972Sdavidcs int i; 751322972Sdavidcs uint8_t name_str[16]; 752322972Sdavidcs 753322972Sdavidcs ctx = device_get_sysctl_ctx(ha->pci_dev); 754322972Sdavidcs children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 755322972Sdavidcs 756322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_xmt", 757322972Sdavidcs CTLFLAG_RD, NULL, "stats_drvr_xmt"); 758322972Sdavidcs children = SYSCTL_CHILDREN(ctx_oid); 759322972Sdavidcs 760322972Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 761322972Sdavidcs 762322972Sdavidcs bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 763322972Sdavidcs snprintf(name_str, sizeof(name_str), "%d", i); 764322972Sdavidcs 765322972Sdavidcs ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 766322972Sdavidcs CTLFLAG_RD, NULL, name_str); 767322972Sdavidcs node_children = SYSCTL_CHILDREN(ctx_oid); 768322972Sdavidcs 769322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 770322972Sdavidcs OID_AUTO, "count", 771322972Sdavidcs CTLFLAG_RD, &ha->tx_ring[i].count, 772322972Sdavidcs "count"); 773322972Sdavidcs 774322972Sdavidcs#ifdef QL_ENABLE_ISCSI_TLV 775322972Sdavidcs SYSCTL_ADD_QUAD(ctx, node_children, 776322972Sdavidcs OID_AUTO, "iscsi_pkt_count", 777322972Sdavidcs CTLFLAG_RD, &ha->tx_ring[i].iscsi_pkt_count, 778322972Sdavidcs "iscsi_pkt_count"); 779322972Sdavidcs#endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 780322972Sdavidcs } 781322972Sdavidcs 782322972Sdavidcs return; 783322972Sdavidcs} 784322972Sdavidcs 785322972Sdavidcsstatic void 786322972Sdavidcsqlnx_add_drvr_stats_sysctls(qla_host_t *ha) 787322972Sdavidcs{ 788322972Sdavidcs qlnx_add_drvr_sds_stats(ha); 789322972Sdavidcs qlnx_add_drvr_rds_stats(ha); 790322972Sdavidcs qlnx_add_drvr_tx_stats(ha); 791322972Sdavidcs return; 792322972Sdavidcs} 793322972Sdavidcs 794250661Sdavidcs/* 795250661Sdavidcs * Name: ql_hw_add_sysctls 796250661Sdavidcs * Function: Add P3Plus specific sysctls 797250661Sdavidcs */ 798250661Sdavidcsvoid 799250661Sdavidcsql_hw_add_sysctls(qla_host_t *ha) 800250661Sdavidcs{ 801250661Sdavidcs device_t dev; 802250661Sdavidcs 803250661Sdavidcs dev = ha->pci_dev; 804250661Sdavidcs 805250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 806250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807250661Sdavidcs OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings, 808250661Sdavidcs ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings"); 809250661Sdavidcs 810250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 811250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812250661Sdavidcs OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings, 813250661Sdavidcs ha->hw.num_sds_rings, "Number of Status Descriptor Rings"); 814250661Sdavidcs 815250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 816250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817250661Sdavidcs OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings, 818250661Sdavidcs ha->hw.num_tx_rings, "Number of Transmit Rings"); 819250661Sdavidcs 820250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 821250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822250661Sdavidcs OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx, 823250661Sdavidcs ha->txr_idx, "Tx Ring Used"); 824250661Sdavidcs 825250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 826250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 827250661Sdavidcs OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs, 828250661Sdavidcs ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt"); 829250661Sdavidcs 830250661Sdavidcs ha->hw.sds_cidx_thres = 32; 831250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 832250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 833250661Sdavidcs OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres, 834250661Sdavidcs ha->hw.sds_cidx_thres, 835250661Sdavidcs "Number of SDS entries to process before updating" 836250661Sdavidcs " SDS Ring Consumer Index"); 837250661Sdavidcs 838250661Sdavidcs ha->hw.rds_pidx_thres = 32; 839250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 840250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 841250661Sdavidcs OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres, 842250661Sdavidcs ha->hw.rds_pidx_thres, 843250661Sdavidcs "Number of Rcv Rings Entries to post before updating" 844250661Sdavidcs " RDS Ring Producer Index"); 845250661Sdavidcs 846284741Sdavidcs ha->hw.rcv_intr_coalesce = (3 << 16) | 256; 847284741Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 848284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 849284741Sdavidcs OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW, 850284741Sdavidcs &ha->hw.rcv_intr_coalesce, 851284741Sdavidcs ha->hw.rcv_intr_coalesce, 852284741Sdavidcs "Rcv Intr Coalescing Parameters\n" 853284741Sdavidcs "\tbits 15:0 max packets\n" 854284741Sdavidcs "\tbits 31:16 max micro-seconds to wait\n" 855284741Sdavidcs "\tplease run\n" 856284741Sdavidcs "\tifconfig <if> down && ifconfig <if> up\n" 857284741Sdavidcs "\tto take effect \n"); 858258155Sdavidcs 859284741Sdavidcs ha->hw.xmt_intr_coalesce = (64 << 16) | 64; 860284741Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 861284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 862284741Sdavidcs OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW, 863284741Sdavidcs &ha->hw.xmt_intr_coalesce, 864284741Sdavidcs ha->hw.xmt_intr_coalesce, 865284741Sdavidcs "Xmt Intr Coalescing Parameters\n" 866284741Sdavidcs "\tbits 15:0 max packets\n" 867284741Sdavidcs "\tbits 31:16 max micro-seconds to wait\n" 868284741Sdavidcs "\tplease run\n" 869284741Sdavidcs "\tifconfig <if> down && ifconfig <if> up\n" 870284741Sdavidcs "\tto take effect \n"); 871284741Sdavidcs 872284741Sdavidcs SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 873284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 874284741Sdavidcs OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW, 875284741Sdavidcs (void *)ha, 0, 876284741Sdavidcs qla_sysctl_port_cfg, "I", 877284741Sdavidcs "Set Port Configuration if values below " 878284741Sdavidcs "otherwise Get Port Configuration\n" 879284741Sdavidcs "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n" 880284741Sdavidcs "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n" 881284741Sdavidcs "\tBits 8-11: std pause cfg; 0 = xmt and rcv;" 882284741Sdavidcs " 1 = xmt only; 2 = rcv only;\n" 883284741Sdavidcs ); 884284741Sdavidcs 885305488Sdavidcs SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 886305488Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 887305488Sdavidcs OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, 888305488Sdavidcs (void *)ha, 0, 889305488Sdavidcs qla_sysctl_set_cam_search_mode, "I", 890305488Sdavidcs "Set CAM Search Mode" 891305488Sdavidcs "\t 1 = search mode internal\n" 892305488Sdavidcs "\t 2 = search mode auto\n"); 893305488Sdavidcs 894305488Sdavidcs SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 895305488Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 896305488Sdavidcs OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, 897305488Sdavidcs (void *)ha, 0, 898305488Sdavidcs qla_sysctl_get_cam_search_mode, "I", 899305488Sdavidcs "Get CAM Search Mode" 900305488Sdavidcs "\t 1 = search mode internal\n" 901305488Sdavidcs "\t 2 = search mode auto\n"); 902305488Sdavidcs 903284741Sdavidcs ha->hw.enable_9kb = 1; 904284741Sdavidcs 905284741Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 906284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 907284741Sdavidcs OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb, 908284741Sdavidcs ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000"); 909284741Sdavidcs 910317109Sdavidcs ha->hw.enable_hw_lro = 1; 911317109Sdavidcs 912317109Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 913317109Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 914317109Sdavidcs OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro, 915317109Sdavidcs ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n" 916317109Sdavidcs "\t 1 : Hardware LRO if LRO is enabled\n" 917317109Sdavidcs "\t 0 : Software LRO if LRO is enabled\n" 918317109Sdavidcs "\t Any change requires ifconfig down/up to take effect\n" 919317109Sdavidcs "\t Note that LRO may be turned off/on via ifconfig\n"); 920317109Sdavidcs 921250661Sdavidcs ha->hw.mdump_active = 0; 922250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 923250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 924250661Sdavidcs OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active, 925250661Sdavidcs ha->hw.mdump_active, 926305487Sdavidcs "Minidump retrieval is Active"); 927250661Sdavidcs 928305487Sdavidcs ha->hw.mdump_done = 0; 929250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 930250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 931305487Sdavidcs OID_AUTO, "mdump_done", CTLFLAG_RW, 932305487Sdavidcs &ha->hw.mdump_done, ha->hw.mdump_done, 933305487Sdavidcs "Minidump has been done and available for retrieval"); 934305487Sdavidcs 935305487Sdavidcs ha->hw.mdump_capture_mask = 0xF; 936305487Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 937305487Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 938305487Sdavidcs OID_AUTO, "minidump_capture_mask", CTLFLAG_RW, 939305487Sdavidcs &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask, 940305487Sdavidcs "Minidump capture mask"); 941250661Sdavidcs#ifdef QL_DBG 942250661Sdavidcs 943289635Sdavidcs ha->err_inject = 0; 944250661Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 945250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 946250661Sdavidcs OID_AUTO, "err_inject", 947250661Sdavidcs CTLFLAG_RW, &ha->err_inject, ha->err_inject, 948250661Sdavidcs "Error to be injected\n" 949250661Sdavidcs "\t\t\t 0: No Errors\n" 950250661Sdavidcs "\t\t\t 1: rcv: rxb struct invalid\n" 951250661Sdavidcs "\t\t\t 2: rcv: mp == NULL\n" 952250661Sdavidcs "\t\t\t 3: lro: rxb struct invalid\n" 953250661Sdavidcs "\t\t\t 4: lro: mp == NULL\n" 954250661Sdavidcs "\t\t\t 5: rcv: num handles invalid\n" 955250661Sdavidcs "\t\t\t 6: reg: indirect reg rd_wr failure\n" 956250661Sdavidcs "\t\t\t 7: ocm: offchip memory rd_wr failure\n" 957250661Sdavidcs "\t\t\t 8: mbx: mailbox command failure\n" 958250661Sdavidcs "\t\t\t 9: heartbeat failure\n" 959305488Sdavidcs "\t\t\t A: temperature failure\n" 960305488Sdavidcs "\t\t\t 11: m_getcl or m_getjcl failure\n" ); 961250661Sdavidcs 962250661Sdavidcs SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 963250661Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 964250661Sdavidcs OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW, 965250661Sdavidcs (void *)ha, 0, 966250661Sdavidcs qla_sysctl_stop_pegs, "I", "Peg Stop"); 967250661Sdavidcs 968250661Sdavidcs#endif /* #ifdef QL_DBG */ 969250661Sdavidcs 970284741Sdavidcs ha->hw.user_pri_nic = 0; 971284741Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 972284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 973284741Sdavidcs OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic, 974284741Sdavidcs ha->hw.user_pri_nic, 975284741Sdavidcs "VLAN Tag User Priority for Normal Ethernet Packets"); 976284741Sdavidcs 977284741Sdavidcs ha->hw.user_pri_iscsi = 4; 978284741Sdavidcs SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 979284741Sdavidcs SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 980284741Sdavidcs OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi, 981284741Sdavidcs ha->hw.user_pri_iscsi, 982284741Sdavidcs "VLAN Tag User Priority for iSCSI Packets"); 983284741Sdavidcs 984322972Sdavidcs qlnx_add_hw_stats_sysctls(ha); 985322972Sdavidcs qlnx_add_drvr_stats_sysctls(ha); 986322972Sdavidcs 987322972Sdavidcs return; 988250661Sdavidcs} 989250661Sdavidcs 990250661Sdavidcsvoid 991250661Sdavidcsql_hw_link_status(qla_host_t *ha) 992250661Sdavidcs{ 993250661Sdavidcs device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui); 994250661Sdavidcs 995250661Sdavidcs if (ha->hw.link_up) { 996250661Sdavidcs device_printf(ha->pci_dev, "link Up\n"); 997250661Sdavidcs } else { 998250661Sdavidcs device_printf(ha->pci_dev, "link Down\n"); 999250661Sdavidcs } 1000250661Sdavidcs 1001250661Sdavidcs if (ha->hw.flags.fduplex) { 1002250661Sdavidcs device_printf(ha->pci_dev, "Full Duplex\n"); 1003250661Sdavidcs } else { 1004250661Sdavidcs device_printf(ha->pci_dev, "Half Duplex\n"); 1005250661Sdavidcs } 1006250661Sdavidcs 1007250661Sdavidcs if (ha->hw.flags.autoneg) { 1008250661Sdavidcs device_printf(ha->pci_dev, "Auto Negotiation Enabled\n"); 1009250661Sdavidcs } else { 1010250661Sdavidcs device_printf(ha->pci_dev, "Auto Negotiation Disabled\n"); 1011250661Sdavidcs } 1012250661Sdavidcs 1013250661Sdavidcs switch (ha->hw.link_speed) { 1014250661Sdavidcs case 0x710: 1015250661Sdavidcs device_printf(ha->pci_dev, "link speed\t\t 10Gps\n"); 1016250661Sdavidcs break; 1017250661Sdavidcs 1018250661Sdavidcs case 0x3E8: 1019250661Sdavidcs device_printf(ha->pci_dev, "link speed\t\t 1Gps\n"); 1020250661Sdavidcs break; 1021250661Sdavidcs 1022250661Sdavidcs case 0x64: 1023250661Sdavidcs device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n"); 1024250661Sdavidcs break; 1025250661Sdavidcs 1026250661Sdavidcs default: 1027250661Sdavidcs device_printf(ha->pci_dev, "link speed\t\t Unknown\n"); 1028250661Sdavidcs break; 1029250661Sdavidcs } 1030250661Sdavidcs 1031250661Sdavidcs switch (ha->hw.module_type) { 1032250661Sdavidcs 1033250661Sdavidcs case 0x01: 1034250661Sdavidcs device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n"); 1035250661Sdavidcs break; 1036250661Sdavidcs 1037250661Sdavidcs case 0x02: 1038250661Sdavidcs device_printf(ha->pci_dev, "Module Type 10GBase-LR\n"); 1039250661Sdavidcs break; 1040250661Sdavidcs 1041250661Sdavidcs case 0x03: 1042250661Sdavidcs device_printf(ha->pci_dev, "Module Type 10GBase-SR\n"); 1043250661Sdavidcs break; 1044250661Sdavidcs 1045250661Sdavidcs case 0x04: 1046250661Sdavidcs device_printf(ha->pci_dev, 1047250661Sdavidcs "Module Type 10GE Passive Copper(Compliant)[%d m]\n", 1048250661Sdavidcs ha->hw.cable_length); 1049250661Sdavidcs break; 1050250661Sdavidcs 1051250661Sdavidcs case 0x05: 1052250661Sdavidcs device_printf(ha->pci_dev, "Module Type 10GE Active" 1053250661Sdavidcs " Limiting Copper(Compliant)[%d m]\n", 1054250661Sdavidcs ha->hw.cable_length); 1055250661Sdavidcs break; 1056250661Sdavidcs 1057250661Sdavidcs case 0x06: 1058250661Sdavidcs device_printf(ha->pci_dev, 1059250661Sdavidcs "Module Type 10GE Passive Copper" 1060250661Sdavidcs " (Legacy, Best Effort)[%d m]\n", 1061250661Sdavidcs ha->hw.cable_length); 1062250661Sdavidcs break; 1063250661Sdavidcs 1064250661Sdavidcs case 0x07: 1065250661Sdavidcs device_printf(ha->pci_dev, "Module Type 1000Base-SX\n"); 1066250661Sdavidcs break; 1067250661Sdavidcs 1068250661Sdavidcs case 0x08: 1069250661Sdavidcs device_printf(ha->pci_dev, "Module Type 1000Base-LX\n"); 1070250661Sdavidcs break; 1071250661Sdavidcs 1072250661Sdavidcs case 0x09: 1073250661Sdavidcs device_printf(ha->pci_dev, "Module Type 1000Base-CX\n"); 1074250661Sdavidcs break; 1075250661Sdavidcs 1076250661Sdavidcs case 0x0A: 1077250661Sdavidcs device_printf(ha->pci_dev, "Module Type 1000Base-T\n"); 1078250661Sdavidcs break; 1079250661Sdavidcs 1080250661Sdavidcs case 0x0B: 1081250661Sdavidcs device_printf(ha->pci_dev, "Module Type 1GE Passive Copper" 1082250661Sdavidcs "(Legacy, Best Effort)\n"); 1083250661Sdavidcs break; 1084250661Sdavidcs 1085250661Sdavidcs default: 1086250661Sdavidcs device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n", 1087250661Sdavidcs ha->hw.module_type); 1088250661Sdavidcs break; 1089250661Sdavidcs } 1090250661Sdavidcs 1091250661Sdavidcs if (ha->hw.link_faults == 1) 1092250661Sdavidcs device_printf(ha->pci_dev, "SFP Power Fault\n"); 1093250661Sdavidcs} 1094250661Sdavidcs 1095250661Sdavidcs/* 1096250661Sdavidcs * Name: ql_free_dma 1097250661Sdavidcs * Function: Frees the DMA'able memory allocated in ql_alloc_dma() 1098250661Sdavidcs */ 1099250661Sdavidcsvoid 1100250661Sdavidcsql_free_dma(qla_host_t *ha) 1101250661Sdavidcs{ 1102250661Sdavidcs uint32_t i; 1103250661Sdavidcs 1104250661Sdavidcs if (ha->hw.dma_buf.flags.sds_ring) { 1105250661Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; i++) { 1106250661Sdavidcs ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]); 1107250661Sdavidcs } 1108250661Sdavidcs ha->hw.dma_buf.flags.sds_ring = 0; 1109250661Sdavidcs } 1110250661Sdavidcs 1111250661Sdavidcs if (ha->hw.dma_buf.flags.rds_ring) { 1112250661Sdavidcs for (i = 0; i < ha->hw.num_rds_rings; i++) { 1113250661Sdavidcs ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]); 1114250661Sdavidcs } 1115250661Sdavidcs ha->hw.dma_buf.flags.rds_ring = 0; 1116250661Sdavidcs } 1117250661Sdavidcs 1118250661Sdavidcs if (ha->hw.dma_buf.flags.tx_ring) { 1119250661Sdavidcs ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring); 1120250661Sdavidcs ha->hw.dma_buf.flags.tx_ring = 0; 1121250661Sdavidcs } 1122305487Sdavidcs ql_minidump_free(ha); 1123250661Sdavidcs} 1124250661Sdavidcs 1125250661Sdavidcs/* 1126250661Sdavidcs * Name: ql_alloc_dma 1127250661Sdavidcs * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts. 1128250661Sdavidcs */ 1129250661Sdavidcsint 1130250661Sdavidcsql_alloc_dma(qla_host_t *ha) 1131250661Sdavidcs{ 1132250661Sdavidcs device_t dev; 1133250661Sdavidcs uint32_t i, j, size, tx_ring_size; 1134250661Sdavidcs qla_hw_t *hw; 1135250661Sdavidcs qla_hw_tx_cntxt_t *tx_cntxt; 1136250661Sdavidcs uint8_t *vaddr; 1137250661Sdavidcs bus_addr_t paddr; 1138250661Sdavidcs 1139250661Sdavidcs dev = ha->pci_dev; 1140250661Sdavidcs 1141250661Sdavidcs QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); 1142250661Sdavidcs 1143250661Sdavidcs hw = &ha->hw; 1144250661Sdavidcs /* 1145250661Sdavidcs * Allocate Transmit Ring 1146250661Sdavidcs */ 1147250661Sdavidcs tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS); 1148250661Sdavidcs size = (tx_ring_size * ha->hw.num_tx_rings); 1149250661Sdavidcs 1150250661Sdavidcs hw->dma_buf.tx_ring.alignment = 8; 1151250661Sdavidcs hw->dma_buf.tx_ring.size = size + PAGE_SIZE; 1152250661Sdavidcs 1153250661Sdavidcs if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) { 1154250661Sdavidcs device_printf(dev, "%s: tx ring alloc failed\n", __func__); 1155250661Sdavidcs goto ql_alloc_dma_exit; 1156250661Sdavidcs } 1157250661Sdavidcs 1158250661Sdavidcs vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b; 1159250661Sdavidcs paddr = hw->dma_buf.tx_ring.dma_addr; 1160250661Sdavidcs 1161250661Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 1162250661Sdavidcs tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1163250661Sdavidcs 1164250661Sdavidcs tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr; 1165250661Sdavidcs tx_cntxt->tx_ring_paddr = paddr; 1166250661Sdavidcs 1167250661Sdavidcs vaddr += tx_ring_size; 1168250661Sdavidcs paddr += tx_ring_size; 1169250661Sdavidcs } 1170250661Sdavidcs 1171250661Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 1172250661Sdavidcs tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1173250661Sdavidcs 1174250661Sdavidcs tx_cntxt->tx_cons = (uint32_t *)vaddr; 1175250661Sdavidcs tx_cntxt->tx_cons_paddr = paddr; 1176250661Sdavidcs 1177250661Sdavidcs vaddr += sizeof (uint32_t); 1178250661Sdavidcs paddr += sizeof (uint32_t); 1179250661Sdavidcs } 1180250661Sdavidcs 1181250661Sdavidcs ha->hw.dma_buf.flags.tx_ring = 1; 1182250661Sdavidcs 1183250661Sdavidcs QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n", 1184250661Sdavidcs __func__, (void *)(hw->dma_buf.tx_ring.dma_addr), 1185250661Sdavidcs hw->dma_buf.tx_ring.dma_b)); 1186250661Sdavidcs /* 1187250661Sdavidcs * Allocate Receive Descriptor Rings 1188250661Sdavidcs */ 1189250661Sdavidcs 1190250661Sdavidcs for (i = 0; i < hw->num_rds_rings; i++) { 1191250661Sdavidcs 1192250661Sdavidcs hw->dma_buf.rds_ring[i].alignment = 8; 1193250661Sdavidcs hw->dma_buf.rds_ring[i].size = 1194250661Sdavidcs (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS; 1195250661Sdavidcs 1196250661Sdavidcs if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) { 1197250661Sdavidcs device_printf(dev, "%s: rds ring[%d] alloc failed\n", 1198250661Sdavidcs __func__, i); 1199250661Sdavidcs 1200250661Sdavidcs for (j = 0; j < i; j++) 1201250661Sdavidcs ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]); 1202250661Sdavidcs 1203250661Sdavidcs goto ql_alloc_dma_exit; 1204250661Sdavidcs } 1205250661Sdavidcs QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n", 1206250661Sdavidcs __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr), 1207250661Sdavidcs hw->dma_buf.rds_ring[i].dma_b)); 1208250661Sdavidcs } 1209250661Sdavidcs 1210250661Sdavidcs hw->dma_buf.flags.rds_ring = 1; 1211250661Sdavidcs 1212250661Sdavidcs /* 1213250661Sdavidcs * Allocate Status Descriptor Rings 1214250661Sdavidcs */ 1215250661Sdavidcs 1216250661Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 1217250661Sdavidcs hw->dma_buf.sds_ring[i].alignment = 8; 1218250661Sdavidcs hw->dma_buf.sds_ring[i].size = 1219250661Sdavidcs (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS; 1220250661Sdavidcs 1221250661Sdavidcs if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) { 1222250661Sdavidcs device_printf(dev, "%s: sds ring alloc failed\n", 1223250661Sdavidcs __func__); 1224250661Sdavidcs 1225250661Sdavidcs for (j = 0; j < i; j++) 1226250661Sdavidcs ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]); 1227250661Sdavidcs 1228250661Sdavidcs goto ql_alloc_dma_exit; 1229250661Sdavidcs } 1230250661Sdavidcs QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n", 1231250661Sdavidcs __func__, i, 1232250661Sdavidcs (void *)(hw->dma_buf.sds_ring[i].dma_addr), 1233250661Sdavidcs hw->dma_buf.sds_ring[i].dma_b)); 1234250661Sdavidcs } 1235250661Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 1236250661Sdavidcs hw->sds[i].sds_ring_base = 1237250661Sdavidcs (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b; 1238250661Sdavidcs } 1239250661Sdavidcs 1240250661Sdavidcs hw->dma_buf.flags.sds_ring = 1; 1241250661Sdavidcs 1242250661Sdavidcs return 0; 1243250661Sdavidcs 1244250661Sdavidcsql_alloc_dma_exit: 1245250661Sdavidcs ql_free_dma(ha); 1246250661Sdavidcs return -1; 1247250661Sdavidcs} 1248250661Sdavidcs 1249250661Sdavidcs#define Q8_MBX_MSEC_DELAY 5000 1250250661Sdavidcs 1251250661Sdavidcsstatic int 1252250661Sdavidcsqla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 1253250661Sdavidcs uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause) 1254250661Sdavidcs{ 1255250661Sdavidcs uint32_t i; 1256250661Sdavidcs uint32_t data; 1257250661Sdavidcs int ret = 0; 1258250661Sdavidcs 1259250661Sdavidcs if (QL_ERR_INJECT(ha, INJCT_MBX_CMD_FAILURE)) { 1260250661Sdavidcs ret = -3; 1261250661Sdavidcs ha->qla_initiate_recovery = 1; 1262250661Sdavidcs goto exit_qla_mbx_cmd; 1263250661Sdavidcs } 1264250661Sdavidcs 1265250661Sdavidcs if (no_pause) 1266250661Sdavidcs i = 1000; 1267250661Sdavidcs else 1268250661Sdavidcs i = Q8_MBX_MSEC_DELAY; 1269250661Sdavidcs 1270250661Sdavidcs while (i) { 1271250661Sdavidcs data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL); 1272250661Sdavidcs if (data == 0) 1273250661Sdavidcs break; 1274250661Sdavidcs if (no_pause) { 1275250661Sdavidcs DELAY(1000); 1276250661Sdavidcs } else { 1277250661Sdavidcs qla_mdelay(__func__, 1); 1278250661Sdavidcs } 1279250661Sdavidcs i--; 1280250661Sdavidcs } 1281250661Sdavidcs 1282250661Sdavidcs if (i == 0) { 1283250661Sdavidcs device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n", 1284250661Sdavidcs __func__, data); 1285250661Sdavidcs ret = -1; 1286250661Sdavidcs ha->qla_initiate_recovery = 1; 1287250661Sdavidcs goto exit_qla_mbx_cmd; 1288250661Sdavidcs } 1289250661Sdavidcs 1290250661Sdavidcs for (i = 0; i < n_hmbox; i++) { 1291250661Sdavidcs WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); 1292250661Sdavidcs h_mbox++; 1293250661Sdavidcs } 1294250661Sdavidcs 1295250661Sdavidcs WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); 1296250661Sdavidcs 1297250661Sdavidcs 1298250661Sdavidcs i = Q8_MBX_MSEC_DELAY; 1299250661Sdavidcs while (i) { 1300250661Sdavidcs data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 1301250661Sdavidcs 1302250661Sdavidcs if ((data & 0x3) == 1) { 1303250661Sdavidcs data = READ_REG32(ha, Q8_FW_MBOX0); 1304250661Sdavidcs if ((data & 0xF000) != 0x8000) 1305250661Sdavidcs break; 1306250661Sdavidcs } 1307250661Sdavidcs if (no_pause) { 1308250661Sdavidcs DELAY(1000); 1309250661Sdavidcs } else { 1310250661Sdavidcs qla_mdelay(__func__, 1); 1311250661Sdavidcs } 1312250661Sdavidcs i--; 1313250661Sdavidcs } 1314250661Sdavidcs if (i == 0) { 1315250661Sdavidcs device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n", 1316250661Sdavidcs __func__, data); 1317250661Sdavidcs ret = -2; 1318250661Sdavidcs ha->qla_initiate_recovery = 1; 1319250661Sdavidcs goto exit_qla_mbx_cmd; 1320250661Sdavidcs } 1321250661Sdavidcs 1322250661Sdavidcs for (i = 0; i < n_fwmbox; i++) { 1323250661Sdavidcs *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2))); 1324250661Sdavidcs } 1325250661Sdavidcs 1326250661Sdavidcs WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 1327250661Sdavidcs WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 1328250661Sdavidcs 1329250661Sdavidcsexit_qla_mbx_cmd: 1330250661Sdavidcs return (ret); 1331250661Sdavidcs} 1332250661Sdavidcs 1333284741Sdavidcsint 1334284741Sdavidcsqla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb, 1335284741Sdavidcs uint32_t *num_rcvq) 1336250661Sdavidcs{ 1337250661Sdavidcs uint32_t *mbox, err; 1338250661Sdavidcs device_t dev = ha->pci_dev; 1339250661Sdavidcs 1340250661Sdavidcs bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX)); 1341250661Sdavidcs 1342250661Sdavidcs mbox = ha->hw.mbox; 1343250661Sdavidcs 1344250661Sdavidcs mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29); 1345250661Sdavidcs 1346250661Sdavidcs if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) { 1347250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1348250661Sdavidcs return (-1); 1349250661Sdavidcs } 1350250661Sdavidcs err = mbox[0] >> 25; 1351250661Sdavidcs 1352284741Sdavidcs if (supports_9kb != NULL) { 1353284741Sdavidcs if (mbox[16] & 0x80) /* bit 7 of mbox 16 */ 1354284741Sdavidcs *supports_9kb = 1; 1355284741Sdavidcs else 1356284741Sdavidcs *supports_9kb = 0; 1357284741Sdavidcs } 1358284741Sdavidcs 1359284741Sdavidcs if (num_rcvq != NULL) 1360284741Sdavidcs *num_rcvq = ((mbox[6] >> 16) & 0xFFFF); 1361284741Sdavidcs 1362250661Sdavidcs if ((err != 1) && (err != 0)) { 1363250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1364250661Sdavidcs return (-1); 1365250661Sdavidcs } 1366250661Sdavidcs return 0; 1367250661Sdavidcs} 1368250661Sdavidcs 1369250661Sdavidcsstatic int 1370284741Sdavidcsqla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs, 1371284741Sdavidcs uint32_t create) 1372250661Sdavidcs{ 1373250661Sdavidcs uint32_t i, err; 1374250661Sdavidcs device_t dev = ha->pci_dev; 1375250661Sdavidcs q80_config_intr_t *c_intr; 1376250661Sdavidcs q80_config_intr_rsp_t *c_intr_rsp; 1377250661Sdavidcs 1378250661Sdavidcs c_intr = (q80_config_intr_t *)ha->hw.mbox; 1379250661Sdavidcs bzero(c_intr, (sizeof (q80_config_intr_t))); 1380250661Sdavidcs 1381250661Sdavidcs c_intr->opcode = Q8_MBX_CONFIG_INTR; 1382250661Sdavidcs 1383250661Sdavidcs c_intr->count_version = (sizeof (q80_config_intr_t) >> 2); 1384250661Sdavidcs c_intr->count_version |= Q8_MBX_CMD_VERSION; 1385250661Sdavidcs 1386250661Sdavidcs c_intr->nentries = num_intrs; 1387250661Sdavidcs 1388250661Sdavidcs for (i = 0; i < num_intrs; i++) { 1389250661Sdavidcs if (create) { 1390250661Sdavidcs c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE; 1391284741Sdavidcs c_intr->intr[i].msix_index = start_idx + 1 + i; 1392250661Sdavidcs } else { 1393250661Sdavidcs c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE; 1394284741Sdavidcs c_intr->intr[i].msix_index = 1395284741Sdavidcs ha->hw.intr_id[(start_idx + i)]; 1396250661Sdavidcs } 1397250661Sdavidcs 1398250661Sdavidcs c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X; 1399250661Sdavidcs } 1400250661Sdavidcs 1401250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)c_intr, 1402250661Sdavidcs (sizeof (q80_config_intr_t) >> 2), 1403250661Sdavidcs ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) { 1404250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1405250661Sdavidcs return (-1); 1406250661Sdavidcs } 1407250661Sdavidcs 1408250661Sdavidcs c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox; 1409250661Sdavidcs 1410250661Sdavidcs err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status); 1411250661Sdavidcs 1412250661Sdavidcs if (err) { 1413250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x, %d]\n", __func__, err, 1414250661Sdavidcs c_intr_rsp->nentries); 1415250661Sdavidcs 1416250661Sdavidcs for (i = 0; i < c_intr_rsp->nentries; i++) { 1417250661Sdavidcs device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n", 1418250661Sdavidcs __func__, i, 1419250661Sdavidcs c_intr_rsp->intr[i].status, 1420250661Sdavidcs c_intr_rsp->intr[i].intr_id, 1421250661Sdavidcs c_intr_rsp->intr[i].intr_src); 1422250661Sdavidcs } 1423250661Sdavidcs 1424250661Sdavidcs return (-1); 1425250661Sdavidcs } 1426250661Sdavidcs 1427250661Sdavidcs for (i = 0; ((i < num_intrs) && create); i++) { 1428250661Sdavidcs if (!c_intr_rsp->intr[i].status) { 1429284741Sdavidcs ha->hw.intr_id[(start_idx + i)] = 1430284741Sdavidcs c_intr_rsp->intr[i].intr_id; 1431284741Sdavidcs ha->hw.intr_src[(start_idx + i)] = 1432284741Sdavidcs c_intr_rsp->intr[i].intr_src; 1433250661Sdavidcs } 1434250661Sdavidcs } 1435250661Sdavidcs 1436250661Sdavidcs return (0); 1437250661Sdavidcs} 1438250661Sdavidcs 1439250661Sdavidcs/* 1440250661Sdavidcs * Name: qla_config_rss 1441250661Sdavidcs * Function: Configure RSS for the context/interface. 1442250661Sdavidcs */ 1443250661Sdavidcsstatic const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL, 1444250661Sdavidcs 0x8030f20c77cb2da3ULL, 1445250661Sdavidcs 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 1446250661Sdavidcs 0x255b0ec26d5a56daULL }; 1447250661Sdavidcs 1448250661Sdavidcsstatic int 1449250661Sdavidcsqla_config_rss(qla_host_t *ha, uint16_t cntxt_id) 1450250661Sdavidcs{ 1451250661Sdavidcs q80_config_rss_t *c_rss; 1452250661Sdavidcs q80_config_rss_rsp_t *c_rss_rsp; 1453250661Sdavidcs uint32_t err, i; 1454250661Sdavidcs device_t dev = ha->pci_dev; 1455250661Sdavidcs 1456250661Sdavidcs c_rss = (q80_config_rss_t *)ha->hw.mbox; 1457250661Sdavidcs bzero(c_rss, (sizeof (q80_config_rss_t))); 1458250661Sdavidcs 1459250661Sdavidcs c_rss->opcode = Q8_MBX_CONFIG_RSS; 1460250661Sdavidcs 1461250661Sdavidcs c_rss->count_version = (sizeof (q80_config_rss_t) >> 2); 1462250661Sdavidcs c_rss->count_version |= Q8_MBX_CMD_VERSION; 1463250661Sdavidcs 1464250661Sdavidcs c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP | 1465250661Sdavidcs Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP); 1466284741Sdavidcs //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP | 1467284741Sdavidcs // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP); 1468250661Sdavidcs 1469250661Sdavidcs c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS; 1470250661Sdavidcs c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE; 1471250661Sdavidcs 1472250661Sdavidcs c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK; 1473250661Sdavidcs 1474250661Sdavidcs c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID; 1475250661Sdavidcs c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS; 1476250661Sdavidcs 1477250661Sdavidcs c_rss->cntxt_id = cntxt_id; 1478250661Sdavidcs 1479250661Sdavidcs for (i = 0; i < 5; i++) { 1480250661Sdavidcs c_rss->rss_key[i] = rss_key[i]; 1481250661Sdavidcs } 1482250661Sdavidcs 1483250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)c_rss, 1484250661Sdavidcs (sizeof (q80_config_rss_t) >> 2), 1485250661Sdavidcs ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) { 1486250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1487250661Sdavidcs return (-1); 1488250661Sdavidcs } 1489250661Sdavidcs c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox; 1490250661Sdavidcs 1491250661Sdavidcs err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status); 1492250661Sdavidcs 1493250661Sdavidcs if (err) { 1494250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1495250661Sdavidcs return (-1); 1496250661Sdavidcs } 1497250661Sdavidcs return 0; 1498250661Sdavidcs} 1499250661Sdavidcs 1500250661Sdavidcsstatic int 1501250661Sdavidcsqla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count, 1502250661Sdavidcs uint16_t cntxt_id, uint8_t *ind_table) 1503250661Sdavidcs{ 1504250661Sdavidcs q80_config_rss_ind_table_t *c_rss_ind; 1505250661Sdavidcs q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp; 1506250661Sdavidcs uint32_t err; 1507250661Sdavidcs device_t dev = ha->pci_dev; 1508250661Sdavidcs 1509250661Sdavidcs if ((count > Q8_RSS_IND_TBL_SIZE) || 1510250661Sdavidcs ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) { 1511250661Sdavidcs device_printf(dev, "%s: illegal count [%d, %d]\n", __func__, 1512250661Sdavidcs start_idx, count); 1513250661Sdavidcs return (-1); 1514250661Sdavidcs } 1515250661Sdavidcs 1516250661Sdavidcs c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox; 1517250661Sdavidcs bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t)); 1518250661Sdavidcs 1519250661Sdavidcs c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE; 1520250661Sdavidcs c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2); 1521250661Sdavidcs c_rss_ind->count_version |= Q8_MBX_CMD_VERSION; 1522250661Sdavidcs 1523250661Sdavidcs c_rss_ind->start_idx = start_idx; 1524250661Sdavidcs c_rss_ind->end_idx = start_idx + count - 1; 1525250661Sdavidcs c_rss_ind->cntxt_id = cntxt_id; 1526250661Sdavidcs bcopy(ind_table, c_rss_ind->ind_table, count); 1527250661Sdavidcs 1528250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind, 1529250661Sdavidcs (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox, 1530250661Sdavidcs (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) { 1531250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1532250661Sdavidcs return (-1); 1533250661Sdavidcs } 1534250661Sdavidcs 1535250661Sdavidcs c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox; 1536250661Sdavidcs err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status); 1537250661Sdavidcs 1538250661Sdavidcs if (err) { 1539250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1540250661Sdavidcs return (-1); 1541250661Sdavidcs } 1542250661Sdavidcs return 0; 1543250661Sdavidcs} 1544250661Sdavidcs 1545250661Sdavidcs/* 1546250661Sdavidcs * Name: qla_config_intr_coalesce 1547250661Sdavidcs * Function: Configure Interrupt Coalescing. 1548250661Sdavidcs */ 1549250661Sdavidcsstatic int 1550284741Sdavidcsqla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable, 1551284741Sdavidcs int rcv) 1552250661Sdavidcs{ 1553250661Sdavidcs q80_config_intr_coalesc_t *intrc; 1554250661Sdavidcs q80_config_intr_coalesc_rsp_t *intrc_rsp; 1555250661Sdavidcs uint32_t err, i; 1556250661Sdavidcs device_t dev = ha->pci_dev; 1557250661Sdavidcs 1558250661Sdavidcs intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox; 1559250661Sdavidcs bzero(intrc, (sizeof (q80_config_intr_coalesc_t))); 1560250661Sdavidcs 1561250661Sdavidcs intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE; 1562250661Sdavidcs intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2); 1563250661Sdavidcs intrc->count_version |= Q8_MBX_CMD_VERSION; 1564250661Sdavidcs 1565284741Sdavidcs if (rcv) { 1566284741Sdavidcs intrc->flags = Q8_MBX_INTRC_FLAGS_RCV; 1567284741Sdavidcs intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF; 1568284741Sdavidcs intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF; 1569284741Sdavidcs } else { 1570284741Sdavidcs intrc->flags = Q8_MBX_INTRC_FLAGS_XMT; 1571284741Sdavidcs intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF; 1572284741Sdavidcs intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF; 1573284741Sdavidcs } 1574284741Sdavidcs 1575250661Sdavidcs intrc->cntxt_id = cntxt_id; 1576250661Sdavidcs 1577250661Sdavidcs if (tenable) { 1578250661Sdavidcs intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC; 1579250661Sdavidcs intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC; 1580250661Sdavidcs 1581250661Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; i++) { 1582250661Sdavidcs intrc->sds_ring_mask |= (1 << i); 1583250661Sdavidcs } 1584250661Sdavidcs intrc->ms_timeout = 1000; 1585250661Sdavidcs } 1586250661Sdavidcs 1587250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)intrc, 1588250661Sdavidcs (sizeof (q80_config_intr_coalesc_t) >> 2), 1589250661Sdavidcs ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) { 1590250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1591250661Sdavidcs return (-1); 1592250661Sdavidcs } 1593250661Sdavidcs intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox; 1594250661Sdavidcs 1595250661Sdavidcs err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status); 1596250661Sdavidcs 1597250661Sdavidcs if (err) { 1598250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1599250661Sdavidcs return (-1); 1600250661Sdavidcs } 1601250661Sdavidcs 1602250661Sdavidcs return 0; 1603250661Sdavidcs} 1604250661Sdavidcs 1605250661Sdavidcs 1606250661Sdavidcs/* 1607250661Sdavidcs * Name: qla_config_mac_addr 1608250661Sdavidcs * Function: binds a MAC address to the context/interface. 1609250661Sdavidcs * Can be unicast, multicast or broadcast. 1610250661Sdavidcs */ 1611250661Sdavidcsstatic int 1612307524Sdavidcsqla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac, 1613307524Sdavidcs uint32_t num_mac) 1614250661Sdavidcs{ 1615250661Sdavidcs q80_config_mac_addr_t *cmac; 1616250661Sdavidcs q80_config_mac_addr_rsp_t *cmac_rsp; 1617250661Sdavidcs uint32_t err; 1618250661Sdavidcs device_t dev = ha->pci_dev; 1619307524Sdavidcs int i; 1620307524Sdavidcs uint8_t *mac_cpy = mac_addr; 1621250661Sdavidcs 1622307524Sdavidcs if (num_mac > Q8_MAX_MAC_ADDRS) { 1623307524Sdavidcs device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n", 1624307524Sdavidcs __func__, (add_mac ? "Add" : "Del"), num_mac); 1625307524Sdavidcs return (-1); 1626307524Sdavidcs } 1627307524Sdavidcs 1628250661Sdavidcs cmac = (q80_config_mac_addr_t *)ha->hw.mbox; 1629250661Sdavidcs bzero(cmac, (sizeof (q80_config_mac_addr_t))); 1630250661Sdavidcs 1631250661Sdavidcs cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR; 1632250661Sdavidcs cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2; 1633250661Sdavidcs cmac->count_version |= Q8_MBX_CMD_VERSION; 1634250661Sdavidcs 1635250661Sdavidcs if (add_mac) 1636250661Sdavidcs cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR; 1637250661Sdavidcs else 1638250661Sdavidcs cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR; 1639250661Sdavidcs 1640250661Sdavidcs cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS; 1641250661Sdavidcs 1642307524Sdavidcs cmac->nmac_entries = num_mac; 1643250661Sdavidcs cmac->cntxt_id = ha->hw.rcv_cntxt_id; 1644250661Sdavidcs 1645307524Sdavidcs for (i = 0; i < num_mac; i++) { 1646307524Sdavidcs bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN); 1647307524Sdavidcs mac_addr = mac_addr + ETHER_ADDR_LEN; 1648307524Sdavidcs } 1649307524Sdavidcs 1650250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)cmac, 1651250661Sdavidcs (sizeof (q80_config_mac_addr_t) >> 2), 1652250661Sdavidcs ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) { 1653250661Sdavidcs device_printf(dev, "%s: %s failed0\n", __func__, 1654250661Sdavidcs (add_mac ? "Add" : "Del")); 1655250661Sdavidcs return (-1); 1656250661Sdavidcs } 1657250661Sdavidcs cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox; 1658250661Sdavidcs 1659250661Sdavidcs err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status); 1660250661Sdavidcs 1661250661Sdavidcs if (err) { 1662307524Sdavidcs device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__, 1663307524Sdavidcs (add_mac ? "Add" : "Del"), err); 1664307524Sdavidcs for (i = 0; i < num_mac; i++) { 1665307524Sdavidcs device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1666307524Sdavidcs __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2], 1667307524Sdavidcs mac_cpy[3], mac_cpy[4], mac_cpy[5]); 1668307524Sdavidcs mac_cpy += ETHER_ADDR_LEN; 1669307524Sdavidcs } 1670250661Sdavidcs return (-1); 1671250661Sdavidcs } 1672250661Sdavidcs 1673250661Sdavidcs return 0; 1674250661Sdavidcs} 1675250661Sdavidcs 1676250661Sdavidcs 1677250661Sdavidcs/* 1678250661Sdavidcs * Name: qla_set_mac_rcv_mode 1679305487Sdavidcs * Function: Enable/Disable AllMulticast and Promiscous Modes. 1680250661Sdavidcs */ 1681250661Sdavidcsstatic int 1682250661Sdavidcsqla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode) 1683250661Sdavidcs{ 1684250661Sdavidcs q80_config_mac_rcv_mode_t *rcv_mode; 1685250661Sdavidcs uint32_t err; 1686250661Sdavidcs q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp; 1687250661Sdavidcs device_t dev = ha->pci_dev; 1688250661Sdavidcs 1689250661Sdavidcs rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox; 1690250661Sdavidcs bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t))); 1691250661Sdavidcs 1692250661Sdavidcs rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE; 1693250661Sdavidcs rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2; 1694250661Sdavidcs rcv_mode->count_version |= Q8_MBX_CMD_VERSION; 1695250661Sdavidcs 1696250661Sdavidcs rcv_mode->mode = mode; 1697250661Sdavidcs 1698250661Sdavidcs rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id; 1699250661Sdavidcs 1700250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode, 1701250661Sdavidcs (sizeof (q80_config_mac_rcv_mode_t) >> 2), 1702250661Sdavidcs ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) { 1703250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 1704250661Sdavidcs return (-1); 1705250661Sdavidcs } 1706250661Sdavidcs rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox; 1707250661Sdavidcs 1708250661Sdavidcs err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status); 1709250661Sdavidcs 1710250661Sdavidcs if (err) { 1711250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1712250661Sdavidcs return (-1); 1713250661Sdavidcs } 1714250661Sdavidcs 1715250661Sdavidcs return 0; 1716250661Sdavidcs} 1717250661Sdavidcs 1718250661Sdavidcsint 1719250661Sdavidcsql_set_promisc(qla_host_t *ha) 1720250661Sdavidcs{ 1721250661Sdavidcs int ret; 1722250661Sdavidcs 1723250661Sdavidcs ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1724250661Sdavidcs ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1725250661Sdavidcs return (ret); 1726250661Sdavidcs} 1727250661Sdavidcs 1728284741Sdavidcsvoid 1729284741Sdavidcsqla_reset_promisc(qla_host_t *ha) 1730284741Sdavidcs{ 1731284741Sdavidcs ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1732284741Sdavidcs (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1733284741Sdavidcs} 1734284741Sdavidcs 1735250661Sdavidcsint 1736250661Sdavidcsql_set_allmulti(qla_host_t *ha) 1737250661Sdavidcs{ 1738250661Sdavidcs int ret; 1739250661Sdavidcs 1740250661Sdavidcs ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE; 1741250661Sdavidcs ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1742250661Sdavidcs return (ret); 1743250661Sdavidcs} 1744250661Sdavidcs 1745284741Sdavidcsvoid 1746284741Sdavidcsqla_reset_allmulti(qla_host_t *ha) 1747284741Sdavidcs{ 1748284741Sdavidcs ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE; 1749284741Sdavidcs (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1750284741Sdavidcs} 1751250661Sdavidcs 1752250661Sdavidcs/* 1753250661Sdavidcs * Name: ql_set_max_mtu 1754250661Sdavidcs * Function: 1755250661Sdavidcs * Sets the maximum transfer unit size for the specified rcv context. 1756250661Sdavidcs */ 1757250661Sdavidcsint 1758250661Sdavidcsql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id) 1759250661Sdavidcs{ 1760250661Sdavidcs device_t dev; 1761250661Sdavidcs q80_set_max_mtu_t *max_mtu; 1762250661Sdavidcs q80_set_max_mtu_rsp_t *max_mtu_rsp; 1763250661Sdavidcs uint32_t err; 1764250661Sdavidcs 1765250661Sdavidcs dev = ha->pci_dev; 1766250661Sdavidcs 1767250661Sdavidcs max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox; 1768250661Sdavidcs bzero(max_mtu, (sizeof (q80_set_max_mtu_t))); 1769250661Sdavidcs 1770250661Sdavidcs max_mtu->opcode = Q8_MBX_SET_MAX_MTU; 1771250661Sdavidcs max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2); 1772250661Sdavidcs max_mtu->count_version |= Q8_MBX_CMD_VERSION; 1773250661Sdavidcs 1774250661Sdavidcs max_mtu->cntxt_id = cntxt_id; 1775250661Sdavidcs max_mtu->mtu = mtu; 1776250661Sdavidcs 1777250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)max_mtu, 1778250661Sdavidcs (sizeof (q80_set_max_mtu_t) >> 2), 1779250661Sdavidcs ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) { 1780250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1781250661Sdavidcs return -1; 1782250661Sdavidcs } 1783250661Sdavidcs 1784250661Sdavidcs max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox; 1785250661Sdavidcs 1786250661Sdavidcs err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status); 1787250661Sdavidcs 1788250661Sdavidcs if (err) { 1789250661Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1790250661Sdavidcs } 1791250661Sdavidcs 1792250661Sdavidcs return 0; 1793250661Sdavidcs} 1794250661Sdavidcs 1795250661Sdavidcsstatic int 1796250661Sdavidcsqla_link_event_req(qla_host_t *ha, uint16_t cntxt_id) 1797250661Sdavidcs{ 1798250661Sdavidcs device_t dev; 1799250661Sdavidcs q80_link_event_t *lnk; 1800250661Sdavidcs q80_link_event_rsp_t *lnk_rsp; 1801250661Sdavidcs uint32_t err; 1802250661Sdavidcs 1803250661Sdavidcs dev = ha->pci_dev; 1804250661Sdavidcs 1805250661Sdavidcs lnk = (q80_link_event_t *)ha->hw.mbox; 1806250661Sdavidcs bzero(lnk, (sizeof (q80_link_event_t))); 1807250661Sdavidcs 1808250661Sdavidcs lnk->opcode = Q8_MBX_LINK_EVENT_REQ; 1809250661Sdavidcs lnk->count_version = (sizeof (q80_link_event_t) >> 2); 1810250661Sdavidcs lnk->count_version |= Q8_MBX_CMD_VERSION; 1811250661Sdavidcs 1812250661Sdavidcs lnk->cntxt_id = cntxt_id; 1813250661Sdavidcs lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC; 1814250661Sdavidcs 1815250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2), 1816250661Sdavidcs ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) { 1817250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1818250661Sdavidcs return -1; 1819250661Sdavidcs } 1820250661Sdavidcs 1821250661Sdavidcs lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox; 1822250661Sdavidcs 1823250661Sdavidcs err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status); 1824250661Sdavidcs 1825250661Sdavidcs if (err) { 1826250661Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1827250661Sdavidcs } 1828250661Sdavidcs 1829250661Sdavidcs return 0; 1830250661Sdavidcs} 1831250661Sdavidcs 1832250661Sdavidcsstatic int 1833250661Sdavidcsqla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id) 1834250661Sdavidcs{ 1835250661Sdavidcs device_t dev; 1836250661Sdavidcs q80_config_fw_lro_t *fw_lro; 1837250661Sdavidcs q80_config_fw_lro_rsp_t *fw_lro_rsp; 1838250661Sdavidcs uint32_t err; 1839250661Sdavidcs 1840250661Sdavidcs dev = ha->pci_dev; 1841250661Sdavidcs 1842250661Sdavidcs fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox; 1843250661Sdavidcs bzero(fw_lro, sizeof(q80_config_fw_lro_t)); 1844250661Sdavidcs 1845250661Sdavidcs fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO; 1846250661Sdavidcs fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2); 1847250661Sdavidcs fw_lro->count_version |= Q8_MBX_CMD_VERSION; 1848250661Sdavidcs 1849250661Sdavidcs fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK; 1850284741Sdavidcs fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK; 1851250661Sdavidcs 1852250661Sdavidcs fw_lro->cntxt_id = cntxt_id; 1853250661Sdavidcs 1854250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)fw_lro, 1855250661Sdavidcs (sizeof (q80_config_fw_lro_t) >> 2), 1856250661Sdavidcs ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) { 1857250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1858250661Sdavidcs return -1; 1859250661Sdavidcs } 1860250661Sdavidcs 1861250661Sdavidcs fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox; 1862250661Sdavidcs 1863250661Sdavidcs err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status); 1864250661Sdavidcs 1865250661Sdavidcs if (err) { 1866250661Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1867250661Sdavidcs } 1868250661Sdavidcs 1869250661Sdavidcs return 0; 1870250661Sdavidcs} 1871250661Sdavidcs 1872305488Sdavidcsstatic int 1873305488Sdavidcsqla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode) 1874305488Sdavidcs{ 1875305488Sdavidcs device_t dev; 1876305488Sdavidcs q80_hw_config_t *hw_config; 1877305488Sdavidcs q80_hw_config_rsp_t *hw_config_rsp; 1878305488Sdavidcs uint32_t err; 1879305488Sdavidcs 1880305488Sdavidcs dev = ha->pci_dev; 1881305488Sdavidcs 1882305488Sdavidcs hw_config = (q80_hw_config_t *)ha->hw.mbox; 1883305488Sdavidcs bzero(hw_config, sizeof (q80_hw_config_t)); 1884305488Sdavidcs 1885305488Sdavidcs hw_config->opcode = Q8_MBX_HW_CONFIG; 1886305488Sdavidcs hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT; 1887305488Sdavidcs hw_config->count_version |= Q8_MBX_CMD_VERSION; 1888305488Sdavidcs 1889305488Sdavidcs hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE; 1890305488Sdavidcs 1891305488Sdavidcs hw_config->u.set_cam_search_mode.mode = search_mode; 1892305488Sdavidcs 1893305488Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 1894305488Sdavidcs (sizeof (q80_hw_config_t) >> 2), 1895305488Sdavidcs ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 1896305488Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1897305488Sdavidcs return -1; 1898305488Sdavidcs } 1899305488Sdavidcs hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 1900305488Sdavidcs 1901305488Sdavidcs err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 1902305488Sdavidcs 1903305488Sdavidcs if (err) { 1904305488Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1905305488Sdavidcs } 1906305488Sdavidcs 1907305488Sdavidcs return 0; 1908305488Sdavidcs} 1909305488Sdavidcs 1910305488Sdavidcsstatic int 1911305488Sdavidcsqla_get_cam_search_mode(qla_host_t *ha) 1912305488Sdavidcs{ 1913305488Sdavidcs device_t dev; 1914305488Sdavidcs q80_hw_config_t *hw_config; 1915305488Sdavidcs q80_hw_config_rsp_t *hw_config_rsp; 1916305488Sdavidcs uint32_t err; 1917305488Sdavidcs 1918305488Sdavidcs dev = ha->pci_dev; 1919305488Sdavidcs 1920305488Sdavidcs hw_config = (q80_hw_config_t *)ha->hw.mbox; 1921305488Sdavidcs bzero(hw_config, sizeof (q80_hw_config_t)); 1922305488Sdavidcs 1923305488Sdavidcs hw_config->opcode = Q8_MBX_HW_CONFIG; 1924305488Sdavidcs hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT; 1925305488Sdavidcs hw_config->count_version |= Q8_MBX_CMD_VERSION; 1926305488Sdavidcs 1927305488Sdavidcs hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE; 1928305488Sdavidcs 1929305488Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 1930305488Sdavidcs (sizeof (q80_hw_config_t) >> 2), 1931305488Sdavidcs ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 1932305488Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1933305488Sdavidcs return -1; 1934305488Sdavidcs } 1935305488Sdavidcs hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 1936305488Sdavidcs 1937305488Sdavidcs err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 1938305488Sdavidcs 1939305488Sdavidcs if (err) { 1940305488Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1941305488Sdavidcs } else { 1942305488Sdavidcs device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__, 1943305488Sdavidcs hw_config_rsp->u.get_cam_search_mode.mode); 1944305488Sdavidcs } 1945305488Sdavidcs 1946305488Sdavidcs return 0; 1947305488Sdavidcs} 1948305488Sdavidcs 1949250661Sdavidcsstatic int 1950284741Sdavidcsqla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size) 1951250661Sdavidcs{ 1952250661Sdavidcs device_t dev; 1953250661Sdavidcs q80_get_stats_t *stat; 1954250661Sdavidcs q80_get_stats_rsp_t *stat_rsp; 1955250661Sdavidcs uint32_t err; 1956250661Sdavidcs 1957250661Sdavidcs dev = ha->pci_dev; 1958250661Sdavidcs 1959250661Sdavidcs stat = (q80_get_stats_t *)ha->hw.mbox; 1960250661Sdavidcs bzero(stat, (sizeof (q80_get_stats_t))); 1961250661Sdavidcs 1962250661Sdavidcs stat->opcode = Q8_MBX_GET_STATS; 1963250661Sdavidcs stat->count_version = 2; 1964250661Sdavidcs stat->count_version |= Q8_MBX_CMD_VERSION; 1965250661Sdavidcs 1966250661Sdavidcs stat->cmd = cmd; 1967250661Sdavidcs 1968250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)stat, 2, 1969284741Sdavidcs ha->hw.mbox, (rsp_size >> 2), 0)) { 1970250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 1971250661Sdavidcs return -1; 1972250661Sdavidcs } 1973250661Sdavidcs 1974250661Sdavidcs stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 1975250661Sdavidcs 1976250661Sdavidcs err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status); 1977250661Sdavidcs 1978250661Sdavidcs if (err) { 1979250661Sdavidcs return -1; 1980250661Sdavidcs } 1981250661Sdavidcs 1982250661Sdavidcs return 0; 1983250661Sdavidcs} 1984250661Sdavidcs 1985250661Sdavidcsvoid 1986250661Sdavidcsql_get_stats(qla_host_t *ha) 1987250661Sdavidcs{ 1988250661Sdavidcs q80_get_stats_rsp_t *stat_rsp; 1989250661Sdavidcs q80_mac_stats_t *mstat; 1990250661Sdavidcs q80_xmt_stats_t *xstat; 1991250661Sdavidcs q80_rcv_stats_t *rstat; 1992250661Sdavidcs uint32_t cmd; 1993284741Sdavidcs int i; 1994322972Sdavidcs struct ifnet *ifp = ha->ifp; 1995250661Sdavidcs 1996322972Sdavidcs if (ifp == NULL) 1997322972Sdavidcs return; 1998322972Sdavidcs 1999322972Sdavidcs if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) != 0) { 2000322972Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 2001322972Sdavidcs return; 2002322972Sdavidcs } 2003322972Sdavidcs 2004322972Sdavidcs if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2005322972Sdavidcs QLA_UNLOCK(ha, __func__); 2006322972Sdavidcs return; 2007322972Sdavidcs } 2008322972Sdavidcs 2009250661Sdavidcs stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 2010250661Sdavidcs /* 2011250661Sdavidcs * Get MAC Statistics 2012250661Sdavidcs */ 2013250661Sdavidcs cmd = Q8_GET_STATS_CMD_TYPE_MAC; 2014284741Sdavidcs// cmd |= Q8_GET_STATS_CMD_CLEAR; 2015250661Sdavidcs 2016250661Sdavidcs cmd |= ((ha->pci_func & 0x1) << 16); 2017250661Sdavidcs 2018322972Sdavidcs if (ha->qla_watchdog_pause) 2019322972Sdavidcs goto ql_get_stats_exit; 2020322972Sdavidcs 2021284741Sdavidcs if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2022250661Sdavidcs mstat = (q80_mac_stats_t *)&stat_rsp->u.mac; 2023322972Sdavidcs bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t)); 2024250661Sdavidcs } else { 2025250661Sdavidcs device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n", 2026250661Sdavidcs __func__, ha->hw.mbox[0]); 2027250661Sdavidcs } 2028250661Sdavidcs /* 2029250661Sdavidcs * Get RCV Statistics 2030250661Sdavidcs */ 2031250661Sdavidcs cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT; 2032284741Sdavidcs// cmd |= Q8_GET_STATS_CMD_CLEAR; 2033250661Sdavidcs cmd |= (ha->hw.rcv_cntxt_id << 16); 2034250661Sdavidcs 2035322972Sdavidcs if (ha->qla_watchdog_pause) 2036322972Sdavidcs goto ql_get_stats_exit; 2037322972Sdavidcs 2038284741Sdavidcs if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2039250661Sdavidcs rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv; 2040322972Sdavidcs bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t)); 2041250661Sdavidcs } else { 2042250661Sdavidcs device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n", 2043250661Sdavidcs __func__, ha->hw.mbox[0]); 2044250661Sdavidcs } 2045322972Sdavidcs 2046322972Sdavidcs if (ha->qla_watchdog_pause) 2047322972Sdavidcs goto ql_get_stats_exit; 2048250661Sdavidcs /* 2049250661Sdavidcs * Get XMT Statistics 2050250661Sdavidcs */ 2051322972Sdavidcs for (i = 0 ; ((i < ha->hw.num_tx_rings) && (!ha->qla_watchdog_pause)); 2052322972Sdavidcs i++) { 2053284741Sdavidcs cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT; 2054284741Sdavidcs// cmd |= Q8_GET_STATS_CMD_CLEAR; 2055284741Sdavidcs cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16); 2056250661Sdavidcs 2057284741Sdavidcs if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t)) 2058284741Sdavidcs == 0) { 2059284741Sdavidcs xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt; 2060322972Sdavidcs bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t)); 2061284741Sdavidcs } else { 2062284741Sdavidcs device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n", 2063284741Sdavidcs __func__, ha->hw.mbox[0]); 2064284741Sdavidcs } 2065284741Sdavidcs } 2066250661Sdavidcs 2067322972Sdavidcsql_get_stats_exit: 2068322972Sdavidcs QLA_UNLOCK(ha, __func__); 2069284741Sdavidcs 2070284741Sdavidcs return; 2071250661Sdavidcs} 2072250661Sdavidcs 2073250661Sdavidcs/* 2074250661Sdavidcs * Name: qla_tx_tso 2075250661Sdavidcs * Function: Checks if the packet to be transmitted is a candidate for 2076250661Sdavidcs * Large TCP Segment Offload. If yes, the appropriate fields in the Tx 2077250661Sdavidcs * Ring Structure are plugged in. 2078250661Sdavidcs */ 2079250661Sdavidcsstatic int 2080250661Sdavidcsqla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr) 2081250661Sdavidcs{ 2082250661Sdavidcs struct ether_vlan_header *eh; 2083250661Sdavidcs struct ip *ip = NULL; 2084250661Sdavidcs struct ip6_hdr *ip6 = NULL; 2085250661Sdavidcs struct tcphdr *th = NULL; 2086250661Sdavidcs uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off; 2087250661Sdavidcs uint16_t etype, opcode, offload = 1; 2088250661Sdavidcs device_t dev; 2089250661Sdavidcs 2090250661Sdavidcs dev = ha->pci_dev; 2091250661Sdavidcs 2092250661Sdavidcs 2093250661Sdavidcs eh = mtod(mp, struct ether_vlan_header *); 2094250661Sdavidcs 2095250661Sdavidcs if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2096250661Sdavidcs ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2097250661Sdavidcs etype = ntohs(eh->evl_proto); 2098250661Sdavidcs } else { 2099250661Sdavidcs ehdrlen = ETHER_HDR_LEN; 2100250661Sdavidcs etype = ntohs(eh->evl_encap_proto); 2101250661Sdavidcs } 2102250661Sdavidcs 2103250661Sdavidcs hdrlen = 0; 2104250661Sdavidcs 2105250661Sdavidcs switch (etype) { 2106250661Sdavidcs case ETHERTYPE_IP: 2107250661Sdavidcs 2108250661Sdavidcs tcp_opt_off = ehdrlen + sizeof(struct ip) + 2109250661Sdavidcs sizeof(struct tcphdr); 2110250661Sdavidcs 2111250661Sdavidcs if (mp->m_len < tcp_opt_off) { 2112250661Sdavidcs m_copydata(mp, 0, tcp_opt_off, hdr); 2113250661Sdavidcs ip = (struct ip *)(hdr + ehdrlen); 2114250661Sdavidcs } else { 2115250661Sdavidcs ip = (struct ip *)(mp->m_data + ehdrlen); 2116250661Sdavidcs } 2117250661Sdavidcs 2118250661Sdavidcs ip_hlen = ip->ip_hl << 2; 2119250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_TCP_LSO; 2120250661Sdavidcs 2121250661Sdavidcs 2122250661Sdavidcs if ((ip->ip_p != IPPROTO_TCP) || 2123250661Sdavidcs (ip_hlen != sizeof (struct ip))){ 2124250661Sdavidcs /* IP Options are not supported */ 2125250661Sdavidcs 2126250661Sdavidcs offload = 0; 2127250661Sdavidcs } else 2128250661Sdavidcs th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 2129250661Sdavidcs 2130250661Sdavidcs break; 2131250661Sdavidcs 2132250661Sdavidcs case ETHERTYPE_IPV6: 2133250661Sdavidcs 2134250661Sdavidcs tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) + 2135250661Sdavidcs sizeof (struct tcphdr); 2136250661Sdavidcs 2137250661Sdavidcs if (mp->m_len < tcp_opt_off) { 2138250661Sdavidcs m_copydata(mp, 0, tcp_opt_off, hdr); 2139250661Sdavidcs ip6 = (struct ip6_hdr *)(hdr + ehdrlen); 2140250661Sdavidcs } else { 2141250661Sdavidcs ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2142250661Sdavidcs } 2143250661Sdavidcs 2144250661Sdavidcs ip_hlen = sizeof(struct ip6_hdr); 2145250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6; 2146250661Sdavidcs 2147250661Sdavidcs if (ip6->ip6_nxt != IPPROTO_TCP) { 2148250661Sdavidcs //device_printf(dev, "%s: ipv6\n", __func__); 2149250661Sdavidcs offload = 0; 2150250661Sdavidcs } else 2151250661Sdavidcs th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 2152250661Sdavidcs break; 2153250661Sdavidcs 2154250661Sdavidcs default: 2155250661Sdavidcs QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__)); 2156250661Sdavidcs offload = 0; 2157250661Sdavidcs break; 2158250661Sdavidcs } 2159250661Sdavidcs 2160250661Sdavidcs if (!offload) 2161250661Sdavidcs return (-1); 2162250661Sdavidcs 2163250661Sdavidcs tcp_hlen = th->th_off << 2; 2164250661Sdavidcs hdrlen = ehdrlen + ip_hlen + tcp_hlen; 2165250661Sdavidcs 2166250661Sdavidcs if (mp->m_len < hdrlen) { 2167250661Sdavidcs if (mp->m_len < tcp_opt_off) { 2168250661Sdavidcs if (tcp_hlen > sizeof(struct tcphdr)) { 2169250661Sdavidcs m_copydata(mp, tcp_opt_off, 2170250661Sdavidcs (tcp_hlen - sizeof(struct tcphdr)), 2171250661Sdavidcs &hdr[tcp_opt_off]); 2172250661Sdavidcs } 2173250661Sdavidcs } else { 2174250661Sdavidcs m_copydata(mp, 0, hdrlen, hdr); 2175250661Sdavidcs } 2176250661Sdavidcs } 2177250661Sdavidcs 2178250661Sdavidcs tx_cmd->mss = mp->m_pkthdr.tso_segsz; 2179250661Sdavidcs 2180250661Sdavidcs tx_cmd->flags_opcode = opcode ; 2181250661Sdavidcs tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen; 2182250661Sdavidcs tx_cmd->total_hdr_len = hdrlen; 2183250661Sdavidcs 2184250661Sdavidcs /* Check for Multicast least significant bit of MSB == 1 */ 2185250661Sdavidcs if (eh->evl_dhost[0] & 0x01) { 2186250661Sdavidcs tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST; 2187250661Sdavidcs } 2188250661Sdavidcs 2189250661Sdavidcs if (mp->m_len < hdrlen) { 2190250661Sdavidcs printf("%d\n", hdrlen); 2191250661Sdavidcs return (1); 2192250661Sdavidcs } 2193250661Sdavidcs 2194250661Sdavidcs return (0); 2195250661Sdavidcs} 2196250661Sdavidcs 2197250661Sdavidcs/* 2198250661Sdavidcs * Name: qla_tx_chksum 2199250661Sdavidcs * Function: Checks if the packet to be transmitted is a candidate for 2200250661Sdavidcs * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx 2201250661Sdavidcs * Ring Structure are plugged in. 2202250661Sdavidcs */ 2203250661Sdavidcsstatic int 2204250661Sdavidcsqla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code, 2205250661Sdavidcs uint32_t *tcp_hdr_off) 2206250661Sdavidcs{ 2207250661Sdavidcs struct ether_vlan_header *eh; 2208250661Sdavidcs struct ip *ip; 2209250661Sdavidcs struct ip6_hdr *ip6; 2210250661Sdavidcs uint32_t ehdrlen, ip_hlen; 2211250661Sdavidcs uint16_t etype, opcode, offload = 1; 2212250661Sdavidcs device_t dev; 2213250661Sdavidcs uint8_t buf[sizeof(struct ip6_hdr)]; 2214250661Sdavidcs 2215250661Sdavidcs dev = ha->pci_dev; 2216250661Sdavidcs 2217250661Sdavidcs *op_code = 0; 2218250661Sdavidcs 2219322972Sdavidcs if ((mp->m_pkthdr.csum_flags & 2220322972Sdavidcs (CSUM_TCP|CSUM_UDP|CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) == 0) 2221250661Sdavidcs return (-1); 2222250661Sdavidcs 2223250661Sdavidcs eh = mtod(mp, struct ether_vlan_header *); 2224250661Sdavidcs 2225250661Sdavidcs if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2226250661Sdavidcs ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2227250661Sdavidcs etype = ntohs(eh->evl_proto); 2228250661Sdavidcs } else { 2229250661Sdavidcs ehdrlen = ETHER_HDR_LEN; 2230250661Sdavidcs etype = ntohs(eh->evl_encap_proto); 2231250661Sdavidcs } 2232250661Sdavidcs 2233250661Sdavidcs 2234250661Sdavidcs switch (etype) { 2235250661Sdavidcs case ETHERTYPE_IP: 2236250661Sdavidcs ip = (struct ip *)(mp->m_data + ehdrlen); 2237250661Sdavidcs 2238250661Sdavidcs ip_hlen = sizeof (struct ip); 2239250661Sdavidcs 2240250661Sdavidcs if (mp->m_len < (ehdrlen + ip_hlen)) { 2241250661Sdavidcs m_copydata(mp, ehdrlen, sizeof(struct ip), buf); 2242250661Sdavidcs ip = (struct ip *)buf; 2243250661Sdavidcs } 2244250661Sdavidcs 2245250661Sdavidcs if (ip->ip_p == IPPROTO_TCP) 2246250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM; 2247250661Sdavidcs else if (ip->ip_p == IPPROTO_UDP) 2248250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM; 2249250661Sdavidcs else { 2250250661Sdavidcs //device_printf(dev, "%s: ipv4\n", __func__); 2251250661Sdavidcs offload = 0; 2252250661Sdavidcs } 2253250661Sdavidcs break; 2254250661Sdavidcs 2255250661Sdavidcs case ETHERTYPE_IPV6: 2256250661Sdavidcs ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2257250661Sdavidcs 2258250661Sdavidcs ip_hlen = sizeof(struct ip6_hdr); 2259250661Sdavidcs 2260250661Sdavidcs if (mp->m_len < (ehdrlen + ip_hlen)) { 2261250661Sdavidcs m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr), 2262250661Sdavidcs buf); 2263250661Sdavidcs ip6 = (struct ip6_hdr *)buf; 2264250661Sdavidcs } 2265250661Sdavidcs 2266250661Sdavidcs if (ip6->ip6_nxt == IPPROTO_TCP) 2267250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6; 2268250661Sdavidcs else if (ip6->ip6_nxt == IPPROTO_UDP) 2269250661Sdavidcs opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6; 2270250661Sdavidcs else { 2271250661Sdavidcs //device_printf(dev, "%s: ipv6\n", __func__); 2272250661Sdavidcs offload = 0; 2273250661Sdavidcs } 2274250661Sdavidcs break; 2275250661Sdavidcs 2276250661Sdavidcs default: 2277250661Sdavidcs offload = 0; 2278250661Sdavidcs break; 2279250661Sdavidcs } 2280250661Sdavidcs if (!offload) 2281250661Sdavidcs return (-1); 2282250661Sdavidcs 2283250661Sdavidcs *op_code = opcode; 2284250661Sdavidcs *tcp_hdr_off = (ip_hlen + ehdrlen); 2285250661Sdavidcs 2286250661Sdavidcs return (0); 2287250661Sdavidcs} 2288250661Sdavidcs 2289250661Sdavidcs#define QLA_TX_MIN_FREE 2 2290250661Sdavidcs/* 2291250661Sdavidcs * Name: ql_hw_send 2292250661Sdavidcs * Function: Transmits a packet. It first checks if the packet is a 2293250661Sdavidcs * candidate for Large TCP Segment Offload and then for UDP/TCP checksum 2294250661Sdavidcs * offload. If either of these creteria are not met, it is transmitted 2295250661Sdavidcs * as a regular ethernet frame. 2296250661Sdavidcs */ 2297250661Sdavidcsint 2298250661Sdavidcsql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs, 2299284741Sdavidcs uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu) 2300250661Sdavidcs{ 2301250661Sdavidcs struct ether_vlan_header *eh; 2302250661Sdavidcs qla_hw_t *hw = &ha->hw; 2303250661Sdavidcs q80_tx_cmd_t *tx_cmd, tso_cmd; 2304250661Sdavidcs bus_dma_segment_t *c_seg; 2305250661Sdavidcs uint32_t num_tx_cmds, hdr_len = 0; 2306250661Sdavidcs uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next; 2307250661Sdavidcs device_t dev; 2308250661Sdavidcs int i, ret; 2309250661Sdavidcs uint8_t *src = NULL, *dst = NULL; 2310250661Sdavidcs uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 2311250661Sdavidcs uint32_t op_code = 0; 2312250661Sdavidcs uint32_t tcp_hdr_off = 0; 2313250661Sdavidcs 2314250661Sdavidcs dev = ha->pci_dev; 2315250661Sdavidcs 2316250661Sdavidcs /* 2317250661Sdavidcs * Always make sure there is atleast one empty slot in the tx_ring 2318250661Sdavidcs * tx_ring is considered full when there only one entry available 2319250661Sdavidcs */ 2320250661Sdavidcs num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2; 2321250661Sdavidcs 2322250661Sdavidcs total_length = mp->m_pkthdr.len; 2323250661Sdavidcs if (total_length > QLA_MAX_TSO_FRAME_SIZE) { 2324250661Sdavidcs device_printf(dev, "%s: total length exceeds maxlen(%d)\n", 2325250661Sdavidcs __func__, total_length); 2326324029Sdavidcs return (EINVAL); 2327250661Sdavidcs } 2328250661Sdavidcs eh = mtod(mp, struct ether_vlan_header *); 2329250661Sdavidcs 2330250661Sdavidcs if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2331250661Sdavidcs 2332250661Sdavidcs bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t)); 2333250661Sdavidcs 2334250661Sdavidcs src = frame_hdr; 2335250661Sdavidcs ret = qla_tx_tso(ha, mp, &tso_cmd, src); 2336250661Sdavidcs 2337250661Sdavidcs if (!(ret & ~1)) { 2338250661Sdavidcs /* find the additional tx_cmd descriptors required */ 2339250661Sdavidcs 2340250661Sdavidcs if (mp->m_flags & M_VLANTAG) 2341250661Sdavidcs tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN; 2342250661Sdavidcs 2343250661Sdavidcs hdr_len = tso_cmd.total_hdr_len; 2344250661Sdavidcs 2345250661Sdavidcs bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2346250661Sdavidcs bytes = QL_MIN(bytes, hdr_len); 2347250661Sdavidcs 2348250661Sdavidcs num_tx_cmds++; 2349250661Sdavidcs hdr_len -= bytes; 2350250661Sdavidcs 2351250661Sdavidcs while (hdr_len) { 2352250661Sdavidcs bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2353250661Sdavidcs hdr_len -= bytes; 2354250661Sdavidcs num_tx_cmds++; 2355250661Sdavidcs } 2356250661Sdavidcs hdr_len = tso_cmd.total_hdr_len; 2357250661Sdavidcs 2358250661Sdavidcs if (ret == 0) 2359250661Sdavidcs src = (uint8_t *)eh; 2360250661Sdavidcs } else 2361250661Sdavidcs return (EINVAL); 2362250661Sdavidcs } else { 2363250661Sdavidcs (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off); 2364250661Sdavidcs } 2365250661Sdavidcs 2366250661Sdavidcs if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) { 2367313070Sdavidcs ql_hw_tx_done_locked(ha, txr_idx); 2368250661Sdavidcs if (hw->tx_cntxt[txr_idx].txr_free <= 2369250661Sdavidcs (num_tx_cmds + QLA_TX_MIN_FREE)) { 2370250661Sdavidcs QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= " 2371250661Sdavidcs "(num_tx_cmds + QLA_TX_MIN_FREE))\n", 2372250661Sdavidcs __func__)); 2373250661Sdavidcs return (-1); 2374250661Sdavidcs } 2375250661Sdavidcs } 2376250661Sdavidcs 2377324761Sdavidcs for (i = 0; i < num_tx_cmds; i++) { 2378324761Sdavidcs int j; 2379324761Sdavidcs 2380324761Sdavidcs j = (tx_idx+i) & (NUM_TX_DESCRIPTORS - 1); 2381324761Sdavidcs 2382324761Sdavidcs if (NULL != ha->tx_ring[txr_idx].tx_buf[j].m_head) { 2383324761Sdavidcs QL_ASSERT(ha, 0, \ 2384324761Sdavidcs ("%s [%d]: txr_idx = %d tx_idx = %d mbuf = %p\n",\ 2385324761Sdavidcs __func__, __LINE__, txr_idx, j,\ 2386324761Sdavidcs ha->tx_ring[txr_idx].tx_buf[j].m_head)); 2387324761Sdavidcs return (EINVAL); 2388324761Sdavidcs } 2389324761Sdavidcs } 2390324761Sdavidcs 2391250661Sdavidcs tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx]; 2392250661Sdavidcs 2393250661Sdavidcs if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) { 2394250661Sdavidcs 2395250661Sdavidcs if (nsegs > ha->hw.max_tx_segs) 2396250661Sdavidcs ha->hw.max_tx_segs = nsegs; 2397250661Sdavidcs 2398250661Sdavidcs bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2399250661Sdavidcs 2400250661Sdavidcs if (op_code) { 2401250661Sdavidcs tx_cmd->flags_opcode = op_code; 2402250661Sdavidcs tx_cmd->tcp_hdr_off = tcp_hdr_off; 2403250661Sdavidcs 2404250661Sdavidcs } else { 2405250661Sdavidcs tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER; 2406250661Sdavidcs } 2407250661Sdavidcs } else { 2408250661Sdavidcs bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t)); 2409250661Sdavidcs ha->tx_tso_frames++; 2410250661Sdavidcs } 2411250661Sdavidcs 2412250661Sdavidcs if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2413250661Sdavidcs tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED; 2414284741Sdavidcs 2415284741Sdavidcs if (iscsi_pdu) 2416284741Sdavidcs eh->evl_tag |= ha->hw.user_pri_iscsi << 13; 2417284741Sdavidcs 2418250661Sdavidcs } else if (mp->m_flags & M_VLANTAG) { 2419250661Sdavidcs 2420250661Sdavidcs if (hdr_len) { /* TSO */ 2421250661Sdavidcs tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED | 2422250661Sdavidcs Q8_TX_CMD_FLAGS_HW_VLAN_ID); 2423250661Sdavidcs tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN; 2424250661Sdavidcs } else 2425250661Sdavidcs tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID; 2426250661Sdavidcs 2427250661Sdavidcs ha->hw_vlan_tx_frames++; 2428250661Sdavidcs tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag; 2429284741Sdavidcs 2430284741Sdavidcs if (iscsi_pdu) { 2431284741Sdavidcs tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13; 2432284741Sdavidcs mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci; 2433284741Sdavidcs } 2434250661Sdavidcs } 2435250661Sdavidcs 2436250661Sdavidcs 2437250661Sdavidcs tx_cmd->n_bufs = (uint8_t)nsegs; 2438250661Sdavidcs tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF); 2439250661Sdavidcs tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8))); 2440250661Sdavidcs tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func); 2441250661Sdavidcs 2442250661Sdavidcs c_seg = segs; 2443250661Sdavidcs 2444250661Sdavidcs while (1) { 2445250661Sdavidcs for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) { 2446250661Sdavidcs 2447250661Sdavidcs switch (i) { 2448250661Sdavidcs case 0: 2449250661Sdavidcs tx_cmd->buf1_addr = c_seg->ds_addr; 2450250661Sdavidcs tx_cmd->buf1_len = c_seg->ds_len; 2451250661Sdavidcs break; 2452250661Sdavidcs 2453250661Sdavidcs case 1: 2454250661Sdavidcs tx_cmd->buf2_addr = c_seg->ds_addr; 2455250661Sdavidcs tx_cmd->buf2_len = c_seg->ds_len; 2456250661Sdavidcs break; 2457250661Sdavidcs 2458250661Sdavidcs case 2: 2459250661Sdavidcs tx_cmd->buf3_addr = c_seg->ds_addr; 2460250661Sdavidcs tx_cmd->buf3_len = c_seg->ds_len; 2461250661Sdavidcs break; 2462250661Sdavidcs 2463250661Sdavidcs case 3: 2464250661Sdavidcs tx_cmd->buf4_addr = c_seg->ds_addr; 2465250661Sdavidcs tx_cmd->buf4_len = c_seg->ds_len; 2466250661Sdavidcs break; 2467250661Sdavidcs } 2468250661Sdavidcs 2469250661Sdavidcs c_seg++; 2470250661Sdavidcs nsegs--; 2471250661Sdavidcs } 2472250661Sdavidcs 2473250661Sdavidcs txr_next = hw->tx_cntxt[txr_idx].txr_next = 2474250661Sdavidcs (hw->tx_cntxt[txr_idx].txr_next + 1) & 2475250661Sdavidcs (NUM_TX_DESCRIPTORS - 1); 2476250661Sdavidcs tx_cmd_count++; 2477250661Sdavidcs 2478250661Sdavidcs if (!nsegs) 2479250661Sdavidcs break; 2480250661Sdavidcs 2481250661Sdavidcs tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2482250661Sdavidcs bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2483250661Sdavidcs } 2484250661Sdavidcs 2485250661Sdavidcs if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2486250661Sdavidcs 2487250661Sdavidcs /* TSO : Copy the header in the following tx cmd descriptors */ 2488250661Sdavidcs 2489250661Sdavidcs txr_next = hw->tx_cntxt[txr_idx].txr_next; 2490250661Sdavidcs 2491250661Sdavidcs tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2492250661Sdavidcs bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2493250661Sdavidcs 2494250661Sdavidcs bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2495250661Sdavidcs bytes = QL_MIN(bytes, hdr_len); 2496250661Sdavidcs 2497250661Sdavidcs dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN; 2498250661Sdavidcs 2499250661Sdavidcs if (mp->m_flags & M_VLANTAG) { 2500250661Sdavidcs /* first copy the src/dst MAC addresses */ 2501250661Sdavidcs bcopy(src, dst, (ETHER_ADDR_LEN * 2)); 2502250661Sdavidcs dst += (ETHER_ADDR_LEN * 2); 2503250661Sdavidcs src += (ETHER_ADDR_LEN * 2); 2504250661Sdavidcs 2505250661Sdavidcs *((uint16_t *)dst) = htons(ETHERTYPE_VLAN); 2506250661Sdavidcs dst += 2; 2507250661Sdavidcs *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag); 2508250661Sdavidcs dst += 2; 2509250661Sdavidcs 2510250661Sdavidcs /* bytes left in src header */ 2511250661Sdavidcs hdr_len -= ((ETHER_ADDR_LEN * 2) + 2512250661Sdavidcs ETHER_VLAN_ENCAP_LEN); 2513250661Sdavidcs 2514250661Sdavidcs /* bytes left in TxCmd Entry */ 2515250661Sdavidcs bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN); 2516250661Sdavidcs 2517250661Sdavidcs 2518250661Sdavidcs bcopy(src, dst, bytes); 2519250661Sdavidcs src += bytes; 2520250661Sdavidcs hdr_len -= bytes; 2521250661Sdavidcs } else { 2522250661Sdavidcs bcopy(src, dst, bytes); 2523250661Sdavidcs src += bytes; 2524250661Sdavidcs hdr_len -= bytes; 2525250661Sdavidcs } 2526250661Sdavidcs 2527250661Sdavidcs txr_next = hw->tx_cntxt[txr_idx].txr_next = 2528250661Sdavidcs (hw->tx_cntxt[txr_idx].txr_next + 1) & 2529250661Sdavidcs (NUM_TX_DESCRIPTORS - 1); 2530250661Sdavidcs tx_cmd_count++; 2531250661Sdavidcs 2532250661Sdavidcs while (hdr_len) { 2533250661Sdavidcs tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2534250661Sdavidcs bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2535250661Sdavidcs 2536250661Sdavidcs bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2537250661Sdavidcs 2538250661Sdavidcs bcopy(src, tx_cmd, bytes); 2539250661Sdavidcs src += bytes; 2540250661Sdavidcs hdr_len -= bytes; 2541250661Sdavidcs 2542250661Sdavidcs txr_next = hw->tx_cntxt[txr_idx].txr_next = 2543250661Sdavidcs (hw->tx_cntxt[txr_idx].txr_next + 1) & 2544250661Sdavidcs (NUM_TX_DESCRIPTORS - 1); 2545250661Sdavidcs tx_cmd_count++; 2546250661Sdavidcs } 2547250661Sdavidcs } 2548250661Sdavidcs 2549250661Sdavidcs hw->tx_cntxt[txr_idx].txr_free = 2550250661Sdavidcs hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count; 2551250661Sdavidcs 2552250661Sdavidcs QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\ 2553250661Sdavidcs txr_idx); 2554250661Sdavidcs QL_DPRINT8(ha, (dev, "%s: return\n", __func__)); 2555250661Sdavidcs 2556250661Sdavidcs return (0); 2557250661Sdavidcs} 2558250661Sdavidcs 2559250661Sdavidcs 2560284741Sdavidcs 2561284741Sdavidcs#define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */ 2562250661Sdavidcsstatic int 2563250661Sdavidcsqla_config_rss_ind_table(qla_host_t *ha) 2564250661Sdavidcs{ 2565250661Sdavidcs uint32_t i, count; 2566284741Sdavidcs uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE]; 2567250661Sdavidcs 2568250661Sdavidcs 2569284741Sdavidcs for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) { 2570250661Sdavidcs rss_ind_tbl[i] = i % ha->hw.num_sds_rings; 2571250661Sdavidcs } 2572250661Sdavidcs 2573284741Sdavidcs for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ; 2574284741Sdavidcs i = i + Q8_CONFIG_IND_TBL_SIZE) { 2575250661Sdavidcs 2576284741Sdavidcs if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) { 2577250661Sdavidcs count = Q8_RSS_IND_TBL_MAX_IDX - i + 1; 2578250661Sdavidcs } else { 2579284741Sdavidcs count = Q8_CONFIG_IND_TBL_SIZE; 2580250661Sdavidcs } 2581250661Sdavidcs 2582250661Sdavidcs if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id, 2583250661Sdavidcs rss_ind_tbl)) 2584250661Sdavidcs return (-1); 2585250661Sdavidcs } 2586250661Sdavidcs 2587250661Sdavidcs return (0); 2588250661Sdavidcs} 2589250661Sdavidcs 2590317109Sdavidcsstatic int 2591317109Sdavidcsqla_config_soft_lro(qla_host_t *ha) 2592317109Sdavidcs{ 2593317109Sdavidcs int i; 2594317109Sdavidcs qla_hw_t *hw = &ha->hw; 2595317109Sdavidcs struct lro_ctrl *lro; 2596317109Sdavidcs 2597317109Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 2598317109Sdavidcs lro = &hw->sds[i].lro; 2599317109Sdavidcs 2600317109Sdavidcs bzero(lro, sizeof(struct lro_ctrl)); 2601317109Sdavidcs 2602317109Sdavidcs#if (__FreeBSD_version >= 1100101) 2603317109Sdavidcs if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) { 2604317109Sdavidcs device_printf(ha->pci_dev, 2605317109Sdavidcs "%s: tcp_lro_init_args [%d] failed\n", 2606317109Sdavidcs __func__, i); 2607317109Sdavidcs return (-1); 2608317109Sdavidcs } 2609317109Sdavidcs#else 2610317109Sdavidcs if (tcp_lro_init(lro)) { 2611317109Sdavidcs device_printf(ha->pci_dev, 2612317109Sdavidcs "%s: tcp_lro_init [%d] failed\n", 2613317109Sdavidcs __func__, i); 2614317109Sdavidcs return (-1); 2615317109Sdavidcs } 2616317109Sdavidcs#endif /* #if (__FreeBSD_version >= 1100101) */ 2617317109Sdavidcs 2618317109Sdavidcs lro->ifp = ha->ifp; 2619317109Sdavidcs } 2620317109Sdavidcs 2621317109Sdavidcs QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__)); 2622317109Sdavidcs return (0); 2623317109Sdavidcs} 2624317109Sdavidcs 2625317109Sdavidcsstatic void 2626317109Sdavidcsqla_drain_soft_lro(qla_host_t *ha) 2627317109Sdavidcs{ 2628317109Sdavidcs int i; 2629317109Sdavidcs qla_hw_t *hw = &ha->hw; 2630317109Sdavidcs struct lro_ctrl *lro; 2631317109Sdavidcs 2632317109Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 2633317109Sdavidcs lro = &hw->sds[i].lro; 2634317109Sdavidcs 2635317109Sdavidcs#if (__FreeBSD_version >= 1100101) 2636317109Sdavidcs tcp_lro_flush_all(lro); 2637317109Sdavidcs#else 2638317109Sdavidcs struct lro_entry *queued; 2639317109Sdavidcs 2640317109Sdavidcs while ((!SLIST_EMPTY(&lro->lro_active))) { 2641317109Sdavidcs queued = SLIST_FIRST(&lro->lro_active); 2642317109Sdavidcs SLIST_REMOVE_HEAD(&lro->lro_active, next); 2643317109Sdavidcs tcp_lro_flush(lro, queued); 2644317109Sdavidcs } 2645317109Sdavidcs#endif /* #if (__FreeBSD_version >= 1100101) */ 2646317109Sdavidcs } 2647317109Sdavidcs 2648317109Sdavidcs return; 2649317109Sdavidcs} 2650317109Sdavidcs 2651317109Sdavidcsstatic void 2652317109Sdavidcsqla_free_soft_lro(qla_host_t *ha) 2653317109Sdavidcs{ 2654317109Sdavidcs int i; 2655317109Sdavidcs qla_hw_t *hw = &ha->hw; 2656317109Sdavidcs struct lro_ctrl *lro; 2657317109Sdavidcs 2658317109Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 2659317109Sdavidcs lro = &hw->sds[i].lro; 2660317109Sdavidcs tcp_lro_free(lro); 2661317109Sdavidcs } 2662317109Sdavidcs 2663317109Sdavidcs return; 2664317109Sdavidcs} 2665317109Sdavidcs 2666317109Sdavidcs 2667250661Sdavidcs/* 2668250661Sdavidcs * Name: ql_del_hw_if 2669250661Sdavidcs * Function: Destroys the hardware specific entities corresponding to an 2670250661Sdavidcs * Ethernet Interface 2671250661Sdavidcs */ 2672250661Sdavidcsvoid 2673250661Sdavidcsql_del_hw_if(qla_host_t *ha) 2674250661Sdavidcs{ 2675284741Sdavidcs uint32_t i; 2676284741Sdavidcs uint32_t num_msix; 2677250661Sdavidcs 2678284741Sdavidcs (void)qla_stop_nic_func(ha); 2679284741Sdavidcs 2680250661Sdavidcs qla_del_rcv_cntxt(ha); 2681307524Sdavidcs 2682250661Sdavidcs qla_del_xmt_cntxt(ha); 2683250661Sdavidcs 2684250661Sdavidcs if (ha->hw.flags.init_intr_cnxt) { 2685284741Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; ) { 2686284741Sdavidcs 2687284741Sdavidcs if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2688284741Sdavidcs num_msix = Q8_MAX_INTR_VECTORS; 2689284741Sdavidcs else 2690284741Sdavidcs num_msix = ha->hw.num_sds_rings - i; 2691284741Sdavidcs qla_config_intr_cntxt(ha, i, num_msix, 0); 2692284741Sdavidcs 2693284741Sdavidcs i += num_msix; 2694284741Sdavidcs } 2695284741Sdavidcs 2696250661Sdavidcs ha->hw.flags.init_intr_cnxt = 0; 2697250661Sdavidcs } 2698307524Sdavidcs 2699317109Sdavidcs if (ha->hw.enable_soft_lro) { 2700317109Sdavidcs qla_drain_soft_lro(ha); 2701317109Sdavidcs qla_free_soft_lro(ha); 2702317109Sdavidcs } 2703317109Sdavidcs 2704284741Sdavidcs return; 2705250661Sdavidcs} 2706250661Sdavidcs 2707284741Sdavidcsvoid 2708284741Sdavidcsqla_confirm_9kb_enable(qla_host_t *ha) 2709284741Sdavidcs{ 2710284741Sdavidcs uint32_t supports_9kb = 0; 2711284741Sdavidcs 2712284741Sdavidcs ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX); 2713284741Sdavidcs 2714284741Sdavidcs /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */ 2715284741Sdavidcs WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); 2716284741Sdavidcs WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 2717284741Sdavidcs 2718284741Sdavidcs qla_get_nic_partition(ha, &supports_9kb, NULL); 2719284741Sdavidcs 2720284741Sdavidcs if (!supports_9kb) 2721284741Sdavidcs ha->hw.enable_9kb = 0; 2722284741Sdavidcs 2723284741Sdavidcs return; 2724284741Sdavidcs} 2725284741Sdavidcs 2726250661Sdavidcs/* 2727250661Sdavidcs * Name: ql_init_hw_if 2728250661Sdavidcs * Function: Creates the hardware specific entities corresponding to an 2729250661Sdavidcs * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address 2730250661Sdavidcs * corresponding to the interface. Enables LRO if allowed. 2731250661Sdavidcs */ 2732250661Sdavidcsint 2733250661Sdavidcsql_init_hw_if(qla_host_t *ha) 2734250661Sdavidcs{ 2735250661Sdavidcs device_t dev; 2736250661Sdavidcs uint32_t i; 2737250661Sdavidcs uint8_t bcast_mac[6]; 2738250661Sdavidcs qla_rdesc_t *rdesc; 2739284741Sdavidcs uint32_t num_msix; 2740250661Sdavidcs 2741250661Sdavidcs dev = ha->pci_dev; 2742250661Sdavidcs 2743250661Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; i++) { 2744250661Sdavidcs bzero(ha->hw.dma_buf.sds_ring[i].dma_b, 2745250661Sdavidcs ha->hw.dma_buf.sds_ring[i].size); 2746250661Sdavidcs } 2747250661Sdavidcs 2748284741Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; ) { 2749250661Sdavidcs 2750284741Sdavidcs if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2751284741Sdavidcs num_msix = Q8_MAX_INTR_VECTORS; 2752284741Sdavidcs else 2753284741Sdavidcs num_msix = ha->hw.num_sds_rings - i; 2754250661Sdavidcs 2755284741Sdavidcs if (qla_config_intr_cntxt(ha, i, num_msix, 1)) { 2756250661Sdavidcs 2757284741Sdavidcs if (i > 0) { 2758284741Sdavidcs 2759284741Sdavidcs num_msix = i; 2760284741Sdavidcs 2761284741Sdavidcs for (i = 0; i < num_msix; ) { 2762284741Sdavidcs qla_config_intr_cntxt(ha, i, 2763284741Sdavidcs Q8_MAX_INTR_VECTORS, 0); 2764284741Sdavidcs i += Q8_MAX_INTR_VECTORS; 2765284741Sdavidcs } 2766284741Sdavidcs } 2767284741Sdavidcs return (-1); 2768284741Sdavidcs } 2769284741Sdavidcs 2770284741Sdavidcs i = i + num_msix; 2771284741Sdavidcs } 2772284741Sdavidcs 2773284741Sdavidcs ha->hw.flags.init_intr_cnxt = 1; 2774284741Sdavidcs 2775250661Sdavidcs /* 2776250661Sdavidcs * Create Receive Context 2777250661Sdavidcs */ 2778250661Sdavidcs if (qla_init_rcv_cntxt(ha)) { 2779250661Sdavidcs return (-1); 2780250661Sdavidcs } 2781250661Sdavidcs 2782250661Sdavidcs for (i = 0; i < ha->hw.num_rds_rings; i++) { 2783250661Sdavidcs rdesc = &ha->hw.rds[i]; 2784250661Sdavidcs rdesc->rx_next = NUM_RX_DESCRIPTORS - 2; 2785250661Sdavidcs rdesc->rx_in = 0; 2786250661Sdavidcs /* Update the RDS Producer Indices */ 2787250661Sdavidcs QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\ 2788250661Sdavidcs rdesc->rx_next); 2789250661Sdavidcs } 2790250661Sdavidcs 2791250661Sdavidcs /* 2792250661Sdavidcs * Create Transmit Context 2793250661Sdavidcs */ 2794250661Sdavidcs if (qla_init_xmt_cntxt(ha)) { 2795250661Sdavidcs qla_del_rcv_cntxt(ha); 2796250661Sdavidcs return (-1); 2797250661Sdavidcs } 2798250661Sdavidcs ha->hw.max_tx_segs = 0; 2799250661Sdavidcs 2800307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1)) 2801250661Sdavidcs return(-1); 2802250661Sdavidcs 2803250661Sdavidcs ha->hw.flags.unicast_mac = 1; 2804250661Sdavidcs 2805250661Sdavidcs bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 2806250661Sdavidcs bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 2807250661Sdavidcs 2808307524Sdavidcs if (qla_config_mac_addr(ha, bcast_mac, 1, 1)) 2809250661Sdavidcs return (-1); 2810250661Sdavidcs 2811250661Sdavidcs ha->hw.flags.bcast_mac = 1; 2812250661Sdavidcs 2813250661Sdavidcs /* 2814250661Sdavidcs * program any cached multicast addresses 2815250661Sdavidcs */ 2816250661Sdavidcs if (qla_hw_add_all_mcast(ha)) 2817250661Sdavidcs return (-1); 2818250661Sdavidcs 2819321494Sdavidcs if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id)) 2820321494Sdavidcs return (-1); 2821321494Sdavidcs 2822250661Sdavidcs if (qla_config_rss(ha, ha->hw.rcv_cntxt_id)) 2823250661Sdavidcs return (-1); 2824250661Sdavidcs 2825250661Sdavidcs if (qla_config_rss_ind_table(ha)) 2826250661Sdavidcs return (-1); 2827250661Sdavidcs 2828284741Sdavidcs if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1)) 2829250661Sdavidcs return (-1); 2830250661Sdavidcs 2831250661Sdavidcs if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id)) 2832250661Sdavidcs return (-1); 2833250661Sdavidcs 2834317109Sdavidcs if (ha->ifp->if_capenable & IFCAP_LRO) { 2835317109Sdavidcs if (ha->hw.enable_hw_lro) { 2836317109Sdavidcs ha->hw.enable_soft_lro = 0; 2837250661Sdavidcs 2838317109Sdavidcs if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id)) 2839317109Sdavidcs return (-1); 2840317109Sdavidcs } else { 2841317109Sdavidcs ha->hw.enable_soft_lro = 1; 2842317109Sdavidcs 2843317109Sdavidcs if (qla_config_soft_lro(ha)) 2844317109Sdavidcs return (-1); 2845317109Sdavidcs } 2846317109Sdavidcs } 2847317109Sdavidcs 2848284741Sdavidcs if (qla_init_nic_func(ha)) 2849284741Sdavidcs return (-1); 2850284741Sdavidcs 2851284741Sdavidcs if (qla_query_fw_dcbx_caps(ha)) 2852284741Sdavidcs return (-1); 2853284741Sdavidcs 2854250661Sdavidcs for (i = 0; i < ha->hw.num_sds_rings; i++) 2855250661Sdavidcs QL_ENABLE_INTERRUPTS(ha, i); 2856250661Sdavidcs 2857250661Sdavidcs return (0); 2858250661Sdavidcs} 2859250661Sdavidcs 2860250661Sdavidcsstatic int 2861284741Sdavidcsqla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx) 2862250661Sdavidcs{ 2863250661Sdavidcs device_t dev = ha->pci_dev; 2864250661Sdavidcs q80_rq_map_sds_to_rds_t *map_rings; 2865284741Sdavidcs q80_rsp_map_sds_to_rds_t *map_rings_rsp; 2866250661Sdavidcs uint32_t i, err; 2867250661Sdavidcs qla_hw_t *hw = &ha->hw; 2868250661Sdavidcs 2869250661Sdavidcs map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox; 2870250661Sdavidcs bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t)); 2871250661Sdavidcs 2872250661Sdavidcs map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS; 2873250661Sdavidcs map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2); 2874250661Sdavidcs map_rings->count_version |= Q8_MBX_CMD_VERSION; 2875250661Sdavidcs 2876250661Sdavidcs map_rings->cntxt_id = hw->rcv_cntxt_id; 2877284741Sdavidcs map_rings->num_rings = num_idx; 2878250661Sdavidcs 2879284741Sdavidcs for (i = 0; i < num_idx; i++) { 2880284741Sdavidcs map_rings->sds_rds[i].sds_ring = i + start_idx; 2881284741Sdavidcs map_rings->sds_rds[i].rds_ring = i + start_idx; 2882284741Sdavidcs } 2883250661Sdavidcs 2884250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)map_rings, 2885250661Sdavidcs (sizeof (q80_rq_map_sds_to_rds_t) >> 2), 2886250661Sdavidcs ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 2887250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 2888250661Sdavidcs return (-1); 2889250661Sdavidcs } 2890250661Sdavidcs 2891284741Sdavidcs map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox; 2892250661Sdavidcs 2893250661Sdavidcs err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status); 2894250661Sdavidcs 2895250661Sdavidcs if (err) { 2896250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 2897250661Sdavidcs return (-1); 2898250661Sdavidcs } 2899250661Sdavidcs 2900250661Sdavidcs return (0); 2901250661Sdavidcs} 2902250661Sdavidcs 2903250661Sdavidcs/* 2904250661Sdavidcs * Name: qla_init_rcv_cntxt 2905250661Sdavidcs * Function: Creates the Receive Context. 2906250661Sdavidcs */ 2907250661Sdavidcsstatic int 2908250661Sdavidcsqla_init_rcv_cntxt(qla_host_t *ha) 2909250661Sdavidcs{ 2910250661Sdavidcs q80_rq_rcv_cntxt_t *rcntxt; 2911250661Sdavidcs q80_rsp_rcv_cntxt_t *rcntxt_rsp; 2912250661Sdavidcs q80_stat_desc_t *sdesc; 2913250661Sdavidcs int i, j; 2914250661Sdavidcs qla_hw_t *hw = &ha->hw; 2915250661Sdavidcs device_t dev; 2916250661Sdavidcs uint32_t err; 2917250661Sdavidcs uint32_t rcntxt_sds_rings; 2918250661Sdavidcs uint32_t rcntxt_rds_rings; 2919284741Sdavidcs uint32_t max_idx; 2920250661Sdavidcs 2921250661Sdavidcs dev = ha->pci_dev; 2922250661Sdavidcs 2923250661Sdavidcs /* 2924250661Sdavidcs * Create Receive Context 2925250661Sdavidcs */ 2926250661Sdavidcs 2927250661Sdavidcs for (i = 0; i < hw->num_sds_rings; i++) { 2928250661Sdavidcs sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0]; 2929250661Sdavidcs 2930250661Sdavidcs for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) { 2931250661Sdavidcs sdesc->data[0] = 1ULL; 2932250661Sdavidcs sdesc->data[1] = 1ULL; 2933250661Sdavidcs } 2934250661Sdavidcs } 2935250661Sdavidcs 2936250661Sdavidcs rcntxt_sds_rings = hw->num_sds_rings; 2937250661Sdavidcs if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) 2938250661Sdavidcs rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS; 2939250661Sdavidcs 2940250661Sdavidcs rcntxt_rds_rings = hw->num_rds_rings; 2941250661Sdavidcs 2942250661Sdavidcs if (hw->num_rds_rings > MAX_RDS_RING_SETS) 2943250661Sdavidcs rcntxt_rds_rings = MAX_RDS_RING_SETS; 2944250661Sdavidcs 2945250661Sdavidcs rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox; 2946250661Sdavidcs bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t))); 2947250661Sdavidcs 2948250661Sdavidcs rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT; 2949250661Sdavidcs rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2); 2950250661Sdavidcs rcntxt->count_version |= Q8_MBX_CMD_VERSION; 2951250661Sdavidcs 2952250661Sdavidcs rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW | 2953250661Sdavidcs Q8_RCV_CNTXT_CAP0_LRO | 2954250661Sdavidcs Q8_RCV_CNTXT_CAP0_HW_LRO | 2955250661Sdavidcs Q8_RCV_CNTXT_CAP0_RSS | 2956250661Sdavidcs Q8_RCV_CNTXT_CAP0_SGL_LRO; 2957250661Sdavidcs 2958284741Sdavidcs if (ha->hw.enable_9kb) 2959284741Sdavidcs rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO; 2960284741Sdavidcs else 2961284741Sdavidcs rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO; 2962284741Sdavidcs 2963250661Sdavidcs if (ha->hw.num_rds_rings > 1) { 2964250661Sdavidcs rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5); 2965250661Sdavidcs rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS; 2966250661Sdavidcs } else 2967250661Sdavidcs rcntxt->nrds_sets_rings = 0x1 | (1 << 5); 2968250661Sdavidcs 2969250661Sdavidcs rcntxt->nsds_rings = rcntxt_sds_rings; 2970250661Sdavidcs 2971250661Sdavidcs rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE; 2972250661Sdavidcs 2973250661Sdavidcs rcntxt->rcv_vpid = 0; 2974250661Sdavidcs 2975250661Sdavidcs for (i = 0; i < rcntxt_sds_rings; i++) { 2976250661Sdavidcs rcntxt->sds[i].paddr = 2977250661Sdavidcs qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr); 2978250661Sdavidcs rcntxt->sds[i].size = 2979250661Sdavidcs qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 2980313070Sdavidcs rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]); 2981313070Sdavidcs rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0); 2982250661Sdavidcs } 2983250661Sdavidcs 2984250661Sdavidcs for (i = 0; i < rcntxt_rds_rings; i++) { 2985250661Sdavidcs rcntxt->rds[i].paddr_std = 2986250661Sdavidcs qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr); 2987284741Sdavidcs 2988284741Sdavidcs if (ha->hw.enable_9kb) 2989284741Sdavidcs rcntxt->rds[i].std_bsize = 2990284741Sdavidcs qla_host_to_le64(MJUM9BYTES); 2991284741Sdavidcs else 2992284741Sdavidcs rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 2993284741Sdavidcs 2994250661Sdavidcs rcntxt->rds[i].std_nentries = 2995250661Sdavidcs qla_host_to_le32(NUM_RX_DESCRIPTORS); 2996250661Sdavidcs } 2997250661Sdavidcs 2998250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 2999250661Sdavidcs (sizeof (q80_rq_rcv_cntxt_t) >> 2), 3000250661Sdavidcs ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) { 3001250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 3002250661Sdavidcs return (-1); 3003250661Sdavidcs } 3004250661Sdavidcs 3005250661Sdavidcs rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox; 3006250661Sdavidcs 3007250661Sdavidcs err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3008250661Sdavidcs 3009250661Sdavidcs if (err) { 3010250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3011250661Sdavidcs return (-1); 3012250661Sdavidcs } 3013250661Sdavidcs 3014250661Sdavidcs for (i = 0; i < rcntxt_sds_rings; i++) { 3015250661Sdavidcs hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i]; 3016250661Sdavidcs } 3017250661Sdavidcs 3018250661Sdavidcs for (i = 0; i < rcntxt_rds_rings; i++) { 3019250661Sdavidcs hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std; 3020250661Sdavidcs } 3021250661Sdavidcs 3022250661Sdavidcs hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id; 3023250661Sdavidcs 3024250661Sdavidcs ha->hw.flags.init_rx_cnxt = 1; 3025250661Sdavidcs 3026250661Sdavidcs if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) { 3027284741Sdavidcs 3028284741Sdavidcs for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) { 3029284741Sdavidcs 3030284741Sdavidcs if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings) 3031284741Sdavidcs max_idx = MAX_RCNTXT_SDS_RINGS; 3032284741Sdavidcs else 3033284741Sdavidcs max_idx = hw->num_sds_rings - i; 3034284741Sdavidcs 3035284741Sdavidcs err = qla_add_rcv_rings(ha, i, max_idx); 3036284741Sdavidcs if (err) 3037284741Sdavidcs return -1; 3038284741Sdavidcs 3039284741Sdavidcs i += max_idx; 3040284741Sdavidcs } 3041250661Sdavidcs } 3042250661Sdavidcs 3043284741Sdavidcs if (hw->num_rds_rings > 1) { 3044284741Sdavidcs 3045284741Sdavidcs for (i = 0; i < hw->num_rds_rings; ) { 3046284741Sdavidcs 3047284741Sdavidcs if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings) 3048284741Sdavidcs max_idx = MAX_SDS_TO_RDS_MAP; 3049284741Sdavidcs else 3050284741Sdavidcs max_idx = hw->num_rds_rings - i; 3051284741Sdavidcs 3052284741Sdavidcs err = qla_map_sds_to_rds(ha, i, max_idx); 3053284741Sdavidcs if (err) 3054284741Sdavidcs return -1; 3055284741Sdavidcs 3056284741Sdavidcs i += max_idx; 3057284741Sdavidcs } 3058250661Sdavidcs } 3059250661Sdavidcs 3060250661Sdavidcs return (0); 3061250661Sdavidcs} 3062250661Sdavidcs 3063250661Sdavidcsstatic int 3064284741Sdavidcsqla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds) 3065250661Sdavidcs{ 3066250661Sdavidcs device_t dev = ha->pci_dev; 3067250661Sdavidcs q80_rq_add_rcv_rings_t *add_rcv; 3068250661Sdavidcs q80_rsp_add_rcv_rings_t *add_rcv_rsp; 3069250661Sdavidcs uint32_t i,j, err; 3070250661Sdavidcs qla_hw_t *hw = &ha->hw; 3071250661Sdavidcs 3072250661Sdavidcs add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox; 3073250661Sdavidcs bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t)); 3074250661Sdavidcs 3075250661Sdavidcs add_rcv->opcode = Q8_MBX_ADD_RX_RINGS; 3076250661Sdavidcs add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2); 3077250661Sdavidcs add_rcv->count_version |= Q8_MBX_CMD_VERSION; 3078250661Sdavidcs 3079284741Sdavidcs add_rcv->nrds_sets_rings = nsds | (1 << 5); 3080250661Sdavidcs add_rcv->nsds_rings = nsds; 3081250661Sdavidcs add_rcv->cntxt_id = hw->rcv_cntxt_id; 3082250661Sdavidcs 3083250661Sdavidcs for (i = 0; i < nsds; i++) { 3084250661Sdavidcs 3085250661Sdavidcs j = i + sds_idx; 3086250661Sdavidcs 3087250661Sdavidcs add_rcv->sds[i].paddr = 3088250661Sdavidcs qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr); 3089250661Sdavidcs 3090250661Sdavidcs add_rcv->sds[i].size = 3091250661Sdavidcs qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 3092250661Sdavidcs 3093313070Sdavidcs add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]); 3094313070Sdavidcs add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0); 3095250661Sdavidcs 3096250661Sdavidcs } 3097313070Sdavidcs 3098284741Sdavidcs for (i = 0; (i < nsds); i++) { 3099250661Sdavidcs j = i + sds_idx; 3100284741Sdavidcs 3101250661Sdavidcs add_rcv->rds[i].paddr_std = 3102250661Sdavidcs qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr); 3103284741Sdavidcs 3104284741Sdavidcs if (ha->hw.enable_9kb) 3105284741Sdavidcs add_rcv->rds[i].std_bsize = 3106284741Sdavidcs qla_host_to_le64(MJUM9BYTES); 3107284741Sdavidcs else 3108284741Sdavidcs add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 3109284741Sdavidcs 3110250661Sdavidcs add_rcv->rds[i].std_nentries = 3111250661Sdavidcs qla_host_to_le32(NUM_RX_DESCRIPTORS); 3112250661Sdavidcs } 3113250661Sdavidcs 3114250661Sdavidcs 3115250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)add_rcv, 3116250661Sdavidcs (sizeof (q80_rq_add_rcv_rings_t) >> 2), 3117250661Sdavidcs ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 3118250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 3119250661Sdavidcs return (-1); 3120250661Sdavidcs } 3121250661Sdavidcs 3122250661Sdavidcs add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox; 3123250661Sdavidcs 3124250661Sdavidcs err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status); 3125250661Sdavidcs 3126250661Sdavidcs if (err) { 3127250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3128250661Sdavidcs return (-1); 3129250661Sdavidcs } 3130250661Sdavidcs 3131284741Sdavidcs for (i = 0; i < nsds; i++) { 3132284741Sdavidcs hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i]; 3133250661Sdavidcs } 3134284741Sdavidcs 3135284741Sdavidcs for (i = 0; i < nsds; i++) { 3136284741Sdavidcs hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std; 3137250661Sdavidcs } 3138284741Sdavidcs 3139250661Sdavidcs return (0); 3140250661Sdavidcs} 3141250661Sdavidcs 3142250661Sdavidcs/* 3143250661Sdavidcs * Name: qla_del_rcv_cntxt 3144250661Sdavidcs * Function: Destroys the Receive Context. 3145250661Sdavidcs */ 3146250661Sdavidcsstatic void 3147250661Sdavidcsqla_del_rcv_cntxt(qla_host_t *ha) 3148250661Sdavidcs{ 3149250661Sdavidcs device_t dev = ha->pci_dev; 3150250661Sdavidcs q80_rcv_cntxt_destroy_t *rcntxt; 3151250661Sdavidcs q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp; 3152250661Sdavidcs uint32_t err; 3153250661Sdavidcs uint8_t bcast_mac[6]; 3154250661Sdavidcs 3155250661Sdavidcs if (!ha->hw.flags.init_rx_cnxt) 3156250661Sdavidcs return; 3157250661Sdavidcs 3158250661Sdavidcs if (qla_hw_del_all_mcast(ha)) 3159250661Sdavidcs return; 3160250661Sdavidcs 3161250661Sdavidcs if (ha->hw.flags.bcast_mac) { 3162250661Sdavidcs 3163250661Sdavidcs bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 3164250661Sdavidcs bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 3165250661Sdavidcs 3166307524Sdavidcs if (qla_config_mac_addr(ha, bcast_mac, 0, 1)) 3167250661Sdavidcs return; 3168250661Sdavidcs ha->hw.flags.bcast_mac = 0; 3169250661Sdavidcs 3170250661Sdavidcs } 3171250661Sdavidcs 3172250661Sdavidcs if (ha->hw.flags.unicast_mac) { 3173307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1)) 3174250661Sdavidcs return; 3175250661Sdavidcs ha->hw.flags.unicast_mac = 0; 3176250661Sdavidcs } 3177250661Sdavidcs 3178250661Sdavidcs rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox; 3179250661Sdavidcs bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t))); 3180250661Sdavidcs 3181250661Sdavidcs rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT; 3182250661Sdavidcs rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2); 3183250661Sdavidcs rcntxt->count_version |= Q8_MBX_CMD_VERSION; 3184250661Sdavidcs 3185250661Sdavidcs rcntxt->cntxt_id = ha->hw.rcv_cntxt_id; 3186250661Sdavidcs 3187250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 3188250661Sdavidcs (sizeof (q80_rcv_cntxt_destroy_t) >> 2), 3189250661Sdavidcs ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) { 3190250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 3191250661Sdavidcs return; 3192250661Sdavidcs } 3193250661Sdavidcs rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox; 3194250661Sdavidcs 3195250661Sdavidcs err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3196250661Sdavidcs 3197250661Sdavidcs if (err) { 3198250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3199250661Sdavidcs } 3200250661Sdavidcs 3201250661Sdavidcs ha->hw.flags.init_rx_cnxt = 0; 3202250661Sdavidcs return; 3203250661Sdavidcs} 3204250661Sdavidcs 3205250661Sdavidcs/* 3206250661Sdavidcs * Name: qla_init_xmt_cntxt 3207250661Sdavidcs * Function: Creates the Transmit Context. 3208250661Sdavidcs */ 3209250661Sdavidcsstatic int 3210250661Sdavidcsqla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3211250661Sdavidcs{ 3212250661Sdavidcs device_t dev; 3213250661Sdavidcs qla_hw_t *hw = &ha->hw; 3214250661Sdavidcs q80_rq_tx_cntxt_t *tcntxt; 3215250661Sdavidcs q80_rsp_tx_cntxt_t *tcntxt_rsp; 3216250661Sdavidcs uint32_t err; 3217250661Sdavidcs qla_hw_tx_cntxt_t *hw_tx_cntxt; 3218313070Sdavidcs uint32_t intr_idx; 3219250661Sdavidcs 3220250661Sdavidcs hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3221250661Sdavidcs 3222250661Sdavidcs dev = ha->pci_dev; 3223250661Sdavidcs 3224250661Sdavidcs /* 3225250661Sdavidcs * Create Transmit Context 3226250661Sdavidcs */ 3227250661Sdavidcs tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox; 3228250661Sdavidcs bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t))); 3229250661Sdavidcs 3230250661Sdavidcs tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT; 3231250661Sdavidcs tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2); 3232250661Sdavidcs tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3233250661Sdavidcs 3234313070Sdavidcs intr_idx = txr_idx; 3235313070Sdavidcs 3236284741Sdavidcs#ifdef QL_ENABLE_ISCSI_TLV 3237284741Sdavidcs 3238284741Sdavidcs tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO | 3239284741Sdavidcs Q8_TX_CNTXT_CAP0_TC; 3240284741Sdavidcs 3241284741Sdavidcs if (txr_idx >= (ha->hw.num_tx_rings >> 1)) { 3242284741Sdavidcs tcntxt->traffic_class = 1; 3243284741Sdavidcs } 3244284741Sdavidcs 3245313070Sdavidcs intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1); 3246313070Sdavidcs 3247284741Sdavidcs#else 3248250661Sdavidcs tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO; 3249250661Sdavidcs 3250284741Sdavidcs#endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 3251284741Sdavidcs 3252250661Sdavidcs tcntxt->ntx_rings = 1; 3253250661Sdavidcs 3254250661Sdavidcs tcntxt->tx_ring[0].paddr = 3255250661Sdavidcs qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr); 3256250661Sdavidcs tcntxt->tx_ring[0].tx_consumer = 3257250661Sdavidcs qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr); 3258250661Sdavidcs tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS); 3259250661Sdavidcs 3260313070Sdavidcs tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]); 3261250661Sdavidcs tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0); 3262250661Sdavidcs 3263250661Sdavidcs hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS; 3264250661Sdavidcs hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0; 3265324325Sdavidcs *hw_tx_cntxt->tx_cons = 0; 3266250661Sdavidcs 3267250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3268250661Sdavidcs (sizeof (q80_rq_tx_cntxt_t) >> 2), 3269250661Sdavidcs ha->hw.mbox, 3270250661Sdavidcs (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) { 3271250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 3272250661Sdavidcs return (-1); 3273250661Sdavidcs } 3274250661Sdavidcs tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox; 3275250661Sdavidcs 3276250661Sdavidcs err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3277250661Sdavidcs 3278250661Sdavidcs if (err) { 3279250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3280250661Sdavidcs return -1; 3281250661Sdavidcs } 3282250661Sdavidcs 3283250661Sdavidcs hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index; 3284250661Sdavidcs hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id; 3285250661Sdavidcs 3286284741Sdavidcs if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0)) 3287284741Sdavidcs return (-1); 3288284741Sdavidcs 3289250661Sdavidcs return (0); 3290250661Sdavidcs} 3291250661Sdavidcs 3292250661Sdavidcs 3293250661Sdavidcs/* 3294250661Sdavidcs * Name: qla_del_xmt_cntxt 3295250661Sdavidcs * Function: Destroys the Transmit Context. 3296250661Sdavidcs */ 3297250661Sdavidcsstatic int 3298250661Sdavidcsqla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3299250661Sdavidcs{ 3300250661Sdavidcs device_t dev = ha->pci_dev; 3301250661Sdavidcs q80_tx_cntxt_destroy_t *tcntxt; 3302250661Sdavidcs q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp; 3303250661Sdavidcs uint32_t err; 3304250661Sdavidcs 3305250661Sdavidcs tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox; 3306250661Sdavidcs bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t))); 3307250661Sdavidcs 3308250661Sdavidcs tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT; 3309250661Sdavidcs tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2); 3310250661Sdavidcs tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3311250661Sdavidcs 3312250661Sdavidcs tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id; 3313250661Sdavidcs 3314250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3315250661Sdavidcs (sizeof (q80_tx_cntxt_destroy_t) >> 2), 3316250661Sdavidcs ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) { 3317250661Sdavidcs device_printf(dev, "%s: failed0\n", __func__); 3318250661Sdavidcs return (-1); 3319250661Sdavidcs } 3320250661Sdavidcs tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox; 3321250661Sdavidcs 3322250661Sdavidcs err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3323250661Sdavidcs 3324250661Sdavidcs if (err) { 3325250661Sdavidcs device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3326250661Sdavidcs return (-1); 3327250661Sdavidcs } 3328250661Sdavidcs 3329250661Sdavidcs return (0); 3330250661Sdavidcs} 3331250661Sdavidcsstatic void 3332250661Sdavidcsqla_del_xmt_cntxt(qla_host_t *ha) 3333250661Sdavidcs{ 3334250661Sdavidcs uint32_t i; 3335250661Sdavidcs 3336250661Sdavidcs if (!ha->hw.flags.init_tx_cnxt) 3337250661Sdavidcs return; 3338250661Sdavidcs 3339250661Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 3340250661Sdavidcs if (qla_del_xmt_cntxt_i(ha, i)) 3341250661Sdavidcs break; 3342250661Sdavidcs } 3343250661Sdavidcs ha->hw.flags.init_tx_cnxt = 0; 3344250661Sdavidcs} 3345250661Sdavidcs 3346250661Sdavidcsstatic int 3347250661Sdavidcsqla_init_xmt_cntxt(qla_host_t *ha) 3348250661Sdavidcs{ 3349250661Sdavidcs uint32_t i, j; 3350250661Sdavidcs 3351250661Sdavidcs for (i = 0; i < ha->hw.num_tx_rings; i++) { 3352250661Sdavidcs if (qla_init_xmt_cntxt_i(ha, i) != 0) { 3353250661Sdavidcs for (j = 0; j < i; j++) 3354250661Sdavidcs qla_del_xmt_cntxt_i(ha, j); 3355250661Sdavidcs return (-1); 3356250661Sdavidcs } 3357250661Sdavidcs } 3358250661Sdavidcs ha->hw.flags.init_tx_cnxt = 1; 3359250661Sdavidcs return (0); 3360250661Sdavidcs} 3361250661Sdavidcs 3362250661Sdavidcsstatic int 3363307524Sdavidcsqla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast) 3364250661Sdavidcs{ 3365250661Sdavidcs int i, nmcast; 3366307524Sdavidcs uint32_t count = 0; 3367307524Sdavidcs uint8_t *mcast; 3368250661Sdavidcs 3369250661Sdavidcs nmcast = ha->hw.nmcast; 3370250661Sdavidcs 3371307524Sdavidcs QL_DPRINT2(ha, (ha->pci_dev, 3372307524Sdavidcs "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast)); 3373307524Sdavidcs 3374307524Sdavidcs mcast = ha->hw.mac_addr_arr; 3375307524Sdavidcs memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3376307524Sdavidcs 3377250661Sdavidcs for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) { 3378250661Sdavidcs if ((ha->hw.mcast[i].addr[0] != 0) || 3379250661Sdavidcs (ha->hw.mcast[i].addr[1] != 0) || 3380250661Sdavidcs (ha->hw.mcast[i].addr[2] != 0) || 3381250661Sdavidcs (ha->hw.mcast[i].addr[3] != 0) || 3382250661Sdavidcs (ha->hw.mcast[i].addr[4] != 0) || 3383250661Sdavidcs (ha->hw.mcast[i].addr[5] != 0)) { 3384250661Sdavidcs 3385307524Sdavidcs bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN); 3386307524Sdavidcs mcast = mcast + ETHER_ADDR_LEN; 3387307524Sdavidcs count++; 3388307524Sdavidcs 3389307524Sdavidcs if (count == Q8_MAX_MAC_ADDRS) { 3390307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3391307524Sdavidcs add_mcast, count)) { 3392307524Sdavidcs device_printf(ha->pci_dev, 3393307524Sdavidcs "%s: failed\n", __func__); 3394307524Sdavidcs return (-1); 3395307524Sdavidcs } 3396307524Sdavidcs 3397307524Sdavidcs count = 0; 3398307524Sdavidcs mcast = ha->hw.mac_addr_arr; 3399307524Sdavidcs memset(mcast, 0, 3400307524Sdavidcs (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3401250661Sdavidcs } 3402250661Sdavidcs 3403250661Sdavidcs nmcast--; 3404250661Sdavidcs } 3405250661Sdavidcs } 3406307524Sdavidcs 3407307524Sdavidcs if (count) { 3408307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast, 3409307524Sdavidcs count)) { 3410307524Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 3411307524Sdavidcs return (-1); 3412307524Sdavidcs } 3413307524Sdavidcs } 3414307524Sdavidcs QL_DPRINT2(ha, (ha->pci_dev, 3415307524Sdavidcs "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast)); 3416307524Sdavidcs 3417250661Sdavidcs return 0; 3418250661Sdavidcs} 3419250661Sdavidcs 3420250661Sdavidcsstatic int 3421307524Sdavidcsqla_hw_add_all_mcast(qla_host_t *ha) 3422307524Sdavidcs{ 3423307524Sdavidcs int ret; 3424307524Sdavidcs 3425307524Sdavidcs ret = qla_hw_all_mcast(ha, 1); 3426307524Sdavidcs 3427307524Sdavidcs return (ret); 3428307524Sdavidcs} 3429307524Sdavidcs 3430324324Sdavidcsint 3431250661Sdavidcsqla_hw_del_all_mcast(qla_host_t *ha) 3432250661Sdavidcs{ 3433307524Sdavidcs int ret; 3434250661Sdavidcs 3435307524Sdavidcs ret = qla_hw_all_mcast(ha, 0); 3436250661Sdavidcs 3437307524Sdavidcs bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS)); 3438307524Sdavidcs ha->hw.nmcast = 0; 3439250661Sdavidcs 3440307524Sdavidcs return (ret); 3441250661Sdavidcs} 3442250661Sdavidcs 3443250661Sdavidcsstatic int 3444307524Sdavidcsqla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta) 3445250661Sdavidcs{ 3446250661Sdavidcs int i; 3447250661Sdavidcs 3448250661Sdavidcs for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3449250661Sdavidcs if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) 3450307524Sdavidcs return (0); /* its been already added */ 3451250661Sdavidcs } 3452307524Sdavidcs return (-1); 3453307524Sdavidcs} 3454250661Sdavidcs 3455307524Sdavidcsstatic int 3456307524Sdavidcsqla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3457307524Sdavidcs{ 3458307524Sdavidcs int i; 3459307524Sdavidcs 3460250661Sdavidcs for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3461250661Sdavidcs 3462250661Sdavidcs if ((ha->hw.mcast[i].addr[0] == 0) && 3463250661Sdavidcs (ha->hw.mcast[i].addr[1] == 0) && 3464250661Sdavidcs (ha->hw.mcast[i].addr[2] == 0) && 3465250661Sdavidcs (ha->hw.mcast[i].addr[3] == 0) && 3466250661Sdavidcs (ha->hw.mcast[i].addr[4] == 0) && 3467250661Sdavidcs (ha->hw.mcast[i].addr[5] == 0)) { 3468250661Sdavidcs 3469250661Sdavidcs bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN); 3470250661Sdavidcs ha->hw.nmcast++; 3471250661Sdavidcs 3472307524Sdavidcs mta = mta + ETHER_ADDR_LEN; 3473307524Sdavidcs nmcast--; 3474307524Sdavidcs 3475307524Sdavidcs if (nmcast == 0) 3476307524Sdavidcs break; 3477250661Sdavidcs } 3478307524Sdavidcs 3479250661Sdavidcs } 3480250661Sdavidcs return 0; 3481250661Sdavidcs} 3482250661Sdavidcs 3483250661Sdavidcsstatic int 3484307524Sdavidcsqla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3485250661Sdavidcs{ 3486250661Sdavidcs int i; 3487250661Sdavidcs 3488250661Sdavidcs for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3489250661Sdavidcs if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) { 3490250661Sdavidcs 3491250661Sdavidcs ha->hw.mcast[i].addr[0] = 0; 3492250661Sdavidcs ha->hw.mcast[i].addr[1] = 0; 3493250661Sdavidcs ha->hw.mcast[i].addr[2] = 0; 3494250661Sdavidcs ha->hw.mcast[i].addr[3] = 0; 3495250661Sdavidcs ha->hw.mcast[i].addr[4] = 0; 3496250661Sdavidcs ha->hw.mcast[i].addr[5] = 0; 3497250661Sdavidcs 3498250661Sdavidcs ha->hw.nmcast--; 3499250661Sdavidcs 3500307524Sdavidcs mta = mta + ETHER_ADDR_LEN; 3501307524Sdavidcs nmcast--; 3502307524Sdavidcs 3503307524Sdavidcs if (nmcast == 0) 3504307524Sdavidcs break; 3505250661Sdavidcs } 3506250661Sdavidcs } 3507250661Sdavidcs return 0; 3508250661Sdavidcs} 3509250661Sdavidcs 3510250661Sdavidcs/* 3511250661Sdavidcs * Name: ql_hw_set_multi 3512307524Sdavidcs * Function: Sets the Multicast Addresses provided by the host O.S into the 3513250661Sdavidcs * hardware (for the given interface) 3514250661Sdavidcs */ 3515250661Sdavidcsint 3516307524Sdavidcsql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt, 3517250661Sdavidcs uint32_t add_mac) 3518250661Sdavidcs{ 3519307524Sdavidcs uint8_t *mta = mcast_addr; 3520250661Sdavidcs int i; 3521250661Sdavidcs int ret = 0; 3522307524Sdavidcs uint32_t count = 0; 3523307524Sdavidcs uint8_t *mcast; 3524250661Sdavidcs 3525307524Sdavidcs mcast = ha->hw.mac_addr_arr; 3526307524Sdavidcs memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3527307524Sdavidcs 3528250661Sdavidcs for (i = 0; i < mcnt; i++) { 3529307524Sdavidcs if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) { 3530307524Sdavidcs if (add_mac) { 3531307524Sdavidcs if (qla_hw_mac_addr_present(ha, mta) != 0) { 3532307524Sdavidcs bcopy(mta, mcast, ETHER_ADDR_LEN); 3533307524Sdavidcs mcast = mcast + ETHER_ADDR_LEN; 3534307524Sdavidcs count++; 3535307524Sdavidcs } 3536307524Sdavidcs } else { 3537307524Sdavidcs if (qla_hw_mac_addr_present(ha, mta) == 0) { 3538307524Sdavidcs bcopy(mta, mcast, ETHER_ADDR_LEN); 3539307524Sdavidcs mcast = mcast + ETHER_ADDR_LEN; 3540307524Sdavidcs count++; 3541307524Sdavidcs } 3542307524Sdavidcs } 3543250661Sdavidcs } 3544307524Sdavidcs if (count == Q8_MAX_MAC_ADDRS) { 3545307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3546307524Sdavidcs add_mac, count)) { 3547307524Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", 3548307524Sdavidcs __func__); 3549307524Sdavidcs return (-1); 3550307524Sdavidcs } 3551307524Sdavidcs 3552307524Sdavidcs if (add_mac) { 3553307524Sdavidcs qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, 3554307524Sdavidcs count); 3555307524Sdavidcs } else { 3556307524Sdavidcs qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, 3557307524Sdavidcs count); 3558307524Sdavidcs } 3559307524Sdavidcs 3560307524Sdavidcs count = 0; 3561307524Sdavidcs mcast = ha->hw.mac_addr_arr; 3562307524Sdavidcs memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3563307524Sdavidcs } 3564250661Sdavidcs 3565250661Sdavidcs mta += Q8_MAC_ADDR_LEN; 3566250661Sdavidcs } 3567307524Sdavidcs 3568307524Sdavidcs if (count) { 3569307524Sdavidcs if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac, 3570307524Sdavidcs count)) { 3571307524Sdavidcs device_printf(ha->pci_dev, "%s: failed\n", __func__); 3572307524Sdavidcs return (-1); 3573307524Sdavidcs } 3574307524Sdavidcs if (add_mac) { 3575307524Sdavidcs qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count); 3576307524Sdavidcs } else { 3577307524Sdavidcs qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count); 3578307524Sdavidcs } 3579307524Sdavidcs } 3580307524Sdavidcs 3581250661Sdavidcs return (ret); 3582250661Sdavidcs} 3583250661Sdavidcs 3584250661Sdavidcs/* 3585313070Sdavidcs * Name: ql_hw_tx_done_locked 3586250661Sdavidcs * Function: Handle Transmit Completions 3587250661Sdavidcs */ 3588313070Sdavidcsvoid 3589313070Sdavidcsql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx) 3590250661Sdavidcs{ 3591250661Sdavidcs qla_tx_buf_t *txb; 3592250661Sdavidcs qla_hw_t *hw = &ha->hw; 3593250661Sdavidcs uint32_t comp_idx, comp_count = 0; 3594250661Sdavidcs qla_hw_tx_cntxt_t *hw_tx_cntxt; 3595250661Sdavidcs 3596250661Sdavidcs hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3597250661Sdavidcs 3598250661Sdavidcs /* retrieve index of last entry in tx ring completed */ 3599250661Sdavidcs comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons)); 3600250661Sdavidcs 3601250661Sdavidcs while (comp_idx != hw_tx_cntxt->txr_comp) { 3602250661Sdavidcs 3603250661Sdavidcs txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp]; 3604250661Sdavidcs 3605250661Sdavidcs hw_tx_cntxt->txr_comp++; 3606250661Sdavidcs if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS) 3607250661Sdavidcs hw_tx_cntxt->txr_comp = 0; 3608250661Sdavidcs 3609250661Sdavidcs comp_count++; 3610250661Sdavidcs 3611250661Sdavidcs if (txb->m_head) { 3612271849Sglebius if_inc_counter(ha->ifp, IFCOUNTER_OPACKETS, 1); 3613250661Sdavidcs 3614250661Sdavidcs bus_dmamap_sync(ha->tx_tag, txb->map, 3615250661Sdavidcs BUS_DMASYNC_POSTWRITE); 3616250661Sdavidcs bus_dmamap_unload(ha->tx_tag, txb->map); 3617250661Sdavidcs m_freem(txb->m_head); 3618250661Sdavidcs 3619250661Sdavidcs txb->m_head = NULL; 3620250661Sdavidcs } 3621250661Sdavidcs } 3622250661Sdavidcs 3623250661Sdavidcs hw_tx_cntxt->txr_free += comp_count; 3624250661Sdavidcs return; 3625250661Sdavidcs} 3626250661Sdavidcs 3627250661Sdavidcsvoid 3628250661Sdavidcsql_update_link_state(qla_host_t *ha) 3629250661Sdavidcs{ 3630250661Sdavidcs uint32_t link_state; 3631250661Sdavidcs uint32_t prev_link_state; 3632250661Sdavidcs 3633250661Sdavidcs if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3634250661Sdavidcs ha->hw.link_up = 0; 3635250661Sdavidcs return; 3636250661Sdavidcs } 3637250661Sdavidcs link_state = READ_REG32(ha, Q8_LINK_STATE); 3638250661Sdavidcs 3639250661Sdavidcs prev_link_state = ha->hw.link_up; 3640250661Sdavidcs 3641250661Sdavidcs if (ha->pci_func == 0) 3642250661Sdavidcs ha->hw.link_up = (((link_state & 0xF) == 1)? 1 : 0); 3643250661Sdavidcs else 3644250661Sdavidcs ha->hw.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0); 3645250661Sdavidcs 3646250661Sdavidcs if (prev_link_state != ha->hw.link_up) { 3647250661Sdavidcs if (ha->hw.link_up) { 3648250661Sdavidcs if_link_state_change(ha->ifp, LINK_STATE_UP); 3649250661Sdavidcs } else { 3650250661Sdavidcs if_link_state_change(ha->ifp, LINK_STATE_DOWN); 3651250661Sdavidcs } 3652250661Sdavidcs } 3653250661Sdavidcs return; 3654250661Sdavidcs} 3655250661Sdavidcs 3656250661Sdavidcsint 3657250661Sdavidcsql_hw_check_health(qla_host_t *ha) 3658250661Sdavidcs{ 3659250661Sdavidcs uint32_t val; 3660250661Sdavidcs 3661250661Sdavidcs ha->hw.health_count++; 3662250661Sdavidcs 3663321496Sdavidcs if (ha->hw.health_count < 500) 3664250661Sdavidcs return 0; 3665250661Sdavidcs 3666250661Sdavidcs ha->hw.health_count = 0; 3667250661Sdavidcs 3668250661Sdavidcs val = READ_REG32(ha, Q8_ASIC_TEMPERATURE); 3669250661Sdavidcs 3670250661Sdavidcs if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) || 3671250661Sdavidcs (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) { 3672250661Sdavidcs device_printf(ha->pci_dev, "%s: Temperature Alert [0x%08x]\n", 3673250661Sdavidcs __func__, val); 3674250661Sdavidcs return -1; 3675250661Sdavidcs } 3676250661Sdavidcs 3677250661Sdavidcs val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT); 3678250661Sdavidcs 3679250661Sdavidcs if ((val != ha->hw.hbeat_value) && 3680289635Sdavidcs (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) { 3681250661Sdavidcs ha->hw.hbeat_value = val; 3682321496Sdavidcs ha->hw.hbeat_failure = 0; 3683250661Sdavidcs return 0; 3684250661Sdavidcs } 3685250661Sdavidcs 3686321496Sdavidcs ha->hw.hbeat_failure++; 3687321496Sdavidcs 3688322972Sdavidcs 3689322972Sdavidcs if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1)) 3690322972Sdavidcs device_printf(ha->pci_dev, "%s: Heartbeat Failue 1[0x%08x]\n", 3691322972Sdavidcs __func__, val); 3692321496Sdavidcs if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */ 3693321496Sdavidcs return 0; 3694322972Sdavidcs else 3695321496Sdavidcs device_printf(ha->pci_dev, "%s: Heartbeat Failue [0x%08x]\n", 3696321496Sdavidcs __func__, val); 3697321496Sdavidcs 3698250661Sdavidcs return -1; 3699250661Sdavidcs} 3700250661Sdavidcs 3701250661Sdavidcsstatic int 3702284741Sdavidcsqla_init_nic_func(qla_host_t *ha) 3703284741Sdavidcs{ 3704284741Sdavidcs device_t dev; 3705284741Sdavidcs q80_init_nic_func_t *init_nic; 3706284741Sdavidcs q80_init_nic_func_rsp_t *init_nic_rsp; 3707284741Sdavidcs uint32_t err; 3708284741Sdavidcs 3709284741Sdavidcs dev = ha->pci_dev; 3710284741Sdavidcs 3711284741Sdavidcs init_nic = (q80_init_nic_func_t *)ha->hw.mbox; 3712284741Sdavidcs bzero(init_nic, sizeof(q80_init_nic_func_t)); 3713284741Sdavidcs 3714284741Sdavidcs init_nic->opcode = Q8_MBX_INIT_NIC_FUNC; 3715284741Sdavidcs init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2); 3716284741Sdavidcs init_nic->count_version |= Q8_MBX_CMD_VERSION; 3717284741Sdavidcs 3718284741Sdavidcs init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN; 3719284741Sdavidcs init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN; 3720284741Sdavidcs init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN; 3721284741Sdavidcs 3722284741Sdavidcs//qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t)); 3723284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)init_nic, 3724284741Sdavidcs (sizeof (q80_init_nic_func_t) >> 2), 3725284741Sdavidcs ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) { 3726284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3727284741Sdavidcs return -1; 3728284741Sdavidcs } 3729284741Sdavidcs 3730284741Sdavidcs init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox; 3731284741Sdavidcs// qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t)); 3732284741Sdavidcs 3733284741Sdavidcs err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status); 3734284741Sdavidcs 3735284741Sdavidcs if (err) { 3736284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3737284741Sdavidcs } 3738284741Sdavidcs 3739284741Sdavidcs return 0; 3740284741Sdavidcs} 3741284741Sdavidcs 3742284741Sdavidcsstatic int 3743284741Sdavidcsqla_stop_nic_func(qla_host_t *ha) 3744284741Sdavidcs{ 3745284741Sdavidcs device_t dev; 3746284741Sdavidcs q80_stop_nic_func_t *stop_nic; 3747284741Sdavidcs q80_stop_nic_func_rsp_t *stop_nic_rsp; 3748284741Sdavidcs uint32_t err; 3749284741Sdavidcs 3750284741Sdavidcs dev = ha->pci_dev; 3751284741Sdavidcs 3752284741Sdavidcs stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox; 3753284741Sdavidcs bzero(stop_nic, sizeof(q80_stop_nic_func_t)); 3754284741Sdavidcs 3755284741Sdavidcs stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC; 3756284741Sdavidcs stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2); 3757284741Sdavidcs stop_nic->count_version |= Q8_MBX_CMD_VERSION; 3758284741Sdavidcs 3759284741Sdavidcs stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN; 3760284741Sdavidcs stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN; 3761284741Sdavidcs 3762284741Sdavidcs//qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t)); 3763284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)stop_nic, 3764284741Sdavidcs (sizeof (q80_stop_nic_func_t) >> 2), 3765284741Sdavidcs ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) { 3766284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3767284741Sdavidcs return -1; 3768284741Sdavidcs } 3769284741Sdavidcs 3770284741Sdavidcs stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox; 3771284741Sdavidcs//qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t)); 3772284741Sdavidcs 3773284741Sdavidcs err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status); 3774284741Sdavidcs 3775284741Sdavidcs if (err) { 3776284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3777284741Sdavidcs } 3778284741Sdavidcs 3779284741Sdavidcs return 0; 3780284741Sdavidcs} 3781284741Sdavidcs 3782284741Sdavidcsstatic int 3783284741Sdavidcsqla_query_fw_dcbx_caps(qla_host_t *ha) 3784284741Sdavidcs{ 3785284741Sdavidcs device_t dev; 3786284741Sdavidcs q80_query_fw_dcbx_caps_t *fw_dcbx; 3787284741Sdavidcs q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp; 3788284741Sdavidcs uint32_t err; 3789284741Sdavidcs 3790284741Sdavidcs dev = ha->pci_dev; 3791284741Sdavidcs 3792284741Sdavidcs fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox; 3793284741Sdavidcs bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t)); 3794284741Sdavidcs 3795284741Sdavidcs fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS; 3796284741Sdavidcs fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2); 3797284741Sdavidcs fw_dcbx->count_version |= Q8_MBX_CMD_VERSION; 3798284741Sdavidcs 3799284741Sdavidcs ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t)); 3800284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx, 3801284741Sdavidcs (sizeof (q80_query_fw_dcbx_caps_t) >> 2), 3802284741Sdavidcs ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) { 3803284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3804284741Sdavidcs return -1; 3805284741Sdavidcs } 3806284741Sdavidcs 3807284741Sdavidcs fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox; 3808284741Sdavidcs ql_dump_buf8(ha, __func__, fw_dcbx_rsp, 3809284741Sdavidcs sizeof (q80_query_fw_dcbx_caps_rsp_t)); 3810284741Sdavidcs 3811284741Sdavidcs err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status); 3812284741Sdavidcs 3813284741Sdavidcs if (err) { 3814284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3815284741Sdavidcs } 3816284741Sdavidcs 3817284741Sdavidcs return 0; 3818284741Sdavidcs} 3819284741Sdavidcs 3820284741Sdavidcsstatic int 3821284741Sdavidcsqla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2, 3822284741Sdavidcs uint32_t aen_mb3, uint32_t aen_mb4) 3823284741Sdavidcs{ 3824284741Sdavidcs device_t dev; 3825284741Sdavidcs q80_idc_ack_t *idc_ack; 3826284741Sdavidcs q80_idc_ack_rsp_t *idc_ack_rsp; 3827284741Sdavidcs uint32_t err; 3828284741Sdavidcs int count = 300; 3829284741Sdavidcs 3830284741Sdavidcs dev = ha->pci_dev; 3831284741Sdavidcs 3832284741Sdavidcs idc_ack = (q80_idc_ack_t *)ha->hw.mbox; 3833284741Sdavidcs bzero(idc_ack, sizeof(q80_idc_ack_t)); 3834284741Sdavidcs 3835284741Sdavidcs idc_ack->opcode = Q8_MBX_IDC_ACK; 3836284741Sdavidcs idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2); 3837284741Sdavidcs idc_ack->count_version |= Q8_MBX_CMD_VERSION; 3838284741Sdavidcs 3839284741Sdavidcs idc_ack->aen_mb1 = aen_mb1; 3840284741Sdavidcs idc_ack->aen_mb2 = aen_mb2; 3841284741Sdavidcs idc_ack->aen_mb3 = aen_mb3; 3842284741Sdavidcs idc_ack->aen_mb4 = aen_mb4; 3843284741Sdavidcs 3844284741Sdavidcs ha->hw.imd_compl= 0; 3845284741Sdavidcs 3846284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)idc_ack, 3847284741Sdavidcs (sizeof (q80_idc_ack_t) >> 2), 3848284741Sdavidcs ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) { 3849284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3850284741Sdavidcs return -1; 3851284741Sdavidcs } 3852284741Sdavidcs 3853284741Sdavidcs idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox; 3854284741Sdavidcs 3855284741Sdavidcs err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status); 3856284741Sdavidcs 3857284741Sdavidcs if (err) { 3858284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3859284741Sdavidcs return(-1); 3860284741Sdavidcs } 3861284741Sdavidcs 3862284741Sdavidcs while (count && !ha->hw.imd_compl) { 3863284741Sdavidcs qla_mdelay(__func__, 100); 3864284741Sdavidcs count--; 3865284741Sdavidcs } 3866284741Sdavidcs 3867284741Sdavidcs if (!count) 3868284741Sdavidcs return -1; 3869284741Sdavidcs else 3870284741Sdavidcs device_printf(dev, "%s: count %d\n", __func__, count); 3871284741Sdavidcs 3872284741Sdavidcs return (0); 3873284741Sdavidcs} 3874284741Sdavidcs 3875284741Sdavidcsstatic int 3876284741Sdavidcsqla_set_port_config(qla_host_t *ha, uint32_t cfg_bits) 3877284741Sdavidcs{ 3878284741Sdavidcs device_t dev; 3879284741Sdavidcs q80_set_port_cfg_t *pcfg; 3880284741Sdavidcs q80_set_port_cfg_rsp_t *pfg_rsp; 3881284741Sdavidcs uint32_t err; 3882284741Sdavidcs int count = 300; 3883284741Sdavidcs 3884284741Sdavidcs dev = ha->pci_dev; 3885284741Sdavidcs 3886284741Sdavidcs pcfg = (q80_set_port_cfg_t *)ha->hw.mbox; 3887284741Sdavidcs bzero(pcfg, sizeof(q80_set_port_cfg_t)); 3888284741Sdavidcs 3889284741Sdavidcs pcfg->opcode = Q8_MBX_SET_PORT_CONFIG; 3890284741Sdavidcs pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2); 3891284741Sdavidcs pcfg->count_version |= Q8_MBX_CMD_VERSION; 3892284741Sdavidcs 3893284741Sdavidcs pcfg->cfg_bits = cfg_bits; 3894284741Sdavidcs 3895284741Sdavidcs device_printf(dev, "%s: cfg_bits" 3896284741Sdavidcs " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 3897284741Sdavidcs " [0x%x, 0x%x, 0x%x]\n", __func__, 3898284741Sdavidcs ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 3899284741Sdavidcs ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 3900284741Sdavidcs ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)); 3901284741Sdavidcs 3902284741Sdavidcs ha->hw.imd_compl= 0; 3903284741Sdavidcs 3904284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 3905284741Sdavidcs (sizeof (q80_set_port_cfg_t) >> 2), 3906284741Sdavidcs ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) { 3907284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3908284741Sdavidcs return -1; 3909284741Sdavidcs } 3910284741Sdavidcs 3911284741Sdavidcs pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox; 3912284741Sdavidcs 3913284741Sdavidcs err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status); 3914284741Sdavidcs 3915284741Sdavidcs if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) { 3916284741Sdavidcs while (count && !ha->hw.imd_compl) { 3917284741Sdavidcs qla_mdelay(__func__, 100); 3918284741Sdavidcs count--; 3919284741Sdavidcs } 3920284741Sdavidcs if (count) { 3921284741Sdavidcs device_printf(dev, "%s: count %d\n", __func__, count); 3922284741Sdavidcs 3923284741Sdavidcs err = 0; 3924284741Sdavidcs } 3925284741Sdavidcs } 3926284741Sdavidcs 3927284741Sdavidcs if (err) { 3928284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3929284741Sdavidcs return(-1); 3930284741Sdavidcs } 3931284741Sdavidcs 3932284741Sdavidcs return (0); 3933284741Sdavidcs} 3934284741Sdavidcs 3935284741Sdavidcs 3936284741Sdavidcsstatic int 3937250661Sdavidcsqla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size) 3938250661Sdavidcs{ 3939250661Sdavidcs uint32_t err; 3940250661Sdavidcs device_t dev = ha->pci_dev; 3941250661Sdavidcs q80_config_md_templ_size_t *md_size; 3942250661Sdavidcs q80_config_md_templ_size_rsp_t *md_size_rsp; 3943250661Sdavidcs 3944305487Sdavidcs#ifndef QL_LDFLASH_FW 3945284741Sdavidcs 3946305487Sdavidcs ql_minidump_template_hdr_t *hdr; 3947305487Sdavidcs 3948305487Sdavidcs hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump; 3949305487Sdavidcs *size = hdr->size_of_template; 3950284741Sdavidcs return (0); 3951284741Sdavidcs 3952284741Sdavidcs#endif /* #ifdef QL_LDFLASH_FW */ 3953284741Sdavidcs 3954250661Sdavidcs md_size = (q80_config_md_templ_size_t *) ha->hw.mbox; 3955250661Sdavidcs bzero(md_size, sizeof(q80_config_md_templ_size_t)); 3956250661Sdavidcs 3957250661Sdavidcs md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE; 3958250661Sdavidcs md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2); 3959250661Sdavidcs md_size->count_version |= Q8_MBX_CMD_VERSION; 3960250661Sdavidcs 3961250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *) md_size, 3962250661Sdavidcs (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox, 3963250661Sdavidcs (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) { 3964250661Sdavidcs 3965250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 3966250661Sdavidcs 3967250661Sdavidcs return (-1); 3968250661Sdavidcs } 3969250661Sdavidcs 3970250661Sdavidcs md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox; 3971250661Sdavidcs 3972250661Sdavidcs err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status); 3973250661Sdavidcs 3974250661Sdavidcs if (err) { 3975250661Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3976250661Sdavidcs return(-1); 3977250661Sdavidcs } 3978250661Sdavidcs 3979250661Sdavidcs *size = md_size_rsp->templ_size; 3980250661Sdavidcs 3981250661Sdavidcs return (0); 3982250661Sdavidcs} 3983250661Sdavidcs 3984250661Sdavidcsstatic int 3985284741Sdavidcsqla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits) 3986284741Sdavidcs{ 3987284741Sdavidcs device_t dev; 3988284741Sdavidcs q80_get_port_cfg_t *pcfg; 3989284741Sdavidcs q80_get_port_cfg_rsp_t *pcfg_rsp; 3990284741Sdavidcs uint32_t err; 3991284741Sdavidcs 3992284741Sdavidcs dev = ha->pci_dev; 3993284741Sdavidcs 3994284741Sdavidcs pcfg = (q80_get_port_cfg_t *)ha->hw.mbox; 3995284741Sdavidcs bzero(pcfg, sizeof(q80_get_port_cfg_t)); 3996284741Sdavidcs 3997284741Sdavidcs pcfg->opcode = Q8_MBX_GET_PORT_CONFIG; 3998284741Sdavidcs pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2); 3999284741Sdavidcs pcfg->count_version |= Q8_MBX_CMD_VERSION; 4000284741Sdavidcs 4001284741Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 4002284741Sdavidcs (sizeof (q80_get_port_cfg_t) >> 2), 4003284741Sdavidcs ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) { 4004284741Sdavidcs device_printf(dev, "%s: failed\n", __func__); 4005284741Sdavidcs return -1; 4006284741Sdavidcs } 4007284741Sdavidcs 4008284741Sdavidcs pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox; 4009284741Sdavidcs 4010284741Sdavidcs err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status); 4011284741Sdavidcs 4012284741Sdavidcs if (err) { 4013284741Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4014284741Sdavidcs return(-1); 4015284741Sdavidcs } 4016284741Sdavidcs 4017284741Sdavidcs device_printf(dev, "%s: [cfg_bits, port type]" 4018284741Sdavidcs " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 4019284741Sdavidcs " [0x%x, 0x%x, 0x%x]\n", __func__, 4020284741Sdavidcs pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type, 4021284741Sdavidcs ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 4022284741Sdavidcs ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 4023284741Sdavidcs ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0) 4024284741Sdavidcs ); 4025284741Sdavidcs 4026284741Sdavidcs *cfg_bits = pcfg_rsp->cfg_bits; 4027284741Sdavidcs 4028284741Sdavidcs return (0); 4029284741Sdavidcs} 4030284741Sdavidcs 4031284741Sdavidcsint 4032313070Sdavidcsql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp) 4033284741Sdavidcs{ 4034284741Sdavidcs struct ether_vlan_header *eh; 4035284741Sdavidcs uint16_t etype; 4036284741Sdavidcs struct ip *ip = NULL; 4037284741Sdavidcs struct ip6_hdr *ip6 = NULL; 4038284741Sdavidcs struct tcphdr *th = NULL; 4039284741Sdavidcs uint32_t hdrlen; 4040284741Sdavidcs uint32_t offset; 4041284741Sdavidcs uint8_t buf[sizeof(struct ip6_hdr)]; 4042284741Sdavidcs 4043284741Sdavidcs eh = mtod(mp, struct ether_vlan_header *); 4044284741Sdavidcs 4045284741Sdavidcs if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4046284741Sdavidcs hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4047284741Sdavidcs etype = ntohs(eh->evl_proto); 4048284741Sdavidcs } else { 4049284741Sdavidcs hdrlen = ETHER_HDR_LEN; 4050284741Sdavidcs etype = ntohs(eh->evl_encap_proto); 4051284741Sdavidcs } 4052284741Sdavidcs 4053284741Sdavidcs if (etype == ETHERTYPE_IP) { 4054284741Sdavidcs 4055284741Sdavidcs offset = (hdrlen + sizeof (struct ip)); 4056284741Sdavidcs 4057284741Sdavidcs if (mp->m_len >= offset) { 4058284741Sdavidcs ip = (struct ip *)(mp->m_data + hdrlen); 4059284741Sdavidcs } else { 4060284741Sdavidcs m_copydata(mp, hdrlen, sizeof (struct ip), buf); 4061284741Sdavidcs ip = (struct ip *)buf; 4062284741Sdavidcs } 4063284741Sdavidcs 4064284741Sdavidcs if (ip->ip_p == IPPROTO_TCP) { 4065284741Sdavidcs 4066284741Sdavidcs hdrlen += ip->ip_hl << 2; 4067284741Sdavidcs offset = hdrlen + 4; 4068284741Sdavidcs 4069284741Sdavidcs if (mp->m_len >= offset) { 4070305487Sdavidcs th = (struct tcphdr *)(mp->m_data + hdrlen);; 4071284741Sdavidcs } else { 4072284741Sdavidcs m_copydata(mp, hdrlen, 4, buf); 4073284741Sdavidcs th = (struct tcphdr *)buf; 4074284741Sdavidcs } 4075284741Sdavidcs } 4076284741Sdavidcs 4077284741Sdavidcs } else if (etype == ETHERTYPE_IPV6) { 4078284741Sdavidcs 4079284741Sdavidcs offset = (hdrlen + sizeof (struct ip6_hdr)); 4080284741Sdavidcs 4081284741Sdavidcs if (mp->m_len >= offset) { 4082284741Sdavidcs ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen); 4083284741Sdavidcs } else { 4084284741Sdavidcs m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf); 4085284741Sdavidcs ip6 = (struct ip6_hdr *)buf; 4086284741Sdavidcs } 4087284741Sdavidcs 4088284741Sdavidcs if (ip6->ip6_nxt == IPPROTO_TCP) { 4089284741Sdavidcs 4090284741Sdavidcs hdrlen += sizeof(struct ip6_hdr); 4091284741Sdavidcs offset = hdrlen + 4; 4092284741Sdavidcs 4093284741Sdavidcs if (mp->m_len >= offset) { 4094305487Sdavidcs th = (struct tcphdr *)(mp->m_data + hdrlen);; 4095284741Sdavidcs } else { 4096284741Sdavidcs m_copydata(mp, hdrlen, 4, buf); 4097284741Sdavidcs th = (struct tcphdr *)buf; 4098284741Sdavidcs } 4099284741Sdavidcs } 4100284741Sdavidcs } 4101284741Sdavidcs 4102284741Sdavidcs if (th != NULL) { 4103284741Sdavidcs if ((th->th_sport == htons(3260)) || 4104284741Sdavidcs (th->th_dport == htons(3260))) 4105284741Sdavidcs return 0; 4106284741Sdavidcs } 4107284741Sdavidcs return (-1); 4108284741Sdavidcs} 4109284741Sdavidcs 4110284741Sdavidcsvoid 4111284741Sdavidcsqla_hw_async_event(qla_host_t *ha) 4112284741Sdavidcs{ 4113284741Sdavidcs switch (ha->hw.aen_mb0) { 4114284741Sdavidcs case 0x8101: 4115284741Sdavidcs (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2, 4116284741Sdavidcs ha->hw.aen_mb3, ha->hw.aen_mb4); 4117284741Sdavidcs 4118284741Sdavidcs break; 4119284741Sdavidcs 4120284741Sdavidcs default: 4121284741Sdavidcs break; 4122284741Sdavidcs } 4123284741Sdavidcs 4124284741Sdavidcs return; 4125284741Sdavidcs} 4126284741Sdavidcs 4127284741Sdavidcs#ifdef QL_LDFLASH_FW 4128284741Sdavidcsstatic int 4129305487Sdavidcsql_get_minidump_template(qla_host_t *ha) 4130250661Sdavidcs{ 4131250661Sdavidcs uint32_t err; 4132250661Sdavidcs device_t dev = ha->pci_dev; 4133250661Sdavidcs q80_config_md_templ_cmd_t *md_templ; 4134250661Sdavidcs q80_config_md_templ_cmd_rsp_t *md_templ_rsp; 4135250661Sdavidcs 4136250661Sdavidcs md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox; 4137250661Sdavidcs bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t))); 4138250661Sdavidcs 4139250661Sdavidcs md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT; 4140250661Sdavidcs md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2); 4141250661Sdavidcs md_templ->count_version |= Q8_MBX_CMD_VERSION; 4142250661Sdavidcs 4143250661Sdavidcs md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr; 4144250661Sdavidcs md_templ->buff_size = ha->hw.dma_buf.minidump.size; 4145250661Sdavidcs 4146250661Sdavidcs if (qla_mbx_cmd(ha, (uint32_t *) md_templ, 4147250661Sdavidcs (sizeof(q80_config_md_templ_cmd_t) >> 2), 4148250661Sdavidcs ha->hw.mbox, 4149250661Sdavidcs (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) { 4150250661Sdavidcs 4151250661Sdavidcs device_printf(dev, "%s: failed\n", __func__); 4152250661Sdavidcs 4153250661Sdavidcs return (-1); 4154250661Sdavidcs } 4155250661Sdavidcs 4156250661Sdavidcs md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox; 4157250661Sdavidcs 4158250661Sdavidcs err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status); 4159250661Sdavidcs 4160250661Sdavidcs if (err) { 4161250661Sdavidcs device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4162250661Sdavidcs return (-1); 4163250661Sdavidcs } 4164250661Sdavidcs 4165250661Sdavidcs return (0); 4166250661Sdavidcs 4167250661Sdavidcs} 4168284741Sdavidcs#endif /* #ifdef QL_LDFLASH_FW */ 4169250661Sdavidcs 4170305487Sdavidcs/* 4171305487Sdavidcs * Minidump related functionality 4172305487Sdavidcs */ 4173305487Sdavidcs 4174305487Sdavidcsstatic int ql_parse_template(qla_host_t *ha); 4175305487Sdavidcs 4176305487Sdavidcsstatic uint32_t ql_rdcrb(qla_host_t *ha, 4177305487Sdavidcs ql_minidump_entry_rdcrb_t *crb_entry, 4178305487Sdavidcs uint32_t * data_buff); 4179305487Sdavidcs 4180305487Sdavidcsstatic uint32_t ql_pollrd(qla_host_t *ha, 4181305487Sdavidcs ql_minidump_entry_pollrd_t *entry, 4182305487Sdavidcs uint32_t * data_buff); 4183305487Sdavidcs 4184305487Sdavidcsstatic uint32_t ql_pollrd_modify_write(qla_host_t *ha, 4185305487Sdavidcs ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 4186305487Sdavidcs uint32_t *data_buff); 4187305487Sdavidcs 4188305487Sdavidcsstatic uint32_t ql_L2Cache(qla_host_t *ha, 4189305487Sdavidcs ql_minidump_entry_cache_t *cacheEntry, 4190305487Sdavidcs uint32_t * data_buff); 4191305487Sdavidcs 4192305487Sdavidcsstatic uint32_t ql_L1Cache(qla_host_t *ha, 4193305487Sdavidcs ql_minidump_entry_cache_t *cacheEntry, 4194305487Sdavidcs uint32_t *data_buff); 4195305487Sdavidcs 4196305487Sdavidcsstatic uint32_t ql_rdocm(qla_host_t *ha, 4197305487Sdavidcs ql_minidump_entry_rdocm_t *ocmEntry, 4198305487Sdavidcs uint32_t *data_buff); 4199305487Sdavidcs 4200305487Sdavidcsstatic uint32_t ql_rdmem(qla_host_t *ha, 4201305487Sdavidcs ql_minidump_entry_rdmem_t *mem_entry, 4202305487Sdavidcs uint32_t *data_buff); 4203305487Sdavidcs 4204305487Sdavidcsstatic uint32_t ql_rdrom(qla_host_t *ha, 4205305487Sdavidcs ql_minidump_entry_rdrom_t *romEntry, 4206305487Sdavidcs uint32_t *data_buff); 4207305487Sdavidcs 4208305487Sdavidcsstatic uint32_t ql_rdmux(qla_host_t *ha, 4209305487Sdavidcs ql_minidump_entry_mux_t *muxEntry, 4210305487Sdavidcs uint32_t *data_buff); 4211305487Sdavidcs 4212305487Sdavidcsstatic uint32_t ql_rdmux2(qla_host_t *ha, 4213305487Sdavidcs ql_minidump_entry_mux2_t *muxEntry, 4214305487Sdavidcs uint32_t *data_buff); 4215305487Sdavidcs 4216305487Sdavidcsstatic uint32_t ql_rdqueue(qla_host_t *ha, 4217305487Sdavidcs ql_minidump_entry_queue_t *queueEntry, 4218305487Sdavidcs uint32_t *data_buff); 4219305487Sdavidcs 4220305487Sdavidcsstatic uint32_t ql_cntrl(qla_host_t *ha, 4221305487Sdavidcs ql_minidump_template_hdr_t *template_hdr, 4222305487Sdavidcs ql_minidump_entry_cntrl_t *crbEntry); 4223305487Sdavidcs 4224305487Sdavidcs 4225305487Sdavidcsstatic uint32_t 4226305487Sdavidcsql_minidump_size(qla_host_t *ha) 4227305487Sdavidcs{ 4228305487Sdavidcs uint32_t i, k; 4229305487Sdavidcs uint32_t size = 0; 4230305487Sdavidcs ql_minidump_template_hdr_t *hdr; 4231305487Sdavidcs 4232305487Sdavidcs hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b; 4233305487Sdavidcs 4234305487Sdavidcs i = 0x2; 4235305487Sdavidcs 4236305487Sdavidcs for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) { 4237305487Sdavidcs if (i & ha->hw.mdump_capture_mask) 4238305487Sdavidcs size += hdr->capture_size_array[k]; 4239305487Sdavidcs i = i << 1; 4240305487Sdavidcs } 4241305487Sdavidcs return (size); 4242305487Sdavidcs} 4243305487Sdavidcs 4244305487Sdavidcsstatic void 4245305487Sdavidcsql_free_minidump_buffer(qla_host_t *ha) 4246305487Sdavidcs{ 4247305487Sdavidcs if (ha->hw.mdump_buffer != NULL) { 4248305487Sdavidcs free(ha->hw.mdump_buffer, M_QLA83XXBUF); 4249305487Sdavidcs ha->hw.mdump_buffer = NULL; 4250305487Sdavidcs ha->hw.mdump_buffer_size = 0; 4251305487Sdavidcs } 4252305487Sdavidcs return; 4253305487Sdavidcs} 4254305487Sdavidcs 4255250661Sdavidcsstatic int 4256305487Sdavidcsql_alloc_minidump_buffer(qla_host_t *ha) 4257250661Sdavidcs{ 4258305487Sdavidcs ha->hw.mdump_buffer_size = ql_minidump_size(ha); 4259305487Sdavidcs 4260305487Sdavidcs if (!ha->hw.mdump_buffer_size) 4261305487Sdavidcs return (-1); 4262305487Sdavidcs 4263305487Sdavidcs ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF, 4264305487Sdavidcs M_NOWAIT); 4265305487Sdavidcs 4266305487Sdavidcs if (ha->hw.mdump_buffer == NULL) 4267305487Sdavidcs return (-1); 4268305487Sdavidcs 4269305487Sdavidcs return (0); 4270305487Sdavidcs} 4271305487Sdavidcs 4272305487Sdavidcsstatic void 4273305487Sdavidcsql_free_minidump_template_buffer(qla_host_t *ha) 4274305487Sdavidcs{ 4275305487Sdavidcs if (ha->hw.mdump_template != NULL) { 4276305487Sdavidcs free(ha->hw.mdump_template, M_QLA83XXBUF); 4277305487Sdavidcs ha->hw.mdump_template = NULL; 4278305487Sdavidcs ha->hw.mdump_template_size = 0; 4279305487Sdavidcs } 4280305487Sdavidcs return; 4281305487Sdavidcs} 4282305487Sdavidcs 4283305487Sdavidcsstatic int 4284305487Sdavidcsql_alloc_minidump_template_buffer(qla_host_t *ha) 4285305487Sdavidcs{ 4286305487Sdavidcs ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size; 4287305487Sdavidcs 4288305487Sdavidcs ha->hw.mdump_template = malloc(ha->hw.mdump_template_size, 4289305487Sdavidcs M_QLA83XXBUF, M_NOWAIT); 4290305487Sdavidcs 4291305487Sdavidcs if (ha->hw.mdump_template == NULL) 4292305487Sdavidcs return (-1); 4293305487Sdavidcs 4294305487Sdavidcs return (0); 4295305487Sdavidcs} 4296305487Sdavidcs 4297305487Sdavidcsstatic int 4298305487Sdavidcsql_alloc_minidump_buffers(qla_host_t *ha) 4299305487Sdavidcs{ 4300305487Sdavidcs int ret; 4301305487Sdavidcs 4302305487Sdavidcs ret = ql_alloc_minidump_template_buffer(ha); 4303305487Sdavidcs 4304305487Sdavidcs if (ret) 4305305487Sdavidcs return (ret); 4306305487Sdavidcs 4307305487Sdavidcs ret = ql_alloc_minidump_buffer(ha); 4308305487Sdavidcs 4309305487Sdavidcs if (ret) 4310305487Sdavidcs ql_free_minidump_template_buffer(ha); 4311305487Sdavidcs 4312305487Sdavidcs return (ret); 4313305487Sdavidcs} 4314305487Sdavidcs 4315305487Sdavidcs 4316305487Sdavidcsstatic uint32_t 4317305487Sdavidcsql_validate_minidump_checksum(qla_host_t *ha) 4318305487Sdavidcs{ 4319305487Sdavidcs uint64_t sum = 0; 4320305487Sdavidcs int count; 4321305487Sdavidcs uint32_t *template_buff; 4322305487Sdavidcs 4323305487Sdavidcs count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t); 4324305487Sdavidcs template_buff = ha->hw.dma_buf.minidump.dma_b; 4325305487Sdavidcs 4326305487Sdavidcs while (count-- > 0) { 4327305487Sdavidcs sum += *template_buff++; 4328305487Sdavidcs } 4329305487Sdavidcs 4330305487Sdavidcs while (sum >> 32) { 4331305487Sdavidcs sum = (sum & 0xFFFFFFFF) + (sum >> 32); 4332305487Sdavidcs } 4333305487Sdavidcs 4334305487Sdavidcs return (~sum); 4335305487Sdavidcs} 4336305487Sdavidcs 4337305487Sdavidcsint 4338305487Sdavidcsql_minidump_init(qla_host_t *ha) 4339305487Sdavidcs{ 4340284741Sdavidcs int ret = 0; 4341250661Sdavidcs uint32_t template_size = 0; 4342250661Sdavidcs device_t dev = ha->pci_dev; 4343250661Sdavidcs 4344250661Sdavidcs /* 4345250661Sdavidcs * Get Minidump Template Size 4346250661Sdavidcs */ 4347250661Sdavidcs ret = qla_get_minidump_tmplt_size(ha, &template_size); 4348250661Sdavidcs 4349250661Sdavidcs if (ret || (template_size == 0)) { 4350250661Sdavidcs device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret, 4351250661Sdavidcs template_size); 4352250661Sdavidcs return (-1); 4353250661Sdavidcs } 4354250661Sdavidcs 4355250661Sdavidcs /* 4356250661Sdavidcs * Allocate Memory for Minidump Template 4357250661Sdavidcs */ 4358250661Sdavidcs 4359250661Sdavidcs ha->hw.dma_buf.minidump.alignment = 8; 4360250661Sdavidcs ha->hw.dma_buf.minidump.size = template_size; 4361250661Sdavidcs 4362284741Sdavidcs#ifdef QL_LDFLASH_FW 4363250661Sdavidcs if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) { 4364250661Sdavidcs 4365250661Sdavidcs device_printf(dev, "%s: minidump dma alloc failed\n", __func__); 4366250661Sdavidcs 4367250661Sdavidcs return (-1); 4368250661Sdavidcs } 4369250661Sdavidcs ha->hw.dma_buf.flags.minidump = 1; 4370250661Sdavidcs 4371250661Sdavidcs /* 4372250661Sdavidcs * Retrieve Minidump Template 4373250661Sdavidcs */ 4374305487Sdavidcs ret = ql_get_minidump_template(ha); 4375284741Sdavidcs#else 4376284741Sdavidcs ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump; 4377305487Sdavidcs 4378284741Sdavidcs#endif /* #ifdef QL_LDFLASH_FW */ 4379250661Sdavidcs 4380305487Sdavidcs if (ret == 0) { 4381305487Sdavidcs 4382305487Sdavidcs ret = ql_validate_minidump_checksum(ha); 4383305487Sdavidcs 4384305487Sdavidcs if (ret == 0) { 4385305487Sdavidcs 4386305487Sdavidcs ret = ql_alloc_minidump_buffers(ha); 4387305487Sdavidcs 4388305487Sdavidcs if (ret == 0) 4389305487Sdavidcs ha->hw.mdump_init = 1; 4390305487Sdavidcs else 4391305487Sdavidcs device_printf(dev, 4392305487Sdavidcs "%s: ql_alloc_minidump_buffers" 4393305487Sdavidcs " failed\n", __func__); 4394305487Sdavidcs } else { 4395305487Sdavidcs device_printf(dev, "%s: ql_validate_minidump_checksum" 4396305487Sdavidcs " failed\n", __func__); 4397305487Sdavidcs } 4398250661Sdavidcs } else { 4399305487Sdavidcs device_printf(dev, "%s: ql_get_minidump_template failed\n", 4400305487Sdavidcs __func__); 4401250661Sdavidcs } 4402250661Sdavidcs 4403305487Sdavidcs if (ret) 4404305487Sdavidcs ql_minidump_free(ha); 4405305487Sdavidcs 4406250661Sdavidcs return (ret); 4407250661Sdavidcs} 4408250661Sdavidcs 4409250661Sdavidcsstatic void 4410305487Sdavidcsql_minidump_free(qla_host_t *ha) 4411250661Sdavidcs{ 4412250661Sdavidcs ha->hw.mdump_init = 0; 4413250661Sdavidcs if (ha->hw.dma_buf.flags.minidump) { 4414250661Sdavidcs ha->hw.dma_buf.flags.minidump = 0; 4415250661Sdavidcs ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump); 4416250661Sdavidcs } 4417305487Sdavidcs 4418305487Sdavidcs ql_free_minidump_template_buffer(ha); 4419305487Sdavidcs ql_free_minidump_buffer(ha); 4420305487Sdavidcs 4421250661Sdavidcs return; 4422250661Sdavidcs} 4423250661Sdavidcs 4424250661Sdavidcsvoid 4425250661Sdavidcsql_minidump(qla_host_t *ha) 4426250661Sdavidcs{ 4427250661Sdavidcs if (!ha->hw.mdump_init) 4428250661Sdavidcs return; 4429250661Sdavidcs 4430305487Sdavidcs if (ha->hw.mdump_done) 4431250661Sdavidcs return; 4432250661Sdavidcs 4433250661Sdavidcs ha->hw.mdump_start_seq_index = ql_stop_sequence(ha); 4434250661Sdavidcs 4435305487Sdavidcs bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size); 4436305487Sdavidcs bzero(ha->hw.mdump_template, ha->hw.mdump_template_size); 4437305487Sdavidcs 4438305487Sdavidcs bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template, 4439305487Sdavidcs ha->hw.mdump_template_size); 4440305487Sdavidcs 4441305487Sdavidcs ql_parse_template(ha); 4442305487Sdavidcs 4443250661Sdavidcs ql_start_sequence(ha, ha->hw.mdump_start_seq_index); 4444250661Sdavidcs 4445305487Sdavidcs ha->hw.mdump_done = 1; 4446305487Sdavidcs 4447250661Sdavidcs return; 4448250661Sdavidcs} 4449305487Sdavidcs 4450305487Sdavidcs 4451305487Sdavidcs/* 4452305487Sdavidcs * helper routines 4453305487Sdavidcs */ 4454305487Sdavidcsstatic void 4455305487Sdavidcsql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize) 4456305487Sdavidcs{ 4457305487Sdavidcs if (esize != entry->hdr.entry_capture_size) { 4458305487Sdavidcs entry->hdr.entry_capture_size = esize; 4459305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG; 4460305487Sdavidcs } 4461305487Sdavidcs return; 4462305487Sdavidcs} 4463305487Sdavidcs 4464305487Sdavidcs 4465305487Sdavidcsstatic int 4466305487Sdavidcsql_parse_template(qla_host_t *ha) 4467305487Sdavidcs{ 4468305487Sdavidcs uint32_t num_of_entries, buff_level, e_cnt, esize; 4469305487Sdavidcs uint32_t end_cnt, rv = 0; 4470305487Sdavidcs char *dump_buff, *dbuff; 4471305487Sdavidcs int sane_start = 0, sane_end = 0; 4472305487Sdavidcs ql_minidump_template_hdr_t *template_hdr; 4473305487Sdavidcs ql_minidump_entry_t *entry; 4474305487Sdavidcs uint32_t capture_mask; 4475305487Sdavidcs uint32_t dump_size; 4476305487Sdavidcs 4477305487Sdavidcs /* Setup parameters */ 4478305487Sdavidcs template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template; 4479305487Sdavidcs 4480305487Sdavidcs if (template_hdr->entry_type == TLHDR) 4481305487Sdavidcs sane_start = 1; 4482305487Sdavidcs 4483305487Sdavidcs dump_buff = (char *) ha->hw.mdump_buffer; 4484305487Sdavidcs 4485305487Sdavidcs num_of_entries = template_hdr->num_of_entries; 4486305487Sdavidcs 4487305487Sdavidcs entry = (ql_minidump_entry_t *) ((char *)template_hdr 4488305487Sdavidcs + template_hdr->first_entry_offset ); 4489305487Sdavidcs 4490305487Sdavidcs template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] = 4491305487Sdavidcs template_hdr->ocm_window_array[ha->pci_func]; 4492305487Sdavidcs template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func; 4493305487Sdavidcs 4494305487Sdavidcs capture_mask = ha->hw.mdump_capture_mask; 4495305487Sdavidcs dump_size = ha->hw.mdump_buffer_size; 4496305487Sdavidcs 4497305487Sdavidcs template_hdr->driver_capture_mask = capture_mask; 4498305487Sdavidcs 4499305487Sdavidcs QL_DPRINT80(ha, (ha->pci_dev, 4500305487Sdavidcs "%s: sane_start = %d num_of_entries = %d " 4501305487Sdavidcs "capture_mask = 0x%x dump_size = %d \n", 4502305487Sdavidcs __func__, sane_start, num_of_entries, capture_mask, dump_size)); 4503305487Sdavidcs 4504305487Sdavidcs for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) { 4505305487Sdavidcs 4506305487Sdavidcs /* 4507305487Sdavidcs * If the capture_mask of the entry does not match capture mask 4508305487Sdavidcs * skip the entry after marking the driver_flags indicator. 4509305487Sdavidcs */ 4510305487Sdavidcs 4511305487Sdavidcs if (!(entry->hdr.entry_capture_mask & capture_mask)) { 4512305487Sdavidcs 4513305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4514305487Sdavidcs entry = (ql_minidump_entry_t *) ((char *) entry 4515305487Sdavidcs + entry->hdr.entry_size); 4516305487Sdavidcs continue; 4517305487Sdavidcs } 4518305487Sdavidcs 4519305487Sdavidcs /* 4520305487Sdavidcs * This is ONLY needed in implementations where 4521305487Sdavidcs * the capture buffer allocated is too small to capture 4522305487Sdavidcs * all of the required entries for a given capture mask. 4523305487Sdavidcs * We need to empty the buffer contents to a file 4524305487Sdavidcs * if possible, before processing the next entry 4525305487Sdavidcs * If the buff_full_flag is set, no further capture will happen 4526305487Sdavidcs * and all remaining non-control entries will be skipped. 4527305487Sdavidcs */ 4528305487Sdavidcs if (entry->hdr.entry_capture_size != 0) { 4529305487Sdavidcs if ((buff_level + entry->hdr.entry_capture_size) > 4530305487Sdavidcs dump_size) { 4531305487Sdavidcs /* Try to recover by emptying buffer to file */ 4532305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4533305487Sdavidcs entry = (ql_minidump_entry_t *) ((char *) entry 4534305487Sdavidcs + entry->hdr.entry_size); 4535305487Sdavidcs continue; 4536305487Sdavidcs } 4537305487Sdavidcs } 4538305487Sdavidcs 4539305487Sdavidcs /* 4540305487Sdavidcs * Decode the entry type and process it accordingly 4541305487Sdavidcs */ 4542305487Sdavidcs 4543305487Sdavidcs switch (entry->hdr.entry_type) { 4544305487Sdavidcs case RDNOP: 4545305487Sdavidcs break; 4546305487Sdavidcs 4547305487Sdavidcs case RDEND: 4548305487Sdavidcs if (sane_end == 0) { 4549305487Sdavidcs end_cnt = e_cnt; 4550305487Sdavidcs } 4551305487Sdavidcs sane_end++; 4552305487Sdavidcs break; 4553305487Sdavidcs 4554305487Sdavidcs case RDCRB: 4555305487Sdavidcs dbuff = dump_buff + buff_level; 4556305487Sdavidcs esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff); 4557305487Sdavidcs ql_entry_err_chk(entry, esize); 4558305487Sdavidcs buff_level += esize; 4559305487Sdavidcs break; 4560305487Sdavidcs 4561305487Sdavidcs case POLLRD: 4562305487Sdavidcs dbuff = dump_buff + buff_level; 4563305487Sdavidcs esize = ql_pollrd(ha, (void *)entry, (void *)dbuff); 4564305487Sdavidcs ql_entry_err_chk(entry, esize); 4565305487Sdavidcs buff_level += esize; 4566305487Sdavidcs break; 4567305487Sdavidcs 4568305487Sdavidcs case POLLRDMWR: 4569305487Sdavidcs dbuff = dump_buff + buff_level; 4570305487Sdavidcs esize = ql_pollrd_modify_write(ha, (void *)entry, 4571305487Sdavidcs (void *)dbuff); 4572305487Sdavidcs ql_entry_err_chk(entry, esize); 4573305487Sdavidcs buff_level += esize; 4574305487Sdavidcs break; 4575305487Sdavidcs 4576305487Sdavidcs case L2ITG: 4577305487Sdavidcs case L2DTG: 4578305487Sdavidcs case L2DAT: 4579305487Sdavidcs case L2INS: 4580305487Sdavidcs dbuff = dump_buff + buff_level; 4581305487Sdavidcs esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff); 4582305487Sdavidcs if (esize == -1) { 4583305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4584305487Sdavidcs } else { 4585305487Sdavidcs ql_entry_err_chk(entry, esize); 4586305487Sdavidcs buff_level += esize; 4587305487Sdavidcs } 4588305487Sdavidcs break; 4589305487Sdavidcs 4590305487Sdavidcs case L1DAT: 4591305487Sdavidcs case L1INS: 4592305487Sdavidcs dbuff = dump_buff + buff_level; 4593305487Sdavidcs esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff); 4594305487Sdavidcs ql_entry_err_chk(entry, esize); 4595305487Sdavidcs buff_level += esize; 4596305487Sdavidcs break; 4597305487Sdavidcs 4598305487Sdavidcs case RDOCM: 4599305487Sdavidcs dbuff = dump_buff + buff_level; 4600305487Sdavidcs esize = ql_rdocm(ha, (void *)entry, (void *)dbuff); 4601305487Sdavidcs ql_entry_err_chk(entry, esize); 4602305487Sdavidcs buff_level += esize; 4603305487Sdavidcs break; 4604305487Sdavidcs 4605305487Sdavidcs case RDMEM: 4606305487Sdavidcs dbuff = dump_buff + buff_level; 4607305487Sdavidcs esize = ql_rdmem(ha, (void *)entry, (void *)dbuff); 4608305487Sdavidcs ql_entry_err_chk(entry, esize); 4609305487Sdavidcs buff_level += esize; 4610305487Sdavidcs break; 4611305487Sdavidcs 4612305487Sdavidcs case BOARD: 4613305487Sdavidcs case RDROM: 4614305487Sdavidcs dbuff = dump_buff + buff_level; 4615305487Sdavidcs esize = ql_rdrom(ha, (void *)entry, (void *)dbuff); 4616305487Sdavidcs ql_entry_err_chk(entry, esize); 4617305487Sdavidcs buff_level += esize; 4618305487Sdavidcs break; 4619305487Sdavidcs 4620305487Sdavidcs case RDMUX: 4621305487Sdavidcs dbuff = dump_buff + buff_level; 4622305487Sdavidcs esize = ql_rdmux(ha, (void *)entry, (void *)dbuff); 4623305487Sdavidcs ql_entry_err_chk(entry, esize); 4624305487Sdavidcs buff_level += esize; 4625305487Sdavidcs break; 4626305487Sdavidcs 4627305487Sdavidcs case RDMUX2: 4628305487Sdavidcs dbuff = dump_buff + buff_level; 4629305487Sdavidcs esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff); 4630305487Sdavidcs ql_entry_err_chk(entry, esize); 4631305487Sdavidcs buff_level += esize; 4632305487Sdavidcs break; 4633305487Sdavidcs 4634305487Sdavidcs case QUEUE: 4635305487Sdavidcs dbuff = dump_buff + buff_level; 4636305487Sdavidcs esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff); 4637305487Sdavidcs ql_entry_err_chk(entry, esize); 4638305487Sdavidcs buff_level += esize; 4639305487Sdavidcs break; 4640305487Sdavidcs 4641305487Sdavidcs case CNTRL: 4642305487Sdavidcs if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) { 4643305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4644305487Sdavidcs } 4645305487Sdavidcs break; 4646305487Sdavidcs default: 4647305487Sdavidcs entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4648305487Sdavidcs break; 4649305487Sdavidcs } 4650305487Sdavidcs /* next entry in the template */ 4651305487Sdavidcs entry = (ql_minidump_entry_t *) ((char *) entry 4652305487Sdavidcs + entry->hdr.entry_size); 4653305487Sdavidcs } 4654305487Sdavidcs 4655305487Sdavidcs if (!sane_start || (sane_end > 1)) { 4656305487Sdavidcs device_printf(ha->pci_dev, 4657305487Sdavidcs "\n%s: Template configuration error. Check Template\n", 4658305487Sdavidcs __func__); 4659305487Sdavidcs } 4660305487Sdavidcs 4661305487Sdavidcs QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n", 4662305487Sdavidcs __func__, template_hdr->num_of_entries)); 4663305487Sdavidcs 4664305487Sdavidcs return 0; 4665305487Sdavidcs} 4666305487Sdavidcs 4667305487Sdavidcs/* 4668305487Sdavidcs * Read CRB operation. 4669305487Sdavidcs */ 4670305487Sdavidcsstatic uint32_t 4671305487Sdavidcsql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry, 4672305487Sdavidcs uint32_t * data_buff) 4673305487Sdavidcs{ 4674305487Sdavidcs int loop_cnt; 4675305487Sdavidcs int ret; 4676305487Sdavidcs uint32_t op_count, addr, stride, value = 0; 4677305487Sdavidcs 4678305487Sdavidcs addr = crb_entry->addr; 4679305487Sdavidcs op_count = crb_entry->op_count; 4680305487Sdavidcs stride = crb_entry->addr_stride; 4681305487Sdavidcs 4682305487Sdavidcs for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 4683305487Sdavidcs 4684305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &value, 1); 4685305487Sdavidcs 4686305487Sdavidcs if (ret) 4687305487Sdavidcs return (0); 4688305487Sdavidcs 4689305487Sdavidcs *data_buff++ = addr; 4690305487Sdavidcs *data_buff++ = value; 4691305487Sdavidcs addr = addr + stride; 4692305487Sdavidcs } 4693305487Sdavidcs 4694305487Sdavidcs /* 4695305487Sdavidcs * for testing purpose we return amount of data written 4696305487Sdavidcs */ 4697305487Sdavidcs return (op_count * (2 * sizeof(uint32_t))); 4698305487Sdavidcs} 4699305487Sdavidcs 4700305487Sdavidcs/* 4701305487Sdavidcs * Handle L2 Cache. 4702305487Sdavidcs */ 4703305487Sdavidcs 4704305487Sdavidcsstatic uint32_t 4705305487Sdavidcsql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry, 4706305487Sdavidcs uint32_t * data_buff) 4707305487Sdavidcs{ 4708305487Sdavidcs int i, k; 4709305487Sdavidcs int loop_cnt; 4710305487Sdavidcs int ret; 4711305487Sdavidcs 4712305487Sdavidcs uint32_t read_value; 4713305487Sdavidcs uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w; 4714305487Sdavidcs uint32_t tag_value, read_cnt; 4715305487Sdavidcs volatile uint8_t cntl_value_r; 4716305487Sdavidcs long timeout; 4717305487Sdavidcs uint32_t data; 4718305487Sdavidcs 4719305487Sdavidcs loop_cnt = cacheEntry->op_count; 4720305487Sdavidcs 4721305487Sdavidcs read_addr = cacheEntry->read_addr; 4722305487Sdavidcs cntrl_addr = cacheEntry->control_addr; 4723305487Sdavidcs cntl_value_w = (uint32_t) cacheEntry->write_value; 4724305487Sdavidcs 4725305487Sdavidcs tag_reg_addr = cacheEntry->tag_reg_addr; 4726305487Sdavidcs 4727305487Sdavidcs tag_value = cacheEntry->init_tag_value; 4728305487Sdavidcs read_cnt = cacheEntry->read_addr_cnt; 4729305487Sdavidcs 4730305487Sdavidcs for (i = 0; i < loop_cnt; i++) { 4731305487Sdavidcs 4732305487Sdavidcs ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4733305487Sdavidcs if (ret) 4734305487Sdavidcs return (0); 4735305487Sdavidcs 4736305487Sdavidcs if (cacheEntry->write_value != 0) { 4737305487Sdavidcs 4738305487Sdavidcs ret = ql_rdwr_indreg32(ha, cntrl_addr, 4739305487Sdavidcs &cntl_value_w, 0); 4740305487Sdavidcs if (ret) 4741305487Sdavidcs return (0); 4742305487Sdavidcs } 4743305487Sdavidcs 4744305487Sdavidcs if (cacheEntry->poll_mask != 0) { 4745305487Sdavidcs 4746305487Sdavidcs timeout = cacheEntry->poll_wait; 4747305487Sdavidcs 4748305487Sdavidcs ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1); 4749305487Sdavidcs if (ret) 4750305487Sdavidcs return (0); 4751305487Sdavidcs 4752305487Sdavidcs cntl_value_r = (uint8_t)data; 4753305487Sdavidcs 4754305487Sdavidcs while ((cntl_value_r & cacheEntry->poll_mask) != 0) { 4755305487Sdavidcs 4756305487Sdavidcs if (timeout) { 4757305487Sdavidcs qla_mdelay(__func__, 1); 4758305487Sdavidcs timeout--; 4759305487Sdavidcs } else 4760305487Sdavidcs break; 4761305487Sdavidcs 4762305487Sdavidcs ret = ql_rdwr_indreg32(ha, cntrl_addr, 4763305487Sdavidcs &data, 1); 4764305487Sdavidcs if (ret) 4765305487Sdavidcs return (0); 4766305487Sdavidcs 4767305487Sdavidcs cntl_value_r = (uint8_t)data; 4768305487Sdavidcs } 4769305487Sdavidcs if (!timeout) { 4770305487Sdavidcs /* Report timeout error. 4771305487Sdavidcs * core dump capture failed 4772305487Sdavidcs * Skip remaining entries. 4773305487Sdavidcs * Write buffer out to file 4774305487Sdavidcs * Use driver specific fields in template header 4775305487Sdavidcs * to report this error. 4776305487Sdavidcs */ 4777305487Sdavidcs return (-1); 4778305487Sdavidcs } 4779305487Sdavidcs } 4780305487Sdavidcs 4781305487Sdavidcs addr = read_addr; 4782305487Sdavidcs for (k = 0; k < read_cnt; k++) { 4783305487Sdavidcs 4784305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4785305487Sdavidcs if (ret) 4786305487Sdavidcs return (0); 4787305487Sdavidcs 4788305487Sdavidcs *data_buff++ = read_value; 4789305487Sdavidcs addr += cacheEntry->read_addr_stride; 4790305487Sdavidcs } 4791305487Sdavidcs 4792305487Sdavidcs tag_value += cacheEntry->tag_value_stride; 4793305487Sdavidcs } 4794305487Sdavidcs 4795305487Sdavidcs return (read_cnt * loop_cnt * sizeof(uint32_t)); 4796305487Sdavidcs} 4797305487Sdavidcs 4798305487Sdavidcs/* 4799305487Sdavidcs * Handle L1 Cache. 4800305487Sdavidcs */ 4801305487Sdavidcs 4802305487Sdavidcsstatic uint32_t 4803305487Sdavidcsql_L1Cache(qla_host_t *ha, 4804305487Sdavidcs ql_minidump_entry_cache_t *cacheEntry, 4805305487Sdavidcs uint32_t *data_buff) 4806305487Sdavidcs{ 4807305487Sdavidcs int ret; 4808305487Sdavidcs int i, k; 4809305487Sdavidcs int loop_cnt; 4810305487Sdavidcs 4811305487Sdavidcs uint32_t read_value; 4812305487Sdavidcs uint32_t addr, read_addr, cntrl_addr, tag_reg_addr; 4813305487Sdavidcs uint32_t tag_value, read_cnt; 4814305487Sdavidcs uint32_t cntl_value_w; 4815305487Sdavidcs 4816305487Sdavidcs loop_cnt = cacheEntry->op_count; 4817305487Sdavidcs 4818305487Sdavidcs read_addr = cacheEntry->read_addr; 4819305487Sdavidcs cntrl_addr = cacheEntry->control_addr; 4820305487Sdavidcs cntl_value_w = (uint32_t) cacheEntry->write_value; 4821305487Sdavidcs 4822305487Sdavidcs tag_reg_addr = cacheEntry->tag_reg_addr; 4823305487Sdavidcs 4824305487Sdavidcs tag_value = cacheEntry->init_tag_value; 4825305487Sdavidcs read_cnt = cacheEntry->read_addr_cnt; 4826305487Sdavidcs 4827305487Sdavidcs for (i = 0; i < loop_cnt; i++) { 4828305487Sdavidcs 4829305487Sdavidcs ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4830305487Sdavidcs if (ret) 4831305487Sdavidcs return (0); 4832305487Sdavidcs 4833305487Sdavidcs ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0); 4834305487Sdavidcs if (ret) 4835305487Sdavidcs return (0); 4836305487Sdavidcs 4837305487Sdavidcs addr = read_addr; 4838305487Sdavidcs for (k = 0; k < read_cnt; k++) { 4839305487Sdavidcs 4840305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4841305487Sdavidcs if (ret) 4842305487Sdavidcs return (0); 4843305487Sdavidcs 4844305487Sdavidcs *data_buff++ = read_value; 4845305487Sdavidcs addr += cacheEntry->read_addr_stride; 4846305487Sdavidcs } 4847305487Sdavidcs 4848305487Sdavidcs tag_value += cacheEntry->tag_value_stride; 4849305487Sdavidcs } 4850305487Sdavidcs 4851305487Sdavidcs return (read_cnt * loop_cnt * sizeof(uint32_t)); 4852305487Sdavidcs} 4853305487Sdavidcs 4854305487Sdavidcs/* 4855305487Sdavidcs * Reading OCM memory 4856305487Sdavidcs */ 4857305487Sdavidcs 4858305487Sdavidcsstatic uint32_t 4859305487Sdavidcsql_rdocm(qla_host_t *ha, 4860305487Sdavidcs ql_minidump_entry_rdocm_t *ocmEntry, 4861305487Sdavidcs uint32_t *data_buff) 4862305487Sdavidcs{ 4863305487Sdavidcs int i, loop_cnt; 4864305487Sdavidcs volatile uint32_t addr; 4865305487Sdavidcs volatile uint32_t value; 4866305487Sdavidcs 4867305487Sdavidcs addr = ocmEntry->read_addr; 4868305487Sdavidcs loop_cnt = ocmEntry->op_count; 4869305487Sdavidcs 4870305487Sdavidcs for (i = 0; i < loop_cnt; i++) { 4871305487Sdavidcs value = READ_REG32(ha, addr); 4872305487Sdavidcs *data_buff++ = value; 4873305487Sdavidcs addr += ocmEntry->read_addr_stride; 4874305487Sdavidcs } 4875305487Sdavidcs return (loop_cnt * sizeof(value)); 4876305487Sdavidcs} 4877305487Sdavidcs 4878305487Sdavidcs/* 4879305487Sdavidcs * Read memory 4880305487Sdavidcs */ 4881305487Sdavidcs 4882305487Sdavidcsstatic uint32_t 4883305487Sdavidcsql_rdmem(qla_host_t *ha, 4884305487Sdavidcs ql_minidump_entry_rdmem_t *mem_entry, 4885305487Sdavidcs uint32_t *data_buff) 4886305487Sdavidcs{ 4887305487Sdavidcs int ret; 4888305487Sdavidcs int i, loop_cnt; 4889305487Sdavidcs volatile uint32_t addr; 4890305487Sdavidcs q80_offchip_mem_val_t val; 4891305487Sdavidcs 4892305487Sdavidcs addr = mem_entry->read_addr; 4893305487Sdavidcs 4894305487Sdavidcs /* size in bytes / 16 */ 4895305487Sdavidcs loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4); 4896305487Sdavidcs 4897305487Sdavidcs for (i = 0; i < loop_cnt; i++) { 4898305487Sdavidcs 4899305487Sdavidcs ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1); 4900305487Sdavidcs if (ret) 4901305487Sdavidcs return (0); 4902305487Sdavidcs 4903305487Sdavidcs *data_buff++ = val.data_lo; 4904305487Sdavidcs *data_buff++ = val.data_hi; 4905305487Sdavidcs *data_buff++ = val.data_ulo; 4906305487Sdavidcs *data_buff++ = val.data_uhi; 4907305487Sdavidcs 4908305487Sdavidcs addr += (sizeof(uint32_t) * 4); 4909305487Sdavidcs } 4910305487Sdavidcs 4911305487Sdavidcs return (loop_cnt * (sizeof(uint32_t) * 4)); 4912305487Sdavidcs} 4913305487Sdavidcs 4914305487Sdavidcs/* 4915305487Sdavidcs * Read Rom 4916305487Sdavidcs */ 4917305487Sdavidcs 4918305487Sdavidcsstatic uint32_t 4919305487Sdavidcsql_rdrom(qla_host_t *ha, 4920305487Sdavidcs ql_minidump_entry_rdrom_t *romEntry, 4921305487Sdavidcs uint32_t *data_buff) 4922305487Sdavidcs{ 4923305487Sdavidcs int ret; 4924305487Sdavidcs int i, loop_cnt; 4925305487Sdavidcs uint32_t addr; 4926305487Sdavidcs uint32_t value; 4927305487Sdavidcs 4928305487Sdavidcs addr = romEntry->read_addr; 4929305487Sdavidcs loop_cnt = romEntry->read_data_size; /* This is size in bytes */ 4930305487Sdavidcs loop_cnt /= sizeof(value); 4931305487Sdavidcs 4932305487Sdavidcs for (i = 0; i < loop_cnt; i++) { 4933305487Sdavidcs 4934305487Sdavidcs ret = ql_rd_flash32(ha, addr, &value); 4935305487Sdavidcs if (ret) 4936305487Sdavidcs return (0); 4937305487Sdavidcs 4938305487Sdavidcs *data_buff++ = value; 4939305487Sdavidcs addr += sizeof(value); 4940305487Sdavidcs } 4941305487Sdavidcs 4942305487Sdavidcs return (loop_cnt * sizeof(value)); 4943305487Sdavidcs} 4944305487Sdavidcs 4945305487Sdavidcs/* 4946305487Sdavidcs * Read MUX data 4947305487Sdavidcs */ 4948305487Sdavidcs 4949305487Sdavidcsstatic uint32_t 4950305487Sdavidcsql_rdmux(qla_host_t *ha, 4951305487Sdavidcs ql_minidump_entry_mux_t *muxEntry, 4952305487Sdavidcs uint32_t *data_buff) 4953305487Sdavidcs{ 4954305487Sdavidcs int ret; 4955305487Sdavidcs int loop_cnt; 4956305487Sdavidcs uint32_t read_value, sel_value; 4957305487Sdavidcs uint32_t read_addr, select_addr; 4958305487Sdavidcs 4959305487Sdavidcs select_addr = muxEntry->select_addr; 4960305487Sdavidcs sel_value = muxEntry->select_value; 4961305487Sdavidcs read_addr = muxEntry->read_addr; 4962305487Sdavidcs 4963305487Sdavidcs for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { 4964305487Sdavidcs 4965305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0); 4966305487Sdavidcs if (ret) 4967305487Sdavidcs return (0); 4968305487Sdavidcs 4969305487Sdavidcs ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 4970305487Sdavidcs if (ret) 4971305487Sdavidcs return (0); 4972305487Sdavidcs 4973305487Sdavidcs *data_buff++ = sel_value; 4974305487Sdavidcs *data_buff++ = read_value; 4975305487Sdavidcs 4976305487Sdavidcs sel_value += muxEntry->select_value_stride; 4977305487Sdavidcs } 4978305487Sdavidcs 4979305487Sdavidcs return (loop_cnt * (2 * sizeof(uint32_t))); 4980305487Sdavidcs} 4981305487Sdavidcs 4982305487Sdavidcsstatic uint32_t 4983305487Sdavidcsql_rdmux2(qla_host_t *ha, 4984305487Sdavidcs ql_minidump_entry_mux2_t *muxEntry, 4985305487Sdavidcs uint32_t *data_buff) 4986305487Sdavidcs{ 4987305487Sdavidcs int ret; 4988305487Sdavidcs int loop_cnt; 4989305487Sdavidcs 4990305487Sdavidcs uint32_t select_addr_1, select_addr_2; 4991305487Sdavidcs uint32_t select_value_1, select_value_2; 4992305487Sdavidcs uint32_t select_value_count, select_value_mask; 4993305487Sdavidcs uint32_t read_addr, read_value; 4994305487Sdavidcs 4995305487Sdavidcs select_addr_1 = muxEntry->select_addr_1; 4996305487Sdavidcs select_addr_2 = muxEntry->select_addr_2; 4997305487Sdavidcs select_value_1 = muxEntry->select_value_1; 4998305487Sdavidcs select_value_2 = muxEntry->select_value_2; 4999305487Sdavidcs select_value_count = muxEntry->select_value_count; 5000305487Sdavidcs select_value_mask = muxEntry->select_value_mask; 5001305487Sdavidcs 5002305487Sdavidcs read_addr = muxEntry->read_addr; 5003305487Sdavidcs 5004305487Sdavidcs for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count; 5005305487Sdavidcs loop_cnt++) { 5006305487Sdavidcs 5007305487Sdavidcs uint32_t temp_sel_val; 5008305487Sdavidcs 5009305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0); 5010305487Sdavidcs if (ret) 5011305487Sdavidcs return (0); 5012305487Sdavidcs 5013305487Sdavidcs temp_sel_val = select_value_1 & select_value_mask; 5014305487Sdavidcs 5015305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5016305487Sdavidcs if (ret) 5017305487Sdavidcs return (0); 5018305487Sdavidcs 5019305487Sdavidcs ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5020305487Sdavidcs if (ret) 5021305487Sdavidcs return (0); 5022305487Sdavidcs 5023305487Sdavidcs *data_buff++ = temp_sel_val; 5024305487Sdavidcs *data_buff++ = read_value; 5025305487Sdavidcs 5026305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0); 5027305487Sdavidcs if (ret) 5028305487Sdavidcs return (0); 5029305487Sdavidcs 5030305487Sdavidcs temp_sel_val = select_value_2 & select_value_mask; 5031305487Sdavidcs 5032305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5033305487Sdavidcs if (ret) 5034305487Sdavidcs return (0); 5035305487Sdavidcs 5036305487Sdavidcs ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5037305487Sdavidcs if (ret) 5038305487Sdavidcs return (0); 5039305487Sdavidcs 5040305487Sdavidcs *data_buff++ = temp_sel_val; 5041305487Sdavidcs *data_buff++ = read_value; 5042305487Sdavidcs 5043305487Sdavidcs select_value_1 += muxEntry->select_value_stride; 5044305487Sdavidcs select_value_2 += muxEntry->select_value_stride; 5045305487Sdavidcs } 5046305487Sdavidcs 5047305487Sdavidcs return (loop_cnt * (4 * sizeof(uint32_t))); 5048305487Sdavidcs} 5049305487Sdavidcs 5050305487Sdavidcs/* 5051305487Sdavidcs * Handling Queue State Reads. 5052305487Sdavidcs */ 5053305487Sdavidcs 5054305487Sdavidcsstatic uint32_t 5055305487Sdavidcsql_rdqueue(qla_host_t *ha, 5056305487Sdavidcs ql_minidump_entry_queue_t *queueEntry, 5057305487Sdavidcs uint32_t *data_buff) 5058305487Sdavidcs{ 5059305487Sdavidcs int ret; 5060305487Sdavidcs int loop_cnt, k; 5061305487Sdavidcs uint32_t read_value; 5062305487Sdavidcs uint32_t read_addr, read_stride, select_addr; 5063305487Sdavidcs uint32_t queue_id, read_cnt; 5064305487Sdavidcs 5065305487Sdavidcs read_cnt = queueEntry->read_addr_cnt; 5066305487Sdavidcs read_stride = queueEntry->read_addr_stride; 5067305487Sdavidcs select_addr = queueEntry->select_addr; 5068305487Sdavidcs 5069305487Sdavidcs for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; 5070305487Sdavidcs loop_cnt++) { 5071305487Sdavidcs 5072305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0); 5073305487Sdavidcs if (ret) 5074305487Sdavidcs return (0); 5075305487Sdavidcs 5076305487Sdavidcs read_addr = queueEntry->read_addr; 5077305487Sdavidcs 5078305487Sdavidcs for (k = 0; k < read_cnt; k++) { 5079305487Sdavidcs 5080305487Sdavidcs ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5081305487Sdavidcs if (ret) 5082305487Sdavidcs return (0); 5083305487Sdavidcs 5084305487Sdavidcs *data_buff++ = read_value; 5085305487Sdavidcs read_addr += read_stride; 5086305487Sdavidcs } 5087305487Sdavidcs 5088305487Sdavidcs queue_id += queueEntry->queue_id_stride; 5089305487Sdavidcs } 5090305487Sdavidcs 5091305487Sdavidcs return (loop_cnt * (read_cnt * sizeof(uint32_t))); 5092305487Sdavidcs} 5093305487Sdavidcs 5094305487Sdavidcs/* 5095305487Sdavidcs * Handling control entries. 5096305487Sdavidcs */ 5097305487Sdavidcs 5098305487Sdavidcsstatic uint32_t 5099305487Sdavidcsql_cntrl(qla_host_t *ha, 5100305487Sdavidcs ql_minidump_template_hdr_t *template_hdr, 5101305487Sdavidcs ql_minidump_entry_cntrl_t *crbEntry) 5102305487Sdavidcs{ 5103305487Sdavidcs int ret; 5104305487Sdavidcs int count; 5105305487Sdavidcs uint32_t opcode, read_value, addr, entry_addr; 5106305487Sdavidcs long timeout; 5107305487Sdavidcs 5108305487Sdavidcs entry_addr = crbEntry->addr; 5109305487Sdavidcs 5110305487Sdavidcs for (count = 0; count < crbEntry->op_count; count++) { 5111305487Sdavidcs opcode = crbEntry->opcode; 5112305487Sdavidcs 5113305487Sdavidcs if (opcode & QL_DBG_OPCODE_WR) { 5114305487Sdavidcs 5115305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, 5116305487Sdavidcs &crbEntry->value_1, 0); 5117305487Sdavidcs if (ret) 5118305487Sdavidcs return (0); 5119305487Sdavidcs 5120305487Sdavidcs opcode &= ~QL_DBG_OPCODE_WR; 5121305487Sdavidcs } 5122305487Sdavidcs 5123305487Sdavidcs if (opcode & QL_DBG_OPCODE_RW) { 5124305487Sdavidcs 5125305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5126305487Sdavidcs if (ret) 5127305487Sdavidcs return (0); 5128305487Sdavidcs 5129305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5130305487Sdavidcs if (ret) 5131305487Sdavidcs return (0); 5132305487Sdavidcs 5133305487Sdavidcs opcode &= ~QL_DBG_OPCODE_RW; 5134305487Sdavidcs } 5135305487Sdavidcs 5136305487Sdavidcs if (opcode & QL_DBG_OPCODE_AND) { 5137305487Sdavidcs 5138305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5139305487Sdavidcs if (ret) 5140305487Sdavidcs return (0); 5141305487Sdavidcs 5142305487Sdavidcs read_value &= crbEntry->value_2; 5143305487Sdavidcs opcode &= ~QL_DBG_OPCODE_AND; 5144305487Sdavidcs 5145305487Sdavidcs if (opcode & QL_DBG_OPCODE_OR) { 5146305487Sdavidcs read_value |= crbEntry->value_3; 5147305487Sdavidcs opcode &= ~QL_DBG_OPCODE_OR; 5148305487Sdavidcs } 5149305487Sdavidcs 5150305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5151305487Sdavidcs if (ret) 5152305487Sdavidcs return (0); 5153305487Sdavidcs } 5154305487Sdavidcs 5155305487Sdavidcs if (opcode & QL_DBG_OPCODE_OR) { 5156305487Sdavidcs 5157305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5158305487Sdavidcs if (ret) 5159305487Sdavidcs return (0); 5160305487Sdavidcs 5161305487Sdavidcs read_value |= crbEntry->value_3; 5162305487Sdavidcs 5163305487Sdavidcs ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5164305487Sdavidcs if (ret) 5165305487Sdavidcs return (0); 5166305487Sdavidcs 5167305487Sdavidcs opcode &= ~QL_DBG_OPCODE_OR; 5168305487Sdavidcs } 5169305487Sdavidcs 5170305487Sdavidcs if (opcode & QL_DBG_OPCODE_POLL) { 5171305487Sdavidcs 5172305487Sdavidcs opcode &= ~QL_DBG_OPCODE_POLL; 5173305487Sdavidcs timeout = crbEntry->poll_timeout; 5174305487Sdavidcs addr = entry_addr; 5175305487Sdavidcs 5176305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5177305487Sdavidcs if (ret) 5178305487Sdavidcs return (0); 5179305487Sdavidcs 5180305487Sdavidcs while ((read_value & crbEntry->value_2) 5181305487Sdavidcs != crbEntry->value_1) { 5182305487Sdavidcs 5183305487Sdavidcs if (timeout) { 5184305487Sdavidcs qla_mdelay(__func__, 1); 5185305487Sdavidcs timeout--; 5186305487Sdavidcs } else 5187305487Sdavidcs break; 5188305487Sdavidcs 5189305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, 5190305487Sdavidcs &read_value, 1); 5191305487Sdavidcs if (ret) 5192305487Sdavidcs return (0); 5193305487Sdavidcs } 5194305487Sdavidcs 5195305487Sdavidcs if (!timeout) { 5196305487Sdavidcs /* 5197305487Sdavidcs * Report timeout error. 5198305487Sdavidcs * core dump capture failed 5199305487Sdavidcs * Skip remaining entries. 5200305487Sdavidcs * Write buffer out to file 5201305487Sdavidcs * Use driver specific fields in template header 5202305487Sdavidcs * to report this error. 5203305487Sdavidcs */ 5204305487Sdavidcs return (-1); 5205305487Sdavidcs } 5206305487Sdavidcs } 5207305487Sdavidcs 5208305487Sdavidcs if (opcode & QL_DBG_OPCODE_RDSTATE) { 5209305487Sdavidcs /* 5210305487Sdavidcs * decide which address to use. 5211305487Sdavidcs */ 5212305487Sdavidcs if (crbEntry->state_index_a) { 5213305487Sdavidcs addr = template_hdr->saved_state_array[ 5214305487Sdavidcs crbEntry-> state_index_a]; 5215305487Sdavidcs } else { 5216305487Sdavidcs addr = entry_addr; 5217305487Sdavidcs } 5218305487Sdavidcs 5219305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5220305487Sdavidcs if (ret) 5221305487Sdavidcs return (0); 5222305487Sdavidcs 5223305487Sdavidcs template_hdr->saved_state_array[crbEntry->state_index_v] 5224305487Sdavidcs = read_value; 5225305487Sdavidcs opcode &= ~QL_DBG_OPCODE_RDSTATE; 5226305487Sdavidcs } 5227305487Sdavidcs 5228305487Sdavidcs if (opcode & QL_DBG_OPCODE_WRSTATE) { 5229305487Sdavidcs /* 5230305487Sdavidcs * decide which value to use. 5231305487Sdavidcs */ 5232305487Sdavidcs if (crbEntry->state_index_v) { 5233305487Sdavidcs read_value = template_hdr->saved_state_array[ 5234305487Sdavidcs crbEntry->state_index_v]; 5235305487Sdavidcs } else { 5236305487Sdavidcs read_value = crbEntry->value_1; 5237305487Sdavidcs } 5238305487Sdavidcs /* 5239305487Sdavidcs * decide which address to use. 5240305487Sdavidcs */ 5241305487Sdavidcs if (crbEntry->state_index_a) { 5242305487Sdavidcs addr = template_hdr->saved_state_array[ 5243305487Sdavidcs crbEntry-> state_index_a]; 5244305487Sdavidcs } else { 5245305487Sdavidcs addr = entry_addr; 5246305487Sdavidcs } 5247305487Sdavidcs 5248305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr, &read_value, 0); 5249305487Sdavidcs if (ret) 5250305487Sdavidcs return (0); 5251305487Sdavidcs 5252305487Sdavidcs opcode &= ~QL_DBG_OPCODE_WRSTATE; 5253305487Sdavidcs } 5254305487Sdavidcs 5255305487Sdavidcs if (opcode & QL_DBG_OPCODE_MDSTATE) { 5256305487Sdavidcs /* Read value from saved state using index */ 5257305487Sdavidcs read_value = template_hdr->saved_state_array[ 5258305487Sdavidcs crbEntry->state_index_v]; 5259305487Sdavidcs 5260305487Sdavidcs read_value <<= crbEntry->shl; /*Shift left operation */ 5261305487Sdavidcs read_value >>= crbEntry->shr; /*Shift right operation */ 5262305487Sdavidcs 5263305487Sdavidcs if (crbEntry->value_2) { 5264305487Sdavidcs /* check if AND mask is provided */ 5265305487Sdavidcs read_value &= crbEntry->value_2; 5266305487Sdavidcs } 5267305487Sdavidcs 5268305487Sdavidcs read_value |= crbEntry->value_3; /* OR operation */ 5269305487Sdavidcs read_value += crbEntry->value_1; /* increment op */ 5270305487Sdavidcs 5271305487Sdavidcs /* Write value back to state area. */ 5272305487Sdavidcs 5273305487Sdavidcs template_hdr->saved_state_array[crbEntry->state_index_v] 5274305487Sdavidcs = read_value; 5275305487Sdavidcs opcode &= ~QL_DBG_OPCODE_MDSTATE; 5276305487Sdavidcs } 5277305487Sdavidcs 5278305487Sdavidcs entry_addr += crbEntry->addr_stride; 5279305487Sdavidcs } 5280305487Sdavidcs 5281305487Sdavidcs return (0); 5282305487Sdavidcs} 5283305487Sdavidcs 5284305487Sdavidcs/* 5285305487Sdavidcs * Handling rd poll entry. 5286305487Sdavidcs */ 5287305487Sdavidcs 5288305487Sdavidcsstatic uint32_t 5289305487Sdavidcsql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry, 5290305487Sdavidcs uint32_t *data_buff) 5291305487Sdavidcs{ 5292305487Sdavidcs int ret; 5293305487Sdavidcs int loop_cnt; 5294305487Sdavidcs uint32_t op_count, select_addr, select_value_stride, select_value; 5295305487Sdavidcs uint32_t read_addr, poll, mask, data_size, data; 5296305487Sdavidcs uint32_t wait_count = 0; 5297305487Sdavidcs 5298305487Sdavidcs select_addr = entry->select_addr; 5299305487Sdavidcs read_addr = entry->read_addr; 5300305487Sdavidcs select_value = entry->select_value; 5301305487Sdavidcs select_value_stride = entry->select_value_stride; 5302305487Sdavidcs op_count = entry->op_count; 5303305487Sdavidcs poll = entry->poll; 5304305487Sdavidcs mask = entry->mask; 5305305487Sdavidcs data_size = entry->data_size; 5306305487Sdavidcs 5307305487Sdavidcs for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 5308305487Sdavidcs 5309305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0); 5310305487Sdavidcs if (ret) 5311305487Sdavidcs return (0); 5312305487Sdavidcs 5313305487Sdavidcs wait_count = 0; 5314305487Sdavidcs 5315305487Sdavidcs while (wait_count < poll) { 5316305487Sdavidcs 5317305487Sdavidcs uint32_t temp; 5318305487Sdavidcs 5319305487Sdavidcs ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1); 5320305487Sdavidcs if (ret) 5321305487Sdavidcs return (0); 5322305487Sdavidcs 5323305487Sdavidcs if ( (temp & mask) != 0 ) { 5324305487Sdavidcs break; 5325305487Sdavidcs } 5326305487Sdavidcs wait_count++; 5327305487Sdavidcs } 5328305487Sdavidcs 5329305487Sdavidcs if (wait_count == poll) { 5330305487Sdavidcs device_printf(ha->pci_dev, 5331305487Sdavidcs "%s: Error in processing entry\n", __func__); 5332305487Sdavidcs device_printf(ha->pci_dev, 5333305487Sdavidcs "%s: wait_count <0x%x> poll <0x%x>\n", 5334305487Sdavidcs __func__, wait_count, poll); 5335305487Sdavidcs return 0; 5336305487Sdavidcs } 5337305487Sdavidcs 5338305487Sdavidcs ret = ql_rdwr_indreg32(ha, read_addr, &data, 1); 5339305487Sdavidcs if (ret) 5340305487Sdavidcs return (0); 5341305487Sdavidcs 5342305487Sdavidcs *data_buff++ = select_value; 5343305487Sdavidcs *data_buff++ = data; 5344305487Sdavidcs select_value = select_value + select_value_stride; 5345305487Sdavidcs } 5346305487Sdavidcs 5347305487Sdavidcs /* 5348305487Sdavidcs * for testing purpose we return amount of data written 5349305487Sdavidcs */ 5350305487Sdavidcs return (loop_cnt * (2 * sizeof(uint32_t))); 5351305487Sdavidcs} 5352305487Sdavidcs 5353305487Sdavidcs 5354305487Sdavidcs/* 5355305487Sdavidcs * Handling rd modify write poll entry. 5356305487Sdavidcs */ 5357305487Sdavidcs 5358305487Sdavidcsstatic uint32_t 5359305487Sdavidcsql_pollrd_modify_write(qla_host_t *ha, 5360305487Sdavidcs ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 5361305487Sdavidcs uint32_t *data_buff) 5362305487Sdavidcs{ 5363305487Sdavidcs int ret; 5364305487Sdavidcs uint32_t addr_1, addr_2, value_1, value_2, data; 5365305487Sdavidcs uint32_t poll, mask, data_size, modify_mask; 5366305487Sdavidcs uint32_t wait_count = 0; 5367305487Sdavidcs 5368305487Sdavidcs addr_1 = entry->addr_1; 5369305487Sdavidcs addr_2 = entry->addr_2; 5370305487Sdavidcs value_1 = entry->value_1; 5371305487Sdavidcs value_2 = entry->value_2; 5372305487Sdavidcs 5373305487Sdavidcs poll = entry->poll; 5374305487Sdavidcs mask = entry->mask; 5375305487Sdavidcs modify_mask = entry->modify_mask; 5376305487Sdavidcs data_size = entry->data_size; 5377305487Sdavidcs 5378305487Sdavidcs 5379305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0); 5380305487Sdavidcs if (ret) 5381305487Sdavidcs return (0); 5382305487Sdavidcs 5383305487Sdavidcs wait_count = 0; 5384305487Sdavidcs while (wait_count < poll) { 5385305487Sdavidcs 5386305487Sdavidcs uint32_t temp; 5387305487Sdavidcs 5388305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5389305487Sdavidcs if (ret) 5390305487Sdavidcs return (0); 5391305487Sdavidcs 5392305487Sdavidcs if ( (temp & mask) != 0 ) { 5393305487Sdavidcs break; 5394305487Sdavidcs } 5395305487Sdavidcs wait_count++; 5396305487Sdavidcs } 5397305487Sdavidcs 5398305487Sdavidcs if (wait_count == poll) { 5399305487Sdavidcs device_printf(ha->pci_dev, "%s Error in processing entry\n", 5400305487Sdavidcs __func__); 5401305487Sdavidcs } else { 5402305487Sdavidcs 5403305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_2, &data, 1); 5404305487Sdavidcs if (ret) 5405305487Sdavidcs return (0); 5406305487Sdavidcs 5407305487Sdavidcs data = (data & modify_mask); 5408305487Sdavidcs 5409305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_2, &data, 0); 5410305487Sdavidcs if (ret) 5411305487Sdavidcs return (0); 5412305487Sdavidcs 5413305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0); 5414305487Sdavidcs if (ret) 5415305487Sdavidcs return (0); 5416305487Sdavidcs 5417305487Sdavidcs /* Poll again */ 5418305487Sdavidcs wait_count = 0; 5419305487Sdavidcs while (wait_count < poll) { 5420305487Sdavidcs 5421305487Sdavidcs uint32_t temp; 5422305487Sdavidcs 5423305487Sdavidcs ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5424305487Sdavidcs if (ret) 5425305487Sdavidcs return (0); 5426305487Sdavidcs 5427305487Sdavidcs if ( (temp & mask) != 0 ) { 5428305487Sdavidcs break; 5429305487Sdavidcs } 5430305487Sdavidcs wait_count++; 5431305487Sdavidcs } 5432305487Sdavidcs *data_buff++ = addr_2; 5433305487Sdavidcs *data_buff++ = data; 5434305487Sdavidcs } 5435305487Sdavidcs 5436305487Sdavidcs /* 5437305487Sdavidcs * for testing purpose we return amount of data written 5438305487Sdavidcs */ 5439305487Sdavidcs return (2 * sizeof(uint32_t)); 5440305487Sdavidcs} 5441305487Sdavidcs 5442305487Sdavidcs 5443