1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/qlnx_ioctl.h 337517 2018-08-09 01:17:35Z davidcs $ 28 * 29 */ 30 31#ifndef _QLNX_IOCTL_H_ 32#define _QLNX_IOCTL_H_ 33 34#include <sys/ioccom.h> 35 36#define QLNX_MAX_HW_FUNCS 2 37 38/* 39 * Read grcdump and grcdump size 40 */ 41 42struct qlnx_grcdump { 43 uint16_t pci_func; 44 uint32_t grcdump_size[QLNX_MAX_HW_FUNCS]; 45 void *grcdump[QLNX_MAX_HW_FUNCS]; 46 uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS]; 47}; 48typedef struct qlnx_grcdump qlnx_grcdump_t; 49 50/* 51 * Read idle_chk and idle_chk size 52 */ 53struct qlnx_idle_chk { 54 uint16_t pci_func; 55 uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS]; 56 void *idle_chk[QLNX_MAX_HW_FUNCS]; 57 uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS]; 58}; 59typedef struct qlnx_idle_chk qlnx_idle_chk_t; 60 61/* 62 * Retrive traces 63 */ 64struct qlnx_trace { 65 uint16_t pci_func; 66 67 uint16_t cmd; 68#define QLNX_MCP_TRACE 0x01 69#define QLNX_REG_FIFO 0x02 70#define QLNX_IGU_FIFO 0x03 71#define QLNX_PROTECTION_OVERRIDE 0x04 72#define QLNX_FW_ASSERTS 0x05 73 74 uint32_t size[QLNX_MAX_HW_FUNCS]; 75 void *buffer[QLNX_MAX_HW_FUNCS]; 76 uint32_t dwords[QLNX_MAX_HW_FUNCS]; 77}; 78typedef struct qlnx_trace qlnx_trace_t; 79 80 81/* 82 * Read driver info 83 */ 84#define QLNX_DRV_INFO_NAME_LENGTH 32 85#define QLNX_DRV_INFO_VERSION_LENGTH 32 86#define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32 87#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32 88#define QLNX_DRV_INFO_BUS_INFO_LENGTH 32 89 90struct qlnx_drvinfo { 91 char drv_name[QLNX_DRV_INFO_NAME_LENGTH]; 92 char drv_version[QLNX_DRV_INFO_VERSION_LENGTH]; 93 char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH]; 94 char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH]; 95 uint32_t eeprom_dump_len; /* in bytes */ 96 uint32_t reg_dump_len; /* in bytes */ 97 char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH]; 98}; 99typedef struct qlnx_drvinfo qlnx_drvinfo_t; 100 101/* 102 * Read Device Setting 103 */ 104struct qlnx_dev_setting { 105 uint32_t supported; /* Features this interface supports */ 106 uint32_t advertising; /* Features this interface advertises */ 107 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 108 uint32_t duplex; /* Duplex, half or full */ 109 uint32_t port; /* Which connector port */ 110 uint32_t phy_address; /* port number*/ 111 uint32_t autoneg; /* Enable or disable autonegotiation */ 112}; 113typedef struct qlnx_dev_setting qlnx_dev_setting_t; 114 115/* 116 * Get Registers 117 */ 118struct qlnx_get_regs { 119 void *reg_buf; 120 uint32_t reg_buf_len; 121}; 122typedef struct qlnx_get_regs qlnx_get_regs_t; 123 124/* 125 * Get/Set NVRAM 126 */ 127struct qlnx_nvram { 128 uint32_t cmd; 129#define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01 130#define QLNX_NVRAM_CMD_READ_NVRAM 0x02 131#define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03 132#define QLNX_NVRAM_CMD_DEL_FILE 0x04 133#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05 134#define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06 135#define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07 136 137 void *data; 138 uint32_t offset; 139 uint32_t data_len; 140 uint32_t magic; 141}; 142typedef struct qlnx_nvram qlnx_nvram_t; 143 144/* 145 * Get/Set Device registers 146 */ 147struct qlnx_reg_rd_wr { 148 uint32_t cmd; 149#define QLNX_REG_READ_CMD 0x01 150#define QLNX_REG_WRITE_CMD 0x02 151 152 uint32_t addr; 153 uint32_t val; 154 155 uint32_t access_type; 156#define QLNX_REG_ACCESS_DIRECT 0x01 157#define QLNX_REG_ACCESS_INDIRECT 0x02 158 159 uint32_t hwfn_index; 160}; 161typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t; 162 163/* 164 * Read/Write PCI Configuration 165 */ 166struct qlnx_pcicfg_rd_wr { 167 uint32_t cmd; 168#define QLNX_PCICFG_READ 0x01 169#define QLNX_PCICFG_WRITE 0x02 170 uint32_t reg; 171 uint32_t val; 172 uint32_t width; 173}; 174typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t; 175 176/* 177 * Read MAC address 178 */ 179struct qlnx_perm_mac_addr { 180 char addr[32]; 181}; 182typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t; 183 184 185/* 186 * Read STORM statistics registers 187 */ 188struct qlnx_storm_stats { 189 190 /* xstorm */ 191 uint32_t xstorm_active_cycles; 192 uint32_t xstorm_stall_cycles; 193 uint32_t xstorm_sleeping_cycles; 194 uint32_t xstorm_inactive_cycles; 195 196 /* ystorm */ 197 uint32_t ystorm_active_cycles; 198 uint32_t ystorm_stall_cycles; 199 uint32_t ystorm_sleeping_cycles; 200 uint32_t ystorm_inactive_cycles; 201 202 /* pstorm */ 203 uint32_t pstorm_active_cycles; 204 uint32_t pstorm_stall_cycles; 205 uint32_t pstorm_sleeping_cycles; 206 uint32_t pstorm_inactive_cycles; 207 208 /* tstorm */ 209 uint32_t tstorm_active_cycles; 210 uint32_t tstorm_stall_cycles; 211 uint32_t tstorm_sleeping_cycles; 212 uint32_t tstorm_inactive_cycles; 213 214 /* mstorm */ 215 uint32_t mstorm_active_cycles; 216 uint32_t mstorm_stall_cycles; 217 uint32_t mstorm_sleeping_cycles; 218 uint32_t mstorm_inactive_cycles; 219 220 /* ustorm */ 221 uint32_t ustorm_active_cycles; 222 uint32_t ustorm_stall_cycles; 223 uint32_t ustorm_sleeping_cycles; 224 uint32_t ustorm_inactive_cycles; 225}; 226 227typedef struct qlnx_storm_stats qlnx_storm_stats_t; 228 229#define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000) 230 231#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \ 232 QLNX_STORM_STATS_SAMPLES_PER_HWFN) 233 234struct qlnx_storm_stats_dump { 235 int num_hwfns; 236 int num_samples; 237 void *buffer[QLNX_MAX_HW_FUNCS]; 238}; 239 240typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t; 241 242#define QLNX_LLDP_TYPE_END_OF_LLDPDU 0 243#define QLNX_LLDP_TYPE_CHASSIS_ID 1 244#define QLNX_LLDP_TYPE_PORT_ID 2 245#define QLNX_LLDP_TYPE_TTL 3 246#define QLNX_LLDP_TYPE_PORT_DESC 4 247#define QLNX_LLDP_TYPE_SYS_NAME 5 248#define QLNX_LLDP_TYPE_SYS_DESC 6 249#define QLNX_LLDP_TYPE_SYS_CAPS 7 250#define QLNX_LLDP_TYPE_MGMT_ADDR 8 251#define QLNX_LLDP_TYPE_ORG_SPECIFIC 127 252 253#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 254#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC 0x04 //Mac Address 255#define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 256#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME 0x06 //Interface Name 257 258#define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 259#define QLNX_LLDP_PORT_ID_SUBTYPE_MAC 0x03 //Mac Address 260#define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 261#define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME 0x05 //Interface Name 262 263#define QLNX_LLDP_SYS_TLV_SIZE 256 264struct qlnx_lldp_sys_tlvs { 265 int discard_mandatory_tlv; 266 uint8_t buf[QLNX_LLDP_SYS_TLV_SIZE]; 267 uint16_t buf_size; 268}; 269typedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t; 270 271 272/* 273 * Read grcdump size 274 */ 275#define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t) 276 277/* 278 * Read grcdump 279 */ 280#define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t) 281 282/* 283 * Read idle_chk size 284 */ 285#define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t) 286 287/* 288 * Read idle_chk 289 */ 290#define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t) 291 292/* 293 * Read driver info 294 */ 295#define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t) 296 297/* 298 * Read Device Setting 299 */ 300#define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t) 301 302/* 303 * Get Registers 304 */ 305#define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t) 306 307/* 308 * Get/Set NVRAM 309 */ 310#define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t) 311 312/* 313 * Get/Set Device registers 314 */ 315#define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t) 316 317/* 318 * Read/Write PCI Configuration 319 */ 320#define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t) 321 322/* 323 * Read MAC address 324 */ 325#define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t) 326 327/* 328 * Read STORM statistics 329 */ 330#define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t) 331 332/* 333 * Read trace size 334 */ 335#define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t) 336 337/* 338 * Read trace 339 */ 340#define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t) 341 342/* 343 * Set LLDP TLVS 344 */ 345#define QLNX_SET_LLDP_TLVS _IOWR('q', 15, qlnx_lldp_sys_tlvs_t) 346 347#endif /* #ifndef _QLNX_IOCTL_H_ */ 348