1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/nvm_cfg.h 337517 2018-08-09 01:17:35Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs 32316485Sdavidcs/**************************************************************************** 33316485Sdavidcs * 34316485Sdavidcs * Name: nvm_cfg.h 35316485Sdavidcs * 36316485Sdavidcs * Description: NVM config file - Generated file from nvm cfg excel. 37316485Sdavidcs * DO NOT MODIFY !!! 38316485Sdavidcs * 39337517Sdavidcs * Created: 12/4/2017 40316485Sdavidcs * 41316485Sdavidcs ****************************************************************************/ 42316485Sdavidcs 43316485Sdavidcs#ifndef NVM_CFG_H 44316485Sdavidcs#define NVM_CFG_H 45316485Sdavidcs 46316485Sdavidcs 47337517Sdavidcs#define NVM_CFG_version 0x83306 48316485Sdavidcs 49337517Sdavidcs#define NVM_CFG_new_option_seq 26 50316485Sdavidcs 51337517Sdavidcs#define NVM_CFG_removed_option_seq 2 52316485Sdavidcs 53337517Sdavidcs#define NVM_CFG_updated_value_seq 5 54337517Sdavidcs 55316485Sdavidcsstruct nvm_cfg_mac_address 56316485Sdavidcs{ 57316485Sdavidcs u32 mac_addr_hi; 58316485Sdavidcs #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 59316485Sdavidcs #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 60316485Sdavidcs u32 mac_addr_lo; 61316485Sdavidcs}; 62316485Sdavidcs 63316485Sdavidcs/****************************************** 64316485Sdavidcs * nvm_cfg1 structs 65316485Sdavidcs ******************************************/ 66316485Sdavidcsstruct nvm_cfg1_glob 67316485Sdavidcs{ 68316485Sdavidcs u32 generic_cont0; /* 0x0 */ 69316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 70316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 71316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 72316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 73316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 74316485Sdavidcs #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 75316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 76316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 77316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 78316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 79316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 80316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 81316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 82316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 83316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 84316485Sdavidcs #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 85316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 86316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 87316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 88316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 89316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 90316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 91316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 92316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 93316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 94316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 95316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 96316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 97316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 98316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 99316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 100316485Sdavidcs #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 101316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 102316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 103316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 104316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 105316485Sdavidcs u32 engineering_change[3]; /* 0x4 */ 106316485Sdavidcs u32 manufacturing_id; /* 0x10 */ 107316485Sdavidcs u32 serial_number[4]; /* 0x14 */ 108316485Sdavidcs u32 pcie_cfg; /* 0x24 */ 109316485Sdavidcs #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 110316485Sdavidcs #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 111316485Sdavidcs #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 112316485Sdavidcs #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 113316485Sdavidcs #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 114316485Sdavidcs #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 115316485Sdavidcs #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 116316485Sdavidcs #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 117316485Sdavidcs #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 118316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 119316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 120316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 121316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 122316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 123316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 124316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 125316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 126316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 127316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 128316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 129316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 130316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 131316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 132316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 133316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 134316485Sdavidcs #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 135316485Sdavidcs #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 136316485Sdavidcs #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 137316485Sdavidcs #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 138316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 139316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 140316485Sdavidcs /* Set the duration, in seconds, fan failure signal should be 141316485Sdavidcs sampled */ 142316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 143316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 144316485Sdavidcs u32 mgmt_traffic; /* 0x28 */ 145316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 146316485Sdavidcs #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 147316485Sdavidcs #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 148316485Sdavidcs #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 149316485Sdavidcs #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 150316485Sdavidcs #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 151316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 152316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 153316485Sdavidcs #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 154316485Sdavidcs #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 155316485Sdavidcs #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 156316485Sdavidcs #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 157316485Sdavidcs #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 158316485Sdavidcs #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 159316485Sdavidcs #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 160316485Sdavidcs #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 161316485Sdavidcs #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 162316485Sdavidcs /* Indicates whether external thermal sonsor is available */ 163316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 164316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 165316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 166316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 167316485Sdavidcs u32 core_cfg; /* 0x2C */ 168316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 169316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 170316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 171316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 172316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 173316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 174316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 175316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 176316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 177316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 178316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 179316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 180316485Sdavidcs #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 181316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 182316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 183316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 184316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 185316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 186316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 187316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 188316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 189316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 190316485Sdavidcs #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 191316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 192316485Sdavidcs #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 193316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 194316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 195316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 196316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 197316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 198316485Sdavidcs #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 199316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 200316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 201316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 202316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 203316485Sdavidcs #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 204316485Sdavidcs #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 205316485Sdavidcs #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 206316485Sdavidcs #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 207316485Sdavidcs u32 e_lane_cfg1; /* 0x30 */ 208316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 209316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 210316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 211316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 212316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 213316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 214316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 215316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 216316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 217316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 218316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 219316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 220316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 221316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 222316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 223316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 224316485Sdavidcs u32 e_lane_cfg2; /* 0x34 */ 225316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 226316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 227316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 228316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 229316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 230316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 231316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 232316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 233316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 234316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 235316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 236316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 237316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 238316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 239316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 240316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 241316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 242316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 243316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 244316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 245316485Sdavidcs #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 246316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 247316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_OFFSET 12 248316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 249316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 250316485Sdavidcs /* Maximum advertised pcie link width */ 251316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 252316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 253316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 254316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 255316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 256316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 257316485Sdavidcs #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 258316485Sdavidcs /* ASPM L1 mode */ 259316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 260316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 261316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 262316485Sdavidcs #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 263316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 264316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 265316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 266316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 267316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 268316485Sdavidcs #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 269316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 270316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 271316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 272316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 273316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 274316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 275316485Sdavidcs /* Set the PLDM sensor modes */ 276316485Sdavidcs #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 277316485Sdavidcs #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 278316485Sdavidcs #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 279316485Sdavidcs #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 280316485Sdavidcs #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 281316485Sdavidcs /* Enable VDM interface */ 282316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 283316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 284316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 285316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 286316485Sdavidcs /* ROL enable */ 287316485Sdavidcs #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 288316485Sdavidcs #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 289316485Sdavidcs #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 290316485Sdavidcs #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 291316485Sdavidcs u32 f_lane_cfg1; /* 0x38 */ 292316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 293316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 294316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 295316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 296316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 297316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 298316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 299316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 300316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 301316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 302316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 303316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 304316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 305316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 306316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 307316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 308316485Sdavidcs u32 f_lane_cfg2; /* 0x3C */ 309316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 310316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 311316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 312316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 313316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 314316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 315316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 316316485Sdavidcs #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 317316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 318316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 319316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 320316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 321316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 322316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 323316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 324316485Sdavidcs #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 325316485Sdavidcs /* Control the period between two successive checks */ 326316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 327316485Sdavidcs #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 328316485Sdavidcs /* Set shutdown temperature */ 329316485Sdavidcs #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 330316485Sdavidcs #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 331316485Sdavidcs /* Set max. count for over operational temperature */ 332316485Sdavidcs #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 333316485Sdavidcs #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 334316485Sdavidcs u32 mps10_preemphasis; /* 0x40 */ 335316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 336316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 337316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 338316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 339316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 340316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 341316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 342316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 343316485Sdavidcs u32 mps10_driver_current; /* 0x44 */ 344316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 345316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 346316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 347316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 348316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 349316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 350316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 351316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 352316485Sdavidcs u32 mps25_preemphasis; /* 0x48 */ 353316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 354316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 355316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 356316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 357316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 358316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 359316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 360316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 361316485Sdavidcs u32 mps25_driver_current; /* 0x4C */ 362316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 363316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 364316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 365316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 366316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 367316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 368316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 369316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 370316485Sdavidcs u32 pci_id; /* 0x50 */ 371316485Sdavidcs #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 372316485Sdavidcs #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 373316485Sdavidcs /* Set caution temperature */ 374337517Sdavidcs #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_MASK 0x00FF0000 375337517Sdavidcs #define NVM_CFG1_GLOB_DEAD_TEMP_TH_TEMPERATURE_OFFSET 16 376316485Sdavidcs /* Set external thermal sensor I2C address */ 377316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 378316485Sdavidcs #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 379316485Sdavidcs u32 pci_subsys_id; /* 0x54 */ 380316485Sdavidcs #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 381316485Sdavidcs #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 382316485Sdavidcs #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 383316485Sdavidcs #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 384316485Sdavidcs u32 bar; /* 0x58 */ 385316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 386316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 387316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 388316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 389316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 390316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 391316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 392316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 393316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 394316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 395316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 396316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 397316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 398316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 399316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 400316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 401316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 402316485Sdavidcs #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 403316485Sdavidcs /* BB VF BAR2 size */ 404316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 405316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 406316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 407316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 408316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 409316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 410316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 411316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 412316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 413316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 414316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 415316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 416316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 417316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 418316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 419316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 420316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 421316485Sdavidcs #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 422316485Sdavidcs /* BB BAR2 size (global) */ 423316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 424316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 425316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 426316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 427316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 428316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 429316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 430316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 431316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 432316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 433316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 434316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 435316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 436316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 437316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 438316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 439316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 440316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 441316485Sdavidcs /* Set the duration, in seconds, fan failure signal should be 442316485Sdavidcs sampled */ 443316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 444316485Sdavidcs #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 445316485Sdavidcs /* This field defines the board total budget for bar2 when disabled 446316485Sdavidcs the regular bar size is used. */ 447316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 448316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 449316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 450316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 451316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 452316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 453316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 454316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 455316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 456316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 457316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 458316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 459316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 460316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 461316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 462316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 463316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 464316485Sdavidcs #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 465316485Sdavidcs /* Enable/Disable Crash dump triggers */ 466316485Sdavidcs #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 467316485Sdavidcs #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 468316485Sdavidcs u32 mps10_txfir_main; /* 0x5C */ 469316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 470316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 471316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 472316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 473316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 474316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 475316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 476316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 477316485Sdavidcs u32 mps10_txfir_post; /* 0x60 */ 478316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 479316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 480316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 481316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 482316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 483316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 484316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 485316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 486316485Sdavidcs u32 mps25_txfir_main; /* 0x64 */ 487316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 488316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 489316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 490316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 491316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 492316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 493316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 494316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 495316485Sdavidcs u32 mps25_txfir_post; /* 0x68 */ 496316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 497316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 498316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 499316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 500316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 501316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 502316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 503316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 504316485Sdavidcs u32 manufacture_ver; /* 0x6C */ 505316485Sdavidcs #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 506316485Sdavidcs #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 507316485Sdavidcs #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 508316485Sdavidcs #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 509316485Sdavidcs #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 510316485Sdavidcs #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 511316485Sdavidcs #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 512316485Sdavidcs #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 513316485Sdavidcs #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 514316485Sdavidcs #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 515316485Sdavidcs /* Select package id method */ 516316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 517316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 518316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 519316485Sdavidcs #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 520316485Sdavidcs #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 521316485Sdavidcs #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 522316485Sdavidcs #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 523316485Sdavidcs #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 524316485Sdavidcs u32 manufacture_time; /* 0x70 */ 525316485Sdavidcs #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 526316485Sdavidcs #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 527316485Sdavidcs #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 528316485Sdavidcs #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 529316485Sdavidcs #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 530316485Sdavidcs #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 531316485Sdavidcs /* Max MSIX for Ethernet in default mode */ 532316485Sdavidcs #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 533316485Sdavidcs #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 534316485Sdavidcs /* PF Mapping */ 535316485Sdavidcs #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 536316485Sdavidcs #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 537316485Sdavidcs #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 538316485Sdavidcs #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 539320164Sdavidcs #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 540320164Sdavidcs #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 541320164Sdavidcs #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 542320164Sdavidcs #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 543337517Sdavidcs /* Enable/Disable PCIE Relaxed Ordering */ 544337517Sdavidcs #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK 0x40000000 545337517Sdavidcs #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_OFFSET 30 546337517Sdavidcs #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED 0x0 547337517Sdavidcs #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED 0x1 548316485Sdavidcs u32 led_global_settings; /* 0x74 */ 549316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 550316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 551316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 552316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 553316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 554316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 555316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 556316485Sdavidcs #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 557316485Sdavidcs /* Max. continues operating temperature */ 558316485Sdavidcs #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 559316485Sdavidcs #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 560316485Sdavidcs /* GPIO which triggers run-time port swap according to the map 561316485Sdavidcs specified in option 205 */ 562316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 563316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 564316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 565316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 566316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 567316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 568316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 569316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 570316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 571316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 572316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 573316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 574316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 575316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 576316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 577316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 578316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 579316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 580316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 581316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 582316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 583316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 584316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 585316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 586316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 587316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 588316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 589316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 590316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 591316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 592316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 593316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 594316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 595316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 596316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 597316485Sdavidcs u32 generic_cont1; /* 0x78 */ 598316485Sdavidcs #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 599316485Sdavidcs #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 600316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 601316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 602316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 603316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 604316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 605316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 606316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 607316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 608316485Sdavidcs /* Enable option 195 - Overriding the PCIe Preset value */ 609316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 610316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 611316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 612316485Sdavidcs #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 613316485Sdavidcs /* PCIe Preset value - applies only if option 194 is enabled */ 614316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 615316485Sdavidcs #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 616316485Sdavidcs /* Port mapping to be used when the run-time GPIO for port-swap is 617316485Sdavidcs defined and set. */ 618316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 619316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 620316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 621316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 622316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 623316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 624316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 625316485Sdavidcs #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 626316485Sdavidcs u32 mbi_version; /* 0x7C */ 627316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 628316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 629316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 630316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 631316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 632316485Sdavidcs #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 633316485Sdavidcs /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 634316485Sdavidcs occurred */ 635316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 636316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 637316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 638316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 639316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 640316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 641316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 642316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 643316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 644316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 645316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 646316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 647316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 648316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 649316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 650316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 651316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 652316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 653316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 654316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 655316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 656316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 657316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 658316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 659316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 660316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 661316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 662316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 663316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 664316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 665316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 666316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 667316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 668316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 669316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 670316485Sdavidcs u32 mbi_date; /* 0x80 */ 671316485Sdavidcs u32 misc_sig; /* 0x84 */ 672316485Sdavidcs /* Define the GPIO mapping to switch i2c mux */ 673316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 674316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 675316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 676316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 677316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 678316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 679316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 680316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 681316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 682316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 683316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 684316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 685316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 686316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 687316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 688316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 689316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 690316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 691316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 692316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 693316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 694316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 695316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 696316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 697316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 698316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 699316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 700316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 701316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 702316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 703316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 704316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 705316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 706316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 707316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 708316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 709316485Sdavidcs #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 710316485Sdavidcs /* Interrupt signal used for SMBus/I2C management interface 711316485Sdavidcs 712316485Sdavidcs 0 = Interrupt event occurred 713316485Sdavidcs 1 = Normal 714316485Sdavidcs */ 715316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 716316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 717316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 718316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 719316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 720316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 721316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 722316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 723316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 724316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 725316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 726316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 727316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 728316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 729316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 730316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 731316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 732316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 733316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 734316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 735316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 736316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 737316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 738316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 739316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 740316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 741316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 742316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 743316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 744316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 745316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 746316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 747316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 748316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 749316485Sdavidcs #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 750316485Sdavidcs /* Set aLOM FAN on GPIO */ 751316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 752316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 753316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 754316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 755316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 756316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 757316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 758316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 759316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 760316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 761316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 762316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 763316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 764316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 765316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 766316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 767316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 768316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 769316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 770316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 771316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 772316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 773316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 774316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 775316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 776316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 777316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 778316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 779316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 780316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 781316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 782316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 783316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 784316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 785316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 786316485Sdavidcs u32 device_capabilities; /* 0x88 */ 787316485Sdavidcs #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 788316485Sdavidcs #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 789316485Sdavidcs #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 790316485Sdavidcs #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 791316485Sdavidcs #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 792316485Sdavidcs u32 power_dissipated; /* 0x8C */ 793316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 794316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 795316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 796316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 797316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 798316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 799316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 800316485Sdavidcs #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 801316485Sdavidcs u32 power_consumed; /* 0x90 */ 802316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 803316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 804316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 805316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 806316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 807316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 808316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 809316485Sdavidcs #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 810316485Sdavidcs u32 efi_version; /* 0x94 */ 811316485Sdavidcs u32 multi_network_modes_capability; /* 0x98 */ 812316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 813316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 814316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 815316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 816316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 817316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 818316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 819316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 820316485Sdavidcs #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 821316485Sdavidcs u32 nvm_cfg_version; /* 0x9C */ 822316485Sdavidcs u32 nvm_cfg_new_option_seq; /* 0xA0 */ 823316485Sdavidcs u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 824316485Sdavidcs u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 825316485Sdavidcs u32 extended_serial_number[8]; /* 0xAC */ 826316485Sdavidcs u32 oem1_number[8]; /* 0xCC */ 827316485Sdavidcs u32 oem2_number[8]; /* 0xEC */ 828316485Sdavidcs u32 mps25_active_txfir_pre; /* 0x10C */ 829316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 830316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 831316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 832316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 833316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 834316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 835316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 836316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 837316485Sdavidcs u32 mps25_active_txfir_main; /* 0x110 */ 838316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 839316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 840316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 841316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 842316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 843316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 844316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 845316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 846316485Sdavidcs u32 mps25_active_txfir_post; /* 0x114 */ 847316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 848316485Sdavidcs #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 849316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 850316485Sdavidcs #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 851316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 852316485Sdavidcs #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 853316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 854316485Sdavidcs #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 855316485Sdavidcs u32 features; /* 0x118 */ 856316485Sdavidcs /* Set the Aux Fan on temperature */ 857316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 858316485Sdavidcs #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 859316485Sdavidcs /* Set NC-SI package ID */ 860316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 861316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 862316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 863316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 864316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 865316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 866316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 867316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 868316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 869316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 870316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 871316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 872316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 873316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 874316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 875316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 876316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 877316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 878316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 879316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 880316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 881316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 882316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 883316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 884316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 885316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 886316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 887316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 888316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 889316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 890316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 891316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 892316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 893316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 894316485Sdavidcs #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 895316485Sdavidcs /* PMBUS Clock GPIO */ 896316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 897316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 898316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 899316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 900316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 901316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 902316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 903316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 904316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 905316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 906316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 907316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 908316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 909316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 910316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 911316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 912316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 913316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 914316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 915316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 916316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 917316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 918316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 919316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 920316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 921316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 922316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 923316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 924316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 925316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 926316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 927316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 928316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 929316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 930316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 931316485Sdavidcs /* PMBUS Data GPIO */ 932316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 933316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 934316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 935316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 936316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 937316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 938316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 939316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 940316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 941316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 942316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 943316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 944316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 945316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 946316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 947316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 948316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 949316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 950316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 951316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 952316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 953316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 954316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 955316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 956316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 957316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 958316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 959316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 960316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 961316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 962316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 963316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 964316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 965316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 966316485Sdavidcs #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 967316485Sdavidcs u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 968316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 969316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 970316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 971316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 972316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 973316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 974316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 975316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 976316485Sdavidcs u32 tx_rx_eq_25g_llpc; /* 0x120 */ 977316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 978316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 979316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 980316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 981316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 982316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 983316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 984316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 985316485Sdavidcs u32 tx_rx_eq_25g_ac; /* 0x124 */ 986316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 987316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 988316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 989316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 990316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 991316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 992316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 993316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 994316485Sdavidcs u32 tx_rx_eq_10g_pc; /* 0x128 */ 995316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 996316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 997316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 998316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 999316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 1000316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 1001316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 1002316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 1003316485Sdavidcs u32 tx_rx_eq_10g_ac; /* 0x12C */ 1004316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 1005316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 1006316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 1007316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 1008316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 1009316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1010316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1011316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1012316485Sdavidcs u32 tx_rx_eq_1g; /* 0x130 */ 1013316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1014316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1015316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1016316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1017316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1018316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1019316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1020316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1021316485Sdavidcs u32 tx_rx_eq_25g_bt; /* 0x134 */ 1022316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1023316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1024316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1025316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1026316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1027316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1028316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1029316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1030316485Sdavidcs u32 tx_rx_eq_10g_bt; /* 0x138 */ 1031316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1032316485Sdavidcs #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1033316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1034316485Sdavidcs #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1035316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1036316485Sdavidcs #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1037316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1038316485Sdavidcs #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1039316485Sdavidcs u32 generic_cont4; /* 0x13C */ 1040316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1041316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1042316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1043316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1044316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1045316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1046316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1047316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1048316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1049316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1050316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1051316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1052316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1053316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1054316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1055316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1056316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1057316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1058316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1059316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1060316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1061316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1062316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1063316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1064316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1065316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1066316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1067316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1068316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1069316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1070316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1071316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1072316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1073316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1074316485Sdavidcs #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1075316485Sdavidcs u32 preboot_debug_mode_std; /* 0x140 */ 1076316485Sdavidcs u32 preboot_debug_mode_ext; /* 0x144 */ 1077337517Sdavidcs u32 ext_phy_cfg1; /* 0x148 */ 1078337517Sdavidcs /* Ext PHY MDI pair swap value */ 1079337517Sdavidcs #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF 1080337517Sdavidcs #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0 1081337517Sdavidcs u32 clocks; /* 0x14C */ 1082337517Sdavidcs /* Sets core clock frequency */ 1083337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF 1084337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0 1085337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0 1086337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1 1087337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2 1088337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3 1089337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4 1090337517Sdavidcs #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5 1091337517Sdavidcs /* Sets MAC clock frequency */ 1092337517Sdavidcs #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00 1093337517Sdavidcs #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8 1094337517Sdavidcs #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0 1095337517Sdavidcs #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1 1096337517Sdavidcs #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2 1097337517Sdavidcs /* Sets storm clock frequency */ 1098337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000 1099337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16 1100337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0 1101337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1 1102337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2 1103337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3 1104337517Sdavidcs #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4 1105337517Sdavidcs u32 reserved[54]; /* 0x150 */ 1106316485Sdavidcs}; 1107316485Sdavidcs 1108316485Sdavidcsstruct nvm_cfg1_path 1109316485Sdavidcs{ 1110316485Sdavidcs u32 reserved[1]; /* 0x0 */ 1111316485Sdavidcs}; 1112316485Sdavidcs 1113316485Sdavidcsstruct nvm_cfg1_port 1114316485Sdavidcs{ 1115316485Sdavidcs u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1116316485Sdavidcs u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1117316485Sdavidcs u32 generic_cont0; /* 0x8 */ 1118316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1119316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1120316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1121316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1122316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1123316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1124316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1125316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1126316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1127316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1128316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1129316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1130316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1131316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1132316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1133316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1134316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1135316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1136316485Sdavidcs #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1137316485Sdavidcs #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1138316485Sdavidcs #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1139316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1140316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1141316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1142316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1143316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1144316485Sdavidcs #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1145316485Sdavidcs #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1146316485Sdavidcs #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1147316485Sdavidcs #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1148316485Sdavidcs #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1149316485Sdavidcs #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1150316485Sdavidcs /* GPIO for HW reset the PHY. In case it is the same for all ports, 1151316485Sdavidcs need to set same value for all ports */ 1152316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1153316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1154316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1155316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1156316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1157316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1158316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1159316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1160316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1161316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1162316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1163316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1164316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1165316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1166316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1167316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1168316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1169316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1170316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1171316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1172316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1173316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1174316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1175316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1176316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1177316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1178316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1179316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1180316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1181316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1182316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1183316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1184316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1185316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1186316485Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1187316485Sdavidcs u32 pcie_cfg; /* 0xC */ 1188316485Sdavidcs #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1189316485Sdavidcs #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1190316485Sdavidcs u32 features; /* 0x10 */ 1191316485Sdavidcs #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1192316485Sdavidcs #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1193316485Sdavidcs #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1194316485Sdavidcs #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1195316485Sdavidcs #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1196316485Sdavidcs #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1197316485Sdavidcs #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1198316485Sdavidcs #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1199316485Sdavidcs u32 speed_cap_mask; /* 0x14 */ 1200316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1201316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1202316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1203316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1204337517Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1205316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1206316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1207316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1208316485Sdavidcs #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1209316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1210316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1211316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1212316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1213337517Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1214316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1215316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1216316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1217316485Sdavidcs #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1218316485Sdavidcs u32 link_settings; /* 0x18 */ 1219316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1220316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1221316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1222316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1223316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1224337517Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 1225316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1226316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1227316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1228316485Sdavidcs #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1229316485Sdavidcs #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1230316485Sdavidcs #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1231316485Sdavidcs #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1232316485Sdavidcs #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1233316485Sdavidcs #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1234316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1235316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1236316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1237316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1238316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1239337517Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3 1240316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1241316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1242316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1243316485Sdavidcs #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1244316485Sdavidcs #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1245316485Sdavidcs #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1246316485Sdavidcs #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1247316485Sdavidcs #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1248316485Sdavidcs #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1249316485Sdavidcs #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1250316485Sdavidcs #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1251316485Sdavidcs #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1252316485Sdavidcs #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1253316485Sdavidcs #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1254316485Sdavidcs #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1255316485Sdavidcs #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1256316485Sdavidcs #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1257316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1258316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1259316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1260316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1261316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1262316485Sdavidcs #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1263316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1264316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1265316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1266316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1267316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1268316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1269316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1270316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1271316485Sdavidcs #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1272316485Sdavidcs #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1273316485Sdavidcs #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1274316485Sdavidcs #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1275316485Sdavidcs #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1276316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1277316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1278316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1279316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1280316485Sdavidcs u32 phy_cfg; /* 0x1C */ 1281316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1282316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1283316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1284316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1285316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1286316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1287316485Sdavidcs #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1288316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1289316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1290316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1291316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1292316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1293316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1294316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1295316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1296316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1297316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1298316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1299316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1300316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1301316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1302316485Sdavidcs #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1303316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1304316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1305316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1306316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1307316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1308316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1309316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1310316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1311316485Sdavidcs #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1312316485Sdavidcs u32 mgmt_traffic; /* 0x20 */ 1313316485Sdavidcs #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1314316485Sdavidcs #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1315316485Sdavidcs u32 ext_phy; /* 0x24 */ 1316316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1317316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1318316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1319316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1320337517Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2 1321316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1322316485Sdavidcs #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1323316485Sdavidcs /* EEE power saving mode */ 1324316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1325316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1326316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1327316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1328316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1329316485Sdavidcs #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1330316485Sdavidcs u32 mba_cfg1; /* 0x28 */ 1331316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1332316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1333316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1334316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1335316485Sdavidcs #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1336316485Sdavidcs #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1337316485Sdavidcs #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1338316485Sdavidcs #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1339316485Sdavidcs #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1340316485Sdavidcs #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1341316485Sdavidcs #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1342316485Sdavidcs #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1343316485Sdavidcs #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1344316485Sdavidcs #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1345316485Sdavidcs #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1346316485Sdavidcs #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1347316485Sdavidcs #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1348316485Sdavidcs #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1349316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1350316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1351316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1352316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1353316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1354337517Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3 1355316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1356316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1357316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1358316485Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1359316485Sdavidcs #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1360316485Sdavidcs #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1361316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1362316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1363316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1364316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1365316485Sdavidcs u32 mba_cfg2; /* 0x2C */ 1366316485Sdavidcs #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1367316485Sdavidcs #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1368316485Sdavidcs #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1369316485Sdavidcs #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1370320164Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 1371320164Sdavidcs #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 1372316485Sdavidcs u32 vf_cfg; /* 0x30 */ 1373316485Sdavidcs #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1374316485Sdavidcs #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1375316485Sdavidcs #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1376316485Sdavidcs #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1377316485Sdavidcs struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1378316485Sdavidcs u32 led_port_settings; /* 0x3C */ 1379316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1380316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1381316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1382316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1383316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1384316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1385316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1386316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1387316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1388316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1389316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1390316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1391316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1392316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1393316485Sdavidcs #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1394337517Sdavidcs /* UID LED Blink Mode Settings */ 1395337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK 0x0F000000 1396337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_OFFSET 24 1397337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED 0x1 1398337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0 0x2 1399337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1 0x4 1400337517Sdavidcs #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2 0x8 1401316485Sdavidcs u32 transceiver_00; /* 0x40 */ 1402316485Sdavidcs /* Define for mapping of transceiver signal module absent */ 1403316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1404316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1405316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1406316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1407316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1408316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1409316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1410316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1411316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1412316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1413316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1414316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1415316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1416316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1417316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1418316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1419316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1420316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1421316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1422316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1423316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1424316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1425316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1426316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1427316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1428316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1429316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1430316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1431316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1432316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1433316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1434316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1435316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1436316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1437316485Sdavidcs #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1438316485Sdavidcs /* Define the GPIO mux settings to switch i2c mux to this port */ 1439316485Sdavidcs #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1440316485Sdavidcs #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1441316485Sdavidcs #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1442316485Sdavidcs #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1443316485Sdavidcs u32 device_ids; /* 0x44 */ 1444316485Sdavidcs #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1445316485Sdavidcs #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1446316485Sdavidcs #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1447316485Sdavidcs #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1448316485Sdavidcs #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1449316485Sdavidcs #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1450316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1451316485Sdavidcs #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1452316485Sdavidcs u32 board_cfg; /* 0x48 */ 1453316485Sdavidcs /* This field defines the board technology 1454316485Sdavidcs (backpane,transceiver,external PHY) */ 1455316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1456316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1457316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1458316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1459316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1460316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1461316485Sdavidcs #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1462316485Sdavidcs /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1463316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1464316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1465316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1466316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1467316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1468316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1469316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1470316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1471316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1472316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1473316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1474316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1475316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1476316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1477316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1478316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1479316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1480316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1481316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1482316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1483316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1484316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1485316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1486316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1487316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1488316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1489316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1490316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1491316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1492316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1493316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1494316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1495316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1496316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1497316485Sdavidcs #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1498316485Sdavidcs u32 mnm_10g_cap; /* 0x4C */ 1499316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1500316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1501316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1502316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1503337517Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1504316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1505316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1506316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1507316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1508316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1509316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1510316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1511316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1512337517Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1513316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1514316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1515316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1516316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1517316485Sdavidcs u32 mnm_10g_ctrl; /* 0x50 */ 1518316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1519316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1520316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1521316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1522316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1523337517Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3 1524316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1525316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1526316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1527316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1528316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1529316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1530316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1531316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1532316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1533337517Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3 1534316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1535316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1536316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1537316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1538316485Sdavidcs /* This field defines the board technology 1539316485Sdavidcs (backpane,transceiver,external PHY) */ 1540316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1541316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1542316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1543316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1544316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1545316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1546316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1547316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1548316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1549316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1550316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1551316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1552316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1553316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1554316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1555316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1556316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1557316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1558316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1559316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1560316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1561316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1562316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1563316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1564316485Sdavidcs u32 mnm_10g_misc; /* 0x54 */ 1565316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1566316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1567316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1568316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1569316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1570316485Sdavidcs #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1571316485Sdavidcs u32 mnm_25g_cap; /* 0x58 */ 1572316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1573316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1574316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1575316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1576337517Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1577316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1578316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1579316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1580316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1581316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1582316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1583316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1584316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1585337517Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1586316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1587316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1588316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1589316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1590316485Sdavidcs u32 mnm_25g_ctrl; /* 0x5C */ 1591316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1592316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1593316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1594316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1595316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1596337517Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3 1597316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1598316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1599316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1600316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1601316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1602316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1603316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1604316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1605316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1606337517Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3 1607316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1608316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1609316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1610316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1611316485Sdavidcs /* This field defines the board technology 1612316485Sdavidcs (backpane,transceiver,external PHY) */ 1613316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1614316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1615316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1616316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1617316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1618316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1619316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1620316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1621316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1622316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1623316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1624316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1625316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1626316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1627316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1628316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1629316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1630316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1631316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1632316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1633316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1634316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1635316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1636316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1637316485Sdavidcs u32 mnm_25g_misc; /* 0x60 */ 1638316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1639316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1640316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1641316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1642316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1643316485Sdavidcs #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1644316485Sdavidcs u32 mnm_40g_cap; /* 0x64 */ 1645316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1646316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1647316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1648316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1649337517Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1650316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1651316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1652316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1653316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1654316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1655316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1656316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1657316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1658337517Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1659316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1660316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1661316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1662316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1663316485Sdavidcs u32 mnm_40g_ctrl; /* 0x68 */ 1664316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1665316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1666316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1667316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1668316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1669337517Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3 1670316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1671316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1672316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1673316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1674316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1675316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1676316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1677316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1678316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1679337517Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3 1680316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1681316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1682316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1683316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1684316485Sdavidcs /* This field defines the board technology 1685316485Sdavidcs (backpane,transceiver,external PHY) */ 1686316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1687316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1688316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1689316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1690316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1691316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1692316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1693316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1694316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1695316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1696316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1697316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1698316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1699316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1700316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1701316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1702316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1703316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1704316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1705316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1706316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1707316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1708316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1709316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1710316485Sdavidcs u32 mnm_40g_misc; /* 0x6C */ 1711316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1712316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1713316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1714316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1715316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1716316485Sdavidcs #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1717316485Sdavidcs u32 mnm_50g_cap; /* 0x70 */ 1718316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1719316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1720316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1721316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1722337517Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 1723316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1724316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1725316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1726316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1727316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1728316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1729316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1730316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1731337517Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 1732316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1733316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1734316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1735316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1736316485Sdavidcs u32 mnm_50g_ctrl; /* 0x74 */ 1737316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1738316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1739316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1740316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1741316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1742337517Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3 1743316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1744316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1745316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1746316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1747316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1748316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1749316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1750316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1751316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1752337517Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3 1753316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1754316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1755316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1756316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1757316485Sdavidcs /* This field defines the board technology 1758316485Sdavidcs (backpane,transceiver,external PHY) */ 1759316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1760316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1761316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1762316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1763316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1764316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1765316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1766316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1767316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1768316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1769316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1770316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1771316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1772316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1773316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1774316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1775316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1776316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1777316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1778316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1779316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1780316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1781316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1782316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1783316485Sdavidcs u32 mnm_50g_misc; /* 0x78 */ 1784316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1785316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1786316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1787316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1788316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1789316485Sdavidcs #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1790316485Sdavidcs u32 mnm_100g_cap; /* 0x7C */ 1791316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1792316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1793316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1794316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1795337517Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4 1796316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1797316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1798316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1799316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1800316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1801316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1802316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1803316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1804337517Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4 1805316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1806316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1807316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1808316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1809316485Sdavidcs u32 mnm_100g_ctrl; /* 0x80 */ 1810316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1811316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1812316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1813316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1814316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1815337517Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3 1816316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1817316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1818316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1819316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1820316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1821316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1822316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1823316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1824316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1825337517Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3 1826316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1827316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1828316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1829316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1830316485Sdavidcs /* This field defines the board technology 1831316485Sdavidcs (backpane,transceiver,external PHY) */ 1832316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1833316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1834316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1835316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1836316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1837316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1838316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1839316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1840316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1841316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1842316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1843316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1844316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1845316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1846316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1847316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1848316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1849316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1850316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1851316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1852316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1853316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1854316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1855316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1856316485Sdavidcs u32 mnm_100g_misc; /* 0x84 */ 1857316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1858316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1859316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1860316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1861316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1862316485Sdavidcs #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1863316485Sdavidcs u32 temperature; /* 0x88 */ 1864316485Sdavidcs #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1865316485Sdavidcs #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1866316485Sdavidcs #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1867316485Sdavidcs #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1868337517Sdavidcs u32 ext_phy_cfg1; /* 0x8C */ 1869337517Sdavidcs /* Ext PHY MDI pair swap value */ 1870337517Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF 1871337517Sdavidcs #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0 1872337517Sdavidcs u32 reserved[114]; /* 0x90 */ 1873316485Sdavidcs}; 1874316485Sdavidcs 1875316485Sdavidcsstruct nvm_cfg1_func 1876316485Sdavidcs{ 1877316485Sdavidcs struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1878316485Sdavidcs u32 rsrv1; /* 0x8 */ 1879316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1880316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1881316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1882316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1883316485Sdavidcs u32 rsrv2; /* 0xC */ 1884316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1885316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1886316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1887316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1888316485Sdavidcs u32 device_id; /* 0x10 */ 1889316485Sdavidcs #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1890316485Sdavidcs #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1891316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1892316485Sdavidcs #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1893316485Sdavidcs u32 cmn_cfg; /* 0x14 */ 1894316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1895316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1896316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1897316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1898316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1899316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1900316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1901316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1902316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1903316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1904316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1905316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1906316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1907316485Sdavidcs #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1908316485Sdavidcs #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1909316485Sdavidcs #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1910316485Sdavidcs #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1911316485Sdavidcs #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1912316485Sdavidcs #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1913316485Sdavidcs #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1914316485Sdavidcs u32 pci_cfg; /* 0x18 */ 1915316485Sdavidcs #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1916316485Sdavidcs #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1917316485Sdavidcs /* AH VF BAR2 size */ 1918316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1919316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1920316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1921316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1922316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1923316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1924316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1925316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1926316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1927316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1928316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1929316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1930316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1931316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1932316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1933316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1934316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1935316485Sdavidcs #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1936316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1937316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1938316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1939316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1940316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1941316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1942316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1943316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1944316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1945316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1946316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1947316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1948316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1949316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1950316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1951316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1952316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1953316485Sdavidcs #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1954316485Sdavidcs #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1955316485Sdavidcs #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1956316485Sdavidcs /* Hide function in npar mode */ 1957316485Sdavidcs #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1958316485Sdavidcs #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1959316485Sdavidcs #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1960316485Sdavidcs #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1961316485Sdavidcs /* AH BAR2 size (per function) */ 1962316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1963316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1964316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1965316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1966316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1967316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1968316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1969316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1970316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1971316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1972316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1973316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1974316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1975316485Sdavidcs #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1976316485Sdavidcs struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1977316485Sdavidcs struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1978316485Sdavidcs u32 preboot_generic_cfg; /* 0x2C */ 1979316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1980316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1981316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1982316485Sdavidcs #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1983316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1984316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1985316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1986316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1987316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1988316485Sdavidcs #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1989316485Sdavidcs u32 features; /* 0x30 */ 1990316485Sdavidcs /* RDMA protocol enablement */ 1991316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1992316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1993316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1994316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1995316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1996316485Sdavidcs #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1997316485Sdavidcs u32 reserved[7]; /* 0x34 */ 1998316485Sdavidcs}; 1999316485Sdavidcs 2000316485Sdavidcsstruct nvm_cfg1 2001316485Sdavidcs{ 2002316485Sdavidcs struct nvm_cfg1_glob glob; /* 0x0 */ 2003316485Sdavidcs struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 2004316485Sdavidcs struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 2005316485Sdavidcs struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 2006316485Sdavidcs}; 2007316485Sdavidcs 2008316485Sdavidcs/****************************************** 2009316485Sdavidcs * nvm_cfg structs 2010316485Sdavidcs ******************************************/ 2011337517Sdavidcs 2012337517Sdavidcsstruct board_info 2013337517Sdavidcs{ 2014337517Sdavidcs u16 vendor_id; 2015337517Sdavidcs u16 eth_did_suffix; 2016337517Sdavidcs u16 sub_vendor_id; 2017337517Sdavidcs u16 sub_device_id; 2018337517Sdavidcs char *board_name; 2019337517Sdavidcs char *friendly_name; 2020337517Sdavidcs}; 2021337517Sdavidcs 2022316485Sdavidcsenum nvm_cfg_sections 2023316485Sdavidcs{ 2024316485Sdavidcs NVM_CFG_SECTION_NVM_CFG1, 2025316485Sdavidcs NVM_CFG_SECTION_MAX 2026316485Sdavidcs}; 2027316485Sdavidcs 2028316485Sdavidcsstruct nvm_cfg 2029316485Sdavidcs{ 2030316485Sdavidcs u32 num_sections; 2031316485Sdavidcs u32 sections_offset[NVM_CFG_SECTION_MAX]; 2032316485Sdavidcs struct nvm_cfg1 cfg1; 2033316485Sdavidcs}; 2034316485Sdavidcs 2035316485Sdavidcs#endif /* NVM_CFG_H */ 2036